URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/
- from Rev 37 to Rev 36
- ↔ Reverse comparison
Rev 37 → Rev 36
/mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd
58,10 → 58,8
entity sys_pipeline is |
generic( |
n : integer := 1536; -- width of the operands (# bits) |
t : integer := 192; -- total number of stages (minimum 2) |
tl : integer := 64; -- lower number of stages (minimum 1) |
split : boolean := true -- if true the pipeline wil be split in 2 parts, |
-- if false there are no lower stages, only t counts |
t : integer := 192; -- total number of stages (divider of n) >= 2 |
tl : integer := 64 -- lower number of stages (best take t = sqrt(n)) |
); |
port( |
-- clock input |
84,45 → 82,42
architecture Structural of sys_pipeline is |
constant s : integer := n/t; |
|
signal m_i : std_logic_vector(n downto 0); |
signal y_i : std_logic_vector(n downto 0); |
|
signal m_i : std_logic_vector(n downto 0); |
signal y_i : std_logic_vector(n downto 0); |
signal r_sel_l : std_logic; |
signal r_sel_h : std_logic; |
|
-- systolic stages signals |
signal my_cin_stage : std_logic_vector((t-1) downto 0); |
signal my_cout_stage : std_logic_vector((t-1) downto 0); |
signal xin_stage : std_logic_vector((t-1) downto 0); |
signal qin_stage : std_logic_vector((t-1) downto 0); |
signal xout_stage : std_logic_vector((t-1) downto 0); |
signal qout_stage : std_logic_vector((t-1) downto 0); |
signal a_msb_stage : std_logic_vector((t-1) downto 0); |
signal a_0_stage : std_logic_vector((t-1) downto 0); |
signal cin_stage : std_logic_vector((t-1) downto 0); |
signal cout_stage : std_logic_vector((t-1) downto 0); |
signal red_cin_stage : std_logic_vector((t-1) downto 0); |
signal my_cin_stage : std_logic_vector((t-1) downto 0); |
signal my_cout_stage : std_logic_vector((t-1) downto 0); |
signal xin_stage : std_logic_vector((t-1) downto 0); |
signal qin_stage : std_logic_vector((t-1) downto 0); |
signal xout_stage : std_logic_vector((t-1) downto 0); |
signal qout_stage : std_logic_vector((t-1) downto 0); |
signal a_msb_stage : std_logic_vector((t-1) downto 0); |
signal a_0_stage : std_logic_vector((t-1) downto 0); |
signal cin_stage : std_logic_vector((t-1) downto 0); |
signal cout_stage : std_logic_vector((t-1) downto 0); |
signal red_cin_stage : std_logic_vector((t-1) downto 0); |
signal red_cout_stage : std_logic_vector((t-1) downto 0); |
signal start_stage : std_logic_vector((t-1) downto 0); |
signal done_stage : std_logic_vector((t-1) downto 0); |
signal r_sel_stage : std_logic_vector((t-1) downto 0); |
|
-- end logic signals |
signal r_sel_end : std_logic; |
|
-- signals needed if pipeline is split |
--------------------------------------- |
signal r_sel_l : std_logic; |
signal r_sel_h : std_logic; |
-- mid end logic signals |
signal a_0_midend : std_logic; |
signal start_stage : std_logic_vector((t-1) downto 0); |
signal done_stage : std_logic_vector((t-1) downto 0); |
signal r_sel_stage : std_logic_vector((t-1) downto 0); |
|
-- mid end signals |
signal a_0_midend : std_logic; |
signal r_sel_midend : std_logic; |
|
-- mid start logic signals |
signal my_cout_midstart : std_logic; |
signal xout_midstart : std_logic; |
signal qout_midstart : std_logic; |
signal cout_midstart : std_logic; |
signal red_cout_midstart : std_logic; |
-- mid start signals |
signal my_cout_midstart : std_logic; |
signal xout_midstart : std_logic; |
signal qout_midstart : std_logic; |
signal cout_midstart : std_logic; |
signal red_cout_midstart : std_logic; |
|
|
-- end signals |
signal r_sel_end : std_logic; |
begin |
|
m_i <= '0' & m; |
173,50 → 168,11
red_cout => red_cin_stage(0) |
); |
|
-- last cell logic |
------------------- |
last_cell : sys_last_cell_logic |
port map ( |
core_clk => core_clk, |
reset => reset, |
a_0 => a_msb_stage(t-1), |
cin => cout_stage(t-1), |
red_cin => red_cout_stage(t-1), |
r_sel => r_sel_end, |
start => done_stage(t-1) |
); |
|
------------------------------------ |
-- SINGLE PART PIPELINE CONNECTIONS |
------------------------------------ |
single_pipeline : if split=false generate |
-- link stages to eachother |
stage_connect : for i in 1 to (t-1) generate |
my_cin_stage(i) <= my_cout_stage(i-1); |
cin_stage(i) <= cout_stage(i-1); |
xin_stage(i) <= xout_stage(i-1); |
qin_stage(i) <= qout_stage(i-1); |
red_cin_stage(i) <= red_cout_stage(i-1); |
start_stage(i) <= done_stage(i-1); |
a_msb_stage(i-1) <= a_0_stage(i); |
r_sel_stage(i) <= r_sel_end; |
end generate; |
r_sel_stage(0) <= r_sel_end; |
|
start_stage(0) <= start; |
next_x <= done_stage(0); |
end generate; |
|
---------------------------------------- |
-- SPLIT PIPELINE CONNECTIONS AND LOGIC |
---------------------------------------- |
split_pipeline : if split=true generate |
-- only start first stage if lower part is used |
with p_sel select |
start_stage(0) <= '0' when "10", |
start when others; |
|
-- select start or midstart stage for requesting new xi bit |
with p_sel select |
next_x <= done_stage(tl) when "10", |
done_stage(0) when others; |
300,6 → 256,19
r_sel_stage(i) <= r_sel_h; |
end generate; |
r_sel_stage(tl) <= r_sel_h; |
|
-- last cell logic |
------------------- |
last_cell : sys_last_cell_logic |
port map ( |
core_clk => core_clk, |
reset => reset, |
a_0 => a_msb_stage(t-1), |
cin => cout_stage(t-1), |
red_cin => red_cout_stage(t-1), |
r_sel => r_sel_end, |
start => done_stage(t-1) |
); |
|
with p_sel select |
r_sel_l <= r_sel_midend when "01", |
309,6 → 278,5
with p_sel select |
r_sel_h <= '0' when "01", |
r_sel_end when others; |
end generate; |
|
|
end Structural; |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
87,10 → 87,14
|
|
architecture Structural of mod_sim_exp_core is |
constant n : integer := 1536; |
constant t : integer := 96; |
constant tl : integer := 32; |
|
-- data busses |
signal xy : std_logic_vector(nr_bits_total-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(nr_bits_total-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(nr_bits_total-1 downto 0); -- result data bus RAM <- multiplier |
signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier |
|
-- control signals |
signal op_sel : std_logic_vector(1 downto 0); -- operand selection |
112,10 → 116,9
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
n => nr_bits_total, |
t => nr_stages_total, |
tl => nr_stages_low, |
split => split_pipeline |
n => n, |
nr_stages => t, --(divides n, bits_low & (n-bits_low)) |
stages_low => tl |
) |
port map( |
core_clk => clk, |
132,7 → 135,7
-- Block ram memory for storing the operands and the modulus |
the_memory : operand_mem |
generic map( |
n => nr_bits_total |
n => n |
) |
port map( |
data_in => data_in, |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
49,26 → 49,8
|
|
package mod_sim_exp_pkg is |
-------------------------------------------------------------------- |
------------------------- CORE PARAMETERS -------------------------- |
-------------------------------------------------------------------- |
-- These 4 parameters affect core workings |
constant nr_bits_total : integer := 1536; |
constant nr_stages_total : integer := 96; |
constant nr_stages_low : integer := 32; |
constant split_pipeline : boolean := true; |
|
-- extra calculated parameters |
constant nr_bits_low : integer := (nr_bits_total/nr_stages_total)*nr_stages_low; |
constant nr_bits_high : integer := nr_bits_total-nr_bits_low; |
constant nr_stages_high : integer := nr_stages_total-nr_stages_low; |
|
|
-------------------------------------------------------------------- |
---------------------- COMPONENT DECLARATIONS ---------------------- |
-------------------------------------------------------------------- |
|
-------------------------------------------------------------------- |
-- d_flip_flop |
-------------------------------------------------------------------- |
-- 1-bit D flip-flop with asynchronous active high reset |
478,9 → 460,9
-- |
component mont_mult_sys_pipeline is |
generic ( |
n : integer := 1536; -- width of the operands |
t : integer := 96; -- total number of stages |
tl : integer := 32 -- lower number of stages |
n : integer := 1536; -- width of the operands |
nr_stages : integer := 96; -- total number of stages |
stages_low : integer := 32 -- lower number of stages |
); |
port ( |
-- clock input |
759,10 → 741,8
component sys_pipeline is |
generic( |
n : integer := 1536; -- width of the operands (# bits) |
t : integer := 192; -- total number of stages (minimum 2) |
tl : integer := 64; -- lower number of stages (minimum 1) |
split : boolean := true -- if true the pipeline wil be split in 2 parts, |
-- if false there are no lower stages, only t counts |
t : integer := 192; -- total number of stages (divider of n) >= 2 |
tl : integer := 64 -- lower number of stages (best take t = sqrt(n)) |
); |
port( |
-- clock input |
784,11 → 764,9
|
component mont_multiplier is |
generic ( |
n : integer := 1536; -- width of the operands |
t : integer := 96; -- total number of stages (minimum 2) |
tl : integer := 32; -- lower number of stages (minimum 1) |
split : boolean := true -- if true the pipeline wil be split in 2 parts, |
-- if false there are no lower stages, only t counts |
n : integer := 1536; -- width of the operands |
nr_stages : integer := 96; -- total number of stages |
stages_low : integer := 32 -- lower number of stages |
); |
port ( |
-- clock input |
/mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd
65,11 → 65,9
-- |
entity mont_multiplier is |
generic ( |
n : integer := 1536; -- width of the operands |
t : integer := 96; -- total number of stages (minimum 2) |
tl : integer := 32; -- lower number of stages (minimum 1) |
split : boolean := true -- if true the pipeline wil be split in 2 parts, |
-- if false there are no lower stages, only t counts |
n : integer := 1536; -- width of the operands |
nr_stages : integer := 96; -- total number of stages |
stages_low : integer := 32 -- lower number of stages |
); |
port ( |
-- clock input |
89,7 → 87,9
end mont_multiplier; |
|
architecture Structural of mont_multiplier is |
constant s : integer := n/t; -- stage width (# bits) |
constant t : integer := nr_stages; |
constant tl : integer := stages_low; |
constant s : integer := n/nr_stages; -- stage width (# bits) |
constant nl : integer := s*tl; -- lower pipeline width (# bits) |
constant nh : integer := n - nl; -- higher pipeline width (# bits) |
|
96,7 → 96,6
signal reset_multiplier : std_logic; |
signal start_multiplier : std_logic; |
|
signal p_sel_i : std_logic_vector(1 downto 0); |
signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part |
signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part |
|
106,7 → 105,7
signal start_first_stage : std_logic; |
|
begin |
|
|
-- multiplier is reset every calculation or reset |
reset_multiplier <= reset or start; |
|
124,8 → 123,8
x_selection : x_shift_reg |
generic map( |
n => n, |
t => t, |
tl => tl |
t => nr_stages, |
tl => stages_low |
) |
port map( |
clk => core_clk, |
133,23 → 132,10
x_in => xy, |
load_x => load_x, |
next_x => next_xi, |
p_sel => p_sel_i, |
p_sel => p_sel, |
xi => xi |
); |
|
---------------------------------------- |
-- SINGLE PIPELINE ASSIGNMENTS |
---------------------------------------- |
single_pipeline : if split=false generate |
p_sel_i <= "11"; |
t_sel <= t; |
n_sel <= n-1; |
end generate; |
|
---------------------------------------- |
-- SPLIT PIPELINE ASSIGNMENTS |
---------------------------------------- |
split_pipeline : if split=true generate |
-- this module controls the pipeline operation |
-- width in stages for selected pipeline |
with p_sel select |
163,14 → 149,11
nh-1 when "10", -- higher pipeline part |
n-1 when others; -- full pipeline |
|
p_sel_i <= p_sel; |
end generate; |
|
-- stepping control logic to keep track off the multiplication and when it is done |
stepping_control : stepping_logic |
generic map( |
n => n, -- max nr of steps required to complete a multiplication |
t => t -- total nr of steps in the pipeline |
t => nr_stages -- total nr of steps in the pipeline |
) |
port map( |
core_clk => core_clk, |
185,9 → 168,8
systolic_array : sys_pipeline |
generic map( |
n => n, |
t => t, |
tl => tl, |
split => split |
t => nr_stages, |
tl => stages_low |
) |
port map( |
core_clk => core_clk, |
197,8 → 179,9
next_x => next_xi, |
start => start_first_stage, |
reset => reset_multiplier, |
p_sel => p_sel_i, |
p_sel => p_sel, |
r => r |
); |
|
end Structural; |
|
/mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd
68,9 → 68,9
-- |
entity mont_mult_sys_pipeline is |
generic ( |
n : integer := 1536; -- width of the operands |
t : integer := 96; -- total number of stages |
tl : integer := 32 -- lower number of stages |
n : integer := 1536; -- width of the operands |
nr_stages : integer := 96; -- total number of stages |
stages_low : integer := 32 -- lower number of stages |
); |
port ( |
-- clock input |
90,8 → 90,8
end mont_mult_sys_pipeline; |
|
architecture Structural of mont_mult_sys_pipeline is |
constant stage_width : integer := n/t; |
constant bits_l : integer := stage_width * tl; |
constant stage_width : integer := n/nr_stages; |
constant bits_l : integer := stage_width * stages_low; |
constant bits_h : integer := n - bits_l; |
|
signal my : std_logic_vector(n downto 0); |
117,8 → 117,8
x_selection : x_shift_reg |
generic map( |
n => n, |
t => t, |
tl => tl |
t => nr_stages, |
tl => stages_low |
) |
port map( |
clk => core_clk, |
179,8 → 179,8
the_multiplier : systolic_pipeline |
generic map( |
n => n, -- width of the operands (# bits) |
t => t, -- number of stages (divider of n) >= 2 |
tl => tl |
t => nr_stages, -- number of stages (divider of n) >= 2 |
tl => stages_low |
) |
port map( |
core_clk => core_clk, |
/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
63,6 → 63,7
end mod_sim_exp_core_tb; |
|
architecture test of mod_sim_exp_core_tb is |
constant nr_stages : integer := 96; |
constant clk_period : time := 10 ns; |
signal clk : std_logic := '0'; |
signal reset : std_logic := '1'; |
254,7 → 255,7
write(Lw, base_width); |
writeline(output, Lw); |
case (base_width) is |
when nr_bits_total => when nr_bits_high => when nr_bits_low => |
when 1536 => when 1024 => when 512 => |
when others => |
write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw); |
assert false report "incompatible base width!!!" severity failure; |
331,9 → 332,9
write(Lw, string'("----- Selecting pipeline: ")); |
writeline(output, Lw); |
case (base_width) is |
when nr_bits_total => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected")); |
when nr_bits_high => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected")); |
when nr_bits_low => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected")); |
when 1536 => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected")); |
when 1024 => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected")); |
when 512 => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected")); |
when others => |
write(Lw, string'(" Invallid bitwidth for design")); |
assert false report "impossible basewidth!" severity failure; |
426,7 → 427,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period); |
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period); |
writeline(output, Lw); |
if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then |
write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw); |
459,7 → 460,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period); |
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period); |
writeline(output, Lw); |
if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then |
write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw); |
492,7 → 493,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period); |
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period); |
writeline(output, Lw); |
if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then |
write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw); |
525,7 → 526,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period); |
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period); |
writeline(output, Lw); |
if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then |
write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw); |
571,7 → 572,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, ((nr_stages_total+(2*(base_width-1)))*clk_period*7*exponent_width)/4); |
write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4); |
writeline(output, Lw); |
write(Lw, string'(" => Done")); |
core_run_auto <= '0'; |
612,7 → 613,7
write(Lw, string'(ToString(timer))); |
writeline(output, Lw); |
write(Lw, string'(" => expected time is ")); |
write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period); |
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period); |
writeline(output, Lw); |
|
when 12 => -- check with result |