URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/
- from Rev 52 to Rev 51
- ↔ Reverse comparison
Rev 52 → Rev 51
/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd
6,7 → 6,18
-- Description ${cursor} |
-------------------------------------------------------------------------------- |
-- |
-- correctly implemented as Block RAM, no other resources needed. |
-- WIDTHA = 32 |
-- SIZEA = 32 |
-- ADDRWIDTHA = 5 |
-- WIDTHB = 512 |
-- SIZEB = 2 |
-- ADDRWIDTHB = 1 |
-- Found 32x32:2x512-bit dual-port RAM <Mram_ram> for signal <ram>. |
-- Found 512-bit register for signal <doB>. |
-- Found 512-bit register for signal <readB>. |
-- Summary: |
-- inferred 1 RAM(s). |
-- inferred 1024 D-type flip-flop(s). |
-- |
|
library ieee; |
18,10 → 29,10
|
generic ( |
WIDTHA : integer := 32; |
SIZEA : integer := 48; |
ADDRWIDTHA : integer := 6; |
WIDTHB : integer := 1536; |
SIZEB : integer := 1; |
SIZEA : integer := 32; |
ADDRWIDTHA : integer := 5; |
WIDTHB : integer := 512; |
SIZEB : integer := 2; |
ADDRWIDTHB : integer := 1 |
); |
|
33,6 → 44,7
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0); |
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); |
diA : in std_logic_vector(WIDTHA-1 downto 0); |
doA : out std_logic_vector(WIDTHA-1 downto 0); |
doB : out std_logic_vector(WIDTHB-1 downto 0) |
); |
|
84,13 → 96,12
-- - the RAM has two write ports, |
-- - the RAM has only one write port whose data width is maxWIDTH |
-- In all other cases, ram can be a signal. |
signal ram : ramType := (others => (others => '0')); |
shared variable ram : ramType := (others => (others => '0')); |
|
attribute ram_style : string; |
attribute ram_style of ram:signal is "block"; |
|
signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); |
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); |
signal addrB_i : std_logic_vector(ADDRWIDTHB-1 downto 0):= (others => '0'); |
signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); |
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); |
|
begin |
|
99,7 → 110,7
begin |
if rising_edge(clkA) then |
if weA = '1' then |
ram(conv_integer(addrA)) <= diA; |
ram(conv_integer(addrA)) := diA; |
end if; |
end if; |
end process; |
109,15 → 120,16
begin |
if rising_edge(clkB) then |
if enB = '1' then |
addrB_i <= addrB; |
for i in 0 to RATIO-1 loop |
readB((i+1)*minWIDTH-1 downto i*minWIDTH) |
<= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO)))); |
end loop; |
end if; |
doB <= readB; |
regB <= readB; |
end if; |
end process; |
|
doA <= regA; |
doB <= regB; |
|
ramoutput : for i in 0 to RATIO-1 generate |
readB((i+1)*minWIDTH-1 downto i*minWIDTH) |
<= ram(conv_integer(addrB_i & conv_std_logic_vector(i,log2(RATIO)))); |
end generate; |
|
end behavioral; |