URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl
- from Rev 17 to Rev 16
- ↔ Reverse comparison
Rev 17 → Rev 16
/core/mod_sim_exp_pkg.vhd
209,71 → 209,6
); |
end component adder_n; |
|
-------------------------------------------------------------------- |
-- standard_cell_block |
-------------------------------------------------------------------- |
-- a standard cell block of (width)-bit for the montgommery multiplier |
-- systolic array |
-- |
component standard_cell_block is |
generic ( |
width : integer := 16 |
); |
port ( |
-- modulus and y operand input (width)-bit |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
-- q and x operand input (serial input) |
x : in std_logic; |
q : in std_logic; |
-- previous result in (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
-- carry in and out |
cin : in std_logic; |
cout : out std_logic; |
-- result out (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end component standard_cell_block; |
|
-------------------------------------------------------------------- |
-- standard_stage |
-------------------------------------------------------------------- |
-- standard stage for use in the montgommery multiplier pipeline |
-- the result is available after 1 clock cycle |
-- |
component standard_stage is |
generic( |
width : integer := 32 |
); |
port( |
-- clock input |
core_clk : in std_logic; |
-- modulus and y operand input (width)-bit |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
-- q and x operand input (serial input) |
xin : in std_logic; |
qin : in std_logic; |
-- q and x operand output (serial output) |
xout : out std_logic; |
qout : out std_logic; |
-- msb input (lsb from next stage, for shift right operation) |
a_msb : in std_logic; |
-- carry out(clocked) and in |
cin : in std_logic; |
cout : out std_logic; |
-- control singals |
start : in std_logic; |
reset : in std_logic; |
done : out std_logic; |
-- result out |
r : out std_logic_vector((width-1) downto 0) |
); |
end component standard_stage; |
|
component autorun_cntrl is |
port ( |
clk : in std_logic; |
512,6 → 447,46
); |
end component operands_sp; |
|
component standard_cell_block is |
generic ( |
width : integer := 16 |
); |
port ( |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
x : in std_logic; |
q : in std_logic; |
a : in std_logic_vector((width-1) downto 0); |
cin : in std_logic; |
cout : out std_logic; |
r : out std_logic_vector((width-1) downto 0) |
); |
end component standard_cell_block; |
|
component standard_stage is |
generic( |
width : integer := 32 |
); |
port( |
core_clk : in std_logic; |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
xin : in std_logic; |
qin : in std_logic; |
xout : out std_logic; |
qout : out std_logic; |
a_msb : in std_logic; |
cin : in std_logic; |
cout : out std_logic; |
start : in std_logic; |
reset : in std_logic; |
done : out std_logic; |
r : out std_logic_vector((width-1) downto 0) |
); |
end component standard_stage; |
|
component stepping_logic is |
generic( |
n : integer := 1536; -- max nr of steps required to complete a multiplication |
/core/standard_stage.vhd
54,35 → 54,26
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- standard stage for use in the montgommery multiplier pipeline |
-- the result is available after 1 clock cycle |
|
entity standard_stage is |
generic( |
width : integer := 32 |
); |
port( |
-- clock input |
core_clk : in std_logic; |
-- modulus and y operand input (width)-bit |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
-- q and x operand input (serial input) |
xin : in std_logic; |
qin : in std_logic; |
-- q and x operand output (serial output) |
xout : out std_logic; |
qout : out std_logic; |
-- msb input (lsb from next stage, for shift right operation) |
a_msb : in std_logic; |
-- carry out(clocked) and in |
cin : in std_logic; |
cout : out std_logic; |
-- control singals |
start : in std_logic; |
reset : in std_logic; |
done : out std_logic; |
-- result out |
r : out std_logic_vector((width-1) downto 0) |
); |
end standard_stage; |
89,23 → 80,42
|
|
architecture Structural of standard_stage is |
-- input |
signal cin_i : std_logic; |
signal xin_i : std_logic; |
signal qin_i : std_logic; |
signal a_msb_i : std_logic; |
|
-- output |
signal cout_i : std_logic; |
signal r_i : std_logic_vector((width-1) downto 0); |
signal cout_reg_i : std_logic; |
signal xout_reg_i : std_logic; |
signal qout_reg_i : std_logic; |
signal r_reg_i : std_logic_vector((width-1) downto 0); |
|
-- interconnect |
signal a : std_logic_vector((width-1) downto 0); |
signal a_i : std_logic_vector((width-1) downto 0); |
|
-- control |
signal done_i : std_logic := '1'; |
begin |
|
-- map internal signals to outputs |
done <= done_i; |
r <= r_reg_i; |
cout <= cout_reg_i; |
qout <= qout_reg_i; |
xout <= xout_reg_i; |
|
-- a is equal to the right shifted version(/2) of r_reg with a_msb as MSB |
a <= a_msb & r_reg_i((width-1) downto 1); |
-- map inputs to internal signals |
xin_i <= xin; |
qin_i <= qin; |
cin_i <= cin; |
a_msb_i <= a_msb; |
|
-- structure of (width) standard_cell_blocks |
a_i <= a_msb_i & r_reg_i((width-1) downto 1); |
|
cell_block : standard_cell_block |
generic map( |
width => width |
114,29 → 124,24
my => my, |
y => y, |
m => m, |
x => xin, |
q => qin, |
a => a, |
cin => cin, |
x => xin_i, |
q => qin_i, |
a => a_i, |
cin => cin_i, |
cout => cout_i, |
r => r_i |
); |
|
-- stage done signal |
-- 1 cycle after start of stage |
done_signal : d_flip_flop |
port map( |
core_clk => core_clk, |
reset => reset, |
din => start, |
dout => done |
core_clk => core_clk, |
reset => reset, |
din => start, |
dout => done_i |
); |
|
-- output registers |
-------------------- |
|
-- result register (width)-bit |
result_reg : register_n |
RESULT_REG : register_n |
generic map( |
width => width |
) |
147,35 → 152,33
din => r_i, |
dout => r_reg_i |
); |
|
-- xout register |
xout_reg : register_1b |
|
XOUT_REG : register_1b |
port map( |
core_clk => core_clk, |
ce => start, |
reset => reset, |
din => xin, |
dout => xout |
din => xin_i, |
dout => xout_reg_i |
); |
|
-- qout register |
qout_reg : register_1b |
|
QOUT_REG : register_1b |
port map( |
core_clk => core_clk, |
ce => start, |
reset => reset, |
din => qin, |
dout => qout |
din => qin_i, |
dout => qout_reg_i |
); |
|
-- carry out register |
cout_reg : register_1b |
COUT_REG : register_1b |
port map( |
core_clk => core_clk, |
ce => start, |
reset => reset, |
din => cout_i, |
dout => cout |
dout => cout_reg_i |
); |
|
end Structural; |
|
|
end Structural; |
/core/standard_cell_block.vhd
6,7 → 6,7
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- a block of (width) cell_1b cells for use in the ---- |
---- a block of [width] cell_1b cells for use in the ---- |
---- montgommery multiplier systolic array ---- |
---- ---- |
---- Dependencies: ---- |
51,26 → 51,20
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- a standard cell block of (width)-bit for the montgommery multiplier |
-- systolic array |
|
entity standard_cell_block is |
generic ( |
width : integer := 16 |
); |
port ( |
-- modulus and y operand input (width)-bit |
my : in std_logic_vector((width-1) downto 0); |
y : in std_logic_vector((width-1) downto 0); |
m : in std_logic_vector((width-1) downto 0); |
-- q and x operand input (serial input) |
x : in std_logic; |
q : in std_logic; |
-- previous result in (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
-- carry in and out |
cin : in std_logic; |
cout : out std_logic; |
-- result out (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end standard_cell_block; |
77,14 → 71,11
|
|
architecture Structural of standard_cell_block is |
-- vector for the carry bits |
signal carry : std_logic_vector(width downto 0); |
begin |
|
-- carry in |
carry(0) <= cin; |
|
-- structure of (width) 1-bit cells |
cell_block : for i in 0 to (width-1) generate |
cells : cell_1b |
port map( |
99,7 → 90,6
r => r(i) |
); |
end generate; |
|
-- carry out |
|
cout <= carry(width); |
end Structural; |