URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl
- from Rev 30 to Rev 25
- ↔ Reverse comparison
Rev 30 → Rev 25
/core/sys_last_cell_logic.vhd
File deleted
/core/sys_pipeline.vhd
107,6 → 107,12
signal my0_mux_result : std_logic; |
signal my0 : std_logic; |
|
-- last cell signals |
signal a_high : std_logic_vector(1 downto 0); |
signal a_high_reg : std_logic_vector(1 downto 0); |
signal red_cout_end : std_logic_vector(1 downto 0); |
|
|
begin |
|
m_i <= '0' & m; |
178,15 → 184,41
|
-- last cell logic |
------------------- |
last_cell : sys_last_cell_logic |
port map ( |
-- half adder: cout_stage(t-1) + a_high_reg(1) |
a_high(0) <= cout_stage(t-1) xor a_high_reg(1); --result |
a_high(1) <= cout_stage(t-1) and a_high_reg(1); --cout |
|
a_msb_stage(t-1) <= a_high_reg(0); |
|
last_reg : register_n |
generic map( |
width => 2 |
) |
port map( |
core_clk => core_clk, |
ce => done_stage(t-1), |
reset => reset, |
a_0 => a_msb_stage(t-1), |
cin => cout_stage(t-1), |
red_cin => red_cout_stage(t-1), |
r_sel => r_sel, |
start => done_stage(t-1) |
din => a_high, |
dout => a_high_reg |
); |
|
-- reduction finishing last 2 bits |
reduction_adder_a : cell_1b_adder |
port map( |
a => '1', -- for 2s complement of m |
b => a_high_reg(0), |
cin => red_cout_stage(t-1), |
cout => red_cout_end(0) |
); |
|
reduction_adder_b : cell_1b_adder |
port map( |
a => '1', -- for 2s complement of m |
b => a_high_reg(1), |
cin => red_cout_end(0), |
cout => red_cout_end(1) |
); |
|
r_sel <= red_cout_end(1); |
|
end Structural; |
/core/mod_sim_exp_pkg.vhd
692,26 → 692,8
r : out std_logic_vector((width-1) downto 0) |
); |
end component sys_stage; |
|
-------------------------------------------------------------------- |
-- sys_last_cell_logic |
-------------------------------------------------------------------- |
-- logic needed as the last piece in the systolic array pipeline |
-- calculates the last 2 bits of the cell_result and finishes the reduction |
-- also generates the result selection signal |
-- |
component sys_last_cell_logic is |
port ( |
core_clk : in std_logic; -- clock input |
reset : in std_logic; |
a_0 : out std_logic; -- a_msb for last stage |
cin : in std_logic; -- cout from last stage |
red_cin : in std_logic; -- red_cout from last stage |
r_sel : out std_logic; -- result selection bit |
start : in std_logic -- done signal from last stage |
); |
end component sys_last_cell_logic; |
|
|
-------------------------------------------------------------------- |
-- sys_pipeline |
-------------------------------------------------------------------- |