URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl
- from Rev 39 to Rev 38
- ↔ Reverse comparison
Rev 39 → Rev 38
/core/mod_sim_exp_pkg.vhd
573,12 → 573,6
); |
end component modulus_ram; |
|
-------------------------------------------------------------------- |
-- mont_ctrl |
-------------------------------------------------------------------- |
-- This module controls the montgommery mutliplier and controls traffic between |
-- RAM and multiplier. Also contains the autorun logic for exponentiations. |
-- |
component mont_ctrl is |
port ( |
clk : in std_logic; |
591,6 → 585,7
op_buffer_empty : in std_logic; |
op_sel_buffer : in std_logic_vector(31 downto 0); |
read_buffer : out std_logic; |
buffer_noread : in std_logic; |
done : out std_logic; |
calc_time : out std_logic; |
-- multiplier side |
618,8 → 613,7
end component operand_dp; |
|
component operand_mem is |
generic( |
n : integer := 1536 |
generic(n : integer := 1536 |
); |
port( |
-- data interface (plb side) |
626,7 → 620,6
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- address structure: |
-- bit: 8 -> '1': modulus |
-- '0': operands |
639,7 → 632,9
xy_out : out std_logic_vector((n-1) downto 0); |
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
-- control signals |
-- control signals |
load_op : in std_logic; |
load_m : in std_logic; |
load_result : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
collision : out std_logic; |
/core/mod_sim_exp_core.vhd
97,7 → 97,9
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand |
signal mult_ready : std_logic; |
signal start_mult : std_logic; |
signal load_op : std_logic; |
signal load_x : std_logic; |
signal load_m : std_logic; |
signal load_result : std_logic; |
|
-- fifo signals |
136,17 → 138,20
data_in => data_in, |
data_out => data_out, |
rw_address => rw_address, |
write_enable => write_enable, |
op_sel => op_sel, |
xy_out => xy, |
m => m, |
result_in => r, |
load_op => load_op, |
load_m => load_m, |
load_result => load_result, |
result_dest_op => result_dest_op, |
collision => collision, |
clk => clk |
); |
|
|
load_op <= write_enable when (rw_address(8) = '0') else '0'; |
load_m <= write_enable when (rw_address(8) = '1') else '0'; |
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3 |
|
-- A fifo for auto-run operand selection |
176,6 → 181,7
op_buffer_empty => fifo_empty, |
op_sel_buffer => fifo_dout, |
read_buffer => fifo_pop, |
buffer_noread => fifo_nopop, |
done => ready, |
calc_time => calc_time, |
op_sel => op_sel, |
/core/operand_mem.vhd
54,8 → 54,7
|
|
entity operand_mem is |
generic( |
n : integer := 1536 |
generic(n : integer := 1536 |
); |
port( |
-- data interface (plb side) |
62,7 → 61,6
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- address structure: |
-- bit: 8 -> '1': modulus |
-- '0': operands |
76,6 → 74,8
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
-- control signals |
load_op : in std_logic; |
load_m : in std_logic; |
load_result : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
collision : out std_logic; |
94,10 → 94,9
signal xy_out_i : std_logic_vector(1535 downto 0); |
signal m_i : std_logic_vector(1535 downto 0); |
signal result_in_i : std_logic_vector(1535 downto 0); |
signal load_op : std_logic; |
|
signal m_addr_i : std_logic_vector(5 downto 0); |
signal load_m : std_logic; |
signal write_m_i : std_logic; |
signal m_data_i : std_logic_vector(31 downto 0); |
|
begin |
114,9 → 113,7
operand_in_sel_i <= rw_address(7 downto 6); |
xy_data_i <= data_in; |
m_data_i <= data_in; |
|
load_op <= write_enable when (rw_address(8) = '0') else '0'; |
load_m <= write_enable when (rw_address(8) = '1') else '0'; |
write_m_i <= load_m; |
|
-- xy operand storage |
xy_ram : operand_ram |
140,7 → 137,7
port map( |
clk => clk, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
write_modulus => write_m_i, |
modulus_in => m_data_i, |
modulus_out => m_i |
); |
/core/sys_last_cell_logic.vhd
68,27 → 68,44
|
|
architecture Behavorial of sys_last_cell_logic is |
signal cin_reg : std_logic; |
signal cell_result_high : std_logic_vector(1 downto 0); |
signal cell_result_high_reg : std_logic_vector(1 downto 0); |
signal red_cout_end : std_logic; |
begin |
|
-- half adder: cout_last_stage + cell_result_high_reg(1) |
cell_result_high(0) <= cin xor cell_result_high_reg(1); --result |
cell_result_high(1) <= cin and cell_result_high_reg(1); --cout |
|
a_0 <= cin_reg; |
a_0 <= cell_result_high_reg(0); |
|
last_reg : register_1b |
last_reg : register_n |
generic map( |
width => 2 |
) |
port map( |
core_clk => core_clk, |
ce => start, |
reset => reset, |
din => cin, |
dout => cin_reg |
din => cell_result_high, |
dout => cell_result_high_reg |
); |
|
-- reduction, finishing last bit |
reduction_adder : cell_1b_adder |
-- reduction, finishing last 2 bits |
reduction_adder_a : cell_1b_adder |
port map( |
a => '1', -- for 2s complement of m |
b => cin_reg, |
b => cell_result_high_reg(0), |
cin => red_cin, |
cout => red_cout_end |
); |
|
reduction_adder_b : cell_1b_adder |
port map( |
a => '1', -- for 2s complement of m |
b => cell_result_high_reg(1), |
cin => red_cout_end, |
cout => r_sel |
); |
|
|
end Behavorial; |
/core/mont_ctrl.vhd
66,6 → 66,7
op_buffer_empty : in std_logic; |
op_sel_buffer : in std_logic_vector(31 downto 0); |
read_buffer : out std_logic; |
buffer_noread : in std_logic; |
done : out std_logic; |
calc_time : out std_logic; |
-- multiplier side |
129,6 → 130,8
else |
start_up_counter <= "100"; |
end if; |
else |
start_up_counter <= start_up_counter; |
end if; |
end process; |
|
159,6 → 162,8
else |
calc_time_i <= calc_time_i; |
end if; |
else |
calc_time_i <= calc_time_i; |
end if; |
end process CALC_TIME_PROC; |
calc_time <= calc_time_i; |
/core/counter_sync.vhd
67,7 → 67,7
begin |
|
-- counter process with asynchronous active high reset |
count_proc: process(core_clk, reset) |
count_proc: process(core_clk, ce, reset) |
variable steps_counter : integer range 0 to max_value-1; |
begin |
if reset = '1' then -- reset counter |
/core/autorun_cntrl.vhd
70,11 → 70,13
signal bit_counter_0_i : std_logic; |
signal bit_counter_15_i : std_logic; |
signal next_bit_i : std_logic := '0'; |
signal next_bit_del_i : std_logic; |
|
signal start_cycle_i : std_logic := '0'; |
signal start_cycle_del_i : std_logic; |
|
signal done_i : std_logic; |
signal start_i : std_logic; |
signal running_i : std_logic; |
|
signal start_multiplier_i : std_logic; |
166,7 → 168,7
end process DEL_PROC; |
|
-- process for delaying signals with 1 clock cycle |
CYCLE_CNTR_PROC: process(clk, start, reset) |
CYCLE_CNTR_PROC: process(clk, start) |
begin |
if start = '1' or reset = '1' then |
cycle_counter_i <= '0'; |
/core/operand_ram.vhd
86,6 → 86,7
signal doutb0 : std_logic_vector(31 downto 0); |
signal doutb1 : std_logic_vector(31 downto 0); |
signal doutb2 : std_logic_vector(31 downto 0); |
signal doutb3 : std_logic_vector(31 downto 0); |
|
begin |
|
120,7 → 121,8
with operand_addr(5 downto 4) select |
result_out <= doutb0 when "00", |
doutb1 when "01", |
doutb2 when others; |
doutb2 when "10", |
doutb3 when others; |
|
-- 3 instances of a dual port ram to store the parts of the operand |
op_0 : operand_dp |