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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk/rtl
    from Rev 36 to Rev 34
    Reverse comparison

Rev 36 → Rev 34

/vhdl/core/mod_sim_exp_core.vhd
114,7 → 114,7
begin
 
-- The actual multiplier
the_multiplier : mont_multiplier
the_multiplier : mont_mult_sys_pipeline
generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
/vhdl/core/sys_pipeline.vhd
85,8 → 85,6
signal m_i : std_logic_vector(n downto 0);
signal y_i : std_logic_vector(n downto 0);
signal r_sel_l : std_logic;
signal r_sel_h : std_logic;
-- systolic stages signals
signal my_cin_stage : std_logic_vector((t-1) downto 0);
103,7 → 101,7
signal red_cout_stage : std_logic_vector((t-1) downto 0);
signal start_stage : std_logic_vector((t-1) downto 0);
signal done_stage : std_logic_vector((t-1) downto 0);
signal r_sel_stage : std_logic_vector((t-1) downto 0);
signal r_sel : std_logic;
 
-- mid end signals
signal a_0_midend : std_logic;
148,11 → 146,13
start => start_stage(i),
reset => reset,
done => done_stage(i),
r_sel => r_sel_stage(i),
r_sel => r_sel,
r => r(((i+1)*s)-1 downto (i*s))
);
end generate;
-- first cell logic
--------------------
first_cell : sys_first_cell_logic
186,9 → 186,7
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_l;
end generate;
r_sel_stage(0) <= r_sel_l;
-- mid end logic
-----------------
253,10 → 251,8
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_h;
end generate;
r_sel_stage(tl) <= r_sel_h;
-- last cell logic
-------------------
last_cell : sys_last_cell_logic
271,12 → 267,6
);
with p_sel select
r_sel_l <= r_sel_midend when "01",
r_sel_end when "11",
'0' when others;
with p_sel select
r_sel_h <= '0' when "01",
r_sel_end when others;
r_sel <= r_sel_midend when "01",
r_sel_end when others;
end Structural;

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