URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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/vhdl/core/register_1b.vhd
6,7 → 6,7
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- 1 bit register with active high asynchronious reset and ce---- |
---- 1 bit register ---- |
---- used in montgommery multiplier systolic array stages ---- |
---- ---- |
---- Dependencies: none ---- |
47,33 → 47,38
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
-- 1-bit register with asynchronous reset and clock enable |
-- Xilinx primitives used |
library UNISIM; |
use UNISIM.VComponents.all; |
|
|
entity register_1b is |
port( |
core_clk : in std_logic; -- clock input |
ce : in std_logic; -- clock enable (active high) |
reset : in std_logic; -- reset (active high) |
din : in std_logic; -- data in |
dout : out std_logic -- data out |
core_clk : in std_logic; |
ce : in std_logic; |
reset : in std_logic; |
din : in std_logic; |
dout : out std_logic |
); |
end register_1b; |
|
|
architecture Behavorial of register_1b is |
architecture Structural of register_1b is |
signal dout_i : std_logic; |
begin |
|
-- process for 1-bit register |
reg_1b : process (reset, ce, core_clk, din) |
begin |
if reset='1' then -- asynchronous active high reset |
dout <= '0'; |
else |
if rising_edge(core_clk) then -- clock in data on rising edge |
if ce='1' then -- active high clock enable to clock in data |
dout <= din; |
end if; |
end if; |
end if; |
end process; |
dout <= dout_i; |
|
FDCE_inst : FDCE |
generic map ( |
INIT => '0' -- Initial value of latch ('0' or '1') |
) |
port map ( |
Q => dout_i, -- Data output |
CLR => reset, -- Asynchronous clear/reset input |
D => din, -- Data input |
C => core_clk, -- Gate input |
CE => ce -- Gate enable input |
); |
|
end Behavorial; |
end Structural; |