OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

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/mod_sim_exp/branches/newRAMstyle/doc/src/plb_interface.tex File deleted \ No newline at end of file
/mod_sim_exp/branches/newRAMstyle/doc/src/Speedtest.xlsx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
mod_sim_exp/branches/newRAMstyle/doc/src/Speedtest.xlsx Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mod_sim_exp/branches/newRAMstyle/doc/src/acknowl.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/acknowl.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/acknowl.tex (nonexistent) @@ -1,30 +0,0 @@ -\chapter*{Acknowledgments} -\addcontentsline{toc}{chapter}{Acknowledgments} -This project is maintained by the DraMCo research group\footnote{\url{http://www.dramco.be/}} of KAHO Sint-Lieven\footnote{\url{http://www.kahosl.be/}}, part of the KU Leuven association\footnote{\url{http://associatie.kuleuven.be/}}. -The base design for this IP core is written by Geoffrey Ottoy, member of the DraMCo research group. Further adjustments have been made by Jonas De Craene - -%\addtocontents{toc}{Document Revision History} - -\chapter*{Document Revision History} -\addcontentsline{toc}{chapter}{Document Revision History} - -\section*{History} -\begin{tabular}{|l|c|l|p{10cm}|} - \hline - \rowcolor{Gray} - \textbf{Revision} & \textbf{Date} & \textbf{By} & \textbf{Description} \\ - \hline - 0 & November 2012 & JDC & First draft of this specification\\ - \hline - 1.0 & November 2012 & JDC & Added sections ``Acknowledgement'' and ``Performance and resource usage'' as well as different fonts for \textit{variables} and \verb|signal_names|\\ - \hline - 1.1 & November 2012 & GO & Added this ``Document Revision History''. Made several small changes in layout and formulation.\\ - \hline -\end{tabular}% - -\section*{Author info} - -\begin{itemize} -\item[GO:] Geoffrey Ottoy\\DraMCo research group\\\url{geoffrey.ottoy@kahosl.be} -\item[JDC:] Jonas De Craene\\KAHO Sint-Lieven\\\url{JonasDC@opencores.org} -\end{itemize} \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/pictures/pipeline_operation.pdf =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/pictures/pipeline_operation.pdf (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/pictures/pipeline_operation.pdf (nonexistent) @@ -1,1182 +0,0 @@ -%PDF-1.5 -%µµµµ -1 0 obj -<>>> -endobj -2 0 obj -<> -endobj -3 0 obj -<>/Pattern<>/Font<>/ProcSet[/PDF/Text/ImageB/ImageC/ImageI] >>/MediaBox[ 0 0 258 279] /Contents 4 0 R/Group<>/Tabs/S/StructParents 0>> -endobj -4 0 obj -<> -stream -xœÝ]M$¹q½0ÿ¡Ž+Áª%3™™L@ÐA_† - 0 ø`ø°^Kk Ý è°¾#â½àGuUVVÍbº«ç°Û$3ÈÈ`ð%#Á:|ýûÃÏþõï~õ/¿>„_üâðË_ÿêðõ?šßÿýã‡pÌ!¾ÿø!.ëqŽ‡!®Ç¼žkÅ0—|ˆË|L£”æã:Ii8Nƒ—¾“‡ç|œKë<áYP²„ŽíYVLxØ(ã€QÐ/Jú,‡õfòÊŽcyø>~øÓO?~ø«’µü=¿þúŠ§E,o÷³p ö/.‡aYõņ)ÛŸOø3èíc/*ø°ôöï?=üðñƒhÂÜhÂ?üpˆ‡=Èþrx'Jñéã‡?P-òQE0Äãñ:¬˜ŽÃ ´é¸®RÊÇq•R<†ì%cq9ƹ4Ï#©—¬g{qÁà ã g”ì…0°7ƒ)’v<×ÏÜb3÷õï¿ýÇ?þø·ßýýðõï×Ãß¿û Izi9ˆpæeôÿýíX)ÐY¦øbÖ߇˜dÞ¿ùݯ‡#ð—߈Ü~áõßá›?}ü° ²\ÂaQ>×c˜¤ï|\¥í¹vP° *±¯ÂO¾ùËÇ¿ùæÌ0ÃeœD.¢§kV=}.C0-Ódïd¦ä­¦xf/©Ò‚‡Ñœ)JìÙfEÂà ŽÇzfIÆÀ¥™\‚´ã¹GÚŽÃç7ÃáMRýbÐúnf¿Bê4ëBÐóÜTÈ–&{ê [à' *^2'<ÌæƒÔKÖ³=lqñ°‘ÆuÀÃÖ3KöB#F3˜rÒŽç*4ÀÔk¶N‡¸SßtÎ!éØ iƒœ¢g² âºçéäL—‘s\ŽA‘Þ4ù¹Vd(ó8Ú[䤛ƒ8ÿSßWö ö$Ú†O‚Ž%tk³bÄà ] þ§>É!½ü®ã¶ÇÌÊÛóÛà­¯xºE´_;~þ+jŽ“.Ý´@^^‘e é`{¶<é6ÊFjš½dü%<Ë戇’ôkϲ"áYPÊƪök{ŒŠFgt»{s"`ᨠ Ò½ùÀ||ÁœÃÊéý³1ËRµÂHÑ1yÎ"'ϯÊU_ñt‹,¿¼Mþp~j„ÇiÑýD53ã,›œäffœ“Á*A”ª™YšaG’”%ôܘ™Ò¥= Ò)àaôŒRcf²Ù¹iÇó`\{#\3çÄ^#üá¥s×M#\•i¼ãÆ9íšQP|l­°Q€<+L')Â\ŸÆ6šY¤ó’uÛXacÀà  üÏÆ -ó6²ºŽÛ—V8Xy~¼õO·ˆöË[á;ÿ/¬ðq>Kkl¦pŒ¹X›i4ä¥UˆRcmz3ìI’²„žsSº´‡A:¬x=£Ôœlv.AÚñ¼6‡Ø›â2XwÁæ;‘Î9ØŒqÓ …’ê=¸¹qîC£¦®¯€þÓâÚ ¹T—Œ)¶ÒÎ"¥—ÊÊñ -¬Prq°ßºv8¬7“%PvŸµÈ+|¾þúŠ§Eüå-òÇV…y -VpµÓ$ÐB¬@Aû‘Í´-IÊR -¯Àj')‘€=W àÀÞL.AÚñ¼FÇÞ,ߣïD:gaôÂóm6`tãˆvPÓÒkq9¦\ì5ùØéw€¶J½ÆfÚd$õ’õܘlaÅà -3ÆAÏ(5†›7ƒ)’v<Ÿ5ÖÁÐó›áð&©~ySýÑgÿ…å.bk›jäÉPlSÙ ÛÆ$JmêÍ0>Iê%ë¹±McÄà - FÏ(5¶)›)v<ïÁΩ·Üõ<{OHÒ»‘ÎYì¼p&DÓ=úÁ½;7…` ­‚ñò)¨¦Û*0¯U°£Öõ8ªÇYl,þYM7oƒmæt,¡Ûjºe -Knºe -ƒEÈ?«éVÚŒ§ë¸}aº“•ç·Á[_ñt‹h¿¸éþÀójº¯²SnŒS -;™‡bœ† ûU7!QjŒSo6ëÓIYBÏÕ8Í‚crã4ÏòpôžYªÆ©7ƒ)'íxÞƒ›KgºgŤ}aGïD:gqóÂL÷5G!¿77N„hýÔ =3òŽáÈŒÊc´r -ÚC,3[æLJšg5fÏ+x{1y´×jÈí5o& ì8>gº7›o¿›$úå"áÿCX:ü§þûðNÔàÔlob½† ¶fð!c±kl"CµÙÌ0n’z©Ä&Ò0e€! -SÒ0­±‰4L½¦(I;ž÷@h --ró¯m@üÉä¿iaú_¢Ÿ$y8°7“Kv<Ÿ³¯›D ·Áa_ñt£˜_ ߉nœZßM¢‹W […áÙÌdaxvMtax¶7# ›¤^*‰.¬`¶ -I™Éžk¢ f3™"iÇócg}_KÚ€Àw"­ 8„›€9V0쾆ÄÑTæè)b3½H$e©FÌyâÞHʘ8ö\Cæ8°7“Kv<Ÿu1ÖèÉ·Áa_ñt£˜_^7^8 kÔ +ûGGÃé«Qƒt“y3\h d¡F -z¢ÿH‰À@ö[¢9*AÐuìîA¿“Ô+á”WÑï‘u øü0ÜÍ…Ç - -h£™ÁH7Z!56 -[i¾(ÿ¬qp^¨6že{ÉÃàü´Ú0$èXMBÙÛà°¯xºQ̯ ¯§ØäR±‚ Qž -Šd)Ï-¹TžHÊf[µNÊRÍ¥B…'DÔ“¥Ðs“K…½L9iÇóìïÖº–iv^Z— pí-ÞFÍYA]…Íáz “¤Qs3X¼¶ŒS²Tµ®ªFéZŒ~%Ç°¥ÙXrÊŽãso€o¿¾âéFñÛ\\N­Þf³‚ËÐÍ),Q·¶Ê -vc Í0Ôœ”¥º‚Qáˤ¾DÑs³‚1pi6¦œ´ãyÞM±³zoȬ}'ÒùtîBÿ°u›Ë•ÌÚñrfí/gÖŠ¬s }®zd§W Lå,/ð†£rÔ’ Ñš#åÏzÔç8»#ê±Ožöq¼WC®¡ª“=rv\=¿*W}ÅÓ-²ü‚`ù¨^ñ1&$•KVðÔ1F \ã‰dMi{^F<ËÖ€gAÉR=¯ô -:’”’è¸WrX¶: ì8ÞƒŽ<ÿ¯RšÇ«‡» -:¾ ÙœÅÆá<6†IÍæ+­nÜà?ŽW±±zÓ½>qj/ýåÔìêM§Ö{3VI½TÜ鬠Sœ¤t˜³çêOçÀl&S$íx> •õXåmpx“T¿

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-trailer -<<44FF30064230A347AE87A647C4B72CFD>] /Prev 176998/XRefStm 176572>> -startxref -178836 -%%EOF \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/operation.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/operation.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/operation.tex (nonexistent) @@ -1,122 +0,0 @@ -\chapter{Operation} - -\section{Pipeline operation} -The operation of the pipeline is shown in Figure~\ref{fig:pipeline_op}. One can see that the stages are started -every 2 clock cycles ($\tau_{c}$ is the core clock period). This is needed because the least significant bit of the next -stage result is needed. Every stage has to run $n$ (the width of the operands) times for the multiplication to be complete. - -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=7cm]{pictures/pipeline_operation.pdf} -\caption{Pipeline operation: Each circle represents an active stage. The number indicates how much times that stage - has run. Dotted line contours indicate the stage is inactive.} -\label{fig:pipeline_op} -\end{figure} - -For performing one Montgomery multiplication using this core, the total computation time $T_m$ for an $n$-bit operand -with a $k$-stage pipeline is given by~(\ref{eq:Tmult}). -\begin{align}\label{eq:Tmult} -T_{m} = \left[k + 2(n - 1)\right] \tau_c -\end{align} -\newpage -\section{Modular Simultaneous exponentiation operations} -Exponentiations are calculated with Algorithm~\ref{alg:mme} which uses the Montgomery multiplier as the main computation -step. It uses the principle of a square-and-multiply algorithm to calculate an exponentiation with 2 bases. -\begin{algorithm}[H] % enter the algorithm environment -\caption{Montgomery simultaneous exponentiation} % give the algorithm a caption -\label{alg:mme} % and a label for \ref{} commands later in the document -\algnewcommand\algorithmicdownto{\textbf{downto}} -\algrenewtext{For}[3]% -{\algorithmicfor\ #1 $\gets$ #2 \algorithmicdownto\ #3 \algorithmicdo} -\algnewcommand\algorithmicswitch{\textbf{switch}} -\algrenewtext{While}[2]% -{\algorithmicswitch\ #1, #2} -\algnewcommand\algorithmicinput{\textbf{Input:}} -\algnewcommand\Input{\item[\algorithmicinput]} -\algnewcommand\algorithmicoutput{\textbf{Output:}} -\algnewcommand\Output{\item[\algorithmicoutput]} -\footnotesize -\begin{algorithmic}[1] % enter the algorithmic environment -\Input $g_{0},\:g_{1},\:e_{0}=(e_{0_{t-1}} \cdots e_{0_{0}})_{2},\:e_{1}=(e_{0_{t-1}} \cdots e_{0_{0}})_{2},\:R^{2}\bmod m,\:m$ -\Output $g_{0}^{e_{0}} \cdot g_{1}^{e_{1}} \bmod m$ -\State $\tilde{g}_{0} := \text{Mont}(g_{0}, R^{2}),\:\tilde{g}_{1} := \text{Mont}(g_{1}, R^{2}),\:\tilde{g}_{01} := \text{Mont}(\tilde{g}_{0}, \tilde{g}_{1})$ -\State $a := \text{Mont}(R^{2}, 1)$ -\Comment This is the same as $a := R \bmod m$. -\For{$i$}{$(t-1)$}{0} -\State $a := \text{Mont}(a, a)$ -\While{$e_{1_{i}}$}{$e_{0_{i}}$} % use as switch statement -\State $0,\:1:\;a := \text{Mont}(a, \tilde{g}_{0})$ -\State $1,\:0:\;a := \text{Mont}(a, \tilde{g}_{1})$ -\State $1,\:1:\;a := \text{Mont}(a, \tilde{g}_{01})$ -\EndWhile -\EndFor -\State $a := \text{Mont}(a, 1)$ -\State \Return{$a$} -\end{algorithmic} -\end{algorithm} -It can be seen that the algorithm requires $R^{2}\bmod m$ which is $2^{2n}\bmod m$. We assume $R^2 \bmod m$ can be -provided or pre-computed. The for loop in the algorithm is executed by the control logic of the core. Apart from this, -a few pre- and one post-calculations have to be performed. - -The computation time for an exponentiation depends on the number of zero's in the exponents, from -Algorithm~\ref{alg:mme} one can see that if both exponent bits are zero at a time, no multiplication has to be -performed. Thus reducing the total time. The average computation time for a modular simultaneous exponentiation, with -$n$-bit base operands and $t$-bit exponents is given by~(\ref{eq:Tsime}). -\begin{align}\label{eq:Tsime} -T_{se} = \frac{7}{4} t \cdot T_{m} = \frac{7}{4}t \cdot [k + 2(n - 1)] \tau_c -\end{align} - -For single base exponentiations, i.e. 1 exponent is equal to zero, the average exponentiation time is given by~(\ref{eq:Texp}). -\begin{align}\label{eq:Texp} -T_{e} = \frac{3}{2} t \cdot T_{m} = \frac{3}{2}t \cdot [k + 2(n - 1)] \tau_c -\end{align} - -The formulas~(\ref{eq:Tsime}) and~(\ref{eq:Texp}) given here are only the theoretical average time for an exponentiation, -excluding the pre- and post-computations. - - -\section{Core operation steps} -The core can operate in 2 modes, multiplication or exponentiation mode. The steps required to do one of these actions -are described here. -\subsection{Single Montgomery multiplication} -The following steps are needed for a single Montgomery multiplication: -\begin{enumerate} - \item load the modulus to the RAM using the 32 bit bus - \item load the desired $x$ and $y$ operands into any 2 locations of the operand RAM using the 32 bit bus. - \item select the correct input operands for the multiplier using \verb|x_sel_single| and \verb|y_sel_single| - \item select the result destination operand using \verb|result_dest_op| - \item set \verb|exp/m| = `0' to select multiplication mode - \item set \verb|p_sel| to choose which pipeline part you will use - \item generate a start pulse for the core - \item wait until interrupt is received and read out result in selected operand -\end{enumerate} - -\textbf{Note:} this computation gives a result \( r = x \cdot y \cdot R^{-1} \bmod m\). If the actual product of $x$ and $y$ is -desired, a final Montgomery multiplication of the result with $R^{2}$ is needed. - -\subsection{Modular simultaneous exponentiation} -The core requires $\tilde{g}_{0}$, $\tilde{g}_{0}$, $\tilde{g}_{01}$ and $a$ to be loaded into the correct operand -spaces before starting the exponentiation. These parameters are calculated using single Montgomery multiplications as follows: -\begin{align*} - \tilde{g}_{0} &= Mont(g_{0}, R^{2}) &\,&= g_{0} \cdot R \bmod m & \hspace{3cm}\text{in operand 0}\hspace{4cm}\\ - \tilde{g}_{1} &= Mont(g_{1}, R^{2}) &\,&= g_{1} \cdot R \bmod m & \hspace{3cm}\text{in operand 1}\hspace{4cm}\\ - \tilde{g}_{01} &= Mont(\tilde{g}_{0}, \tilde{g}_{1}) &\,&= g_{0} \cdot g_{1} \cdot R \bmod m & \hspace{3cm}\text{in operand 2}\hspace{4cm}\\ - a &= Mont(R^{2}, 1) &\,&= R \bmod m &\hspace{3cm}\text{in operand 3}\hspace{4cm} -\end{align*} -When the exponentiation is done, a final multiplication has to be started by the software to multiply $a$ with 1. -The steps needed for a full simultaneous exponentiation are: - - -\begin{enumerate} - \item load the modulus to the RAM using the 32 bit bus - \item load the desired $g_0$, $g_1$ operands and \(R^{2} \bmod m\) into the operand RAM using the 32 bit bus. - \item set \verb|p_sel| to choose which pipeline part you will use - \item compute $\tilde{g}_{0}$ by using a single Montgomery multiplication of $g_{0}$ with $R^{2}$ and place the result $\tilde{g}_{0}$ in operand 0. - \item compute $\tilde{g}_{1}$ by using a single Montgomery multiplication of $g_{1}$ with $R^{2}$ and place the result $\tilde{g}_{1}$ in operand 1. - \item compute $\tilde{g}_{01}$ by using a single Montgomery multiplication of $\tilde{g}_{0}$ with $\tilde{g}_{1}$ and place the result $\tilde{g}_{01}$ in operand 2. - \item compute $a$ by using a single Montgomery multiplication of $R^{2}$ with $1$ and place the result $a$ in operand 3. - \item set the core in exponentiation mode ($exp/m$='1') - \item generate a start pulse for the core - \item wait until interrupt is received - \item perform the post-computation using a single Montgomery multiplication of $a$(in operand 3) with 1 and read out result -\end{enumerate} \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/introduction.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/introduction.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/introduction.tex (nonexistent) @@ -1,18 +0,0 @@ -\chapter{Introduction} -The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations -in embedded systems. It is able to compute a double exponentiation as given by~(\ref{eq:mse}) -\begin{align}\label{eq:mse} -g_{0}^{e_0} \cdot g_{1}^{e_1} \bmod m -\end{align} -where: -\begin{align} - g_{0} &= \left(g_{0_{n-1}}, \cdots, g_{0_{1}}, g_{0_{0}}\right)_{2}\hspace{1.5cm} \text{with } n \text{ being the number of bits of the base operands}\nonumber \\ - g_{1} &= \left(g_{1_{n-1}}, \cdots, g_{1_{1}}, g_{1_{0}}\right)_{2}\nonumber \\ - m &=\left(m_{n-1}, \cdots, m_{1}, m_{0}\right)_{2}\nonumber \\ - e_{0} &=\left(e_{0_{t-1}}, \cdots, e_{0_{1}}, e_{0_{0}}\right)_{2}\hspace{1.5cm} \text{with } t \text{ being the number of bits of the exponents}\nonumber \\ - e_{1} &=\left(e_{1_{t-1}}, \cdots, e_{1_{1}}, e_{1_{0}}\right)_{2}\nonumber -\end{align} -This operation is commonly used in anonymous credential and authentication cryptosystems like DSA \footnote{FIPS-186-3, the third and current revision to the official DSA specification:\\\hspace*{1cm}\url{http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf}}, Idemix \footnote{IBM Idemix project website: \url{https://www.zurich.ibm.com/security/idemix/}}, etc.. For this reason the core is designed with the use of large base operands in mind ($n$=512, 1024, 1536 bit and more..). The hardware is optimized for these -simultaneous exponentiations, but also supports single base exponentiations and single Montgomery multiplications. -Flexibility is offered to the user by providing the possibility to split the multiplier pipeline into 2 smaller parts, so that in total -3 different base operand lengths can be supported. The length of the exponents can be chosen freely\footnote{The controlling software is responsible for loading in the desired number of exponent bits into the core's exponent FIFO} \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/performance.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/performance.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/performance.tex (nonexistent) @@ -1,100 +0,0 @@ -\chapter{Performance and resource usage} - -This Modular Simultaneous Exponentiation IP core is designed to speed up modular simultaneous exponentiations on embedded systems. -On embedded processors, software implementations (even with specialized libraries like GMP\footnote{GNU Multiple Precision Arithmetic Library -- Project website: \url{http://gmplib.org/}}), demand much CPU time when large operands are used. -Practical tests of this core have shown a significant speed-up compared to software computations. For $n=1536$ and $t=1024$, hardware is about 70 times faster than a GMP-based implementation (with embedded linux) an a 100 MHz MicroBlaze processor (32-bit).\\ - -For the multiplier, execution time is given by~(\ref{eq:Tmult}), where $\tau_c$ is defined by the core operating -frequency. Since the maximum frequency is highly influenced by the latency in the critical path, we can expect to -achieve higher frequencies for shorter stage lengths. This trend is seen in Figure~\ref{fig:Virtex6exctime} for -different operand lengths, which are results used from the static timing analysis during synthesis. A minimum execution -time in this graph is found when the maximum operating frequency of the core first reaches the maximum frequency of the -FGPA in use. Beyond that point, using a smaller stage width has no positive effect anymore because the frequency can not -rise anymore and the number of clock cycles to complete a multiplication increases. Another remark that can be made is -that splitting the pipeline, has no considerable effect on the performance of the core. - -\begin{figure}[H] -\centering -\includegraphics[trim=2cm 2cm 2cm 2cm, width=16cm]{pictures/Virtex6_stagewidth.pdf} -\caption{Example of multiplication execution time in function of the stage width for a Virtex6 FPGA.} -\label{fig:Virtex6exctime} -\end{figure} - -In general, shorter stage lengths result in smaller execution times. However, using more stages implies that more -flip-flops will be needed, thus more resources are used. A balance must be found between a execution time and resources. -Currently, the core's operating frequency is the same as the bus frequency of the embedded processor. For optimal -operation of the core, the stage width must be chosen so that the maximum frequency given in synthesis is just above or -equal to the bus frequency. - -In the tables below resource usage and timing results are shown for different operand lengths and FPGA's. As a rule of thumb, the number of flip-flops is given by~(\ref{eq:ff}). -\begin{align}\label{eq:ff} -5+2\cdot n+6\cdot\frac{n}{s}+\lceil\log_{2}(n)\rceil+\lceil\log_{2}(\frac{n}{s})\rceil -\end{align} -where $s$ is the stage width. - -The number of LUTs is almost completely determined by $n$ and the number of LUT-inputs. A pre-synthesis estimate can be made with~(\ref{eq:lut4}) and~(\ref{eq:lut6}). -\begin{align} -8\cdot n \hspace{1cm}\text{for 4-input LUTs} \label{eq:lut4}\\ -6\cdot n \hspace{1cm}\text{for 6-input LUTs} \label{eq:lut6} -\end{align} -\newline - -Results for a Virtex 6 device xc6vlx240t-1ff1156, speedgrade -1\\ -Synthesis settings: Optimization: area, Effort: high\\ -% Table generated by Excel2LaTeX from sheet 'Virtex 6' -\begin{tabular}{rcccccccccccc} -\hline -\hline -$n$ & \multicolumn{3}{c}{512} & & \multicolumn{3}{c}{1024} & & \multicolumn{3}{c}{2048} & [bit] \bigstrut[t]\\ -$stage width$ & 64 & 16 & 4 & & 64 & 16 & 4 & & 64 & 16 & 4 & [bit] \bigstrut[b]\\ -\hline -$f_{max}$ & 64,91 & 199,96 & 395,57 & & 64,91 & 199,66 & 358,62 & & 94,91 & 199,96 & 358,62 & [MHz] \bigstrut[t]\\ -$T_m@f_{max}$ & 15,87 & 5,27 & 2,91 & & 31,77 & 10,55 & 9,63 & & 63,57 & 21,11 & 12,84 & [$\mu$s] \\ -$cycles$ & 1030 & 1054 & 1150 & & 2062 & 2110 & 3454 & & 4126 & 4222 & 4606 & [cycles] \\ -\textbf{Resources} & & & & & & & & & & & & \\ -Flipflops & 1089 & 1235 & 1813 & & 2163 & 2453 & 5401 & & 4309 & 4887 & 7193 & \\ -LUT's & 3094 & 3096 & 3102 & & 6169 & 6171 & 9252 & & 12315 & 12318 & 12324 & \bigstrut[b]\\ -\hline -\hline -\end{tabular}% -\vspace{1cm} -\newline -Results for a Spartan 3 device xc3s1000-5fg320, speedgrade -5\\ -Synthesis settings: Optimization: area, Effort: high\\ -% Table generated by Excel2LaTeX from sheet 'Spartan 3' -\begin{tabular}{rccccccccc} -\hline -\hline -$n$ & \multicolumn{3}{c}{256} & & \multicolumn{4}{c}{512} & [bit] \bigstrut[t]\\ -$stage width$ & 32 & 8 & 2 & & 64 & 32 & 8 & 2 & [bit] \bigstrut[b]\\ -\hline -$f_max$ & 21,49 & 69,30 & 127,32 & & 11,36 & 21,49 & 69,30 & 127,32 & [MHz] \bigstrut[t]\\ -$T_m@f_{max}$ & 24,1 & 7,82 & 5,01 & & 90,7 & 48,29 & 15,67 & 10,04 & [$\mu$s] \\ -$cycles$ & 518 & 542 & 638 & & 1030 & 1038 & 1086 & 1278 & [cycles] \\ -\textbf{Resources} & & & & & & & & & \\ -Flipflops & 576 & 722 & 1300 & & 1089 & 1138 & 1428 & 2582 & \\ -LUT's & 2072 & 2074 & 2079 & & 4124 & 4126 & 4128 & 4135 & \bigstrut[b]\\ -\hline -\hline -\end{tabular}% -\vspace{1cm} -\newline -Results for a Virtex 4 device xc4vlx200-11ff1513, speedgrade -11\\ -Synthesis settings: Optimization: area, Effort: high\\ -% Table generated by Excel2LaTeX from sheet 'Virtex 4' -\begin{tabular}{rcccccccccc} -\hline -\hline -$n$ & \multicolumn{4}{c}{512} & & \multicolumn{4}{c}{1024} & [bit] \bigstrut[t]\\ -$stage width$ & 64 & 32 & 8 & 2 & & 128 & 32 & 8 & 2 & [bit] \bigstrut[b]\\ -\hline -$f_{max}$ & 22,83 & 43,05 & 138,31 & 246,98 & & 11,77 & 43,05 & 138,31 & 246,98 & [MHz] \bigstrut[t]\\ -$T_m@f_{max}$ & 45,12 & 24,11 & 7,85 & 5,17 & & 87,5 & 24,5 & 8,31 & 6,21 & [$\mu$s] \\ -$cycles$ & 1030 & 1038 & 1086 & 1278 & & 1030 & 1054 & 1150 & 1534 & [cycles] \\ -\textbf{Resources} & & & & & & & & & & \\ -Flipflops & 1089 & 1138 & 1428 & 2582 & & 2114 & 2260 & 2838 & 5144 & \\ -LUT's & 4124 & 4126 & 4128 & 4135 & & 8225 & 8230 & 8234 & 8238 & \bigstrut[b]\\ -\hline -\hline -\end{tabular}% - Index: mod_sim_exp/branches/newRAMstyle/doc/src/architecture.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/architecture.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/architecture.tex (nonexistent) @@ -1,179 +0,0 @@ -\chapter{Architecture} - -\section{Block diagram} -The architecture for the full IP core is shown in the Figure~\ref{blockdiagram}. It consists of 2 major parts, the actual -exponentiation core (\verb|mod_sim_exp_core| entity) with a bus interface wrapped around it. In the following sections these -different blocks are described in detail.\\ -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/block_diagram.pdf} -\caption{Block diagram of the Modular Simultaneous Exponentiation IP core} -\label{blockdiagram} -\end{figure} -\newpage - -\section{Exponentiation core} -The exponentiation core (\verb|mod_sim_exp_core| entity) is the top level of the modular simultaneous exponentiation -core. It is made up by 4 main blocks (Figure~\ref{msec_structure}):\\ - -\begin{itemize} - \item a pipelined Montgomery multiplier as the main processing unit - \item RAM to store the operands and the modulus - \item a FIFO to store the exponents - \item a control unit which controls the multiplier for the exponentiation and multiplication operations -\end{itemize} - -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=10cm]{pictures/mod_sim_exp_core.pdf} -\cprotect\caption{\verb|mod_sim_exp_core| structure} -\label{msec_structure} -\end{figure} - -\subsection{Multiplier} -The kernel of this design is a pipelined Montgomery multiplier. A Montgomery multiplication\cite{MontModMul} allows efficient implementation of a -modular multiplication without explicitly carrying out the classical modular reduction step. Right-shift operations ensure that the length of the (intermediate) results does not exceed $n+1$ bits. The result of a Montgomery multiplication is given by~(\ref{eq:mont}): -\begin{align}\label{eq:mont} -r = x \cdot y \cdot R^{-1} \bmod m \hspace{1.5cm}\text{with } R = 2^{n} -\end{align} -For the structure of the multiplier, the work of \textit{Nedjah and Mourelle}\cite{NedMour} is used as a basis. They show that for large operands ($>$512 bits) the $time\times area$ product is minimal when a systolic implementation is used. This construction is composed of cells that each compute a bit of the (intermediate) result. - -Because a fully unrolled two-dimensional systolic implementation would require too many resources, a systolic array (one-dimensional) implementation is chosen. This implies that the intermediate results are fed back to the same same array of cells through a register. A shift register will shift-in a bit of the $x$ operand for every step in the calculation (figure~\ref{mult_structure}). When multiplication is completed, a final check is made to ensure the result is smaller than the modulus. If not, a final reduction with $m$ is necessary. - -\textbf{Note:} For this implementation the modulus $m$ has to be uneven to obtain a correct result. However, we can assume that for cryptographic applications, this is the case. - - -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/mult_structure.pdf} -\caption{Multiplier structure. For clarification the $my$ adder and reduction logic are depicted separately, whereas in practice they are internal parts of the stages. (See Figure~\ref{stage_structure})} -\label{mult_structure} -\end{figure} - -\subsubsection{Stage and pipeline structure} -The Montgomery algorithm uses a series of additions and right shifts to obtain the desired result. The main disadvantage is the carry propagation in the adder, and therefore a pipelined version is used. The length of the operands ($n$) and the number of pipeline stages can be chosen before synthesis. The user has the option to split the pipeline into 2 smaller parts so there are 3 operand lengths available during runtime\footnote{e.g. a total pipeline length of 1536 bit split into a part of 512 bit and a part of 1024 bit}. - -The stages and first and last cell logic design are presented in Figure~\ref{stage_structure}. Each stage takes in a part of the modulus $m$ and $y$ operand and for each step of the multiplication, a bit of the $x$ operand is fed to the pipeline (together with the generated $q$ signal), starting with the Least Significant Bit. The systolic array cells need the modulus $m$, the operand $y$ and the sum $m+y$ as an input. The result from the cells is latched into a register, and then passed back to the systolic cells for the next bit of $x$. During this pass the right shift operation is -implemented. Each stage thus needs the least significant bit from the next stage to calculate the next step. Final reduction logic is also present in the stages for when the multiplication is complete. - -An example of the standard pipeline structure is presented in Figure~\ref{pipeline_structure}. It is constructed using stages with a predefined width. The first cell logic processes the first bit of the $m$ and $y$ operand and generates the $q$ signal. The last cell logic finishes the reduction and selects the correct result. For operation of this pipeline, it is clear that each stage can only compute a step every 2 clock cycles. This is because the stages rely on the result of the next stage. - -In Figure~\ref{pipeline_structure_split} an example pipeline design is drawn for a split pipeline. All multiplexers on -this figure are controlled by the pipeline select signal (\verb|p_sel|). During runtime the user can choose which part -of the pipeline is used, the lower or higher part or the full pipeline. - -\newpage -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=25cm, angle=90]{pictures/sys_stage.pdf} -\caption{Pipeline stage and first and last cell logic} -\label{stage_structure} -\end{figure} -\newpage - -\newpage -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=25cm, angle=90]{pictures/sys_pipeline_notsplit.pdf} -\caption{Example of the pipeline structure (3 stages)} -\label{pipeline_structure} -\end{figure} -\newpage - -\newpage -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=22cm, angle=90]{pictures/sys_pipeline.pdf} -\caption{Example of a split pipeline (1+2 stages)} -\label{pipeline_structure_split} -\end{figure} -\newpage - - -\subsection{Operand RAM and exponent FIFO} -In the core's RAM there is space for 4 operands and 1 modulus. Currently this is instantiated using Xilinx BRAM -primitives, so there is a fixed RAM of 4x1536 bit for the operands + 1536 bit for the modulus available. If using a split -pipeline, it is important that operands for the higher part of the pipeline are loaded into the RAM with preceding -zero's for the lower bits of the pipeline. To store the exponents there is a FIFO of 32 bit wide and 512 deep (also a -Xilinx primitive, FIFO18E1), so it is able to store 2 exponents of each 8192 bit long. Every 32 bit entry has to be -pushed in as 16 bit of $e_0$ for the lower part [15:0] and 16 bit of $e_1$ for the higher part [31:16]. Starting -with the least significant word and ending with the most significant word of the exponents. - -\subsection{Control unit} -The control unit loads in the operands and has full control over the multiplier. For single multiplications, it latches in -the $x$ operand, then places the $y$ operand on the bus and starts the multiplier. In case of an exponentiation, the FIFO is -emptied while the necessary single multiplications are performed. When the computation is done, the ready signal is -asserted to notify the system. - -\newpage -\subsection{IO ports and memory map} -The \verb|mod_sim_exp_core| IO ports\\ -\newline -% Table generated by Excel2LaTeX -\begin{tabular}{|l|c|c|p{8cm}|} -\hline -\rowcolor{Gray} -\textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \bigstrut\\ -\hline -\verb|clk| & 1 & in & core clock input \bigstrut\\ -\hline -\verb|reset| & 1 & in & reset signal (active high) resets the pipeline, fifo and control logic \bigstrut\\ -\hline -\multicolumn{4}{|l|}{\textbf{\textit{operand memory interface}}} \bigstrut\\ -\hline -\verb|rw_address| & 9 & in & operand memory read/write address (structure descibed below) \bigstrut\\ -\hline -\verb|data_out| & 32 & out & operand data out (0 is lsb) \bigstrut\\ -\hline -\verb|data_in| & 32 & in & operand data in (0 is lsb) \bigstrut\\ -\hline -\verb|write_enable| & 1 & in & write enable signal, latches \verb|data_in| to operand RAM \bigstrut\\ -\hline -\verb|collision| & 1 & out & collision output, asserts on a write error \bigstrut\\ -\hline -\multicolumn{4}{|l|}{\textbf{\textit{exponent FIFO interface}}} \bigstrut\\ -\hline -\verb|fifo_din| & 32 & in & FIFO data in, bits [31:16] for $e_1$ operand and bits [15:0] for $e_0$ operand \bigstrut\\ -\hline -\verb|fifo_push| & 1 & in & push \verb|fifo_din| into the FIFO \bigstrut\\ -\hline -\verb|fifo_nopush| & 1 & out & flag to indicate if there was an error pushing the word to the FIFO \bigstrut\\ -\hline -\verb|fifo_full| & 1 & out & flag to indicate the FIFO is full \bigstrut\\ -\hline -\multicolumn{4}{|l|}{\textbf{\textit{control signals}}} \bigstrut\\ -\hline -\verb|x_sel_single| & 2 & in & selection for x operand source during single multiplication \bigstrut\\ -\hline -\verb|y_sel_single| & 2 & in & selection for y operand source during single multiplication \bigstrut\\ -\hline -\verb|dest_op_single| & 2 & in & selection for the result destination operand for single multiplication \bigstrut\\ -\hline -\verb|p_sel| & 2 & in & specifies which pipeline part to use for exponentiation / multiplication. \bigstrut[t]\\ - & & & ``01'' : use lower pipeline part \\ - & & & ``10'' : use higher pipeline part \\ - & & & ``11'' : use full pipeline \bigstrut[b]\\ -\hline -\verb|exp_m| & 1 & in & core operation mode. ``0'' for single multiplications and ``1'' for exponentiations \bigstrut\\ -\hline -\verb|start| & 1 & in & start the calculation for current mode \bigstrut\\ -\hline -\verb|ready| & 1 & out & indicates the multiplication/exponentiation is done \bigstrut\\ -\hline -\verb|calc_time| & 1 & out & is high during a multiplication, indicator for used calculation time \bigstrut\\ -\hline -\end{tabular}% -\newpage -The following figure describes the structure of the Operand RAM memory, for every operand there is a space of 2048 bits -reserved.\\ -\begin{figure}[H] -\centering -\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/msec_memory.pdf} -\caption{RAM structure of the exponentiation core} -\label{RAM_structure} -\end{figure} - -\section{Bus interface} -The bus interface implements the register necessary for the control unit inputs to the \verb|mod_sim_exp_core| entity. -It also maps the memory to the required bus and connects the interrupt signals. The embedded processor then has full control -over the core. \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp_style.sty =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp_style.sty (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp_style.sty (nonexistent) @@ -1,139 +0,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% This syntax file is intended for students of the % -% KaHo St. Lieven writing their master thesis. % -% We hope they can use it as a helping hand in writing % -% their thesis. % -% % -% This package will take care of the formatting of the % -% document. When all student used this syntax (or % -% another), we can come to an universal thesis format % -% which adds to the professionalism of our university % -% documents % -% % -% Syntax originally written by Filip Van Rysselberghe % -% Adapted for KaHo St. Lieven by Bart Blanckaert % -% minor correction: "Katholieke Hogeschool Sint-Lieven" % -% instead of "KaHo Sint-Lieven Hogeschool" necessary % -% for official publication, by Karel Van den Steen % -% % -% Modified by Koen Vangheluwe based on PhD stylefile of RUG % -% minor corrections by Jannes Verstichel and Tom Hamelinckx % -% Last modified: 17/05/2011 v0.92 % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\makeatletter - -% fancyheadings -\usepackage{fancyhdr} -\pagestyle{fancy} -\renewcommand{\chaptermark}[1]{\markboth{\thechapter\ #1}{}} -\renewcommand{\sectionmark}[1]{\markright{\thesection\ #1}} -\fancyhf{} -%\fancyhead[RE,LO]{\scriptsize\bfseries\sffamily\rightmark} -\fancyhead[LO,RE]{\scriptsize\bfseries\sffamily\leftmark} % hoofdstuk titel -\fancyhead[RO,LE]{\scriptsize\bfseries\sffamily\thetitle\space-- \version} % document naam -\fancyfoot[RO,LE]{\scriptsize\bfseries\sffamily\thepage} % pagina nummer -\fancyfoot[LO,RE]{\scriptsize\bfseries\sffamily\dramco} % dramco, kaho, kul -%\fancyfoot[C]{\scriptsize\bfseries\sffamily\thetitle -- \version} -\renewcommand{\headrulewidth}{.8pt} -\renewcommand{\footrulewidth}{.8pt} -\fancypagestyle{plain}{ - \fancyhf{} - \fancyfoot[RO,LE]{\scriptsize\bfseries\sffamily\thepage} - \fancyfoot[LO,RE]{\scriptsize\bfseries\sffamily\dramco} - \renewcommand{\headrulewidth}{0pt} - \renewcommand{\footrulewidth}{.8pt} -} - -% Koen Vangheluwe 29/05/2009: toegevoegd om "\headheight is too small" warning te voorkomen -\setlength{\headheight}{14pt} - -% Koen Vangheluwe 16/03/2010: toegevoegd wegens voor witte pagina's met empty style bij het gebruik van twoside en report -\def\cleardoublepage{\clearpage\if@twoside \ifodd\c@page\else - \hbox{} - \thispagestyle{empty} - \newpage - \if@twocolumn\hbox{}\newpage\fi\fi\fi} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% We'll head off with the definitions of the new commands % -% as promotor, copromotor, etc % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\promotorA[#1]#2{\gdef\@promotorAtype{#1}\gdef\@promotorAname{#2}} -\def\authorEmail#1{\gdef\@authorEmail{#1}} -\def\hwDesigner#1{\gdef\@hwDesigner{#1}} -\def\hwCoDesigner#1{\gdef\@hwCoDesigner{#1}} -\def\company#1{\gdef\@company{#1}} - -\newcommand{\footstar}[1]{$^*$ \footnotetext{$^*$#1}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% Secondly we declare and fill in the newly created variables % -% Sometimes we use standard definitions as is the case for % -% the titles. % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\@title{} -\def\@author{} -\def\@authorEmail{} - -\def\@hwDesigner{} -\def\@hwCoDesigner{} -\def\@company{} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% This function formats the titlepage using the % -% variables set before. % -% Variables used: % -% - dept % -% - title % -% - author % -% - degree % -% % -% When one of those wasn't specified in the tex-file % -% you will end up with an incomplete and non uniform % -% titlepage % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\titlep{% - \thispagestyle{empty} - \includegraphics[width=8cm]{pictures/opencores.jpg} - \hfill - \vspace{7cm} - \begin{center} - \bf{\Huge\textsf{\@title}} - \end{center} - \vfill - \vspace{7cm} - \includegraphics[width=\textwidth]{pictures/logos.jpg} - \cleardoublepage -} - -% Indentation -\setlength{\parindent}{0pt} -%\setlength{\parskip}{1ex plus 0.5ex minus 0.25ex} -\setlength{\abovedisplayskip}{12pt plus 3pt} -\setlength{\belowdisplayskip}{12pt plus 3pt} -\setlength{\abovedisplayshortskip}{12pt plus 3pt} -\setlength{\belowdisplayshortskip}{12pt plus 3pt} - -%\parskip 1mm - -%%%%%%%%%%%%%%%%%%%%%%%%&&&&&&&&&&&%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% BeforePreface adds the titlepage and when you % -% turned on the acknowledgements page, it will be generated too % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\preface{ - - - \pagenumbering{roman} - \titlep - - \input{acknowl} - \tableofcontents - - \cleardoublepage - \pagenumbering{arabic} -} - -% Start with pagestyle{headings} in case front matter isn't processed -\pagenumbering{arabic} -\makeatother \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/license.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/license.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/license.tex (nonexistent) @@ -1,15 +0,0 @@ -\chapter*{License} -Copyright (C) 2011 DraMCo research group and OPENCORES.ORG \\This project may be used and distributed without restriction -provided that the copyright statement is not removed from the files and that any derivative work contains the original -copyright notice and the associated disclaimer.\\ - -This project is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later -version.\\ - -This project is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more -details.\\ - -You should have received a copy of the GNU Lesser General Public License along with this source; if not, download it -from http://www.opencores.org/lgpl.shtml \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp.tex =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp.tex (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/mod_sim_exp.tex (nonexistent) @@ -1,63 +0,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% % -% LaTeX, Modular Simultaneous Exponentiation core documentation % -% % -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\documentclass[11pt,a4paper,twoside]{report} - -\usepackage[a4paper,left=2.5cm, right=2cm, top=2cm, bottom=2cm]{geometry} -\usepackage{graphicx} -\usepackage[latin1]{inputenc} -\usepackage{listings} % for showing source code -\usepackage{verbatim} -\usepackage{hyperref} -\usepackage{url} -\usepackage[small,bf,hang]{caption} -\usepackage{pslatex} -\usepackage{bigstrut} -\usepackage{color, colortbl} -\usepackage[bottom]{footmisc} % to place footnotes at the bottom - -\usepackage{algorithm} % for pseudocode -\usepackage{algorithmicx} -\usepackage[noend]{algpseudocode} -\usepackage[fleqn]{amsmath} - -\usepackage{cprotect} % for verb in caption - -\usepackage{sectsty} % adjust fonts from sections and captions -\allsectionsfont{\sffamily} -\chapterfont{\raggedright\sffamily} - -\usepackage{float} % ex. \begin{figure}[H] - -\newcommand{\tab}{\hspace*{2em}} -\newcommand{\version}{v1.1} -\newcommand{\dramco}{DraMCo research group -- KAHO Sint-Lieven\\Association KU Leuven} -\newcommand{\thetitle}{Modular Simultaneous Exponentiation\\IP Core Specification} - -\usepackage{mod_sim_exp_style} -\definecolor{Gray}{gray}{0.9} -\bibliographystyle{ieeetr} - -\title{\thetitle} -\author{Jonas De Craene} -\authorEmail{JonasDC@opencores.org} -\hwDesigner{Geoffrey Ottoy, DraMCo research group} -\hwCoDesigner{Jonas De Craene} -\company{DraMCo research group, \href{mailto:info@dramco.org}{info@dramco.org}} - -\begin{document} - -\preface -\raggedbottom -\input{introduction} -\input{architecture} -\input{operation} -\input{plb_interface} -\input{performance} - -\bibliography{cited} - -\input{license} -\end{document} Index: mod_sim_exp/branches/newRAMstyle/doc/src/cited.bib =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/cited.bib (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/cited.bib (nonexistent) @@ -1,31 +0,0 @@ -@article{MontModMul, - author = {Peter L. Montgomery }, - title = {Modular Multiplication Without Trail Division}, - year = {1985}, - journal = {Mathematics of Computation}, - volume = {44}, - number = {170}, - pages = {519-521} -} - -@article{NedMour, - author = {Nedjah N. de Macedo Mourelle L.}, - title = {Three Hardware Architectures for the Binary Modular Exponentiation: Sequential, Parallel, and Systolic}, - journal = {IEEE Transactions on Circuits and Systems - I: Regular Papers}, - volume = {53}, - number = {3}, - pages = {627-633}, - year = {2006} -} - -@misc{XilinxPLB, - author = {Xilinx}, - title = {PLBV46 SLAVE SINGLE (v1.01a) DS561}, - howpublished = {\url{http://www.xilinx.com/support/documentation/ip_documentation/plbv46_slave_single.pdf}} -} - -@misc{XilinxIntr, - author = {Xilinx}, - title = {Interrupt Control (v2.01a) DS516}, - howpublished = {\url{http://www.xilinx.com/support/documentation/ip_documentation/interrupt_control.pdf}} -} Index: mod_sim_exp/branches/newRAMstyle/doc/src/tables.xlsx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mod_sim_exp/branches/newRAMstyle/doc/src/tables.xlsx =================================================================== --- mod_sim_exp/branches/newRAMstyle/doc/src/tables.xlsx (revision 67) +++ mod_sim_exp/branches/newRAMstyle/doc/src/tables.xlsx (nonexistent)
mod_sim_exp/branches/newRAMstyle/doc/src/tables.xlsx Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mod_sim_exp/branches/newRAMstyle/sim/Makefile =================================================================== --- mod_sim_exp/branches/newRAMstyle/sim/Makefile (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sim/Makefile (nonexistent) @@ -1,71 +0,0 @@ -#VCOM = /usr/local/bin/vcom -VCOMOPS = -explicit -check_synthesis -2002 -quiet -#MAKEFLAGS = --silent -HDL_DIR = ../rtl/vhdl/ - - -## -# avs_aes hdl files -## -CORE_SRC =$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \ - $(HDL_DIR)/core/adder_block.vhd \ - $(HDL_DIR)/core/autorun_cntrl.vhd \ - $(HDL_DIR)/core/cell_1b_adder.vhd \ - $(HDL_DIR)/core/cell_1b_mux.vhd \ - $(HDL_DIR)/core/cell_1b.vhd \ - $(HDL_DIR)/core/counter_sync.vhd \ - $(HDL_DIR)/core/d_flip_flop.vhd \ - $(HDL_DIR)/core/fifo_primitive.vhd \ - $(HDL_DIR)/core/modulus_ram.vhd \ - $(HDL_DIR)/core/mont_ctrl.vhd \ - $(HDL_DIR)/core/mod_sim_exp_core.vhd \ - $(HDL_DIR)/core/operand_dp.vhd \ - $(HDL_DIR)/core/operand_mem.vhd \ - $(HDL_DIR)/core/operand_ram.vhd \ - $(HDL_DIR)/core/operands_sp.vhd \ - $(HDL_DIR)/core/register_1b.vhd \ - $(HDL_DIR)/core/register_n.vhd \ - $(HDL_DIR)/core/standard_cell_block.vhd \ - $(HDL_DIR)/core/stepping_logic.vhd \ - $(HDL_DIR)/core/x_shift_reg.vhd \ - $(HDL_DIR)/core/sys_stage.vhd \ - $(HDL_DIR)/core/sys_last_cell_logic.vhd \ - $(HDL_DIR)/core/sys_first_cell_logic.vhd \ - $(HDL_DIR)/core/sys_pipeline.vhd \ - $(HDL_DIR)/core/mont_multiplier.vhd \ - - -## -# Testbench HDL file -## -TB_SRC_DIR = ../bench/vhdl/ -TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd - -####################################### -all: mod_sim_exp - -clean: - rm -rf *_lib - -mod_sim_exp_lib: - vlib mod_sim_exp - -work_lib: - vlib work - -libs: mod_sim_exp work_lib - -mod_sim_exp_com: mod_sim_exp_lib - #echo -- - #echo building Modular Exponentiation Core - #echo -- - vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) - -mod_sim_exp_tb: work_lib - #echo -- - #echo building Modular Exponentiation Core Testbench - #echo -- - vcom $(VCOMOPS) -work work $(TB_SRC) - -mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb - vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb Index: mod_sim_exp/branches/newRAMstyle/sim/mod_sim_exp.do =================================================================== --- mod_sim_exp/branches/newRAMstyle/sim/mod_sim_exp.do (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sim/mod_sim_exp.do (nonexistent) @@ -1,2 +0,0 @@ -nolog -all -run -all \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/sim/out =================================================================== --- mod_sim_exp/branches/newRAMstyle/sim/out (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sim/out (nonexistent)
mod_sim_exp/branches/newRAMstyle/sim/out Property changes : Deleted: svn:ignore ## -1 +0,0 ## -sim_output.txt Index: mod_sim_exp/branches/newRAMstyle/sim/src/sim_input.txt =================================================================== --- mod_sim_exp/branches/newRAMstyle/sim/src/sim_input.txt (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sim/src/sim_input.txt (nonexistent) @@ -1,86 +0,0 @@ --- input generator program --- generates test values per bit input pair --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -512 -128 -24975b1d37a43bd7f7dfd3273f5ec1a26fcc9d7df3c448f4c9ff6408bc35a26f6897875b2213ac6a6ccfc061ce46d6df12ec86f376377b51c9b4feccafbb8f3d -d81ddf249fc542fecf52269df27e64bf995a026b71ff631d3dfa8c84a14ebef82079ff92946188eba0c2a04b54c1f324c073081f38380719ab64359dddcb8266 -f42b1776c84acd0e9983b2ede9391126 -b9671c7bbce53881ac1112b0b83be497 -f628fd05af868a7d066aed834cdb9d9e3a3a5b60ded9799b40fa0edbbcc80b1808182f5eaeb77735213231178f3637cea7b9b0b7da170b8903bb7f28f0e8393d -40dc9d887efb51275cd5a25c7921d9a9d176ecc55506b71db0e0dc7b92433274d6f6c29301ac0bf68a9cd96f7eb018797b714465c544f4c7c62fa2c3779da899 -09d702fa50797582f995127cb3246261c5c5a49f21268664bf05f1244337f4e7f7e7d0a1514888cadecdcee870c9c83158464f4825e8f476fc4480d70f17c6c3 -52dcefc28c657903548086a23e868781fdd34c6b49c6d32031423b4a478a5889ffb983d434f11a9c18e83dd0dad3d82547cb28f3f04de8188cc07e98aff33df0 -6af4590e9c711a276abb98454796629f4ff290f5b3eb76db0f527243b5b187a5e1e868d649b618820ec0f6a94d3c25b8d3daca641544a70087b440e325e6407d -9e75604d7e2fa8586421372e59e3bc2ec4c6cb7d26a58cb14cd9e6818b8b68b02b41d3a9099acfe2ac85423216611152b32b6105499a15c81e20bf9cbdf200e8 -7ac5af5644c929b02d301a14890bd3e19a6d469e69b12b603b975ab4dbaaf8d8bc31c82a69a3f1ce08d4711df4ad9e558a6e5519f2244378ca6a70ed753add30 --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -512 -32 -de0bbade38204e63359a46e672a8d0a2fd5300692ab48f9ef732f5c3fa212b90c98229bbb79bece734a622154c904dce9a0f53d4a88b3e558ef7612f6694ce75 -2e5d3fea7d9d0d33ac553eecd5c3f27a310115d283e49377820195c8e67781b6f112a625b14b747fa4cc13d06eba0917246c775f5c732865701ae9349ea8729c -64150a6d -8593f0d7 -18f204fe6846aeb6f58174d57a3372363c0d9fcfaa3dc18b1eff7e89bf7678636580d17dd84a873b14b9c0e1680bbdc87647f3c382902d2f58d2754b39bca875 -098eb081ecfa53f3f90e7dbf1e10b6e29ee45d6b02bff85403b335c0c6d5e1ab6eec5d670afb95713ed15f9723e5faedd6a42d95effafa771cb0c72d3a73c905 -068bce0fed3d2cda68f16fa939fd89e1a777c1e359967090ca050e9e855f4c1e08f7d1158d16b7b130be7731ef8a962b61307a5ce65e3c2687c76b0fbea16b6e -14026cdda1794a94d7fa3cc76c69f6e43b5da0597c4040c6eb5cf65f677cac9bd85b08af0c998241ed365decd2d1cf2a62ccb6138a409224f7f03184d2cd77b5 -047d6c7653eca32d15971be88eba38526fea6bbb9f991ad6c8d9ede11bb11dc888444923c5732d57d31a4aeea397179007927ba14cfdd1078664dcbbfcc3aaf4 -00a84956047b71ed15148f0fc4be161c3fe4fe03650dff8e239982c0ebbbdbfbea2087f0c2f725a023e1e568e56e980e36524cbc29190b698bcb62534aa47c3b -0ae33423c12184905fb44e34ae955ac5a502c9983910135ae22ae1f477c7e4532cf1134dde48ccc4126124f91085d64d6106c503b6e71b0ce5333d679b0f016f --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -1024 -16 -895f783fab56a353b58a8c4316eacf3012c77e6fbfdb4be7ed3cd27fc1c72a98f7733050ae2a4bd8c2b356f3f81de6f56258f69355b9321117b905723db3fe533ff94c12502b145c53e61608834634eae18e60c5b991b9f8d71b2d971cbe5ac9e09f4814addab421efdcc2870d2c92c87003fcff55ccba1d4f22f5ab90950fb0 -2a46626cf17c40bc08e57582f9852ad12cf0ee16f2440678d35a31147278a27658a66182b41c8327a559d058a9e9df5a55fe9eeccd16fd651c2d7f13a9942e7418052b4ae1b98f8ca3f3e828532a453289bd47b363738f866debf04222abeecac1e11f980b6f115f097f4540aa7735b993f17f55083caeb6a80f80d092c59d2f -7c1f -5eb8 -20f8be80ba9b4c7ca011f74c2d41581f0036d233b5e8e58b6dd5ca6db0625d764b927a43fe78844090c6843f29a331b76f8ece93e7e313eccb9bcb6ed2330923899aae43a0fd2430cb6772793755e74862e61e2ac376cfab9d61827e646421b28e9e0e2aca4625731aebbb69ea37e0fa859e499b8a186c8ee6196954170eb807 -06412c26297124ba58188bc306fa67d5e2349d33c677cb3701084ab808780e2d89f5d0b912e4866f37f4fec043a08c1991c2ef1a4d9f81b6bd6e8449cf2dfa510a0417db84ec15bea71c17b483852b918137926002c232d2adfd304c7a1beef79b83544bc405d714a10e1b2ed02e33cfbf25b0dffdda16e76d92e84d778dcc27 -1932ca7ae5c0e8979f823ceac3369726fe80409606a1b92fff2777002d4f71c3eefea8240ab4623c0a926245dc89a3fbf31859f4a8ca74866ebd6ff8409ac0073cc53c26991402aa702bdeaf7ca6ad054bb52cd4a7c0524eb2556e8b4143141e19ad9cd47814f9da438de01a9878d92658abfcbf39550817b54e1eb35e98f7cf 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-1324646bfb0bad60a82843ae9b47e64d4fb298550061b01755aed16ba0448afc9cac7557640de2e8eda59e5c9e29483ed5181d997d9f73e8edcfd671a724cc1f2ec976ed97b392148d8f1156f0cb4cab35a2b378c7a63b539daa0588260aa6fb2ab3f8ad497c96305a0fa081ee6ab4bb7067d3ea85c6455bf6f9af37deb38eb3 --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -1536 -16 -b2c5bdfaf2ba8f23d35f13f9f77a1b8efd364518248b0ab2010d3260a3445f5a0a8aa4198b0c3207d3458a2e1539a16f8d4ae39b8913a951884085dcf22f2fb08291d7363204e5335e697f7398a9eceb1cafbcd348517674f15bbcbea90537ca2c8e6364d67421f29b9ae1c2e5f17872c08b122dd36a9965916287d08d8e2ece0500d4f1e37b45e29cb056efcd1449220d602e7cf13ec97b6c4f17a7e57af9c8ec65cb9864b7a4c83290855c8ffc55bc1da64e43b9ec4e9f266dce489d14aa8c -c7a679c71dcaa96a8401dd62d7e71f68532c71819b8fe7ab721fb04b4dced1df8486000094ae3410622cd598ed3e74ab64952eee06659e1a891ccbd3702155bcbd3931224694faa89b4055c056e0aa844139fbbfe3d9b568b58387f1a955ee2e0043e5adbea47beace8589dd09bd98826db084ec7172c76b92d315d164f26c049784ed73ae654e5ca1c1d1faf227ce981b624ea7f57aab0a06b88d2b3105b957b1a19d1899b8e544f05c6de4756b8b095d2e346da3ecdb386b33fbe48f5254b1 -ed01 -611e -da67cd50b638d8454a6854741126c4a07cc716330a37576e5021ca2fd2f24b31e027c0b9bc2929f2a2a38c9d003ae5b45d153957d2d0fe1cd05a87f375d050f6341d1e83f0583276902503259190aa7b0353e99a8b404da6feabe3a3b4a54263523a3619aedffe301db8be0aa07b04b8d8c1210cbb3034856d6f46dec94cf866558439083e26bd03dc4c11a81239654b516b2f891d20d0f7fc98547fac560ab315de74e6eb71dccef15a3ac85d3daa6072603a608a1d9201d5f09ad67ed8ce95 -27d738be5b0ccb62aec64623adfec2fb3fbdc26be7040817f764250d3f8f324ac468575a3953cfa8ea853097d17b71e3ed7a81255688a155c1f84c81f8288019a364e4a267a828ab90919f1d034743f88b81aecef510ef66dc7c45971ec384c4433bd9377cf72c97af9af5b36ea8522dea929d219819bd178b910c8c54365d5071ad39c2527b64d878d3df051b0fc82c71155571f9ea89f9a16b1ec77a05d39fd6840328958da9bb19c637d3952d0b704ff176b4ce18d782030310527785f8b6 -259832af49c727bab597ab8beed93b5f8338e9ccf5c8a891afde35d02d0db4ce1fd83f4643d6d60d5d5c7362ffc51a4ba2eac6a82d2f01e32fa5780c8a2faf09cbe2e17c0fa7cd896fdafcda6e6f5584fcac166574bfb25901541c5c4b5abd9cadc5c9e6512001cfe24741f55f84fb47273edef344cfcb7a9290b92136b30799aa7bc6f7c1d942fc23b3ee57edc69ab4ae94d076e2df2f080367ab8053a9f54cea218b19148e23310ea5c537a2c2559f8d9fc59f75e26dfe2a0f65298127316b -bf4e8a2aff25f970db92a08206b2662fade7e2dee533fc585f0ebf85280f8760a45a7af38aec082a8bf07b380a3814e52b38147b7e92cde28cb7d0500bacba0e79a7d9752bc3f6b4a8ce7e9091d8f614fe8b970135d27e63f81faa587f35871abd5b3a8d4bd84e6ab717d1e49c5f92470547d4bf977a07eefcbdebe1754278afc06505e4058c099da4632614db98d9e3d7447e2a48403bd9cda0efb7fbc4e43a9e962cc9abe24f6312893a165927614519ccf6897d3f17f3d9ff5ca3abb00117 -4505cc0eb73a76e09af6c512b4b3611d7c3b3108a68ad4d08aca6ca13756e553efe6ade8c7a0ae6b5bbad04ba0a281824de0a13763c3aca96930c4f9aec2e9ed52e9f329db58ec6acc4d1a86df706f3e74b2e088f9064caef6a0074d63e726243779721517848124ea65c1ccd3e8a1471afa3f25811a577757aa2807577a7c6a77c3634813f92cdaade697cb17fa0555918d53a75e05c263e807f107437a5c4032c68f18b8ca54a61caff215debc1a0988933e6e442501a8fbc497403631d543 -51fe92e79cf87e206a6a1d6192cc670090a20ad3fcc36f13ce25fc7ca15f7c0cf5fc1f466beb949c01af87520731b63699900f0d4bbc21d2fc13b30a66fd767d76b6d391fb1418edc2e07057d9fa124c99dfe154e46f98a718a09ccfd01862ebbff0221cdfe9039851872526aee09be7efe4f1fe3d2fdf747e0ab0fce0f5062e7379e19fbe8f25647a081a90e5a8c9c28fa7a2d600c9072b139c901236ec3e04ab2e67c684348d07c0857b7d85dabe1e232eeb63675c63d6732f2bfea20dcd6b -5ed841eda3b8c955fe433d971816c55f290735fd5c60aa5c0021f441172383463e18835ff4962fcc76c9b59894a8a11c5748183a3453c9e9d3caace2834a285f326d49742b2e56ff7d1dccb91bb2f3059f6a3c509c7fb62d929b8002619bb70676b5ec0617b3d36fd2fabb2701ff9c0b94b3942673de0fe22e4d13969398f8da5563959c05328ef7767b6e4e11e4e31a3196f35919b29464e45e5a8a461bd9533a11a3bdf9c1f57ec911b496b05072f45427293234f8189d0649f8a05b91ffb5 --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -1024 -512 -0126538af61e4b9f2405432519e527626a7ea735b5459b6427ec6cba1cab45bf7aab3960e23bc7155efb1817eae0633b99b178ec507dfce68c2ce2631a625123ebe9cf0b8c142464ed1766b69d7eb5c50bc8c63238b615ebfce42d087ed87c6cb3cd7d83d561dd350f9aee914cb73edcbfcb307e1cf03ea2be449e902d3c15d5 -035eba4b3cf6071c40367c2041ef9ffac1d2c79350add0d1fdf4ee9f51a64a16c7c8f6d6413633936d759972da423643be8db98385c24d66909cea2796b8226b766f7fc5cae66d2b3f31c84c8480be3e406162450ab0af1def7fbe722db19f19a7ea88beb2e91def31de051b36bd6547b986b04b55adbd048314b61252b8a9e0 -a9f9dd3f39ec1201fcfaa04bb03fa4c349a339d12936c0eb50eb5e369b13ef6b511105b6a2b25c28c15a9cf28ba4b4feae22142bee272537ddf138c6b3e2cda6 -96c8d52f036b4737cc82a3bc596fb56ccb664c98abd4fc3f21682bf7d1f58dc7ec16c3c10da1827e071d840349c281b57f7d11c7f67432f04da27baff2beee40 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-4285a744d12f6aa1c9f4582446dd94ff628277af87556f6f17843436b0e9137289ab910d65b32e53b301bc36e0f0d5b13969e2ec3e6df758c743dfe9a55d6fabb95da94bd0a8b602fc9d8df22c66743b9e7cec51209dd8d1116f3236545bd248cf7d3e7c051776ada4dfbb49e712d96b65ee552cd4105dd28083ea55a954d063 -39524dd2f0bc2a1d467576b8993f857856fb73ee13118371d3ab937502597964a2108e33eb5bdbfc7e6b8ffefb7cd4e3e989c40ea68e3c22f6e1890317431bb98f0001383a6958534c2c9b3b0756961ce1f082747a13d603ba82a8600f27ac90fae049302cb538afa101e21f3320f5e3329f485e42bb0f72b2cbd376216f8eb9 -4ce2fb9260e27689d8f0f458f220d54e75f6d9ee6a21135c8943c285392c3b6d6cadda3304d456d43d3d54add2abd1c61da46344bf721d43f3e600d1af39849b319faeb8f3a7237c37bf7201c41916bf2dd54ba1d482195f588e06f4c482c74d264e7d3effcd375839593384a8df9baed7c6c51029dbdbee7091007e05ac2027 -0aa2585482729c69fa31c138cd8f6a92068ddae69dcc6b42d5ab3ca4a510ebb3c03c5d346a970c180bc6af7dcb92b2e08edb9088812833d47004025ab398558022f0b6cb836936a2c42b05f3c00e69f4b81e2195319b0bfeaaffedc38e16c0d3b6e2538da25b22b11b3234aec3848136ed9c4bd4bcaab9d3ffa5066678971c7d --- base_width, exp_width, g0, g1, e0, e1, m, R^2, result -1536 -1024 -b715f2aa7bbe5d63f9e346a354be5b4aaf95a52abdc71ec6ed17158105ea05eecb9ac14c45c871eba0b4806fc2c902a71a642aaa6ffd31418495b6337be786c39b309e7f2828b7a9eaf39efe24d34be63f5bedff9b3ff5c8d9b3d3abe05d899165992b3279857e6888c89e02a489690979376f05e3299360868a37fb8014494edef41c009b5f29ca0110b390d11c13574297784180be412ff866338e1e8a3a1c0f885e07b4cb38b2836dc1307ce2fc60abd9a47ca24ddfe030f470060a07f742 -96815116c690888a046c216cf843d63b0a71eb930063bbdb884d4c9efd372339bf2bef0fd77793eda3d89508c83719acd72725df7a456c5acfaa54ad27fafcf461e92981322977a38543f3af1c1cd8027e4a4f35b16e1657cfc7ed6ab932fffb0dfd75374195e5fc3f30a36b0eb2ab17c06312d850e541be4b24c664811e80cb0a8d4ed6b21f1533d55477d1b8ac8e4b25441b52f75a90c23e7c81b42da33e9f7d6a02b8c172a8341aec8222fa2f9540a64c79a0e8837c0b02c82f75aa0a529b -3d4f5df1fd0608dcdf41292cd1de964de30857a70c90e7a7eefdc466536e91d3e54f0432b0cd3dcefb8f817903498c2774bfc2d311b1d26616cfb90aa08c53e65e98b0674b1e93be44b23dc41f6c4eb5c911111ad90be093cf6d8a1ffe1c7160797d7708bcb4c28aa937b49835f12fbd95dfe180e645801fa2298d6f66797843 -f08a44e041abe9132a7ae203dea533ffe043e52ad362a7e52e690c6f6be93c7764505ff8ab421c0d07aeed189e06619b72712729e743275562fcc12a8305eb92b4243ea28343d4c2e1238afe94021cab7a0d78bbe1e875fad56837189c46d04e7efb4f72aa81b931a73b40c4c6b9d18c70882d52769649e271e724f08604a0e6 -f2a61d1861dbbab3ea6d7654fc1271b0a53a3319215334aafc6d22b8e29913f15be747ec36b7623fbf1c9c32f12a5493fe585e2d1d0fae7a653966632f7d3db993b85403fe179955cb944b2a400624da1d353599e37b40432ddd88cd8f7ff40b96f9bd9019334c935cca7a527bf1bd7d2271b1effcf8b1348948de020935779bdf8192b2c07ad6549837072505edff25ec7d1b9ea671a839c0039ab85146217a6367395890cd978cfd461fe82f3bb22f074c6c33ec4ccf395799ab830fbcc731 -7f879e0b0ef3066c64170ebedffd4fdbe9dc108c912ba300c3a28f815e65714e332c67b83f9101f9d1bfe774ef5e2ab8553b57df41d725b7472c80e6fb5c1e7d01cfecf247e1fa2f9899684aee009f2d4c9eb0a5d9ed8cc1f02e86a585550b124e9c31843d490c9d651b1033535779b0d4febf509dac2983b1aed065dc2ce4f220fa90216e292ec44c6161139c9255f5d8e6aa24018d7580db19fce33859135b8900f077c8c12945feb9c7e8f013e9aa9ba5829cee86c3f20402187a0714baf8 -0d59e2e79e24454c159289ab03ed8e4f5ac5cce6deaccb550392dd471d66ec0ea418b813c9489dc040e363cd0ed5ab6c01a7a1d2e2f051859ac6999cd082c2466c47abfc01e866aa346bb4d5bff9db25e2caca661c84bfbcd222773270800bf46906426fe6ccb36ca33585ad840e4282dd8e4e1003074ecb76b721fdf6ca8864207e6d4d3f8529ab67c8f8dafa1200da1382e461598e57c63ffc6547aeb9de859c98c6a76f32687302b9e017d0c44dd0f8b393cc13b330c6a866547cf04338cf -a24d5ff5ec90041f8585e5a3eaa80d4ae79d51c503fdc297af56a80e3bf58e733426cd856674044ff48a614486e19aac545bc5c9d4d26c7dbc82293e217afc9401e5fbe0e1f2201707524fff02516afd014c97e45d7f2ebca4995ad9d71c5d64595b3a799211ee7a00d100dde2bd668c8ebefdd33ff85dedc7ba36aad28473071f79984d691203febdc8d4cb1429c06aabd28682324869a628e58d693233293fb6b80350489dfc8262492d55b84cb58f66dd7ab085f769588c92c98577dae82a -1300e3e89ba220fb27e1d2ba33f31cd2f425f88fc232904e9636bd8bce5ab3132213ad74050662839715dc75efb6eba06b76142087de5abcf7dd7fa46c59508c2ed48ed23ce28601f85cdf3fc2bceaaa58d553c7fc5fb2b1de38baac935232d301521759c94dbb17bd2717e95fd898edf1d07119e0804fdca0bf1472f67cf24c7b3b3d05427e2215fb76b12d4541a17d151c66266735375d93290ee0dd1853bb2f0e0da52ddd5fabb78a0429eabc57dc5183698dcd0eeb7855db074adbc031c1 -61b777b3f0d965918154c110832797ac576ee410393a854f63b65e671a5ff8d7a06fcabeb78dd88ca33235d82089cc479d40f73fec8b70909511c751a96996d2fd55ccd161883739ac16a2fa3cdef00ac8a44dfb4a694903edc7cbf0bcabdb516c6739255f046799c31ad9127033e418d32c64dff6477cc7e6b9567ebfe81b91f02a88d739da6185eb436b747582936cbce1a2083a901f367d420adb95a48b5e2e94fd4a32844ca4fd11f97d521ac0c747b8f1844d5047bef01a6aba7ee4e903 -df854897557eebad8b4b05d4d0f460bd52bee45a5b0044ad3dd41ceba28f474a90c1541c8b2b456c9b0d673e75e8eff3e904ed6386764bd31b54bc3ae639bd50cae76b4925d303e85eba38a08fb867c9b350b4c465a9c5800c19378b39dc00e17bfd5e696b31c5e2eeff4b7c9811a3c15decd58bf6ecca7eafcab4a74864626516b0203434c2ca1685729e1ef74a09294b710e2168d8063f3a026f6e263b26fa6be9be46f3ea4b7ab1ec7bd85d4ffa63f54e1fdabe07b3368377387052dc55b6 Index: mod_sim_exp/branches/newRAMstyle/sim/src/sim_mult_input.txt =================================================================== --- mod_sim_exp/branches/newRAMstyle/sim/src/sim_mult_input.txt (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sim/src/sim_mult_input.txt (nonexistent) @@ -1,127 +0,0 @@ --- input generator program --- generates test values for multiplier testbench --- x, y, m, result -53e61608834634eae18e60c5b991b9f8d71b2d971cbe5ac9e09f4814addab421efdcc2870d2c92c87003fcff55ccba1d4f22f5ab90950fb020f8be80ba9b4c7ca011f74c2d41581f0036d233b5e8e58b6dd5ca6db0625d764b927a43fe78844090c6843f29a331b76f8ece93e7e313eccb9bcb6ed2330923899aae43a0fd2430cb6772793755e74862e61e2ac376cfab9d61827e646421b28e9e0e2aca4625731aebbb69ea37e0fa859e499b8a186c8ee6196954170eb8068593f0d764150a6d -281d2450fb801da066c8f6ded6b0e52a3dac5b06c9b87ab1b98b8bc3fec0305217617dcf521ba13284d317cf9387d89f668a77f5f603d7d804d7e1ebcfed747f7e9c79cb45a3c796dd21dca6446bff5f3f4f61547a8ec6dc87f70007bb0d0e871bdd6034b504ea047ccd079f45e3290616e8261439fc0a17d468b142a245de837b2a8e38517c8db806fa26b39ba0281ff318f6ca93426fe8f87fd83b57e2fb6e8613fae2a05de379028df84982dc5ef1f260ebeb9cd706d90bec6c867e73b5ae -2e5d3fea7d9d0d33ac553eecd5c3f27a310115d283e49377820195c8e67781b6f112a625b14b747fa4cc13d06eba0917246c775f5c732865701ae9349ea8729cde0bbade38204e63359a46e672a8d0a2fd5300692ab48f9ef732f5c3fa212b90c98229bbb79bece734a622154c904dce9a0f53d4a88b3e558ef7612f6694ce7518f204fe6846aeb6f58174d57a3372363c0d9fcfaa3dc18b1eff7e89bf7678636580d17dd84a873b14b9c0e1680bbdc87647f3c382902d2f58d2754b39bca875 -29140212acd8740607cfcdc1a566e44a24d122f4ce5ac6080a6b52ce0e49f2668b07a1c19b3031b6daad9222582854ec088b515a225c2b40faff6bcf4174eed2448b122f712a8aa8101cdb4e9f1d183b9aa952b7ee85f4f61013c08d4d0a091dfb099b40a482d40c6366d34563091bdf63ff7fa59de0d162e9b5fdeecec7d9b538d36b4611cb1b469bea02e78f30b612567012f8ba1f50beb9a94ed7a3cc87452830c23af7a51725512be7de0e9ef801ccc3225f59a7ad008d0d55d688b43661 --- x, y, m, result -7cc716330a37576e5021ca2fd2f24b31e027c0b9bc2929f2a2a38c9d003ae5b45d153957d2d0fe1cd05a87f375d050f6341d1e83f0583276902503259190aa7b0353e99a8b404da6feabe3a3b4a54263523a3619aedffe301db8be0aa07b04b8d8c1210cbb3034856d6f46dec94cf866558439083e26bd03dc4c11a81239654b516b2f891d20d0f7fc98547fac560ab315de74e6eb71dccef15a3ac85d3daa6072603a608a1d9201d5f09ad67ed8ce94a6b25eb8a8fc7c1f2a46626cf17c40bc -025a82b89f8df97d24457adabe8d71547932939de3798812b66fe245a8dfa10a4ad9c30f35524607492bc874c537e0919628407a494e9ec98a07900650221fed8a938fa08cfe21a9c62d0332cd7a9cc7d180f09f0dbff606e3a7e65c3eee75f76642cb165f9794632d2cb116499915da1163e396d821637a47a0f37a14f43eeb1dfcd5b9257642687b2a58c2007c748f961c1b956be83d6b2b6de70bf7de53bd069694c0943a99761d80181a46aa47fff21704dd8ddab1422641191a8afa07e6 -08e57582f9852ad12cf0ee16f2440678d35a31147278a27658a66182b41c8327a559d058a9e9df5a55fe9eeccd16fd651c2d7f13a9942e7418052b4ae1b98f8ca3f3e828532a453289bd47b363738f866debf04222abeecac1e11f980b6f115f097f4540aa7735b993f17f55083caeb6a80f80d092c59d2f895f783fab56a353b58a8c4316eacf3012c77e6fbfdb4be7ed3cd27fc1c72a98f7733050ae2a4bd8c2b356f3f81de6f56258f69355b9321117b905723db3fe533ff94c12502b145d -08e4197f1c9b38dd964a07317ec91387c7c0e6e24ec6d19b3e8f593552d524c9bc0348d8f0cc229a3ba6fe9ca8e219e3047323d5074756e783c14ff0f66e12c73cdde3123c0643c4f3301f4d25d71a1cfee87ba02789f700ffdccddf4cdc25cf5a9dd0ea926bd596a2e5b08ab2e79ac188b6d6b8b5d6a4901db97ed4a5136aac1496bbfcca283d9d8568afe79955188fbaab77cf4e222ffab441553f2b26501d569e2ed2700e3622a3c15a4f1b93bba77fff312011bc3f793b25c9e2f2935e5a --- x, y, m, result -532c71819b8fe7ab721fb04b4dced1df8486000094ae3410622cd598ed3e74ab64952eee06659e1a891ccbd3702155bcbd3931224694faa89b4055c056e0aa844139fbbfe3d9b568b58387f1a955ee2e0043e5adbea47beace8589dd09bd98826db084ec7172c76b92d315d164f26c049784ed73ae654e5ca1c1d1faf227ce981b624ea7f57aab0a06b88d2b3105b957b1a19d1899b8e544f05c6de4756b8b095d2e346da3ecdb386b33fbe48f5254b1b2c5bdfaf2ba8f23d35f13f9f77a1b8e -2edde8a2abd33709760f08338f2603ef03e9fb17a40a905fd138bd887fe192c3499881e837e30894ade6d1d9d80600afe24a43d147098f723b3a4f92d3f4c9eb0c29339d26416f9754408a8a8e7139e3cdb1be621b1c7c3cecdfb49ff5ec3f441330cd3e4c8f55ff4e7ff8746b53e2b4423a8bd6027afdeea7cae939b028f85eb9af1aa34e3dba8c0ae7f9019ffa63cbd9538b58b4b31836728fb824e3c82025aa553da6b1b36ef019d77ce842d63d0722cb99fc40d8e6b425e45c2bcf7675ee -fd364518248b0ab2010d3260a3445f5a0a8aa4198b0c3207d3458a2e1539a16f8d4ae39b8913a951884085dcf22f2fb08291d7363204e5335e697f7398a9eceb1cafbcd348517674f15bbcbea90537ca2c8e6364d67421f29b9ae1c2e5f17872c08b122dd36a9965916287d08d8e2ece0500d4f1e37b45e29cb056efcd1449220d602e7cf13ec97b6c4f17a7e57af9c8ec65cb9864b7a4c83290855c8ffc55bc1da64e43b9ec4e9f266dce489d14aa8cda67cd50b638d8454a6854741126c4a1 -dd6f908415f8bcb9abf4efb3975a5aa8c77fafcbfa6b0c6c2b8c7cc47f8e8b0dd361003322b9bf9b34ce587a58dd249b239e37034b44265b8569ece779f82d03e88eb18db6b5cfba0b7c326b7793889bf2905180180983bed767e62cb76d97633af1b64f9cb29b59af9d7c5b2e6e3869c7dad3f3d49f0d1747b54dd74f42644bbeb72031c971e136ae3e0fea8cba9b7cc79a3880a73e483e4a7f90d9a77bd00c69683d61ddef9b83a024d75a95fee0d4d3757a5d5b1db1deb108a75fba244c75 --- x, y, m, result -be449e902d3c15d582c446d9e92eecb5e5fbca71054a857fb1034b61da0412b91adef3d7f1eb2c535e06fba295d0b284b6a68ac4a863cca066972fa321e81874b531fce0066a9b0853e6c06e863235e023a604ae694e55595d939aa4522bf699278dc2d8efce5159bb4f969137483722a7a515bb500d476fab7a907cb7d58884b067254ab6c13349b9671c7bbce53881ac1112b0b83be497f42b1776c84acd0e9983b2ede9391126d81ddf249fc542fecf52269df27e64bf995a026b71ff631d -229fdaaec4289b13fe8499b8b2a273f67f9630c0663a14f4657c795ed19b9beb2d9e6ba08935f17f52e4b86d25d74a67c37c8c041ab9455f1f084d5ab9942518f0d23d3cab5bb5e9537c8f35de80edc62dd51990de636e3a9dbb6893dfa7a88e72ab334eee79ece1fcdbb083dc4df36ff39ff9a65ee028d3efac71f02c68e6477d6bcb14a88b8a4b2f284ac80d7a2d796c7c44e567266d3cc0d1b695d9d5dd566d27d3d598a40d859cafb2fd3a6a3ebbef1b936944dc3b27c411c9c4f86ca97b -3dfa8c84a14ebef82079ff92946188eba0c2a04b54c1f324c073081f38380719ab64359dddcb826624975b1d37a43bd7f7dfd3273f5ec1a26fcc9d7df3c448f4c9ff6408bc35a26f6897875b2213ac6a6ccfc061ce46d6df12ec86f376377b51c9b4feccafbb8f3df628fd05af868a7d066aed834cdb9d9e3a3a5b60ded9799b40fa0edbbcc80b1808182f5eaeb77735213231178f3637cea7b9b0b7da170b8903bb7f28f0e8393daf89611e3aa8ed01c7a679c71dcaa96a8401dd62d7e71f69 -2d2e8292b4d76354773c846e80069e3e9ffc59719410220574b52afcd94f582650725d1cfe06f1a6cccf598e7b49df4ef57cef26a12fc58a8992e9fd889535f660e66e833c12c2cb5c16fe9683dd977528cb274b6fbd17236dc1eb38190adee9fe82ab3c0a5951314130c5b34f3beb8558da09539d7fcec64c3198a8f9f94619705f2d6df75906c50ab1d34ddd5ef88fc489f426007c76232f74f2c4881aa940ee57938e39063d1459172c886e779e9d1e370a4fdfe98875420b121cba413b00 --- x, y, m, result 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-909cea2796b8226b766f7fc5cae66d2b3f31c84c8480be3e406162450ab0af1def7fbe722db19f19a7ea88beb2e91def31de051b36bd6547b986b04b55adbd048314b61252b8a9e00126538af61e4b9f2405432519e527626a7ea735b5459b6427ec6cba1cab45bf7aab3960e23bc7155efb1817eae0633b99b178ec507dfce68c2ce2631a625123ebe9cf0b8c142464ed1766b69d7eb5c50bc8c63238b615ebfce42d087ed87c6cb3cd7d83d561dd350f9aee914cb73edcbfcb307e1cf03ea3 -78a18445fc4e11957e873abacb6992d46fab8570c61e9ff9c3ad6ac42c92bcac3d289650236d07c7a78f7d92503326a2e6e57a8a1e48f493b630253c5939aec36d4200975c3ab1ec49c1edc4b9e427ec172e8d4ee41df31cb618900d5977968b5bd4bac8ea08412863f1ebee7a7f41438ee4833679af041e42ca0e5b984a16e9b2343f22b7a0edcbec37381ee72d8395072fb19b8fed08acd9215d554b2267c26a1e4932c203195e456907911714f9f309d38b5628e665befa0ec0e1477384b1 --- x, y, m, result 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-62fcc12a8305eb92b4243ea28343d4c2e1238afe94021cab7a0d78bbe1e875fad56837189c46d04e7efb4f72aa81b931a73b40c4c6b9d18c70882d52769649e271e724f08604a0e63d4f5df1fd0608dcdf41292cd1de964de30857a70c90e7a7eefdc466536e91d3e54f0432b0cd3dcefb8f817903498c2774bfc2d311b1d26616cfb90aa08c53e65e98b0674b1e93be44b23dc41f6c4eb5c911111ad90be093cf6d8a1ffe1c7160797d7708bcb4c28aa937b49835f12fbd95dfe180e645801f -7d49f655b8667eabba8b3dbd2ffadb250a934aea3c36542864b923b515bfda13a9d7316c8d64f2872211555ff3602349b6d06c1e8cadb6074eff8298b5bbdefc15f2f08740c71013d60ba03de320e1546396a334125f255d1ecee470723af91d7677f19ed2a73f0c48fb6b9d9222b2e279309707cd81350ffef57d778f136a3c50639adb752e0f58e5a809d4a8ed15d90c1273b4635b59073686f946946c5eb4210b545ed5cb6272568fb0173fa140c3189e5a851d2bcb10c7cc95811826e811 -a2298d6f6679784396815116c690888a046c216cf843d63b0a71eb930063bbdb884d4c9efd372339bf2bef0fd77793eda3d89508c83719acd72725df7a456c5acfaa54ad27fafcf461e92981322977a38543f3af1c1cd8027e4a4f35b16e1657cfc7ed6ab932fffb0dfd75374195e5fc3f30a36b0eb2ab17c06312d850e541be4b24c664811e80cb0a8d4ed6b21f1533d55477d1b8ac8e4b25441b52f75a90c23e7c81b42da33e9f7d6a02b8c172a8341aec8222fa2f9540a64c79a0e8837c0b -9e13514fe5fa670bd744b7ef3a6102b2ea1601cf80298a48f62c9a78b3f40d5ace7e2857bf2df8a959b5a3b657850e0c36a6063f90ff4ab4d19857b29af2d7003ab7bfc320b5d95c2531a343be250768274cc5c38a0ca0e9cf4a4d8f517711e36b396546f775386e8b1db413ab000ef2fc43547bb01d28a66ecefe39a299c7d44fa5f522bb3993a1a136b02c401e3372b2f4edb65261ed59b127063661c6b7c579b7098e86b886965da6d819e319fed015a56255243a3f5cc63638621248f80d --- x, y, m, result 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-e0aa4bcb02f7e9e49692fd279e5102c63133f66ea0183ad6b5f24f2430736c0dc7486d4f2a9e0aa658eda7db3a908efbb3c1d6ed1c7f27c2034ec1ce8be9a4b8e5552e1cdc27cd78e0864371d9802cbeae36857fcd296922528a1966f8b32e32ae5557a5a9002b4ad763bb7bf50e05e31e0a98e500e5f43a59dbc6c76c8f8330805e4ee38ee9349ff08a44e041abe9132a7ae203dea533ffe043e52ad362a7e52e690c6f6be93c7764505ff8ab421c0d07aeed189e06619b72712729e7432755 -3f36c162be0f06570f2c74aeeb584f45a12f95b691fb605858229ed42879cf13fdcc9375ce0ca60135aeef1181ee14c88ff489f27f89a5ff30bfb2c922f47c59e7e6e9bec588e8b0be70e05aaa71f38a714d996aa8909d065288b22b2742807059add3ec0a0a7911297d72eb5c970414a26a4aab789169fd694d185d91f8fca4ed59f821146d47b9e423189199432e42e6f40e6bc79eced5e622aaeafdcbcc285b6156f7e9263bc6b06313124fc4d27241401f8a55c412a4cb1d63da683576e5 --- x, y, m, result -5ab045b42aa62e2b430a692d385849d0084e7a8e11ece2225c3cb5c393988f0ec08ff29dce9d081f16c787bab4eecb2a011989dc31b2e389973d5c4b2d8fd3e13f419697bfa5ae62e0ecaf69bb443faa1d1ca7c88cc1485e0e542c16825fcac0be41bdee32dbd4c6cf4d036d760e3c5173bef4fb2b3e4b103ad8082249c14baa80e85fe0bcf8a253dd36dfd2744533a593165b021872f5ce857da213ecab759e432beeb23cae1ad0836581105496558519fa901451856d68bf52a57db2d87a34 -31a5ae819137e2b166c05c8389a2c99fcb56ba8d2bb525020175a1c3b8e70b785f0dc344e1a3302ff6c9495119f6d5e735558728c1b3eef9c1b9e7097af05ddae501ca8a4b361cf60603e6362a4e6d62b09146f7d9fed448e6054a89851a539769a48b7265b29486a4cce66927d90eec39bd6e9c64ab368300a0233ddf12f1148fb5e8ce4e2914583a38f1260b1d2614fcee30a2e997f3025c1dd9509b3cc898009c4a7223e64fcb0dd5cd6cc327fd6b0e70f0e48432f2bc673b626326efbacd -341c4c871bf58078144f57425c3fc3dfa090fbb680e17e4b161c5a459a1911775034477104b7c374bbd21d2212778155dd9ee244136816960f2464e0d10e31ba71013d0318b1dbd0b049084c00624093e85839cd58ef2c749dc35dae9cfa046f669913a5414eabc6514b1b23dc60f4a977e3aa552d45b23380bb1498c5ed431c430d4cc265a07403091e668a7511be81a6e583ed9677699b25069a079cc133ab7860c946f4c4ae7d46497d33070a9a9684a27fdaad4e4380ededa4695e681519 -264f01daaa47334f48016a2a90831dd167ec353b7d791c6c4ef2a09f999a49449ffafbc448ba444686b6427938593f8866d5c97b50517dca549052258e5250f8494e4987760e85417791efe7cd68b234e0a1f67658cce6b9e20870875aa91a6b9d5b2444e9c6b11796cc86516164539d90afc40285b0ad367bb14048f41407161eaef682de73616c935396227a5ade5d629bfb5b6c63ee0b30ee8abae1fae7742f7c47f2eb411c1d805183df5063ffb45f9053f636334ef051cdd6820338fa29 --- x, y, m, result -21038003813bf3e6331af4714f03cbe6d812169c6cfad8fc0a0b1f074ecd0943dfa26cdbe05fd38943e1d66c1249944e2ccb6009f1545995a9604c326325a28d28b2343cd8095adbeaff6317d0c9101cc8346ca25bd9f34293d3d29b312439c4bdb1fc14ef9e7aa3db6ed0af3b0bae589c2841cfd059a45a4447d17d2cedf655887063dd41e8a8bab49ab8924c1789242a4690c35a1a02db93dcda752a813cef0911302b7a344f894ec884f2403858c1d88b97248ec1b59a9caa63039d6f6c61 -3b3a623bf8dd6decfb0e14214966cded0de7406080f591e687021f9d6ef2b5e81d2a8e17644cf1e9ca7309c912490c16999f0f8d3eaf764c3a33896724f0a9c456153ea5ff1b5bce11d71d535807336acefbda25b0f2b4e551f407de7e4066d9490394b8da0454e6d629aecc5eab8d98626eb4e2425cedd37d2a8ecbfd6bb84066d6c17cd05cb5584a7b59fdc37d5db67c690a189629e526652fc5f9607d0d47f6755c4f08e3ecddb74ea59c9088bd3b522c113143181f91b39fb3c1162f543e -60f6704c35bc87d7edda8f848edf19ebe104e32a7d25b5253bfd996621284cef35766572c78c1635bb7ee7c4daf81cc17e7cc8c0c8fca8d5dd6ce8ceeb0781ab5214f2095c3ed948ff26706405d5630c79268d3496434d0562cb2045e0017dbb8fcbb11c22f14e7627703cecc970e2de91ecd3e9bc6b575ade98802aad7a30f027263655e0a0ea62cf511a8dcdc0ce5e3d7f74d7d0014f612ac2a6ad1a8a9ab3d08cda37bcd9c8bf1d7077c17e9e78cf3699995ef5dd39ab20586b55f56995c5 -28f81ba268cffc72caff7900c50a0bfe55cca904729cca38ae6b31147a989b8c45899b4b7660fea756ff0b279ed64b1b0b8a4f64215d641f9b4ead1a1d9b57bcf22620381aedf038897c9b0014130aa954bcd09bcf37954ed2bc6304cbef847521f7a3e484370e7d504fda12af5c1b2b76b25d8dcc01f3630e1bc3b0227cd78ece7b22f2205931f0b892ca27bca0c244c677a0cbe12f2333473b87588611d9d5a62b0bf225cbb25be4aa376095cb8e71d32fe6c24aac634859481f105267b8cd --- x, y, m, result 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-6d8114a306f79329139f632c98e34b03de0ca0ae677c56c623d0f0ee9ed7458d66049cc9d4ea9c310623c90f1c04c6c2fe9c0adcf6e6ebaa083c4cd3b8f7e0bf7a2245fe79b02ec78147e3275d82222141bb2da8857889646ac721582fe23999ea86b5a2c843f6674bf9cb1c6a0bd0e13ff33c19f0cbb72ff70654d2a64c460a1188a26a4beb414075682a595c90939b9ef4abcd7f8e69697d725ea3129ff79bc9008ce1a3c0c59ab56e5e6ba1b3ee5dff2e295569c1364eb8db9e703416960d -2d55dddd298f7d568cd9fb26fa9103fab71a5eeacbf736d78bbcc0ab08f158079a7ee7e15bc785ea8639458b3df09d81054673a21a7ea90360f41a53c0bf242019edf2853b8ef3323a9a43ac1fef1187b290a3c33372a869c6b78c89a7f5cfa270739c61694896d2835460cf4761cd8b946a20913d4c022dae0de139dec7a7c9b35482f4b54223583c50fe37140a6634fbf7b68e0f868b45a6b7fcae6f39fde126bead6cb16ff7666ba1dd38552a51ba6c2c4b0605eff9c73c1f1fdc670f93cf --- x, y, m, result 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-c2454aa891f5dba11ff450afcd26afc571858df2230ee7c33e86e814c52780128400e8efd60a3980557b3e95e8e6b01ce80d9a3a08faf1730d065ef1229a853be5558da54d189215b844fb02b2e27026f80c7c99d2c6404c40a2dda986050e33e926ef7c0fa60c32f92a04dc7bb706d52fbaa8d616ab8d1c139fedfcb334646bb7422dd3d2b45dc4699940c5599a8dbfcb983cae10f7202f7d62bfe612e6cc8013c743e33f50fbe3ca6fc10dc3915fd64289ab032c02ec2b22d4820b4f4fdecd -9e4bb95740d06b1a4264175651a64fbed16f8e12b6ed0741b1af8859eccac70be4f3e632b1e31590c6da5196d83e81f616b897a2929d9e62d7d2b109a0d62499463c20608e8181123f8f3d7ddfe5aca157b2fcd27efbfe32ed474244acd53c205ef9a9146eb5ac1fdcdc7d50b980117151c09d4b1af692bb309d590f4d756a6229ba0163a4585dca6a35fe2a5d1e9d65d3e458b13918eac0e5bebecfdb52dbba164d073e4e03f0ddd3f62332bc0427ee74a9f269408f03e80e7a9402299d4fad --- x, y, m, result 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-a42b9f1752ebee13497d62d013af00871e03ff635ae5b0aef7e5d8af4456f848d6563e961e96fd5d9f7d85f2d12178bc4976222dd3450480223cd8889c65c63a185a0ad0804a8d4a2b87d1056596ee174050a4ba755fc884d5b4db41cff6f2ca17f57d388f0c8439a80f0c54b5105baafec9e23f6d0a3bd25f3953ab7377a7c9a4dc693372f62b0f2980e43da3cda33af8a9cd502481f32794ef5090864bdeac1eac5efdf2c187bd2c1bb88eff32a393f4747a4c1af5565bd6a84510edfd23bd -29d118f6030a1fde0542380a2551900d03a0aab11652b14f4d47e78c0eec78e8473b20d99430bcbdb1099bd337324d3c8f9cfad40aa39e0afa395dc009453fcc6a38ec6001fd101f9363bc5281af14845a23b0024b5344f2fae5f5443ce1a4956b0f12edf95ffb650aabab6fed04444624971e5ca641dbf5f13c767ad2c8114d96031cd17c64505250e59d381e62f5b9b1fda668b2f06b162b0b660e20a1624da8ed80e29d792fe407d62d1608c227de4982a0cf544daee9e08357531cbf0110 --- x, y, m, result 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-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.231013975/append=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.231013975/appendContributed=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.725964274/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.725964274/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.725964274/append=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.725964274/appendContributed=true Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/sim.txt =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/sim.txt (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/sim.txt (nonexistent) @@ -1,7 +0,0 @@ -512 -32 -1024 -16 -1536 -16 -0 Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/ModExp.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/ModExp.exe =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/ModExp.exe (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/ModExp.exe (nonexistent)
mod_sim_exp/branches/newRAMstyle/sw/ModExp/Release/ModExp.exe Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/.project =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModExp/.project (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModExp/.project (nonexistent) @@ -1,26 +0,0 @@ - - - ModExp - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/src/ModExp.c =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModExp/src/ModExp.c (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModExp/src/ModExp.c (nonexistent) @@ -1,113 +0,0 @@ -/* - ============================================================================ - Name : ModExp.c - Author : - Version : - Copyright : Your copyright notice - Description : Hello World in C, Ansi-style - ============================================================================ - */ - -#include -#include -#include - -int main(void) { - unsigned int base_width, exp_width; - mpz_t m, g0, g1, e0, e1, R, R2, result, tmp, gt0, gt1, gt01; - gmp_randstate_t state; - - gmp_randinit_default(state); - mpz_init(m); - mpz_init(g0); - mpz_init(g1); - mpz_init(e0); - mpz_init(e1); - mpz_init(R); - mpz_init(R2); - mpz_init(result); - mpz_init(tmp); - mpz_init(gt0); - mpz_init(gt1); - mpz_init(gt01); - - printf("-- input generator program\n"); - printf("-- generates test values per bit input pair\n"); - - while (1){ - - //read in base_width - scanf("%d", &base_width); - if (base_width == 0) break; - scanf("%d", &exp_width); - - //generate modulus (must be uneven) - mpz_urandomb(m, state, base_width); - mpz_setbit(m, 0); //uneven - - //generate g0 - mpz_urandomb(g0, state, base_width); - - //generate g1 - mpz_urandomb(g1, state, base_width); - - //generate e0 - mpz_urandomb(e0, state, exp_width); - - //generate e1 - mpz_urandomb(e1, state, exp_width); - - //calculate R - mpz_set_ui(R, 2); - mpz_powm_ui(R, R, base_width, m); //R = 2^n mod m - - //calculate R2 - mpz_set_ui(R2, 2); - mpz_powm(R2, R, R2, m); //R2 = R² mod m = 2^2n mod m - - //calc precompute values - mpz_mul(gt0, g0, R); - mpz_powm_ui(gt0, gt0, 1, m); - mpz_mul(gt1, g1, R); - mpz_powm_ui(gt1, gt1, 1, m); - mpz_mul(gt01, g0, g1); - mpz_mul(gt01, gt01, R); - mpz_powm_ui(gt01, gt01, 1, m); - - //calculate result - mpz_powm(result, g0, e0, m); - mpz_powm(tmp, g1, e1, m); - mpz_mul(result, result, tmp); - mpz_powm_ui(result, result, 1, m); - - printf("-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result\n"); - printf("%d\n", base_width); - printf("%d\n", exp_width); - gmp_printf("%Zx\n", g0); - gmp_printf("%Zx\n", g1); - gmp_printf("%Zx\n", e0); - gmp_printf("%Zx\n", e1); - gmp_printf("%Zx\n", m); - gmp_printf("%Zx\n", R2); - gmp_printf("%Zx\n", R); - gmp_printf("%Zx\n", gt0); - gmp_printf("%Zx\n", gt1); - gmp_printf("%Zx\n", gt01); - gmp_printf("%Zx\n", result); - } - - mpz_clear(g0); - mpz_clear(g1); - mpz_clear(e0); - mpz_clear(e1); - mpz_clear(m); - mpz_clear(result); - mpz_clear(tmp); - mpz_clear(R); - mpz_clear(R2); - mpz_clear(gt0); - mpz_clear(gt1); - mpz_clear(gt01); - - return EXIT_SUCCESS; -} Index: mod_sim_exp/branches/newRAMstyle/sw/ModExp/.cproject =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModExp/.cproject (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModExp/.cproject (nonexistent) @@ -1,124 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/src/ModMult.c =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModMult/src/ModMult.c (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModMult/src/ModMult.c (nonexistent) @@ -1,70 +0,0 @@ -/* - ============================================================================ - Name : ModExp.c - Author : - Version : - Copyright : Your copyright notice - Description : Hello World in C, Ansi-style - ============================================================================ - */ - -#include -#include -#include - -int main(void) { - unsigned int base_width; - mpz_t x, m, r, R, R2; - gmp_randstate_t state; - - gmp_randinit_mt(state); - mpz_init(x); - mpz_init(m); - mpz_init(r); - mpz_init(R); - mpz_init(R2); - - printf("-- input generator program\n"); - printf("-- generates test values for multiplier testbench\n"); - - while (1){ - - //read in base_width - scanf("%d", &base_width); - if (base_width == 0) break; - - //generate modulus (must be uneven) - mpz_urandomb(m, state, base_width); - mpz_setbit(m, 0); //uneven - - //generate x - mpz_urandomb(x, state, base_width); - - //calculate R - mpz_set_ui(R, 2); - mpz_powm_ui(R, R, base_width, m); //R = 2^n mod m - - //calculate R2 - mpz_set_ui(R2, 2); - mpz_powm(R2, R, R2, m); //R2 = R² mod m = 2^2n mod m - - //calculate result - mpz_mul(r, x, R); - mpz_powm_ui(r, r, 1, m); - - printf("-- x, y, m, result\n"); - gmp_printf("%Zx\n", x); - gmp_printf("%Zx\n", R2); - gmp_printf("%Zx\n", m); - gmp_printf("%Zx\n", r); - } - - mpz_clear(x); - mpz_clear(R2); - mpz_clear(m); - mpz_clear(r); - mpz_clear(R); - gmp_randclear(state); - - return EXIT_SUCCESS; -} Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/.cproject =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModMult/.cproject (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModMult/.cproject (nonexistent) @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/.settings/org.eclipse.cdt.managedbuilder.core.prefs =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModMult/.settings/org.eclipse.cdt.managedbuilder.core.prefs (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModMult/.settings/org.eclipse.cdt.managedbuilder.core.prefs (nonexistent) @@ -1,21 +0,0 @@ -eclipse.preferences.version=1 -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/CPATH/delimiter=; -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/CPATH/operation=remove -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/C_INCLUDE_PATH/delimiter=; -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/C_INCLUDE_PATH/operation=remove -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/append=true -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/appendContributed=true -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/CPATH/delimiter=; -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/CPATH/operation=remove -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/C_INCLUDE_PATH/delimiter=; -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/C_INCLUDE_PATH/operation=remove -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/append=true -environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/appendContributed=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/append=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.2041168883/appendContributed=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/append=true -environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.release.2071011908/appendContributed=true Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/Release/ModMult.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/Release/ModMult.exe =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModMult/Release/ModMult.exe (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModMult/Release/ModMult.exe (nonexistent)
mod_sim_exp/branches/newRAMstyle/sw/ModMult/Release/ModMult.exe Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mod_sim_exp/branches/newRAMstyle/sw/ModMult/.project =================================================================== --- mod_sim_exp/branches/newRAMstyle/sw/ModMult/.project (revision 67) +++ mod_sim_exp/branches/newRAMstyle/sw/ModMult/.project (nonexistent) @@ -1,26 +0,0 @@ - - - ModMult - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - Index: mod_sim_exp/branches/newRAMstyle/bench/vhdl/mod_sim_exp_core_tb.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/bench/vhdl/mod_sim_exp_core_tb.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/bench/vhdl/mod_sim_exp_core_tb.vhd (nonexistent) @@ -1,701 +0,0 @@ ----------------------------------------------------------------------- ----- mod_sim_exp_core_tb ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- testbench for the modular simultaneous exponentiation ---- ----- core. Performs some exponentiations to verify the design ---- ----- Takes input parameters from sim_input.txt en writes ---- ----- result and output to sim_output.txt ---- ----- ---- ----- Dependencies: ---- ----- - multiplier_core ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -library std; -use std.textio.all; - -library ieee; -use ieee.std_logic_textio.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - -entity mod_sim_exp_core_tb is -end mod_sim_exp_core_tb; - -architecture test of mod_sim_exp_core_tb is - constant CLK_PERIOD : time := 10 ns; - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - file input : text open read_mode is "src/sim_input.txt"; - file output : text open write_mode is "out/sim_output.txt"; - - ------------------------------------------------------------------ - -- Core parameters - ------------------------------------------------------------------ - constant C_NR_BITS_TOTAL : integer := 1536; - constant C_NR_STAGES_TOTAL : integer := 96; - constant C_NR_STAGES_LOW : integer := 32; - constant C_SPLIT_PIPELINE : boolean := true; - - -- extra calculated constants - constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW; - constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW; - - ------------------------------------------------------------------ - -- Signals for multiplier core memory space - ------------------------------------------------------------------ - signal core_rw_address : std_logic_vector (8 downto 0); - signal core_data_in : std_logic_vector(31 downto 0); - signal core_fifo_din : std_logic_vector(31 downto 0); - signal core_data_out : std_logic_vector(31 downto 0); - signal core_write_enable : std_logic; - signal core_fifo_push : std_logic; - ------------------------------------------------------------------ - -- Signals for multiplier core control - ------------------------------------------------------------------ - signal core_start : std_logic; - signal core_exp_m : std_logic; - signal core_p_sel : std_logic_vector(1 downto 0); - signal core_dest_op_single : std_logic_vector(1 downto 0); - signal core_x_sel_single : std_logic_vector(1 downto 0); - signal core_y_sel_single : std_logic_vector(1 downto 0); - signal calc_time : std_logic; - ------------------------------------------------------------------ - -- Signals for multiplier core interrupt - ------------------------------------------------------------------ - signal core_fifo_full : std_logic; - signal core_fifo_nopush : std_logic; - signal core_ready : std_logic; - signal core_mem_collision : std_logic; - -begin - ------------------------------------------- --- Generate clk ------------------------------------------- -clk_process : process -begin - while (true) loop - clk <= '0'; - wait for CLK_PERIOD/2; - clk <= '1'; - wait for CLK_PERIOD/2; - end loop; -end process; - ------------------------------------------- --- Stimulus Process ------------------------------------------- -stim_proc : process - procedure waitclk(n : natural := 1) is - begin - for i in 1 to n loop - wait until rising_edge(clk); - end loop; - end waitclk; - - procedure loadOp(constant op_sel : std_logic_vector(2 downto 0); - variable op_data : std_logic_vector(2047 downto 0)) is - begin - wait until rising_edge(clk); - core_rw_address <= op_sel & "000000"; - wait until rising_edge(clk); - core_write_enable <= '1'; - for i in 0 to (1536/32)-1 loop - assert (core_mem_collision='0') - report "collision detected while writing operand!!" severity failure; - case (core_p_sel) is - when "11" => - core_data_in <= op_data(((i+1)*32)-1 downto (i*32)); - when "01" => - if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32)); - else core_data_in <= x"00000000"; end if; - when "10" => - if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32)); - else core_data_in <= x"00000000"; end if; - when others => - core_data_in <= x"00000000"; - end case; - - wait until rising_edge(clk); - core_rw_address <= core_rw_address+"000000001"; - end loop; - core_write_enable <= '0'; - wait until rising_edge(clk); - end loadOp; - - procedure readOp(constant op_sel : std_logic_vector(2 downto 0); - variable op_data : out std_logic_vector(2047 downto 0); - variable op_width : integer) is - begin - wait until rising_edge(clk); - core_dest_op_single <= op_sel(1 downto 0); - if (core_p_sel = "10") then - core_rw_address <= op_sel & "010000"; - else - core_rw_address <= op_sel & "000000"; - end if; - waitclk(2); - - for i in 0 to (op_width/32)-2 loop - op_data(((i+1)*32)-1 downto (i*32)) := core_data_out; - core_rw_address <= core_rw_address+"000000001"; - waitclk(2); - end loop; - op_data(op_width-1 downto op_width-32) := core_data_out; - wait until rising_edge(clk); - end readOp; - - function ToString(constant Timeval : time) return string is - variable StrPtr : line; - begin - write(StrPtr,Timeval); - return StrPtr.all; - end ToString; - - -- variables to read file - variable L : line; - variable Lw : line; - variable base_width : integer; - variable exponent_width : integer; - variable g0 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable g1 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable e0 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable e1 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable m : std_logic_vector(2047 downto 0) := (others=>'0'); - variable R2 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable R : std_logic_vector(2047 downto 0) := (others=>'0'); - variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0'); - variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048)); - variable result : std_logic_vector(2047 downto 0) := (others=>'0'); - variable data_read : std_logic_vector(2047 downto 0) := (others=>'0'); - variable good_value : boolean; - variable param_count : integer := 0; - - -- constants for operand selection - constant op_modulus : std_logic_vector(2 downto 0) := "100"; - constant op_0 : std_logic_vector(2 downto 0) := "000"; - constant op_1 : std_logic_vector(2 downto 0) := "001"; - constant op_2 : std_logic_vector(2 downto 0) := "010"; - constant op_3 : std_logic_vector(2 downto 0) := "011"; - - variable timer : time; -begin - -- initialisation - -- memory - core_write_enable <= '0'; - core_data_in <= x"00000000"; - core_rw_address <= "000000000"; - -- fifo - core_fifo_din <= x"00000000"; - core_fifo_push <= '0'; - -- control - core_start <= '0'; - core_exp_m <= '0'; - core_x_sel_single <= "00"; - core_y_sel_single <= "01"; - core_dest_op_single <= "01"; - core_p_sel <= "11"; - - -- Generate active high reset signal - reset <= '1'; - waitclk(100); - reset <= '0'; - waitclk(100); - - while not endfile(input) loop - readline(input, L); -- read next line - next when L(1)='-'; -- skip comment lines - -- read input values - case param_count is - when 0 => -- base width - read(L, base_width, good_value); - assert good_value report "Can not read base width" severity failure; - assert false report "Simulating exponentiation" severity note; - write(Lw, string'("----------------------------------------------")); - writeline(output, Lw); - write(Lw, string'("-- EXPONENTIATION --")); - writeline(output, Lw); - write(Lw, string'("----------------------------------------------")); - writeline(output, Lw); - write(Lw, string'("----- Variables used:")); - writeline(output, Lw); - write(Lw, string'("base width: ")); - write(Lw, base_width); - writeline(output, Lw); - case (base_width) is - when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW => - when others => - write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw); - assert false report "incompatible base width!!!" severity failure; - end case; - - when 1 => -- exponent width - read(L, exponent_width, good_value); - assert good_value report "Can not read exponent width" severity failure; - write(Lw, string'("exponent width: ")); - write(Lw, exponent_width); - writeline(output, Lw); - - when 2 => -- g0 - hread(L, g0(base_width-1 downto 0), good_value); - assert good_value report "Can not read g0! (wrong lenght?)" severity failure; - write(Lw, string'("g0: ")); - hwrite(Lw, g0(base_width-1 downto 0)); - writeline(output, Lw); - - when 3 => -- g1 - hread(L, g1(base_width-1 downto 0), good_value); - assert good_value report "Can not read g1! (wrong lenght?)" severity failure; - write(Lw, string'("g1: ")); - hwrite(Lw, g1(base_width-1 downto 0)); - writeline(output, Lw); - - when 4 => -- e0 - hread(L, e0(exponent_width-1 downto 0), good_value); - assert good_value report "Can not read e0! (wrong lenght?)" severity failure; - write(Lw, string'("e0: ")); - hwrite(Lw, e0(exponent_width-1 downto 0)); - writeline(output, Lw); - - when 5 => -- e1 - hread(L, e1(exponent_width-1 downto 0), good_value); - assert good_value report "Can not read e1! (wrong lenght?)" severity failure; - write(Lw, string'("e1: ")); - hwrite(Lw, e1(exponent_width-1 downto 0)); - writeline(output, Lw); - - when 6 => -- m - hread(L, m(base_width-1 downto 0), good_value); - assert good_value report "Can not read m! (wrong lenght?)" severity failure; - write(Lw, string'("m: ")); - hwrite(Lw, m(base_width-1 downto 0)); - writeline(output, Lw); - - when 7 => -- R^2 - hread(L, R2(base_width-1 downto 0), good_value); - assert good_value report "Can not read R2! (wrong lenght?)" severity failure; - write(Lw, string'("R2: ")); - hwrite(Lw, R2(base_width-1 downto 0)); - writeline(output, Lw); - - when 8 => -- R - hread(L, R(base_width-1 downto 0), good_value); - assert good_value report "Can not read R! (wrong lenght?)" severity failure; - - when 9 => -- gt0 - hread(L, gt0(base_width-1 downto 0), good_value); - assert good_value report "Can not read gt0! (wrong lenght?)" severity failure; - - when 10 => -- gt1 - hread(L, gt1(base_width-1 downto 0), good_value); - assert good_value report "Can not read gt1! (wrong lenght?)" severity failure; - - when 11 => -- gt01 - hread(L, gt01(base_width-1 downto 0), good_value); - assert good_value report "Can not read gt01! (wrong lenght?)" severity failure; - - -- select pipeline for all computations - ---------------------------------------- - writeline(output, Lw); - write(Lw, string'("----- Selecting pipeline: ")); - writeline(output, Lw); - case (base_width) is - when C_NR_BITS_TOTAL => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected")); - when NR_BITS_HIGH => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected")); - when NR_BITS_LOW => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected")); - when others => - write(Lw, string'(" Invallid bitwidth for design")); - assert false report "impossible basewidth!" severity failure; - end case; - writeline(output, Lw); - - writeline(output, Lw); - write(Lw, string'("----- Writing operands:")); - writeline(output, Lw); - - -- load the modulus - -------------------- - loadOp(op_modulus, m); -- visual check needed - write(Lw, string'(" m written")); - writeline(output, Lw); - - -- load g0 - ----------- - loadOp(op_0, g0); - -- verify - readOp(op_0, data_read, base_width); - if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" g0 written in operand_0")); writeline(output, Lw); - else - write(Lw, string'(" failed to write g0 to operand_0!")); writeline(output, Lw); - assert false report "Load g0 to op0 data verify failed!!" severity failure; - end if; - - -- load g1 - ----------- - loadOp(op_1, g1); - -- verify - readOp(op_1, data_read, base_width); - if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" g1 written in operand_1")); writeline(output, Lw); - else - write(Lw, string'(" failed to write g1 to operand_1!")); writeline(output, Lw); - assert false report "Load g1 to op1 data verify failed!!" severity failure; - end if; - - -- load R2 - ----------- - loadOp(op_2, R2); - -- verify - readOp(op_2, data_read, base_width); - if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" R^2 written in operand_2")); writeline(output, Lw); - else - write(Lw, string'(" failed to write R^2 to operand_2!")); writeline(output, Lw); - assert false report "Load R2 to op2 data verify failed!!" severity failure; - end if; - - -- load a=1 - ------------ - loadOp(op_3, one); - -- verify - readOp(op_3, data_read, base_width); - if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" 1 written in operand_3")); writeline(output, Lw); - else - write(Lw, string'(" failed to write 1 to operand_3!")); writeline(output, Lw); - assert false report "Load 1 to op3 data verify failed!!" severity failure; - end if; - - writeline(output, Lw); - write(Lw, string'("----- Pre-computations: ")); - writeline(output, Lw); - - -- compute gt0 - --------------- - core_x_sel_single <= "00"; -- g0 - core_y_sel_single <= "10"; -- R^2 - core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m - wait until rising_edge(clk); - timer := NOW; - core_start <= '1'; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready = '1'; - timer := NOW-timer; - waitclk(10); - readOp(op_0, data_read, base_width); - write(Lw, string'(" Computed gt0: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" Read gt0: ")); - hwrite(Lw, gt0(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD); - writeline(output, Lw); - if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw); - else - write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw); - assert false report "gt0 is incorrect!!!" severity failure; - end if; - - -- compute gt1 - --------------- - core_x_sel_single <= "01"; -- g1 - core_y_sel_single <= "10"; -- R^2 - core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m - wait until rising_edge(clk); - timer := NOW; - core_start <= '1'; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready = '1'; - timer := NOW-timer; - waitclk(10); - readOp(op_1, data_read, base_width); - write(Lw, string'(" Computed gt1: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" Read gt1: ")); - hwrite(Lw, gt1(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD); - writeline(output, Lw); - if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw); - else - write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw); - assert false report "gt1 is incorrect!!!" severity failure; - end if; - - -- compute a - ------------- - core_x_sel_single <= "10"; -- R^2 - core_y_sel_single <= "11"; -- 1 - core_dest_op_single <= "11"; -- op_3 = (R) mod m - wait until rising_edge(clk); - core_start <= '1'; - timer := NOW; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready = '1'; - timer := NOW-timer; - waitclk(10); - readOp(op_3, data_read, base_width); - write(Lw, string'(" Computed a=(R)mod m: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" Read (R)mod m: ")); - hwrite(Lw, R(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD); - writeline(output, Lw); - if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw); - else - write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw); - assert false report "(R)mod m is incorrect!!!" severity failure; - end if; - - -- compute gt01 - --------------- - core_x_sel_single <= "00"; -- gt0 - core_y_sel_single <= "01"; -- gt1 - core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m - wait until rising_edge(clk); - core_start <= '1'; - timer := NOW; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready = '1'; - timer := NOW-timer; - waitclk(10); - readOp(op_2, data_read, base_width); - write(Lw, string'(" Computed gt01: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" Read gt01: ")); - hwrite(Lw, gt01(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD); - writeline(output, Lw); - if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw); - else - write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw); - assert false report "gt01 is incorrect!!!" severity failure; - end if; - - -- load exponent fifo - ---------------------- - writeline(output, Lw); - write(Lw, string'("----- Loading exponent fifo: ")); - writeline(output, Lw); - for i in (exponent_width/16)-1 downto 0 loop - core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16)); - wait until rising_edge(clk); - core_fifo_push <= '1'; - wait until rising_edge(clk); - assert (core_fifo_full='0' and core_fifo_nopush='0') - report "Fifo error, full or nopush" severity warning; - core_fifo_push <= '0'; - wait until rising_edge(clk); - end loop; - waitclk(10); - write(Lw, string'(" => Done")); - writeline(output, Lw); - - -- start exponentiation - ------------------------ - writeline(output, Lw); - write(Lw, string'("----- Starting exponentiation: ")); - writeline(output, Lw); - core_exp_m <= '1'; - wait until rising_edge(clk); - timer := NOW; - core_start <= '1'; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready='1'; - timer := NOW-timer; - waitclk(10); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4); - writeline(output, Lw); - write(Lw, string'(" => Done")); - core_exp_m <= '0'; - writeline(output, Lw); - - -- post-computations - --------------------- - writeline(output, Lw); - write(Lw, string'("----- Post-computations: ")); - writeline(output, Lw); - -- load in 1 to operand 2 - loadOp(op_2, one); - -- verify - readOp(op_2, data_read, base_width); - if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" 1 written in operand_2")); writeline(output, Lw); - else - write(Lw, string'(" failed to write 1 to operand_2!")); writeline(output, Lw); - assert false report "Load 1 to op2 data verify failed!!" severity failure; - end if; - -- compute result - core_x_sel_single <= "11"; -- a - core_y_sel_single <= "10"; -- 1 - core_dest_op_single <= "11"; -- op_3 = (a) mod m - wait until rising_edge(clk); - timer := NOW; - core_start <= '1'; - wait until rising_edge(clk); - core_start <= '0'; - wait until core_ready = '1'; - timer := NOW-timer; - waitclk(10); - readOp(op_3, data_read, base_width); - write(Lw, string'(" Computed result: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" => calc time is ")); - write(Lw, string'(ToString(timer))); - writeline(output, Lw); - write(Lw, string'(" => expected time is ")); - write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD); - writeline(output, Lw); - - when 12 => -- check with result - hread(L, result(base_width-1 downto 0), good_value); - assert good_value report "Can not read result! (wrong lenght?)" severity failure; - writeline(output, Lw); - write(Lw, string'("----- verifying result: ")); - writeline(output, Lw); - write(Lw, string'(" Read result: ")); - hwrite(Lw, result(base_width-1 downto 0)); - writeline(output, Lw); - write(Lw, string'(" Computed result: ")); - hwrite(Lw, data_read(base_width-1 downto 0)); - writeline(output, Lw); - if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then - write(Lw, string'(" => Result is correct!")); writeline(output, Lw); - else - write(Lw, string'(" Error: result is incorrect!!!")); writeline(output, Lw); - assert false report "result is incorrect!!!" severity failure; - end if; - writeline(output, Lw); - - when others => - assert false report "undefined state!" severity failure; - end case; - - if (param_count = 12) then - param_count := 0; - else - param_count := param_count+1; - end if; - end loop; - - wait for 1 us; - assert false report "End of simulation" severity failure; - -end process; - ------------------------------------------- --- Multiplier core instance ------------------------------------------- -the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core -generic map( - C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, - C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, - C_NR_STAGES_LOW => C_NR_STAGES_LOW, - C_SPLIT_PIPELINE => C_SPLIT_PIPELINE -) -port map( - clk => clk, - reset => reset, --- operand memory interface (plb shared memory) - write_enable => core_write_enable, - data_in => core_data_in, - rw_address => core_rw_address, - data_out => core_data_out, - collision => core_mem_collision, --- op_sel fifo interface - fifo_din => core_fifo_din, - fifo_push => core_fifo_push, - fifo_full => core_fifo_full, - fifo_nopush => core_fifo_nopush, --- ctrl signals - start => core_start, - exp_m => core_exp_m, - ready => core_ready, - x_sel_single => core_x_sel_single, - y_sel_single => core_y_sel_single, - dest_op_single => core_dest_op_single, - p_sel => core_p_sel, - calc_time => calc_time -); - -end test; Index: mod_sim_exp/branches/newRAMstyle/bench/vhdl/multiplier_tb.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/bench/vhdl/multiplier_tb.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/bench/vhdl/multiplier_tb.vhd (nonexistent) @@ -1,284 +0,0 @@ ----------------------------------------------------------------------- ----- multiplier_tb ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- testbench for the Montgomery multiplier ---- ----- Performs some multiplications to verify the design ---- ----- Takes input parameters from sim_mult_input.txt and writes ---- ----- result and output to sim_mult_output.txt ---- ----- ---- ----- Dependencies: ---- ----- - mont_multiplier ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -library std; -use std.textio.all; - -library ieee; -use ieee.std_logic_textio.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - -entity multiplier_tb is -end multiplier_tb; - -architecture test of multiplier_tb is - constant CLK_PERIOD : time := 10 ns; - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - file input : text open read_mode is "src/sim_mult_input.txt"; - file output : text open write_mode is "out/sim_mult_output.txt"; - - ------------------------------------------------------------------ - -- Core parameters - ------------------------------------------------------------------ - constant NR_BITS_TOTAL : integer := 1536; - constant NR_STAGES_TOTAL : integer := 96; - constant NR_STAGES_LOW : integer := 32; - constant SPLIT_PIPELINE : boolean := true; - - -- extra calculated constants - constant NR_BITS_LOW : integer := (NR_BITS_TOTAL/NR_STAGES_TOTAL)*NR_STAGES_LOW; - constant NR_BITS_HIGH : integer := NR_BITS_TOTAL-NR_BITS_LOW; - - -- the width of the input operand for the mulitplier test - constant TEST_NR_BITS : integer := NR_BITS_LOW; - - ------------------------------------------------------------------ - -- Signals for multiplier core memory space - ------------------------------------------------------------------ - -- data busses - signal xy : std_logic_vector(NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier - signal m : std_logic_vector(NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier - signal r : std_logic_vector(NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier - - -- control signals - signal p_sel : std_logic_vector(1 downto 0); -- operand selection - signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand - signal ready : std_logic; - signal start : std_logic; - signal load_op : std_logic; - signal load_x : std_logic; - signal load_m : std_logic; - signal load_result : std_logic; -begin - ------------------------------------------- --- Generate clk ------------------------------------------- -clk_process : process -begin - while (true) loop - clk <= '0'; - wait for CLK_PERIOD/2; - clk <= '1'; - wait for CLK_PERIOD/2; - end loop; -end process; - ------------------------------------------- --- Stimulus Process ------------------------------------------- -stim_proc : process - procedure waitclk(n : natural := 1) is - begin - for i in 1 to n loop - wait until rising_edge(clk); - end loop; - end waitclk; - - function ToString(constant Timeval : time) return string is - variable StrPtr : line; - begin - write(StrPtr,Timeval); - return StrPtr.all; - end ToString; - - -- variables to read file - variable L : line; - variable Lw : line; - variable x_op : std_logic_vector((NR_BITS_TOTAL-1) downto 0) := (others=>'0'); - variable y_op : std_logic_vector((NR_BITS_TOTAL-1) downto 0) := (others=>'0'); - variable m_op : std_logic_vector((NR_BITS_TOTAL-1) downto 0) := (others=>'0'); - variable result : std_logic_vector((NR_BITS_TOTAL-1) downto 0) := (others=>'0'); - variable good_value : boolean; - variable param_count : integer := 0; - - variable timer : time; -begin - -- initialisation - xy <= (others=>'0'); - m <= (others=>'0'); - start <='0'; - reset <= '0'; - load_x <= '0'; - write(Lw, string'("----- Selecting pipeline: ")); - writeline(output, Lw); - case (TEST_NR_BITS) is - when NR_BITS_TOTAL => p_sel <= "11"; write(Lw, string'(" Full pipeline selected")); - when NR_BITS_HIGH => p_sel <= "10"; write(Lw, string'(" Upper pipeline selected")); - when NR_BITS_LOW => p_sel <= "01"; write(Lw, string'(" Lower pipeline selected")); - when others => - write(Lw, string'(" Invallid bitwidth for design")); - assert false report "impossible basewidth!" severity failure; - end case; - writeline(output, Lw); - - -- Generate active high reset signal - reset <= '1'; - waitclk(10); - reset <= '0'; - waitclk(10); - - while not endfile(input) loop - readline(input, L); -- read next line - next when L(1)='-'; -- skip comment lines - -- read input values - case param_count is - when 0 => - hread(L, x_op(TEST_NR_BITS-1 downto 0), good_value); - assert good_value report "Can not read x operand" severity failure; - assert false report "Simulating multiplication" severity note; - write(Lw, string'("----------------------------------------------")); - writeline(output, Lw); - write(Lw, string'("-- MULTIPLICATION --")); - writeline(output, Lw); - write(Lw, string'("----------------------------------------------")); - writeline(output, Lw); - write(Lw, string'("----- Variables used:")); - writeline(output, Lw); - write(Lw, string'("x: ")); - hwrite(Lw, x_op(TEST_NR_BITS-1 downto 0)); - writeline(output, Lw); - - when 1 => - hread(L, y_op(TEST_NR_BITS-1 downto 0), good_value); - assert good_value report "Can not read y operand" severity failure; - write(Lw, string'("y: ")); - hwrite(Lw, y_op(TEST_NR_BITS-1 downto 0)); - writeline(output, Lw); - - when 2 => - hread(L, m_op(TEST_NR_BITS-1 downto 0), good_value); - assert good_value report "Can not read m operand" severity failure; - write(Lw, string'("m: ")); - hwrite(Lw, m_op(TEST_NR_BITS-1 downto 0)); - writeline(output, Lw); - - -- load in x - xy <= x_op; - wait until rising_edge(clk); - load_x <='1'; - wait until rising_edge(clk); - load_x <='0'; - - -- put y and m on the bus - xy <= y_op; - m <= m_op; - wait until rising_edge(clk); - - -- start multiplication and wait for result - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - - wait until ready='1'; - wait until rising_edge(clk); - writeline(output, Lw); - write(Lw, string'(" Computed result: ")); - hwrite(Lw, r(TEST_NR_BITS-1 downto 0)); - writeline(output, Lw); - - when 3 => - hread(L, result(TEST_NR_BITS-1 downto 0), good_value); - assert good_value report "Can not read result" severity failure; - write(Lw, string'(" Read result: ")); - hwrite(Lw, result(TEST_NR_BITS-1 downto 0)); - writeline(output, Lw); - - if (r(TEST_NR_BITS-1 downto 0) = result(TEST_NR_BITS-1 downto 0)) then - write(Lw, string'(" => result is correct!")); writeline(output, Lw); - else - write(Lw, string'(" => Error: result is incorrect!!!")); writeline(output, Lw); - assert false report "result is incorrect!!!" severity error; - end if; - - when others => - assert false report "undefined state!" severity failure; - end case; - - if (param_count = 3) then - param_count := 0; - else - param_count := param_count+1; - end if; - end loop; - - wait for 1 us; - assert false report "End of simulation" severity failure; - -end process; - ------------------------------------------- --- Multiplier instance ------------------------------------------- -the_multiplier : mont_multiplier - generic map( - n => NR_BITS_TOTAL, - t => NR_STAGES_TOTAL, - tl => NR_STAGES_LOW, - split => SPLIT_PIPELINE - ) - port map( - core_clk => clk, - xy => xy, - m => m, - r => r, - start => start, - reset => reset, - p_sel => p_sel, - load_x => load_x, - ready => ready - ); - -end test; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/user_logic.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/user_logic.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/user_logic.vhd (nonexistent) @@ -1,441 +0,0 @@ ------------------------------------------------------------------------------- --- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------- --- --- *************************************************************************** --- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. ** --- ** ** --- ** Xilinx, Inc. ** --- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** --- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** --- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** --- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** --- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** --- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** --- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** --- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** --- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** --- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** --- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** --- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** --- ** FOR A PARTICULAR PURPOSE. ** --- ** ** --- *************************************************************************** --- ------------------------------------------------------------------------------- --- Filename: user_logic.vhd --- Version: 2.00.a --- Description: User logic. --- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard) --- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------- --- Naming Conventions: --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: "C_*" --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- combinatorial signals: "*_com" --- pipelined or register delay signals: "*_d#" --- counter signals: "*cnt*" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- device pins: "*_pin" --- ports: "- Names begin with Uppercase" --- processes: "*_PROCESS" --- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------- - --- DO NOT EDIT BELOW THIS LINE -------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library proc_common_v3_00_a; -use proc_common_v3_00_a.proc_common_pkg.all; - --- DO NOT EDIT ABOVE THIS LINE -------------------- - ---USER libraries added here -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - ------------------------------------------------------------------------------- --- Entity section ------------------------------------------------------------------------------- --- Definition of Generics: --- C_SLV_AWIDTH -- Slave interface address bus width --- C_SLV_DWIDTH -- Slave interface data bus width --- C_NUM_REG -- Number of software accessible registers --- C_NUM_MEM -- Number of memory spaces --- C_NUM_INTR -- Number of interrupt event --- --- Definition of Ports: --- Bus2IP_Clk -- Bus to IP clock --- Bus2IP_Reset -- Bus to IP reset --- Bus2IP_Addr -- Bus to IP address bus --- Bus2IP_CS -- Bus to IP chip select for user logic memory selection --- Bus2IP_RNW -- Bus to IP read/not write --- Bus2IP_Data -- Bus to IP data bus --- Bus2IP_BE -- Bus to IP byte enables --- Bus2IP_RdCE -- Bus to IP read chip enable --- Bus2IP_WrCE -- Bus to IP write chip enable --- IP2Bus_Data -- IP to Bus data bus --- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement --- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement --- IP2Bus_Error -- IP to Bus error response --- IP2Bus_IntrEvent -- IP to Bus interrupt event ------------------------------------------------------------------------------- - -entity user_logic is - generic - ( - -- ADD USER GENERICS BELOW THIS LINE --------------- - --USER generics added here - -- Multiplier parameters - C_NR_BITS_TOTAL : integer := 1536; - C_NR_STAGES_TOTAL : integer := 96; - C_NR_STAGES_LOW : integer := 32; - C_SPLIT_PIPELINE : boolean := true; - -- ADD USER GENERICS ABOVE THIS LINE --------------- - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol parameters, do not add to or delete - C_SLV_AWIDTH : integer := 32; - C_SLV_DWIDTH : integer := 32; - C_NUM_REG : integer := 1; - C_NUM_MEM : integer := 6; - C_NUM_INTR : integer := 1 - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - port - ( - -- ADD USER PORTS BELOW THIS LINE ------------------ - --USER ports added here - calc_time : out std_logic; - -- ctrl_sigs : out std_logic_vector( downto ); - -- ADD USER PORTS ABOVE THIS LINE ------------------ - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol ports, do not add to or delete - Bus2IP_Clk : in std_logic; - Bus2IP_Reset : in std_logic; - Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1); - Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1); - Bus2IP_RNW : in std_logic; - Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); - Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); - Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); - Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); - IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); - IP2Bus_RdAck : out std_logic; - IP2Bus_WrAck : out std_logic; - IP2Bus_Error : out std_logic; - IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1) - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - - attribute SIGIS : string; - attribute SIGIS of Bus2IP_Clk : signal is "CLK"; - attribute SIGIS of Bus2IP_Reset : signal is "RST"; - -end entity user_logic; - ------------------------------------------------------------------------------- --- Architecture section ------------------------------------------------------------------------------- - -architecture IMP of user_logic is - - --USER signal declarations added here, as needed for user logic - - ------------------------------------------------------------------ - -- Signals for multiplier core slave model s/w accessible register - ------------------------------------------------------------------ - signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); - signal slv_reg_write_sel : std_logic_vector(0 to 0); - signal slv_reg_read_sel : std_logic_vector(0 to 0); - signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); - signal slv_read_ack : std_logic; - signal slv_write_ack : std_logic; - - signal load_flags : std_logic; - - ------------------------------------------------------------------ - -- Signals for multiplier core interrupt - ------------------------------------------------------------------ - signal core_interrupt : std_logic_vector(0 to 0); - signal core_fifo_full : std_logic; - signal core_fifo_nopush : std_logic; - signal core_ready : std_logic; - signal core_mem_collision : std_logic; - - ------------------------------------------------------------------ - -- Signals for multiplier core control - ------------------------------------------------------------------ - signal core_start : std_logic; - signal core_exp_m : std_logic; - signal core_p_sel : std_logic_vector(1 downto 0); - signal core_dest_op_single : std_logic_vector(1 downto 0); - signal core_x_sel_single : std_logic_vector(1 downto 0); - signal core_y_sel_single : std_logic_vector(1 downto 0); - signal core_flags : std_logic_vector(15 downto 0); - - ------------------------------------------------------------------ - -- Signals for multiplier core memory space - ------------------------------------------------------------------ - signal mem_address : std_logic_vector(0 to 5); - signal mem_select : std_logic_vector(0 to 5); - signal mem_read_enable : std_logic; - signal mem_read_enable_dly1 : std_logic; - signal mem_read_req : std_logic; - signal mem_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); - signal mem_read_ack_dly1 : std_logic; - signal mem_read_ack : std_logic; - signal mem_write_ack : std_logic; - - signal core_rw_address : std_logic_vector (8 downto 0); - signal core_data_in : std_logic_vector(31 downto 0); - signal core_fifo_din : std_logic_vector(31 downto 0); - signal sel_mno : std_logic; - signal sel_op : std_logic_vector(1 downto 0); - signal core_data_out : std_logic_vector(31 downto 0); - signal core_write_enable : std_logic; - signal core_fifo_push : std_logic; -begin - - --USER logic implementation added here - --ctrl_sigs <= - - ------------------------------------------ - -- Example code to read/write user logic slave model s/w accessible registers - -- - -- Note: - -- The example code presented here is to show you one way of reading/writing - -- software accessible registers implemented in the user logic slave model. - -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond - -- to one software accessible register by the top level template. For example, - -- if you have four 32 bit software accessible registers in the user logic, - -- you are basically operating on the following memory mapped registers: - -- - -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register - -- "1000" C_BASEADDR + 0x0 - -- "0100" C_BASEADDR + 0x4 - -- "0010" C_BASEADDR + 0x8 - -- "0001" C_BASEADDR + 0xC - -- - ------------------------------------------ - slv_reg_write_sel <= Bus2IP_WrCE(0 to 0); - slv_reg_read_sel <= Bus2IP_RdCE(0 to 0); - slv_write_ack <= Bus2IP_WrCE(0); - slv_read_ack <= Bus2IP_RdCE(0); - - -- implement slave model software accessible register(s) - SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is - begin - if Bus2IP_Clk'event and Bus2IP_Clk = '1' then - if Bus2IP_Reset = '1' then - slv_reg0 <= (others => '0'); - elsif load_flags = '1' then - slv_reg0 <= slv_reg0(0 to 15) & core_flags; - else - case slv_reg_write_sel is - when "1" => - for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop - if ( Bus2IP_BE(byte_index) = '1' ) then - slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); - end if; - end loop; - when others => null; - end case; - end if; - end if; - - end process SLAVE_REG_WRITE_PROC; - - -- implement slave model software accessible register(s) read mux - SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is - begin - - case slv_reg_read_sel is - when "1" => slv_ip2bus_data <= slv_reg0; - when others => slv_ip2bus_data <= (others => '0'); - end case; - - end process SLAVE_REG_READ_PROC; - - ------------------------------------------ - -- Multiplier core interrupts form IP core interrupt - ------------------------------------------ - - core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush; - IP2Bus_IntrEvent <= core_interrupt; - - FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is - begin - if Bus2IP_Reset = '1' then - core_flags <= (others => '0'); - load_flags <= '0'; - elsif rising_edge(Bus2IP_Clk) then - if core_start = '1' then - core_flags <= (others => '0'); - else - if core_ready = '1' then - core_flags(15) <= '1'; - else - core_flags(15) <= core_flags(15); - end if; - if core_mem_collision = '1' then - core_flags(14) <= '1'; - else - core_flags(14) <= core_flags(14); - end if; - if core_fifo_full = '1' then - core_flags(13) <= '1'; - else - core_flags(13) <= core_flags(13); - end if; - if core_fifo_nopush = '1' then - core_flags(12) <= '1'; - else - core_flags(12) <= core_flags(12); - end if; - end if; - -- - load_flags <= core_interrupt(0); - end if; - end process FLAGS_CNTRL_PROC; - - ------------------------------------------ - -- Example code to access user logic memory region - -- - -- Note: - -- The example code presented here is to show you one way of using - -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS, - -- and Bus2IP_RNW IPIC signals are dedicated to these user logic - -- memory spaces. Each user logic memory space has its own address - -- range and is allocated one bit on the Bus2IP_CS signal to indicated - -- selection of that memory space. Typically these user logic memory - -- spaces are used to implement memory controller type cores, but it - -- can also be used in cores that need to access additional address space - -- (non C_BASEADDR based), s.t. bridges. This code snippet infers - -- 6 256x32-bit (byte accessible) single-port Block RAM by XST. - ------------------------------------------ - mem_select <= Bus2IP_CS; - mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW; - mem_read_ack <= mem_read_ack_dly1; - mem_write_ack <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW); - mem_address <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3); - - -- implement single clock wide read request - mem_read_req <= mem_read_enable and not(mem_read_enable_dly1); - BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is - begin - - if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then - if ( Bus2IP_Reset = '1' ) then - mem_read_enable_dly1 <= '0'; - - else - mem_read_enable_dly1 <= mem_read_enable; - end if; - end if; - - end process BRAM_RD_REQ_PROC; - - -- this process generates the read acknowledge 1 clock after read enable - -- is presented to the BRAM block. The BRAM block has a 1 clock delay - -- from read enable to data out. - BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is - begin - - if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then - if ( Bus2IP_Reset = '1' ) then - mem_read_ack_dly1 <= '0'; - else - mem_read_ack_dly1 <= mem_read_req; - end if; - end if; - - end process BRAM_RD_ACK_PROC; - - -- address logic - Sel_MNO <= mem_select(0); - with mem_select(1 to 4) select - Sel_Op <= "00" when "1000", - "01" when "0100", - "10" when "0010", - "11" when others; - - - core_rw_address <= Sel_MNO & Sel_Op & mem_address; - - -- data-in - core_data_in <= Bus2IP_Data; - core_fifo_din <= Bus2IP_Data; - core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW); - core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW); - -- no read mux required, we can only read from core_data_out - mem_ip2bus_data <= core_data_out; - - ------------------------------------------ - -- Map slv_reg0 bits to core control signals - ------------------------------------------ - core_start <= slv_reg0(8); - core_exp_m <= slv_reg0(9); - core_p_sel <= slv_reg0(0 to 1); - core_dest_op_single <= slv_reg0(2 to 3); - core_x_sel_single <= slv_reg0(4 to 5); - core_y_sel_single <= slv_reg0(6 to 7); - - ------------------------------------------ - -- Multiplier core instance - ------------------------------------------ - the_multiplier: mod_sim_exp_core - generic map( - C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, - C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, - C_NR_STAGES_LOW => C_NR_STAGES_LOW, - C_SPLIT_PIPELINE => C_SPLIT_PIPELINE - ) - port map( - clk => Bus2IP_Clk, - reset => Bus2IP_Reset, - -- operand memory interface (plb shared memory) - write_enable => core_write_enable, - data_in => core_data_in, - rw_address => core_rw_address, - data_out => core_data_out, - collision => core_mem_collision, - -- op_sel fifo interface - fifo_din => core_fifo_din, - fifo_push => core_fifo_push, - fifo_full => core_fifo_full, - fifo_nopush => core_fifo_nopush, - -- ctrl signals - start => core_start, - exp_m => core_exp_m, - ready => core_ready, - x_sel_single => core_x_sel_single, - y_sel_single => core_y_sel_single, - dest_op_single => core_dest_op_single, - p_sel => core_p_sel, - calc_time => calc_time - ); - - - ------------------------------------------ - -- Drive IP to Bus signals - ------------------------------------------ - IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else - mem_ip2bus_data when mem_read_ack = '1' else - (others => '0'); - - IP2Bus_WrAck <= slv_write_ack or mem_write_ack; - IP2Bus_RdAck <= slv_read_ack or mem_read_ack; - IP2Bus_Error <= '0'; - -end IMP; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mont_mult1536.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mont_mult1536.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mont_mult1536.vhd (nonexistent) @@ -1,640 +0,0 @@ ------------------------------------------------------------------------------- --- mont_mult1536.vhd - entity/architecture pair ------------------------------------------------------------------------------- --- IMPORTANT: --- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. --- --- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. --- --- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW --- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION --- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------- --- --- *************************************************************************** --- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. ** --- ** ** --- ** Xilinx, Inc. ** --- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** --- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** --- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** --- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** --- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** --- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** --- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** --- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** --- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** --- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** --- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** --- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** --- ** FOR A PARTICULAR PURPOSE. ** --- ** ** --- *************************************************************************** --- ------------------------------------------------------------------------------- --- Filename: mont_mult1536.vhd --- Version: 2.00.a --- Description: Top level design, instantiates library components and user logic. --- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard) --- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------- --- Naming Conventions: --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: "C_*" --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- combinatorial signals: "*_com" --- pipelined or register delay signals: "*_d#" --- counter signals: "*cnt*" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- device pins: "*_pin" --- ports: "- Names begin with Uppercase" --- processes: "*_PROCESS" --- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library proc_common_v3_00_a; -use proc_common_v3_00_a.proc_common_pkg.all; -use proc_common_v3_00_a.ipif_pkg.all; -use proc_common_v3_00_a.soft_reset; - -library interrupt_control_v2_01_a; -use interrupt_control_v2_01_a.interrupt_control; - -library plbv46_slave_single_v1_01_a; -use plbv46_slave_single_v1_01_a.plbv46_slave_single; - -library mod_sim_exp; -use mod_sim_exp.user_logic; - ------------------------------------------------------------------------------- --- Entity section ------------------------------------------------------------------------------- --- Definition of Generics: --- C_BASEADDR -- PLBv46 slave: base address --- C_HIGHADDR -- PLBv46 slave: high address --- C_SPLB_AWIDTH -- PLBv46 slave: address bus width --- C_SPLB_DWIDTH -- PLBv46 slave: data bus width --- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters --- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width --- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width --- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme --- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts --- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master --- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds --- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer --- C_FAMILY -- Xilinx FPGA family --- C_MEM0_BASEADDR -- User memory space 0 base address --- C_MEM0_HIGHADDR -- User memory space 0 high address --- C_MEM1_BASEADDR -- User memory space 1 base address --- C_MEM1_HIGHADDR -- User memory space 1 high address --- C_MEM2_BASEADDR -- User memory space 2 base address --- C_MEM2_HIGHADDR -- User memory space 2 high address --- C_MEM3_BASEADDR -- User memory space 3 base address --- C_MEM3_HIGHADDR -- User memory space 3 high address --- C_MEM4_BASEADDR -- User memory space 4 base address --- C_MEM4_HIGHADDR -- User memory space 4 high address --- C_MEM5_BASEADDR -- User memory space 5 base address --- C_MEM5_HIGHADDR -- User memory space 5 high address --- --- Definition of Ports: --- SPLB_Clk -- PLB main bus clock --- SPLB_Rst -- PLB main bus reset --- PLB_ABus -- PLB address bus --- PLB_UABus -- PLB upper address bus --- PLB_PAValid -- PLB primary address valid indicator --- PLB_SAValid -- PLB secondary address valid indicator --- PLB_rdPrim -- PLB secondary to primary read request indicator --- PLB_wrPrim -- PLB secondary to primary write request indicator --- PLB_masterID -- PLB current master identifier --- PLB_abort -- PLB abort request indicator --- PLB_busLock -- PLB bus lock --- PLB_RNW -- PLB read/not write --- PLB_BE -- PLB byte enables --- PLB_MSize -- PLB master data bus size --- PLB_size -- PLB transfer size --- PLB_type -- PLB transfer type --- PLB_lockErr -- PLB lock error indicator --- PLB_wrDBus -- PLB write data bus --- PLB_wrBurst -- PLB burst write transfer indicator --- PLB_rdBurst -- PLB burst read transfer indicator --- PLB_wrPendReq -- PLB write pending bus request indicator --- PLB_rdPendReq -- PLB read pending bus request indicator --- PLB_wrPendPri -- PLB write pending request priority --- PLB_rdPendPri -- PLB read pending request priority --- PLB_reqPri -- PLB current request priority --- PLB_TAttribute -- PLB transfer attribute --- Sl_addrAck -- Slave address acknowledge --- Sl_SSize -- Slave data bus size --- Sl_wait -- Slave wait indicator --- Sl_rearbitrate -- Slave re-arbitrate bus indicator --- Sl_wrDAck -- Slave write data acknowledge --- Sl_wrComp -- Slave write transfer complete indicator --- Sl_wrBTerm -- Slave terminate write burst transfer --- Sl_rdDBus -- Slave read data bus --- Sl_rdWdAddr -- Slave read word address --- Sl_rdDAck -- Slave read data acknowledge --- Sl_rdComp -- Slave read transfer complete indicator --- Sl_rdBTerm -- Slave terminate read burst transfer --- Sl_MBusy -- Slave busy indicator --- Sl_MWrErr -- Slave write error indicator --- Sl_MRdErr -- Slave read error indicator --- Sl_MIRQ -- Slave interrupt indicator --- IP2INTC_Irpt -- Interrupt output to processor ------------------------------------------------------------------------------- - -entity mont_mult1536 is - generic - ( - -- ADD USER GENERICS BELOW THIS LINE --------------- - --USER generics added here - -- Multiplier parameters - C_NR_BITS_TOTAL : integer := 1536; - C_NR_STAGES_TOTAL : integer := 96; - C_NR_STAGES_LOW : integer := 32; - C_SPLIT_PIPELINE : boolean := true; - -- ADD USER GENERICS ABOVE THIS LINE --------------- - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol parameters, do not add to or delete - C_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_HIGHADDR : std_logic_vector := X"00000000"; - C_SPLB_AWIDTH : integer := 32; - C_SPLB_DWIDTH : integer := 128; - C_SPLB_NUM_MASTERS : integer := 8; - C_SPLB_MID_WIDTH : integer := 3; - C_SPLB_NATIVE_DWIDTH : integer := 32; - C_SPLB_P2P : integer := 0; - C_SPLB_SUPPORT_BURSTS : integer := 0; - C_SPLB_SMALLEST_MASTER : integer := 32; - C_SPLB_CLK_PERIOD_PS : integer := 10000; - C_INCLUDE_DPHASE_TIMER : integer := 0; - C_FAMILY : string := "virtex5"; - C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM0_HIGHADDR : std_logic_vector := X"00000000"; - C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM1_HIGHADDR : std_logic_vector := X"00000000"; - C_MEM2_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM2_HIGHADDR : std_logic_vector := X"00000000"; - C_MEM3_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM3_HIGHADDR : std_logic_vector := X"00000000"; - C_MEM4_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM4_HIGHADDR : std_logic_vector := X"00000000"; - C_MEM5_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_MEM5_HIGHADDR : std_logic_vector := X"00000000" - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - port - ( - -- ADD USER PORTS BELOW THIS LINE ------------------ - --USER ports added here - calc_time : out std_logic; - -- ADD USER PORTS ABOVE THIS LINE ------------------ - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol ports, do not add to or delete - SPLB_Clk : in std_logic; - SPLB_Rst : in std_logic; - PLB_ABus : in std_logic_vector(0 to 31); - PLB_UABus : in std_logic_vector(0 to 31); - PLB_PAValid : in std_logic; - PLB_SAValid : in std_logic; - PLB_rdPrim : in std_logic; - PLB_wrPrim : in std_logic; - PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); - PLB_abort : in std_logic; - PLB_busLock : in std_logic; - PLB_RNW : in std_logic; - PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); - PLB_MSize : in std_logic_vector(0 to 1); - PLB_size : in std_logic_vector(0 to 3); - PLB_type : in std_logic_vector(0 to 2); - PLB_lockErr : in std_logic; - PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); - PLB_wrBurst : in std_logic; - PLB_rdBurst : in std_logic; - PLB_wrPendReq : in std_logic; - PLB_rdPendReq : in std_logic; - PLB_wrPendPri : in std_logic_vector(0 to 1); - PLB_rdPendPri : in std_logic_vector(0 to 1); - PLB_reqPri : in std_logic_vector(0 to 1); - PLB_TAttribute : in std_logic_vector(0 to 15); - Sl_addrAck : out std_logic; - Sl_SSize : out std_logic_vector(0 to 1); - Sl_wait : out std_logic; - Sl_rearbitrate : out std_logic; - Sl_wrDAck : out std_logic; - Sl_wrComp : out std_logic; - Sl_wrBTerm : out std_logic; - Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); - Sl_rdWdAddr : out std_logic_vector(0 to 3); - Sl_rdDAck : out std_logic; - Sl_rdComp : out std_logic; - Sl_rdBTerm : out std_logic; - Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - IP2INTC_Irpt : out std_logic - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - - attribute SIGIS : string; - attribute SIGIS of SPLB_Clk : signal is "CLK"; - attribute SIGIS of SPLB_Rst : signal is "RST"; - attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH"; - -end entity mont_mult1536; - ------------------------------------------------------------------------------- --- Architecture section ------------------------------------------------------------------------------- - -architecture IMP of mont_mult1536 is - - ------------------------------------------ - -- Array of base/high address pairs for each address range - ------------------------------------------ - constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); - constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; - constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; - constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; - constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; - constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200"; - constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF"; - - constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := - ( - ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address - ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address - ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address - ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address - ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address - ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address - ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address - ZERO_ADDR_PAD & C_MEM0_HIGHADDR, -- user logic memory space 0 high address - ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address - ZERO_ADDR_PAD & C_MEM1_HIGHADDR, -- user logic memory space 1 high address - ZERO_ADDR_PAD & C_MEM2_BASEADDR, -- user logic memory space 2 base address - ZERO_ADDR_PAD & C_MEM2_HIGHADDR, -- user logic memory space 2 high address - ZERO_ADDR_PAD & C_MEM3_BASEADDR, -- user logic memory space 3 base address - ZERO_ADDR_PAD & C_MEM3_HIGHADDR, -- user logic memory space 3 high address - ZERO_ADDR_PAD & C_MEM4_BASEADDR, -- user logic memory space 4 base address - ZERO_ADDR_PAD & C_MEM4_HIGHADDR, -- user logic memory space 4 high address - ZERO_ADDR_PAD & C_MEM5_BASEADDR, -- user logic memory space 5 base address - ZERO_ADDR_PAD & C_MEM5_HIGHADDR -- user logic memory space 5 high address - ); - - ------------------------------------------ - -- Array of desired number of chip enables for each address range - ------------------------------------------ - constant USER_SLV_NUM_REG : integer := 1; - constant USER_NUM_REG : integer := USER_SLV_NUM_REG; - constant RST_NUM_CE : integer := 1; - constant INTR_NUM_CE : integer := 16; - constant USER_NUM_MEM : integer := 6; - - constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := - ( - 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space - 1 => RST_NUM_CE, -- number of ce for soft reset space - 2 => INTR_NUM_CE, -- number of ce for interrupt control space - 3 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable) - 4 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable) - 5 => 1, -- number of ce for user logic memory space 2 (always 1 chip enable) - 6 => 1, -- number of ce for user logic memory space 3 (always 1 chip enable) - 7 => 1, -- number of ce for user logic memory space 4 (always 1 chip enable) - 8 => 1 -- number of ce for user logic memory space 5 (always 1 chip enable) - ); - - ------------------------------------------ - -- Ratio of bus clock to core clock (for use in dual clock systems) - -- 1 = ratio is 1:1 - -- 2 = ratio is 2:1 - ------------------------------------------ - constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; - - ------------------------------------------ - -- Width of the slave data bus (32 only) - ------------------------------------------ - constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; - - constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; - - ------------------------------------------ - -- Width of triggered reset in bus clocks - ------------------------------------------ - constant RESET_WIDTH : integer := 4; - - ------------------------------------------ - -- Number of device level interrupts - ------------------------------------------ - constant INTR_NUM_IPIF_IRPT_SRC : integer := 4; - - ------------------------------------------ - -- Capture mode for each IP interrupt (generated by user logic) - -- 1 = pass through (non-inverting) - -- 2 = pass through (inverting) - -- 3 = registered level (non-inverting) - -- 4 = registered level (inverting) - -- 5 = positive edge detect - -- 6 = negative edge detect - ------------------------------------------ - constant USER_NUM_INTR : integer := 1; - constant USER_INTR_CAPTURE_MODE : integer := 1; - - constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := - ( - 0 => USER_INTR_CAPTURE_MODE - ); - - ------------------------------------------ - -- Device priority encoder feature inclusion/omission - -- true = include priority encoder - -- false = omit priority encoder - ------------------------------------------ - constant INTR_INCLUDE_DEV_PENCODER : boolean := false; - - ------------------------------------------ - -- Device ISC feature inclusion/omission - -- true = include device ISC - -- false = omit device ISC - ------------------------------------------ - constant INTR_INCLUDE_DEV_ISC : boolean := false; - - ------------------------------------------ - -- Width of the slave address bus (32 only) - ------------------------------------------ - constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH; - - ------------------------------------------ - -- Index for CS/CE - ------------------------------------------ - constant USER_SLV_CS_INDEX : integer := 0; - constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); - constant RST_CS_INDEX : integer := 1; - constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX); - constant INTR_CS_INDEX : integer := 2; - constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX); - constant USER_MEM0_CS_INDEX : integer := 3; - constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX; - - constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; - - ------------------------------------------ - -- IP Interconnect (IPIC) signal declarations - ------------------------------------------ - signal ipif_Bus2IP_Clk : std_logic; - signal ipif_Bus2IP_Reset : std_logic; - signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal ipif_IP2Bus_WrAck : std_logic; - signal ipif_IP2Bus_RdAck : std_logic; - signal ipif_IP2Bus_Error : std_logic; - signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); - signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal ipif_Bus2IP_RNW : std_logic; - signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); - signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); - signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); - signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); - signal rst_Bus2IP_Reset : std_logic; - signal rst_IP2Bus_WrAck : std_logic; - signal rst_IP2Bus_Error : std_logic; - signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1); - signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1); - signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal intr_IP2Bus_WrAck : std_logic; - signal intr_IP2Bus_RdAck : std_logic; - signal intr_IP2Bus_Error : std_logic; - signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); - signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); - signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); - signal user_IP2Bus_RdAck : std_logic; - signal user_IP2Bus_WrAck : std_logic; - signal user_IP2Bus_Error : std_logic; - signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1); - -begin - - ------------------------------------------ - -- instantiate plbv46_slave_single - ------------------------------------------ - PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single - generic map - ( - C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, - C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, - C_SPLB_P2P => C_SPLB_P2P, - C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, - C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, - C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, - C_SPLB_AWIDTH => C_SPLB_AWIDTH, - C_SPLB_DWIDTH => C_SPLB_DWIDTH, - C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, - C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, - C_FAMILY => C_FAMILY - ) - port map - ( - SPLB_Clk => SPLB_Clk, - SPLB_Rst => SPLB_Rst, - PLB_ABus => PLB_ABus, - PLB_UABus => PLB_UABus, - PLB_PAValid => PLB_PAValid, - PLB_SAValid => PLB_SAValid, - PLB_rdPrim => PLB_rdPrim, - PLB_wrPrim => PLB_wrPrim, - PLB_masterID => PLB_masterID, - PLB_abort => PLB_abort, - PLB_busLock => PLB_busLock, - PLB_RNW => PLB_RNW, - PLB_BE => PLB_BE, - PLB_MSize => PLB_MSize, - PLB_size => PLB_size, - PLB_type => PLB_type, - PLB_lockErr => PLB_lockErr, - PLB_wrDBus => PLB_wrDBus, - PLB_wrBurst => PLB_wrBurst, - PLB_rdBurst => PLB_rdBurst, - PLB_wrPendReq => PLB_wrPendReq, - PLB_rdPendReq => PLB_rdPendReq, - PLB_wrPendPri => PLB_wrPendPri, - PLB_rdPendPri => PLB_rdPendPri, - PLB_reqPri => PLB_reqPri, - PLB_TAttribute => PLB_TAttribute, - Sl_addrAck => Sl_addrAck, - Sl_SSize => Sl_SSize, - Sl_wait => Sl_wait, - Sl_rearbitrate => Sl_rearbitrate, - Sl_wrDAck => Sl_wrDAck, - Sl_wrComp => Sl_wrComp, - Sl_wrBTerm => Sl_wrBTerm, - Sl_rdDBus => Sl_rdDBus, - Sl_rdWdAddr => Sl_rdWdAddr, - Sl_rdDAck => Sl_rdDAck, - Sl_rdComp => Sl_rdComp, - Sl_rdBTerm => Sl_rdBTerm, - Sl_MBusy => Sl_MBusy, - Sl_MWrErr => Sl_MWrErr, - Sl_MRdErr => Sl_MRdErr, - Sl_MIRQ => Sl_MIRQ, - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => ipif_Bus2IP_Reset, - IP2Bus_Data => ipif_IP2Bus_Data, - IP2Bus_WrAck => ipif_IP2Bus_WrAck, - IP2Bus_RdAck => ipif_IP2Bus_RdAck, - IP2Bus_Error => ipif_IP2Bus_Error, - Bus2IP_Addr => ipif_Bus2IP_Addr, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_RNW => ipif_Bus2IP_RNW, - Bus2IP_BE => ipif_Bus2IP_BE, - Bus2IP_CS => ipif_Bus2IP_CS, - Bus2IP_RdCE => ipif_Bus2IP_RdCE, - Bus2IP_WrCE => ipif_Bus2IP_WrCE - ); - - ------------------------------------------ - -- instantiate soft_reset - ------------------------------------------ - SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset - generic map - ( - C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, - C_RESET_WIDTH => RESET_WIDTH - ) - port map - ( - Bus2IP_Reset => ipif_Bus2IP_Reset, - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX), - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Reset2IP_Reset => rst_Bus2IP_Reset, - Reset2Bus_WrAck => rst_IP2Bus_WrAck, - Reset2Bus_Error => rst_IP2Bus_Error, - Reset2Bus_ToutSup => open - ); - - ------------------------------------------ - -- instantiate interrupt_control - ------------------------------------------ - INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control - generic map - ( - C_NUM_CE => INTR_NUM_CE, - C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC, - C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY, - C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER, - C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC, - C_IPIF_DWIDTH => IPIF_SLV_DWIDTH - ) - port map - ( - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => rst_Bus2IP_Reset, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1), - Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1), - IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts, - IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts, - IP2Bus_IntrEvent => user_IP2Bus_IntrEvent, - Intr2Bus_DevIntr => IP2INTC_Irpt, - Intr2Bus_DBus => intr_IP2Bus_Data, - Intr2Bus_WrAck => intr_IP2Bus_WrAck, - Intr2Bus_RdAck => intr_IP2Bus_RdAck, - Intr2Bus_Error => intr_IP2Bus_Error, - Intr2Bus_Retry => open, - Intr2Bus_ToutSup => open - ); - - -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored - intr_IPIF_Reg_Interrupts(0) <= '0'; - intr_IPIF_Reg_Interrupts(1) <= '0'; - intr_IPIF_Lvl_Interrupts(0) <= '0'; - intr_IPIF_Lvl_Interrupts(1) <= '0'; - intr_IPIF_Lvl_Interrupts(2) <= '0'; - intr_IPIF_Lvl_Interrupts(3) <= '0'; - - ------------------------------------------ - -- instantiate User Logic - ------------------------------------------ - USER_LOGIC_I : entity mod_sim_exp.user_logic - generic map - ( - -- MAP USER GENERICS BELOW THIS LINE --------------- - --USER generics mapped here - -- Multiplier parameters - C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, - C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, - C_NR_STAGES_LOW => C_NR_STAGES_LOW, - C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, - -- MAP USER GENERICS ABOVE THIS LINE --------------- - - C_SLV_AWIDTH => USER_SLV_AWIDTH, - C_SLV_DWIDTH => USER_SLV_DWIDTH, - C_NUM_REG => USER_NUM_REG, - C_NUM_MEM => USER_NUM_MEM, - C_NUM_INTR => USER_NUM_INTR - ) - port map - ( - -- MAP USER PORTS BELOW THIS LINE ------------------ - --USER ports mapped here - calc_time => calc_time, - -- MAP USER PORTS ABOVE THIS LINE ------------------ - - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => rst_Bus2IP_Reset, - Bus2IP_Addr => ipif_Bus2IP_Addr, - Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1), - Bus2IP_RNW => ipif_Bus2IP_RNW, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Bus2IP_RdCE => user_Bus2IP_RdCE, - Bus2IP_WrCE => user_Bus2IP_WrCE, - IP2Bus_Data => user_IP2Bus_Data, - IP2Bus_RdAck => user_IP2Bus_RdAck, - IP2Bus_WrAck => user_IP2Bus_WrAck, - IP2Bus_Error => user_IP2Bus_Error, - IP2Bus_IntrEvent => user_IP2Bus_IntrEvent - ); - - ------------------------------------------ - -- connect internal signals - ------------------------------------------ - IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is - begin - - case ipif_Bus2IP_CS is - when "100000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "010000000" => ipif_IP2Bus_Data <= (others => '0'); - when "001000000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data; - when "000100000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000010000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000001000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when others => ipif_IP2Bus_Data <= (others => '0'); - end case; - - end process IP2BUS_DATA_MUX_PROC; - - ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck or intr_IP2Bus_WrAck; - ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck; - ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error or intr_IP2Bus_Error; - - user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); - user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); - -end IMP; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd (nonexistent) @@ -1,639 +0,0 @@ ------------------------------------------------------------------------------- --- mont_mult1536.vhd - entity/architecture pair ------------------------------------------------------------------------------- --- IMPORTANT: --- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. --- --- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. --- --- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW --- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION --- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------- --- --- *************************************************************************** --- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. ** --- ** ** --- ** Xilinx, Inc. ** --- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** --- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** --- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** --- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** --- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** --- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** --- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** --- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** --- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** --- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** --- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** --- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** --- ** FOR A PARTICULAR PURPOSE. ** --- ** ** --- *************************************************************************** --- ------------------------------------------------------------------------------- --- Filename: mont_mult1536.vhd --- Version: 2.00.a --- Description: Top level design, instantiates library components and user logic. --- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard) --- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------- --- Naming Conventions: --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: "C_*" --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- combinatorial signals: "*_com" --- pipelined or register delay signals: "*_d#" --- counter signals: "*cnt*" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- device pins: "*_pin" --- ports: "- Names begin with Uppercase" --- processes: "*_PROCESS" --- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library proc_common_v3_00_a; -use proc_common_v3_00_a.proc_common_pkg.all; -use proc_common_v3_00_a.ipif_pkg.all; -use proc_common_v3_00_a.soft_reset; - -library interrupt_control_v2_01_a; -use interrupt_control_v2_01_a.interrupt_control; - -library plbv46_slave_single_v1_01_a; -use plbv46_slave_single_v1_01_a.plbv46_slave_single; - -library mod_sim_exp; -use mod_sim_exp.user_logic; - ------------------------------------------------------------------------------- --- Entity section ------------------------------------------------------------------------------- --- Definition of Generics: --- C_BASEADDR -- PLBv46 slave: base address --- C_HIGHADDR -- PLBv46 slave: high address --- C_SPLB_AWIDTH -- PLBv46 slave: address bus width --- C_SPLB_DWIDTH -- PLBv46 slave: data bus width --- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters --- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width --- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width --- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme --- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts --- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master --- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds --- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer --- C_FAMILY -- Xilinx FPGA family --- C_MEM0_BASEADDR -- User memory space 0 base address --- C_MEM0_HIGHADDR -- User memory space 0 high address --- C_MEM1_BASEADDR -- User memory space 1 base address --- C_MEM1_HIGHADDR -- User memory space 1 high address --- C_MEM2_BASEADDR -- User memory space 2 base address --- C_MEM2_HIGHADDR -- User memory space 2 high address --- C_MEM3_BASEADDR -- User memory space 3 base address --- C_MEM3_HIGHADDR -- User memory space 3 high address --- C_MEM4_BASEADDR -- User memory space 4 base address --- C_MEM4_HIGHADDR -- User memory space 4 high address --- C_MEM5_BASEADDR -- User memory space 5 base address --- C_MEM5_HIGHADDR -- User memory space 5 high address --- --- Definition of Ports: --- SPLB_Clk -- PLB main bus clock --- SPLB_Rst -- PLB main bus reset --- PLB_ABus -- PLB address bus --- PLB_UABus -- PLB upper address bus --- PLB_PAValid -- PLB primary address valid indicator --- PLB_SAValid -- PLB secondary address valid indicator --- PLB_rdPrim -- PLB secondary to primary read request indicator --- PLB_wrPrim -- PLB secondary to primary write request indicator --- PLB_masterID -- PLB current master identifier --- PLB_abort -- PLB abort request indicator --- PLB_busLock -- PLB bus lock --- PLB_RNW -- PLB read/not write --- PLB_BE -- PLB byte enables --- PLB_MSize -- PLB master data bus size --- PLB_size -- PLB transfer size --- PLB_type -- PLB transfer type --- PLB_lockErr -- PLB lock error indicator --- PLB_wrDBus -- PLB write data bus --- PLB_wrBurst -- PLB burst write transfer indicator --- PLB_rdBurst -- PLB burst read transfer indicator --- PLB_wrPendReq -- PLB write pending bus request indicator --- PLB_rdPendReq -- PLB read pending bus request indicator --- PLB_wrPendPri -- PLB write pending request priority --- PLB_rdPendPri -- PLB read pending request priority --- PLB_reqPri -- PLB current request priority --- PLB_TAttribute -- PLB transfer attribute --- Sl_addrAck -- Slave address acknowledge --- Sl_SSize -- Slave data bus size --- Sl_wait -- Slave wait indicator --- Sl_rearbitrate -- Slave re-arbitrate bus indicator --- Sl_wrDAck -- Slave write data acknowledge --- Sl_wrComp -- Slave write transfer complete indicator --- Sl_wrBTerm -- Slave terminate write burst transfer --- Sl_rdDBus -- Slave read data bus --- Sl_rdWdAddr -- Slave read word address --- Sl_rdDAck -- Slave read data acknowledge --- Sl_rdComp -- Slave read transfer complete indicator --- Sl_rdBTerm -- Slave terminate read burst transfer --- Sl_MBusy -- Slave busy indicator --- Sl_MWrErr -- Slave write error indicator --- Sl_MRdErr -- Slave read error indicator --- Sl_MIRQ -- Slave interrupt indicator --- IP2INTC_Irpt -- Interrupt output to processor ------------------------------------------------------------------------------- - -entity mod_sim_exp_IPcore is - generic - ( - -- ADD USER GENERICS BELOW THIS LINE --------------- - --USER generics added here - -- Multiplier parameters - C_NR_BITS_TOTAL : integer := 1536; - C_NR_STAGES_TOTAL : integer := 96; - C_NR_STAGES_LOW : integer := 32; - C_SPLIT_PIPELINE : boolean := true; - -- ADD USER GENERICS ABOVE THIS LINE --------------- - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol parameters, do not add to or delete - C_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_HIGHADDR : std_logic_vector := X"00000000"; - C_SPLB_AWIDTH : integer := 32; - C_SPLB_DWIDTH : integer := 128; - C_SPLB_NUM_MASTERS : integer := 8; - C_SPLB_MID_WIDTH : integer := 3; - C_SPLB_NATIVE_DWIDTH : integer := 32; - C_SPLB_P2P : integer := 0; - C_SPLB_SUPPORT_BURSTS : integer := 0; - C_SPLB_SMALLEST_MASTER : integer := 32; - C_SPLB_CLK_PERIOD_PS : integer := 10000; - C_INCLUDE_DPHASE_TIMER : integer := 0; - C_FAMILY : string := "virtex5"; - C_M_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_M_HIGHADDR : std_logic_vector := X"00000000"; - C_OP0_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_OP0_HIGHADDR : std_logic_vector := X"00000000"; - C_OP1_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_OP1_HIGHADDR : std_logic_vector := X"00000000"; - C_OP2_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_OP2_HIGHADDR : std_logic_vector := X"00000000"; - C_OP3_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_OP3_HIGHADDR : std_logic_vector := X"00000000"; - C_FIFO_BASEADDR : std_logic_vector := X"FFFFFFFF"; - C_FIFO_HIGHADDR : std_logic_vector := X"00000000" - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - port - ( - -- ADD USER PORTS BELOW THIS LINE ------------------ - --USER ports added here - calc_time : out std_logic; - -- ADD USER PORTS ABOVE THIS LINE ------------------ - - -- DO NOT EDIT BELOW THIS LINE --------------------- - -- Bus protocol ports, do not add to or delete - SPLB_Clk : in std_logic; - SPLB_Rst : in std_logic; - PLB_ABus : in std_logic_vector(0 to 31); - PLB_UABus : in std_logic_vector(0 to 31); - PLB_PAValid : in std_logic; - PLB_SAValid : in std_logic; - PLB_rdPrim : in std_logic; - PLB_wrPrim : in std_logic; - PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); - PLB_abort : in std_logic; - PLB_busLock : in std_logic; - PLB_RNW : in std_logic; - PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); - PLB_MSize : in std_logic_vector(0 to 1); - PLB_size : in std_logic_vector(0 to 3); - PLB_type : in std_logic_vector(0 to 2); - PLB_lockErr : in std_logic; - PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); - PLB_wrBurst : in std_logic; - PLB_rdBurst : in std_logic; - PLB_wrPendReq : in std_logic; - PLB_rdPendReq : in std_logic; - PLB_wrPendPri : in std_logic_vector(0 to 1); - PLB_rdPendPri : in std_logic_vector(0 to 1); - PLB_reqPri : in std_logic_vector(0 to 1); - PLB_TAttribute : in std_logic_vector(0 to 15); - Sl_addrAck : out std_logic; - Sl_SSize : out std_logic_vector(0 to 1); - Sl_wait : out std_logic; - Sl_rearbitrate : out std_logic; - Sl_wrDAck : out std_logic; - Sl_wrComp : out std_logic; - Sl_wrBTerm : out std_logic; - Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); - Sl_rdWdAddr : out std_logic_vector(0 to 3); - Sl_rdDAck : out std_logic; - Sl_rdComp : out std_logic; - Sl_rdBTerm : out std_logic; - Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); - IP2INTC_Irpt : out std_logic - -- DO NOT EDIT ABOVE THIS LINE --------------------- - ); - - attribute SIGIS : string; - attribute SIGIS of SPLB_Clk : signal is "CLK"; - attribute SIGIS of SPLB_Rst : signal is "RST"; - attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH"; - -end entity mod_sim_exp_IPcore; - ------------------------------------------------------------------------------- --- Architecture section ------------------------------------------------------------------------------- - -architecture IMP of mod_sim_exp_IPcore is - - ------------------------------------------ - -- Array of base/high address pairs for each address range - ------------------------------------------ - constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); - constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; - constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; - constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; - constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; - constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200"; - constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF"; - - constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := - ( - ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address - ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address - ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address - ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address - ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address - ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address - ZERO_ADDR_PAD & C_M_BASEADDR, -- user logic memory space 0 base address - ZERO_ADDR_PAD & C_M_HIGHADDR, -- user logic memory space 0 high address - ZERO_ADDR_PAD & C_OP0_BASEADDR, -- user logic memory space 1 base address - ZERO_ADDR_PAD & C_OP0_HIGHADDR, -- user logic memory space 1 high address - ZERO_ADDR_PAD & C_OP1_BASEADDR, -- user logic memory space 2 base address - ZERO_ADDR_PAD & C_OP1_HIGHADDR, -- user logic memory space 2 high address - ZERO_ADDR_PAD & C_OP2_BASEADDR, -- user logic memory space 3 base address - ZERO_ADDR_PAD & C_OP2_HIGHADDR, -- user logic memory space 3 high address - ZERO_ADDR_PAD & C_OP3_BASEADDR, -- user logic memory space 4 base address - ZERO_ADDR_PAD & C_OP3_HIGHADDR, -- user logic memory space 4 high address - ZERO_ADDR_PAD & C_FIFO_BASEADDR, -- user logic memory space 5 base address - ZERO_ADDR_PAD & C_FIFO_HIGHADDR -- user logic memory space 5 high address - ); - - ------------------------------------------ - -- Array of desired number of chip enables for each address range - ------------------------------------------ - constant USER_SLV_NUM_REG : integer := 1; - constant USER_NUM_REG : integer := USER_SLV_NUM_REG; - constant RST_NUM_CE : integer := 1; - constant INTR_NUM_CE : integer := 16; - constant USER_NUM_MEM : integer := 6; - - constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := - ( - 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space - 1 => RST_NUM_CE, -- number of ce for soft reset space - 2 => INTR_NUM_CE, -- number of ce for interrupt control space - 3 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable) - 4 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable) - 5 => 1, -- number of ce for user logic memory space 2 (always 1 chip enable) - 6 => 1, -- number of ce for user logic memory space 3 (always 1 chip enable) - 7 => 1, -- number of ce for user logic memory space 4 (always 1 chip enable) - 8 => 1 -- number of ce for user logic memory space 5 (always 1 chip enable) - ); - - ------------------------------------------ - -- Ratio of bus clock to core clock (for use in dual clock systems) - -- 1 = ratio is 1:1 - -- 2 = ratio is 2:1 - ------------------------------------------ - constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; - - ------------------------------------------ - -- Width of the slave data bus (32 only) - ------------------------------------------ - constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; - - constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; - - ------------------------------------------ - -- Width of triggered reset in bus clocks - ------------------------------------------ - constant RESET_WIDTH : integer := 4; - - ------------------------------------------ - -- Number of device level interrupts - ------------------------------------------ - constant INTR_NUM_IPIF_IRPT_SRC : integer := 4; - - ------------------------------------------ - -- Capture mode for each IP interrupt (generated by user logic) - -- 1 = pass through (non-inverting) - -- 2 = pass through (inverting) - -- 3 = registered level (non-inverting) - -- 4 = registered level (inverting) - -- 5 = positive edge detect - -- 6 = negative edge detect - ------------------------------------------ - constant USER_NUM_INTR : integer := 1; - constant USER_INTR_CAPTURE_MODE : integer := 1; - - constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := - ( - 0 => USER_INTR_CAPTURE_MODE - ); - - ------------------------------------------ - -- Device priority encoder feature inclusion/omission - -- true = include priority encoder - -- false = omit priority encoder - ------------------------------------------ - constant INTR_INCLUDE_DEV_PENCODER : boolean := false; - - ------------------------------------------ - -- Device ISC feature inclusion/omission - -- true = include device ISC - -- false = omit device ISC - ------------------------------------------ - constant INTR_INCLUDE_DEV_ISC : boolean := false; - - ------------------------------------------ - -- Width of the slave address bus (32 only) - ------------------------------------------ - constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH; - - ------------------------------------------ - -- Index for CS/CE - ------------------------------------------ - constant USER_SLV_CS_INDEX : integer := 0; - constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); - constant RST_CS_INDEX : integer := 1; - constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX); - constant INTR_CS_INDEX : integer := 2; - constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX); - constant USER_MEM0_CS_INDEX : integer := 3; - constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX; - - constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; - - ------------------------------------------ - -- IP Interconnect (IPIC) signal declarations - ------------------------------------------ - signal ipif_Bus2IP_Clk : std_logic; - signal ipif_Bus2IP_Reset : std_logic; - signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal ipif_IP2Bus_WrAck : std_logic; - signal ipif_IP2Bus_RdAck : std_logic; - signal ipif_IP2Bus_Error : std_logic; - signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); - signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal ipif_Bus2IP_RNW : std_logic; - signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); - signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); - signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); - signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); - signal rst_Bus2IP_Reset : std_logic; - signal rst_IP2Bus_WrAck : std_logic; - signal rst_IP2Bus_Error : std_logic; - signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1); - signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1); - signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); - signal intr_IP2Bus_WrAck : std_logic; - signal intr_IP2Bus_RdAck : std_logic; - signal intr_IP2Bus_Error : std_logic; - signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); - signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); - signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); - signal user_IP2Bus_RdAck : std_logic; - signal user_IP2Bus_WrAck : std_logic; - signal user_IP2Bus_Error : std_logic; - signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1); - -begin - - ------------------------------------------ - -- instantiate plbv46_slave_single - ------------------------------------------ - PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single - generic map - ( - C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, - C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, - C_SPLB_P2P => C_SPLB_P2P, - C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, - C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, - C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, - C_SPLB_AWIDTH => C_SPLB_AWIDTH, - C_SPLB_DWIDTH => C_SPLB_DWIDTH, - C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, - C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, - C_FAMILY => C_FAMILY - ) - port map - ( - SPLB_Clk => SPLB_Clk, - SPLB_Rst => SPLB_Rst, - PLB_ABus => PLB_ABus, - PLB_UABus => PLB_UABus, - PLB_PAValid => PLB_PAValid, - PLB_SAValid => PLB_SAValid, - PLB_rdPrim => PLB_rdPrim, - PLB_wrPrim => PLB_wrPrim, - PLB_masterID => PLB_masterID, - PLB_abort => PLB_abort, - PLB_busLock => PLB_busLock, - PLB_RNW => PLB_RNW, - PLB_BE => PLB_BE, - PLB_MSize => PLB_MSize, - PLB_size => PLB_size, - PLB_type => PLB_type, - PLB_lockErr => PLB_lockErr, - PLB_wrDBus => PLB_wrDBus, - PLB_wrBurst => PLB_wrBurst, - PLB_rdBurst => PLB_rdBurst, - PLB_wrPendReq => PLB_wrPendReq, - PLB_rdPendReq => PLB_rdPendReq, - PLB_wrPendPri => PLB_wrPendPri, - PLB_rdPendPri => PLB_rdPendPri, - PLB_reqPri => PLB_reqPri, - PLB_TAttribute => PLB_TAttribute, - Sl_addrAck => Sl_addrAck, - Sl_SSize => Sl_SSize, - Sl_wait => Sl_wait, - Sl_rearbitrate => Sl_rearbitrate, - Sl_wrDAck => Sl_wrDAck, - Sl_wrComp => Sl_wrComp, - Sl_wrBTerm => Sl_wrBTerm, - Sl_rdDBus => Sl_rdDBus, - Sl_rdWdAddr => Sl_rdWdAddr, - Sl_rdDAck => Sl_rdDAck, - Sl_rdComp => Sl_rdComp, - Sl_rdBTerm => Sl_rdBTerm, - Sl_MBusy => Sl_MBusy, - Sl_MWrErr => Sl_MWrErr, - Sl_MRdErr => Sl_MRdErr, - Sl_MIRQ => Sl_MIRQ, - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => ipif_Bus2IP_Reset, - IP2Bus_Data => ipif_IP2Bus_Data, - IP2Bus_WrAck => ipif_IP2Bus_WrAck, - IP2Bus_RdAck => ipif_IP2Bus_RdAck, - IP2Bus_Error => ipif_IP2Bus_Error, - Bus2IP_Addr => ipif_Bus2IP_Addr, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_RNW => ipif_Bus2IP_RNW, - Bus2IP_BE => ipif_Bus2IP_BE, - Bus2IP_CS => ipif_Bus2IP_CS, - Bus2IP_RdCE => ipif_Bus2IP_RdCE, - Bus2IP_WrCE => ipif_Bus2IP_WrCE - ); - - ------------------------------------------ - -- instantiate soft_reset - ------------------------------------------ - SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset - generic map - ( - C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, - C_RESET_WIDTH => RESET_WIDTH - ) - port map - ( - Bus2IP_Reset => ipif_Bus2IP_Reset, - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX), - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Reset2IP_Reset => rst_Bus2IP_Reset, - Reset2Bus_WrAck => rst_IP2Bus_WrAck, - Reset2Bus_Error => rst_IP2Bus_Error, - Reset2Bus_ToutSup => open - ); - - ------------------------------------------ - -- instantiate interrupt_control - ------------------------------------------ - INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control - generic map - ( - C_NUM_CE => INTR_NUM_CE, - C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC, - C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY, - C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER, - C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC, - C_IPIF_DWIDTH => IPIF_SLV_DWIDTH - ) - port map - ( - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => rst_Bus2IP_Reset, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1), - Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1), - IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts, - IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts, - IP2Bus_IntrEvent => user_IP2Bus_IntrEvent, - Intr2Bus_DevIntr => IP2INTC_Irpt, - Intr2Bus_DBus => intr_IP2Bus_Data, - Intr2Bus_WrAck => intr_IP2Bus_WrAck, - Intr2Bus_RdAck => intr_IP2Bus_RdAck, - Intr2Bus_Error => intr_IP2Bus_Error, - Intr2Bus_Retry => open, - Intr2Bus_ToutSup => open - ); - - -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored - intr_IPIF_Reg_Interrupts(0) <= '0'; - intr_IPIF_Reg_Interrupts(1) <= '0'; - intr_IPIF_Lvl_Interrupts(0) <= '0'; - intr_IPIF_Lvl_Interrupts(1) <= '0'; - intr_IPIF_Lvl_Interrupts(2) <= '0'; - intr_IPIF_Lvl_Interrupts(3) <= '0'; - - ------------------------------------------ - -- instantiate User Logic - ------------------------------------------ - USER_LOGIC_I : entity mod_sim_exp.user_logic - generic map - ( - -- MAP USER GENERICS BELOW THIS LINE --------------- - -- Multiplier parameters - C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, - C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, - C_NR_STAGES_LOW => C_NR_STAGES_LOW, - C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, - -- MAP USER GENERICS ABOVE THIS LINE --------------- - - C_SLV_AWIDTH => USER_SLV_AWIDTH, - C_SLV_DWIDTH => USER_SLV_DWIDTH, - C_NUM_REG => USER_NUM_REG, - C_NUM_MEM => USER_NUM_MEM, - C_NUM_INTR => USER_NUM_INTR - ) - port map - ( - -- MAP USER PORTS BELOW THIS LINE ------------------ - --USER ports mapped here - calc_time => calc_time, - -- MAP USER PORTS ABOVE THIS LINE ------------------ - - Bus2IP_Clk => ipif_Bus2IP_Clk, - Bus2IP_Reset => rst_Bus2IP_Reset, - Bus2IP_Addr => ipif_Bus2IP_Addr, - Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1), - Bus2IP_RNW => ipif_Bus2IP_RNW, - Bus2IP_Data => ipif_Bus2IP_Data, - Bus2IP_BE => ipif_Bus2IP_BE, - Bus2IP_RdCE => user_Bus2IP_RdCE, - Bus2IP_WrCE => user_Bus2IP_WrCE, - IP2Bus_Data => user_IP2Bus_Data, - IP2Bus_RdAck => user_IP2Bus_RdAck, - IP2Bus_WrAck => user_IP2Bus_WrAck, - IP2Bus_Error => user_IP2Bus_Error, - IP2Bus_IntrEvent => user_IP2Bus_IntrEvent - ); - - ------------------------------------------ - -- connect internal signals - ------------------------------------------ - IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is - begin - - case ipif_Bus2IP_CS is - when "100000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "010000000" => ipif_IP2Bus_Data <= (others => '0'); - when "001000000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data; - when "000100000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000010000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000001000" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when "000000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data; - when others => ipif_IP2Bus_Data <= (others => '0'); - end case; - - end process IP2BUS_DATA_MUX_PROC; - - ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck or intr_IP2Bus_WrAck; - ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck; - ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error or intr_IP2Bus_Error; - - user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); - user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); - -end IMP; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/std_functions.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/std_functions.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/std_functions.vhd (nonexistent) @@ -1,81 +0,0 @@ ----------------------------------------------------------------------- ----- std_functions ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- package with standard functions used in this project ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package std_functions is - function max(L, R: INTEGER) return INTEGER; - function min(L, R: INTEGER) return INTEGER; - function log2 (val: INTEGER) return natural; -end std_functions; - -package body std_functions is - function max(L, R: INTEGER) return INTEGER is - begin - if L > R then - return L; - else - return R; - end if; - end; - - function min(L, R: INTEGER) return INTEGER is - begin - if L < R then - return L; - else - return R; - end if; - end; - - function log2 (val: INTEGER) return natural is - variable res : natural; - begin - for i in 0 to 31 loop - if (val <= (2**i)) then - res := i; - exit; - end if; - end loop; - return res; - end function Log2; -end std_functions; \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_multiplier.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_multiplier.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_multiplier.vhd (nonexistent) @@ -1,204 +0,0 @@ ----------------------------------------------------------------------- ----- mont_multiplier ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- n-bit montgomery multiplier with a pipelined systolic ---- ----- array ---- ----- ---- ----- Dependencies: ---- ----- - x_shift_reg ---- ----- - adder_n ---- ----- - d_flip_flop ---- ----- - sys_pipeline ---- ----- - cell_1b_adder ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- Structural description of the montgommery multiply pipeline --- contains the x operand shift register, my adder, the pipeline and --- reduction adder. To do a multiplication, the following actions must take place: --- --- * load in the x operand in the shift register using the xy bus and load_x --- * place the y operand on the xy bus for the rest of the operation --- * generate a start pulse of 1 clk cycle long on start --- * wait for ready signal --- * result is avaiable on the r bus --- -entity mont_multiplier is - generic ( - n : integer := 1536; -- width of the operands - t : integer := 96; -- total number of stages (minimum 2) - tl : integer := 32; -- lower number of stages (minimum 1) - split : boolean := true -- if true the pipeline wil be split in 2 parts, - -- if false there are no lower stages, only t counts - ); - port ( - -- clock input - core_clk : in std_logic; - -- operand inputs - xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand - m : in std_logic_vector((n-1) downto 0); -- modulus - -- result output - r : out std_logic_vector((n-1) downto 0); -- result - -- control signals - start : in std_logic; - reset : in std_logic; - p_sel : in std_logic_vector(1 downto 0); - load_x : in std_logic; - ready : out std_logic - ); -end mont_multiplier; - -architecture Structural of mont_multiplier is - constant s : integer := n/t; -- stage width (# bits) - constant nl : integer := s*tl; -- lower pipeline width (# bits) - constant nh : integer := n - nl; -- higher pipeline width (# bits) - - signal reset_multiplier : std_logic; - signal start_multiplier : std_logic; - - signal p_sel_i : std_logic_vector(1 downto 0); - signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part - signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part - - signal next_xi : std_logic; - signal xi : std_logic; - - signal start_first_stage : std_logic; - -begin - - -- multiplier is reset every calculation or reset - reset_multiplier <= reset or start; - - -- start is delayed 1 cycle - delay_1_cycle : d_flip_flop - port map( - core_clk => core_clk, - reset => reset, - din => start, - dout => start_multiplier - ); - - -- register to store the x value in - -- outputs the operand in serial using a shift register - x_selection : x_shift_reg - generic map( - n => n, - t => t, - tl => tl - ) - port map( - clk => core_clk, - reset => reset, - x_in => xy, - load_x => load_x, - next_x => next_xi, - p_sel => p_sel_i, - xi => xi - ); - ----------------------------------------- --- SINGLE PIPELINE ASSIGNMENTS ----------------------------------------- -single_pipeline : if split=false generate - p_sel_i <= "11"; - t_sel <= t; - n_sel <= n-1; -end generate; - ----------------------------------------- --- SPLIT PIPELINE ASSIGNMENTS ----------------------------------------- -split_pipeline : if split=true generate - -- this module controls the pipeline operation - -- width in stages for selected pipeline - with p_sel select - t_sel <= tl when "01", -- lower pipeline part - t-tl when "10", -- higher pipeline part - t when others; -- full pipeline - - -- width in bits for selected pipeline - with p_sel select - n_sel <= nl-1 when "01", -- lower pipeline part - nh-1 when "10", -- higher pipeline part - n-1 when others; -- full pipeline - - p_sel_i <= p_sel; -end generate; - - -- stepping control logic to keep track off the multiplication and when it is done - stepping_control : stepping_logic - generic map( - n => n, -- max nr of steps required to complete a multiplication - t => t -- total nr of steps in the pipeline - ) - port map( - core_clk => core_clk, - start => start_multiplier, - reset => reset_multiplier, - t_sel => t_sel, - n_sel => n_sel, - start_first_stage => start_first_stage, - stepping_done => ready - ); - - systolic_array : sys_pipeline - generic map( - n => n, - t => t, - tl => tl, - split => split - ) - port map( - core_clk => core_clk, - y => xy, - m => m, - xi => xi, - next_x => next_xi, - start => start_first_stage, - reset => reset_multiplier, - p_sel => p_sel_i, - r => r - ); - -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_mem.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_mem.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_mem.vhd (nonexistent) @@ -1,148 +0,0 @@ ----------------------------------------------------------------------- ----- operand_mem ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- BRAM memory and logic to the store 4 (1536-bit) operands ---- ----- and the modulus for the montgomery multiplier ---- ----- ---- ----- Dependencies: ---- ----- - operand_ram ---- ----- - modulus_ram ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - - -entity operand_mem is - generic( - n : integer := 1536 - ); - port( - -- data interface (plb side) - data_in : in std_logic_vector(31 downto 0); - data_out : out std_logic_vector(31 downto 0); - rw_address : in std_logic_vector(8 downto 0); - write_enable : in std_logic; - -- address structure: - -- bit: 8 -> '1': modulus - -- '0': operands - -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0' - -- don't care in case of modulus - -- bits: 5-0 -> modulus_addr / operand_addr resp. - - -- operand interface (multiplier side) - op_sel : in std_logic_vector(1 downto 0); - xy_out : out std_logic_vector((n-1) downto 0); - m : out std_logic_vector((n-1) downto 0); - result_in : in std_logic_vector((n-1) downto 0); - -- control signals - load_result : in std_logic; - result_dest_op : in std_logic_vector(1 downto 0); - collision : out std_logic; - -- system clock - clk : in std_logic - ); -end operand_mem; - - -architecture Behavioral of operand_mem is - signal xy_data_i : std_logic_vector(31 downto 0); - signal xy_addr_i : std_logic_vector(5 downto 0); - signal operand_in_sel_i : std_logic_vector(1 downto 0); - signal collision_i : std_logic; - - signal xy_out_i : std_logic_vector(1535 downto 0); - signal m_i : std_logic_vector(1535 downto 0); - signal result_in_i : std_logic_vector(1535 downto 0); - signal load_op : std_logic; - - signal m_addr_i : std_logic_vector(5 downto 0); - signal load_m : std_logic; - signal m_data_i : std_logic_vector(31 downto 0); - -begin - - -- map outputs - xy_out <= xy_out_i((n-1) downto 0); - m <= m_i((n-1) downto 0); - result_in_i((n-1) downto 0) <= result_in; - collision <= collision_i; - - -- map inputs - xy_addr_i <= rw_address(5 downto 0); - m_addr_i <= rw_address(5 downto 0); - operand_in_sel_i <= rw_address(7 downto 6); - xy_data_i <= data_in; - m_data_i <= data_in; - - load_op <= write_enable when (rw_address(8) = '0') else '0'; - load_m <= write_enable when (rw_address(8) = '1') else '0'; - - -- xy operand storage - xy_ram : operand_ram - port map( - clk => clk, - collision => collision_i, - operand_addr => xy_addr_i, - operand_in => xy_data_i, - operand_in_sel => operand_in_sel_i, - result_out => data_out, - write_operand => load_op, - operand_out => xy_out_i, - operand_out_sel => op_sel, - result_dest_op => result_dest_op, - write_result => load_result, - result_in => result_in_i - ); - - -- modulus storage - m_ram : modulus_ram - port map( - clk => clk, - modulus_addr => m_addr_i, - write_modulus => load_m, - modulus_in => m_data_i, - modulus_out => m_i - ); - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/modulus_ram.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/modulus_ram.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/modulus_ram.vhd (nonexistent) @@ -1,113 +0,0 @@ ----------------------------------------------------------------------- ----- modulus_ram ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- BRAM memory and logic to store the 1536-bit modulus ---- ----- ---- ----- Dependencies: ---- ----- - operands_sp (coregen) ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - - -entity modulus_ram is - port( - clk : in std_logic; - modulus_addr : in std_logic_vector(5 downto 0); - write_modulus : in std_logic; - modulus_in : in std_logic_vector(31 downto 0); - modulus_out : out std_logic_vector(1535 downto 0) - ); -end modulus_ram; - - -architecture Behavioral of modulus_ram is - signal part_enable : std_logic_vector(3 downto 0); - signal wea : std_logic_vector(3 downto 0); - signal addra : std_logic_vector(4 downto 0); -begin - - -- the blockram has a write depth of 2 but we only use the lower half - addra <= '0' & modulus_addr(3 downto 0); - - -- the two highest bits of the address are used to select the bloc - with modulus_addr(5 downto 4) select - part_enable <= "0001" when "00", - "0010" when "01", - "0100" when "10", - "1000" when others; - - with write_modulus select - wea <= part_enable when '1', - "0000" when others; - - -- 4 instances of 512 bits blockram - modulus_0 : operands_sp - port map ( - clka => clk, - wea => wea(0 downto 0), - addra => addra, - dina => modulus_in, - douta => modulus_out(511 downto 0) - ); - - modulus_1 : operands_sp - port map ( - clka => clk, - wea => wea(1 downto 1), - addra => addra, - dina => modulus_in, - douta => modulus_out(1023 downto 512) - ); - - modulus_2 : operands_sp - port map ( - clka => clk, - wea => wea(2 downto 2), - addra => addra, - dina => modulus_in, - douta => modulus_out(1535 downto 1024) - ); - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_ram.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_ram.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_ram.vhd (nonexistent) @@ -1,168 +0,0 @@ ----------------------------------------------------------------------- ----- operand_ram ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- BRAM memory and logic to the store 4 (1536-bit) operands ---- ----- for the montgomery multiplier ---- ----- ---- ----- Dependencies: ---- ----- - operand_dp (coregen) ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - - -entity operand_ram is - port( -- write_operand_ack voorzien? - -- global ports - clk : in std_logic; - collision : out std_logic; - -- bus side connections (32-bit serial) - operand_addr : in std_logic_vector(5 downto 0); - operand_in : in std_logic_vector(31 downto 0); - operand_in_sel : in std_logic_vector(1 downto 0); - result_out : out std_logic_vector(31 downto 0); - write_operand : in std_logic; - -- multiplier side connections (1536 bit parallel) - result_dest_op : in std_logic_vector(1 downto 0); - operand_out : out std_logic_vector(1535 downto 0); - operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side - write_result : in std_logic; - result_in : in std_logic_vector(1535 downto 0) - ); -end operand_ram; - - -architecture Behavioral of operand_ram is - -- port a signals - signal addra : std_logic_vector(5 downto 0); - signal part_enable : std_logic_vector(3 downto 0); - signal wea : std_logic_vector(3 downto 0); - signal write_operand_i : std_logic; - - -- port b signals - signal addrb : std_logic_vector(5 downto 0); - signal web : std_logic_vector(0 downto 0); - signal doutb0 : std_logic_vector(31 downto 0); - signal doutb1 : std_logic_vector(31 downto 0); - signal doutb2 : std_logic_vector(31 downto 0); - -begin - - -- WARNING: Very Important! - -- wea & web signals must never be high at the same time !! - -- web has priority - write_operand_i <= write_operand and not write_result; - web(0) <= write_result; - collision <= write_operand and write_result; - - -- the dual port ram has a depth of 4 (each layer contains an operand) - -- result is always stored in position 3 - -- doutb is always result - with write_operand_i select - addra <= operand_in_sel & operand_addr(3 downto 0) when '1', - operand_out_sel & "0000" when others; - - with operand_addr(5 downto 4) select - part_enable <= "0001" when "00", - "0010" when "01", - "0100" when "10", - "1000" when others; - - with write_operand_i select - wea <= part_enable when '1', - "0000" when others; - - -- we can only read back from the result (stored in result_dest_op) - addrb <= result_dest_op & operand_addr(3 downto 0); - - - with operand_addr(5 downto 4) select - result_out <= doutb0 when "00", - doutb1 when "01", - doutb2 when others; - - -- 3 instances of a dual port ram to store the parts of the operand - op_0 : operand_dp - port map ( - clka => clk, - wea => wea(0 downto 0), - addra => addra, - dina => operand_in, - douta => operand_out(511 downto 0), - clkb => clk, - web => web, - addrb => addrb, - dinb => result_in(511 downto 0), - doutb => doutb0 - ); - - op_1 : operand_dp - port map ( - clka => clk, - wea => wea(1 downto 1), - addra => addra, - dina => operand_in, - douta => operand_out(1023 downto 512), - clkb => clk, - web => web, - addrb => addrb, - dinb => result_in(1023 downto 512), - doutb => doutb1 - ); - - op_2 : operand_dp - port map ( - clka => clk, - wea => wea(2 downto 2), - addra => addra, - dina => operand_in, - douta => operand_out(1535 downto 1024), - clkb => clk, - web => web, - addrb => addrb, - dinb => result_in(1535 downto 1024), - doutb => doutb2 - ); - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/adder_block.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/adder_block.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/adder_block.vhd (nonexistent) @@ -1,106 +0,0 @@ ----------------------------------------------------------------------- ----- adder_block ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- Adder block with a flipflop for the carry out so result ---- ----- is available after 1 clock cycle ---- ----- for use in the montgommery multiplier pre and post ---- ----- computation adders ---- ----- ---- ----- Dependencies: ---- ----- - cell_1b_adder ---- ----- - d_flip_flop ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- (width)-bit full adder block using cell_1b_adders --- with buffered carry out -> result after 1 clock cycle -entity adder_block is - generic ( - width : integer := 32 --adder operand widths - ); - port ( - -- clock input - core_clk : in std_logic; - -- adder input operands a, b (width)-bit - a : in std_logic_vector((width-1) downto 0); - b : in std_logic_vector((width-1) downto 0); - -- carry in, out - cin : in std_logic; - cout : out std_logic; - -- adder result out (width)-bit - r : out std_logic_vector((width-1) downto 0) - ); -end adder_block; - - -architecture Structural of adder_block is - -- vector for the carry bits - signal carry : std_logic_vector(width downto 0); -begin - -- carry in - carry(0) <= cin; - - -- structure of (width) cell_1b_adders - adder_chain : for i in 0 to (width-1) generate - adders : cell_1b_adder - port map( - a => a(i), - b => b(i), - cin => carry(i), - cout => carry(i+1), - r => r(i) - ); - end generate; - - -- buffer the carry every clock cycle - carry_reg : d_flip_flop - port map( - core_clk => core_clk, - reset => '0', - din => carry(width), - dout => cout - ); - -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_mux.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_mux.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_mux.vhd (nonexistent) @@ -1,78 +0,0 @@ ----------------------------------------------------------------------- ----- cel_1b_mux ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 1-bit mux for a standard cell in the montgommery ---- ----- multiplier systolic array ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- 1-bit mux for a standard cell in the montgommery multiplier systolic array -entity cell_1b_mux is - port ( - -- input bits - my : in std_logic; - y : in std_logic; - m : in std_logic; - -- selection bits - x : in std_logic; - q : in std_logic; - -- mux out - result : out std_logic - ); -end cell_1b_mux; - - -architecture Behavioral of cell_1b_mux is - signal sel : std_logic_vector(1 downto 0); -begin - -- selection bits - sel <= x & q; - -- multipexer - with sel select - result <= my when "11", - y when "10", - m when "01", - '0' when others; - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/autorun_cntrl.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/autorun_cntrl.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/autorun_cntrl.vhd (nonexistent) @@ -1,185 +0,0 @@ ----------------------------------------------------------------------- ----- autorun_ctrl ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- autorun control unit for a pipelined montgomery ---- ----- multiplier ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - - -entity autorun_cntrl is - port ( - clk : in std_logic; - reset : in std_logic; - start : in std_logic; - done : out std_logic; - op_sel : out std_logic_vector (1 downto 0); - start_multiplier : out std_logic; - multiplier_done : in std_logic; - read_buffer : out std_logic; - buffer_din : in std_logic_vector (31 downto 0); - buffer_empty : in std_logic - ); -end autorun_cntrl; - - -architecture Behavioral of autorun_cntrl is - - signal bit_counter_i : integer range 0 to 15 := 0; - signal bit_counter_0_i : std_logic; - signal bit_counter_15_i : std_logic; - signal next_bit_i : std_logic := '0'; - - signal start_cycle_i : std_logic := '0'; - signal start_cycle_del_i : std_logic; - - signal done_i : std_logic; - signal running_i : std_logic; - - signal start_multiplier_i : std_logic; - signal start_multiplier_del_i : std_logic; - signal mult_done_del_i : std_logic; - - signal e0_i : std_logic_vector(15 downto 0); - signal e1_i : std_logic_vector(15 downto 0); - signal e0_bit_i : std_logic; - signal e1_bit_i : std_logic; - signal e_bits_i : std_logic_vector(1 downto 0); - signal e_bits_0_i : std_logic; - signal cycle_counter_i : std_logic; - signal op_sel_sel_i : std_logic; - signal op_sel_i : std_logic_vector(1 downto 0); -begin - - done <= done_i; - - -- the two exponents - e0_i <= buffer_din(15 downto 0); - e1_i <= buffer_din(31 downto 16); - - -- generate the index to select a single bit from the two exponents - SYNC_BIT_COUNTER: process (clk, reset) - begin - if reset = '1' then - bit_counter_i <= 15; - elsif rising_edge(clk) then - if start = '1' then -- make sure we start @ bit 0 - bit_counter_i <= 15; - elsif next_bit_i = '1' then -- count - if bit_counter_i = 0 then - bit_counter_i <= 15; - else - bit_counter_i <= bit_counter_i - 1; - end if; - end if; - end if; - end process SYNC_BIT_COUNTER; - -- signal when bit_counter_i = 0 - bit_counter_0_i <= '1' when bit_counter_i=0 else '0'; - bit_counter_15_i <= '1' when bit_counter_i=15 else '0'; - -- the bits... - e0_bit_i <= e0_i(bit_counter_i); - e1_bit_i <= e1_i(bit_counter_i); - e_bits_i <= e0_bit_i & e1_bit_i; - e_bits_0_i <= '1' when (e_bits_i = "00") else '0'; - - -- operand pre-select - with e_bits_i select - op_sel_i <= "00" when "10", -- gt0 - "01" when "01", -- gt1 - "10" when "11", -- gt01 - "11" when others; - - -- select operands - op_sel_sel_i <= '0' when e_bits_0_i = '1' else (cycle_counter_i); - op_sel <= op_sel_i when op_sel_sel_i = '1' else "11"; - - -- process that drives running_i signal ('1' when in autorun, '0' when not) - RUNNING_PROC: process(clk, reset) - begin - if reset = '1' then - running_i <= '0'; - elsif rising_edge(clk) then - running_i <= start or (running_i and (not done_i)); - end if; - end process RUNNING_PROC; - - -- ctrl logic - start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i)); - read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15' - start_multiplier <= start_multiplier_del_i and running_i; - - -- start/stop logic - start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal) - done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty - next_bit_i <= (mult_done_del_i and e_bits_0_i) or (mult_done_del_i and (not e_bits_0_i) and (not cycle_counter_i)); - - -- process for delaying signals with 1 clock cycle - DEL_PROC: process(clk) - begin - if rising_edge(clk) then - start_multiplier_del_i <= start_multiplier_i; - start_cycle_del_i <= start_cycle_i; - mult_done_del_i <= multiplier_done; - end if; - end process DEL_PROC; - - -- process for delaying signals with 1 clock cycle - CYCLE_CNTR_PROC: process(clk, start, reset) - begin - if start = '1' or reset = '1' then - cycle_counter_i <= '0'; - elsif rising_edge(clk) then - if (e_bits_0_i = '0') and (multiplier_done = '1') then - cycle_counter_i <= not cycle_counter_i; - elsif (e_bits_0_i = '1') and (multiplier_done = '1') then - cycle_counter_i <= '0'; - else - cycle_counter_i <= cycle_counter_i; - end if; - end if; - end process CYCLE_CNTR_PROC; - -end Behavioral; - Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_adder.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_adder.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b_adder.vhd (nonexistent) @@ -1,74 +0,0 @@ ----------------------------------------------------------------------- ----- cell_1b_adder ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- This file contains the implementation of a 1-bit full ---- ----- adder cell using combinatorial logic ---- ----- used in adder_block ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- 1-bit full adder cell -entity cell_1b_adder is - port ( - -- input operands a, b - a : in std_logic; - b : in std_logic; - -- carry in, out - cin : in std_logic; - cout : out std_logic; - -- result out - r : out std_logic - ); -end cell_1b_adder; - - -architecture Behavioral of cell_1b_adder is - signal a_xor_b : std_logic; -begin - -- 1-bit full adder with combinatorial logic - -- uses 2 XOR's, 2 AND's and 1 OR port - a_xor_b <= a xor b; - r <= a_xor_b xor cin; - cout <= (a and b) or (cin and a_xor_b); -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_stage.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_stage.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_stage.vhd (nonexistent) @@ -1,226 +0,0 @@ ----------------------------------------------------------------------- ----- sys_stage ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- stage for use in the montgommery multiplier pipelined ---- ----- systolic array ---- ----- ---- ----- Dependencies: ---- ----- - adder_block ---- ----- - standard_cell_block ---- ----- - d_flip_flop ---- ----- - register_n ---- ----- - register_1b ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - -entity sys_stage is - generic( - width : integer := 32 -- width of the stage - ); - port( - -- clock input - core_clk : in std_logic; - -- modulus and y operand input (width)-bit - y : in std_logic_vector((width-1) downto 0); - m : in std_logic_vector((width) downto 0); - my_cin : in std_logic; - my_cout : out std_logic; - -- q and x operand input (serial input) - xin : in std_logic; - qin : in std_logic; - -- q and x operand output (serial output) - xout : out std_logic; - qout : out std_logic; - -- msb input (lsb from next stage, for shift right operation) - a_msb : in std_logic; - a_0 : out std_logic; - -- carry out(clocked) and in - cin : in std_logic; - cout : out std_logic; - -- reduction adder carry's - red_cin : in std_logic; - red_cout : out std_logic; - -- control singals - start : in std_logic; - reset : in std_logic; - done : out std_logic; - -- result out - r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result - r : out std_logic_vector((width-1) downto 0) - ); -end sys_stage; - -architecture Structural of sys_stage is - signal my : std_logic_vector((width-1) downto 0); - signal m_inv : std_logic_vector((width-1) downto 0); - signal a : std_logic_vector((width-1) downto 0); - signal cell_result : std_logic_vector((width-1) downto 0); - signal cell_result_reg : std_logic_vector((width-1) downto 0); - signal red_r : std_logic_vector((width-1) downto 0); - - signal cout_i : std_logic; - -begin - - -- my adder - ------------ - my_adder : adder_block - generic map ( - width => width - ) - port map( - core_clk => core_clk, - a => m(width downto 1), - b => y, - cin => my_cin, - cout => my_cout, - r => my - ); - - - -- systolic pipeline cells - --------------------------- - a <= a_msb & cell_result_reg((width-1) downto 1); - a_0 <= cell_result_reg(0); - sys_cells : standard_cell_block - generic map ( - width => width - ) - port map ( - -- modulus and y operand input (width)-bit - my => my, - y => y, - m => m(width downto 1), - -- q and x operand input (serial input) - x => xin, - q => qin, - -- previous result in (width)-bit - a => a, - -- carry in and out - cin => cin, - cout => cout_i, - -- result out (width)-bit - r => cell_result - ); - - -- cell result register (width)-bit - result_reg : register_n - generic map( - width => width - ) - port map( - core_clk => core_clk, - ce => start, - reset => reset, - din => cell_result, - dout => cell_result_reg - ); - - - -- result reduction - -------------------- - m_inv <= not(m(width-1 downto 0)); - - reduction_adder : adder_block - generic map ( - width => width - ) - port map( - core_clk => core_clk, - a => m_inv, - b => cell_result_reg, - cin => red_cin, - cout => red_cout, - r => red_r - ); - - with r_sel select - r <= cell_result_reg when '0', - red_r when others; - - - -- stage clocked outputs - ------------------------- - -- stage done signal - -- 1 cycle after start of stage - done_signal : d_flip_flop - port map( - core_clk => core_clk, - reset => reset, - din => start, - dout => done - ); - - -- xout register - xout_reg : register_1b - port map( - core_clk => core_clk, - ce => start, - reset => reset, - din => xin, - dout => xout - ); - - -- qout register - qout_reg : register_1b - port map( - core_clk => core_clk, - ce => start, - reset => reset, - din => qin, - dout => qout - ); - - -- carry out register - cout_reg : register_1b - port map( - core_clk => core_clk, - ce => start, - reset => reset, - din => cout_i, - dout => cout - ); - -end Structural; - Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_first_cell_logic.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_first_cell_logic.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_first_cell_logic.vhd (nonexistent) @@ -1,97 +0,0 @@ ----------------------------------------------------------------------- ----- sys_first_cell_logic ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- first cell logic for use int the montogommery mulitplier ---- ----- pipelined systolic array ---- ----- ---- ----- Dependencies: ---- ----- - register_n ---- ----- - cell_1b_adder ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- logic needed as the first piece in the systolic array pipeline --- calculates the first my_cout and generates q signal -entity sys_first_cell_logic is - port ( - m0 : in std_logic; -- lsb from m operand - y0 : in std_logic; -- lsb from y operand - my_cout : out std_logic; -- my_cin for first stage - xi : in std_logic; -- xi operand input - xout : out std_logic; -- xin for first stage - qout : out std_logic; -- qin for first stage - cout : out std_logic; -- cin for first stage - a_0 : in std_logic; -- a_0 from first stage - red_cout : out std_logic -- red_cin for first stage - ); -end sys_first_cell_logic; - -architecture Behavorial of sys_first_cell_logic is - -- first cell signals - signal my0_mux_result : std_logic; - signal my0 : std_logic; - signal qout_i : std_logic; -begin - -- half adder for m0 +y0 - my0 <= m0 xor y0; - my_cout <= m0 and y0; -- carry - - xout <= xi; - qout_i <= (xi and y0) xor a_0; - cout <= my0_mux_result and a_0; - red_cout <= '1'; -- add 1 for 2s complement - - my0_mux : cell_1b_mux - port map( - my => my0, - m => m0, - y => y0, - x => xi, - q => qout_i, - result => my0_mux_result - ); - - qout <= qout_i; - -end Behavorial; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_n.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_n.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_n.vhd (nonexistent) @@ -1,81 +0,0 @@ ----------------------------------------------------------------------- ----- register_n ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- n bit register with active high asynchronious reset and ce---- ----- used in montgommery multiplier systolic array stages ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- n-bit register with asynchronous reset and clock enable -entity register_n is - generic( - width : integer := 4 - ); - port( - core_clk : in std_logic; -- clock input - ce : in std_logic; -- clock enable (active high) - reset : in std_logic; -- reset (active high) - din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit - dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit - ); -end register_n; - - -architecture Behavorial of register_n is -begin - -- process for (width)-bit register - reg_nb : process (reset, ce, core_clk, din) - begin - if reset='1' then -- asynchronous active high reset - dout <= (others=>'0'); - else - if rising_edge(core_clk) then -- clock in data on rising edge - if ce='1' then -- active high clock enable to clock in data - dout <= din; - end if; - end if; - end if; - end process; - -end Behavorial; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/cell_1b.vhd (nonexistent) @@ -1,102 +0,0 @@ ----------------------------------------------------------------------- ----- cell_1b ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 1-bit cell for use in the montgommery multiplier systolic ---- ----- array ---- ----- ---- ----- Dependencies: ---- ----- - cell_1bit_adder ---- ----- - cell_1bit_mux ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- 1-bit cell for the systolic array -entity cell_1b is - port ( - -- operand input bits (m+y, y and m) - my : in std_logic; - y : in std_logic; - m : in std_logic; - -- operand x input bit and q - x : in std_logic; - q : in std_logic; - -- previous result input bit - a : in std_logic; - -- carry's - cin : in std_logic; - cout : out std_logic; - -- cell result out - r : out std_logic - ); -end cell_1b; - - -architecture Structural of cell_1b is - -- mux to adder connection - signal mux2adder : std_logic; -begin - - -- mux for my, y and m input bits - cell_mux : cell_1b_mux - port map( - my => my, - y => y, - m => m, - x => x, - q => q, - result => mux2adder - ); - - -- full adder for a+mux2adder - cell_adder : cell_1b_adder - port map( - a => a, - b => mux2adder, - cin => cin, - cout => cout, - r => r - ); - -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_ctrl.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_ctrl.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mont_ctrl.vhd (nonexistent) @@ -1,197 +0,0 @@ ----------------------------------------------------------------------- ----- mont_ctrl ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- control unit for a pipelined montgomery multiplier, with ---- ----- split pipeline operation and "auto-run" support ---- ----- ---- ----- Dependencies: ---- ----- - autorun_cntrl ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - - --- This module controls the montgommery mutliplier and controls traffic between --- RAM and multiplier. Also contains the autorun logic for exponentiations. -entity mont_ctrl is - port ( - clk : in std_logic; - reset : in std_logic; - -- bus side - start : in std_logic; - x_sel_single : in std_logic_vector(1 downto 0); - y_sel_single : in std_logic_vector(1 downto 0); - run_auto : in std_logic; - op_buffer_empty : in std_logic; - op_sel_buffer : in std_logic_vector(31 downto 0); - read_buffer : out std_logic; - done : out std_logic; - calc_time : out std_logic; - -- multiplier side - op_sel : out std_logic_vector(1 downto 0); - load_x : out std_logic; - load_result : out std_logic; - start_multiplier : out std_logic; - multiplier_ready : in std_logic - ); -end mont_ctrl; - - -architecture Behavioral of mont_ctrl is - signal start_d : std_logic; -- delayed version of start input - signal start_pulse : std_logic; - signal auto_start_pulse : std_logic; - signal start_multiplier_i : std_logic; - signal start_up_counter : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start - - signal calc_time_i : std_logic; -- high ('1') during multiplication - - signal x_sel : std_logic_vector(1 downto 0); -- the operand used as x input - signal y_sel : std_logic_vector(1 downto 0); -- the operand used as y input - signal x_sel_buffer : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun) - - signal auto_done : std_logic; - signal start_auto : std_logic; - signal auto_multiplier_done_i : std_logic; - -begin - - ----------------------------------------------------------------------------------- - -- Processes related to starting and stopping the multiplier - ----------------------------------------------------------------------------------- - -- generate a start pulse (duration 1 clock cycle) based on ext. start sig - START_PULSE_PROC: process(clk) - begin - if rising_edge(clk) then - start_d <= start; - end if; - end process START_PULSE_PROC; - start_pulse <= start and (not start_d); - start_auto <= start_pulse and run_auto; - - -- to start the multiplier we first need to select the x_operand and - -- clock it in the x shift register - -- the we select the y_operand and start the multiplier - - -- start_up_counter - -- default state : "100" - -- at start pulse counter resets to 0 and counts up to "100" - START_MULT_PROC: process(clk, reset) - begin - if reset = '1' then - start_up_counter <= "100"; - elsif rising_edge(clk) then - if start_pulse = '1' or auto_start_pulse = '1' then - start_up_counter <= "000"; - elsif start_up_counter(2) /= '1' then - start_up_counter <= start_up_counter + '1'; - else - start_up_counter <= "100"; - end if; - end if; - end process; - - -- select operands (autorun/single run) - x_sel <= x_sel_buffer when (run_auto = '1') else x_sel_single; - y_sel <= "11" when (run_auto = '1') else y_sel_single; -- y is operand3 in auto mode - - -- clock operands to operand_mem output (first x, then y) - with start_up_counter(2 downto 1) select - op_sel <= x_sel when "00", -- start_up_counter="00x" (first 2 cycles) - y_sel when others; -- - load_x <= start_up_counter(0) and (not start_up_counter(1)); -- latch x operand if start_up_counter="x01" - - -- start multiplier when start_up_counter="x11" - start_multiplier_i <= start_up_counter(1) and start_up_counter(0); - start_multiplier <= start_multiplier_i; - - -- signal calc time is high during multiplication - CALC_TIME_PROC: process(clk, reset) - begin - if reset = '1' then - calc_time_i <= '0'; - elsif rising_edge(clk) then - if start_multiplier_i = '1' then - calc_time_i <= '1'; - elsif multiplier_ready = '1' then - calc_time_i <= '0'; - else - calc_time_i <= calc_time_i; - end if; - end if; - end process CALC_TIME_PROC; - calc_time <= calc_time_i; - - -- what happens when a multiplication has finished - load_result <= multiplier_ready; - -- ignore multiplier_ready when in automode, the logic will assert auto_done when finished - done <= ((not run_auto) and multiplier_ready) or auto_done; - - ----------------------------------------------------------------------------------- - -- Processes related to op_buffer cntrl and auto_run mode - -- start_auto -> start autorun mode operation - -- auto_start_pulse <- autorun logic starts the multiplier - -- auto_done <- autorun logic signals when autorun operation has finished - -- x_sel_buffer <- autorun logic determines which operand is used as x - - -- check buffer empty signal - ----------------------------------------------------------------------------------- - - -- multiplier_ready is only passed to autorun control when in autorun mode - auto_multiplier_done_i <= (multiplier_ready and run_auto); - - autorun_control_logic : autorun_cntrl port map( - clk => clk, - reset => reset, - start => start_auto, - done => auto_done, - op_sel => x_sel_buffer, - start_multiplier => auto_start_pulse, - multiplier_done => auto_multiplier_done_i, - read_buffer => read_buffer, - buffer_din => op_sel_buffer, - buffer_empty => op_buffer_empty - ); - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/x_shift_reg.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/x_shift_reg.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/x_shift_reg.vhd (nonexistent) @@ -1,100 +0,0 @@ ----------------------------------------------------------------------- ----- x_shift_reg ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- n bit shift register for the x operand of the multiplier ---- ----- with bit output ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- shift register for the x operand of the multiplier --- outputs the lsb of the register or bit at offset according to the --- selected pipeline part -entity x_shift_reg is - generic( - n : integer := 1536; -- width of the operands (# bits) - t : integer := 48; -- total number of stages - tl : integer := 16 -- lower number of stages - ); - port( - -- clock input - clk : in std_logic; - -- x operand in (n-bit) - x_in : in std_logic_vector((n-1) downto 0); - -- control signals - reset : in std_logic; -- reset, clears register - load_x : in std_logic; -- load operand into shift register - next_x : in std_logic; -- next bit of x - p_sel : in std_logic_vector(1 downto 0); -- pipeline selection - -- x operand bit out (serial) - xi : out std_logic - ); -end x_shift_reg; - - -architecture Behavioral of x_shift_reg is - signal x_reg : std_logic_vector((n-1) downto 0); -- register - constant s : integer := n/t; -- stage width - constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline -begin - - REG_PROC: process(reset, clk) - begin - if reset = '1' then -- Reset, clear the register - x_reg <= (others => '0'); - elsif rising_edge(clk) then - if load_x = '1' then -- Load_x, load the register with x_in - x_reg <= x_in; - elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in - x_reg((n-2) downto 0) <= x_reg((n-1) downto 1); - else -- else remember state - x_reg <= x_reg; - end if; - end if; - end process; - - with p_sel select -- pipeline select - xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline - x_reg(0) when others; -- use LS bit for lower part of pipeline - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_pipeline.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_pipeline.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_pipeline.vhd (nonexistent) @@ -1,314 +0,0 @@ ----------------------------------------------------------------------- ----- sys_pipeline ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- the pipelined systolic array for a montgommery multiplier ---- ----- ---- ----- Dependencies: ---- ----- - sys_stage ---- ----- - register_n ---- ----- - d_flip_flop ---- ----- - cell_1b_adder ---- ----- - cell_1b_mux ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- the pipelined systolic array for a montgommery multiplier --- contains a structural description of the pipeline using the systolic stages -entity sys_pipeline is - generic( - n : integer := 1536; -- width of the operands (# bits) - t : integer := 192; -- total number of stages (minimum 2) - tl : integer := 64; -- lower number of stages (minimum 1) - split : boolean := true -- if true the pipeline wil be split in 2 parts, - -- if false there are no lower stages, only t counts - ); - port( - -- clock input - core_clk : in std_logic; - -- modulus and y opperand input (n)-bit - y : in std_logic_vector((n-1) downto 0); - m : in std_logic_vector((n-1) downto 0); - -- x operand input (serial) - xi : in std_logic; - next_x : out std_logic; -- next x operand bit - -- control signals - start : in std_logic; -- start multiplier - reset : in std_logic; - p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used - -- result out - r : out std_logic_vector((n-1) downto 0) - ); -end sys_pipeline; - -architecture Structural of sys_pipeline is - constant s : integer := n/t; - - signal m_i : std_logic_vector(n downto 0); - signal y_i : std_logic_vector(n downto 0); - - -- systolic stages signals - signal my_cin_stage : std_logic_vector((t-1) downto 0); - signal my_cout_stage : std_logic_vector((t-1) downto 0); - signal xin_stage : std_logic_vector((t-1) downto 0); - signal qin_stage : std_logic_vector((t-1) downto 0); - signal xout_stage : std_logic_vector((t-1) downto 0); - signal qout_stage : std_logic_vector((t-1) downto 0); - signal a_msb_stage : std_logic_vector((t-1) downto 0); - signal a_0_stage : std_logic_vector((t-1) downto 0); - signal cin_stage : std_logic_vector((t-1) downto 0); - signal cout_stage : std_logic_vector((t-1) downto 0); - signal red_cin_stage : std_logic_vector((t-1) downto 0); - signal red_cout_stage : std_logic_vector((t-1) downto 0); - signal start_stage : std_logic_vector((t-1) downto 0); - signal done_stage : std_logic_vector((t-1) downto 0); - signal r_sel_stage : std_logic_vector((t-1) downto 0); - - -- end logic signals - signal r_sel_end : std_logic; - - -- signals needed if pipeline is split - --------------------------------------- - signal r_sel_l : std_logic; - signal r_sel_h : std_logic; - -- mid end logic signals - signal a_0_midend : std_logic; - signal r_sel_midend : std_logic; - - -- mid start logic signals - signal my_cout_midstart : std_logic; - signal xout_midstart : std_logic; - signal qout_midstart : std_logic; - signal cout_midstart : std_logic; - signal red_cout_midstart : std_logic; - - -begin - - m_i <= '0' & m; - y_i <= '0' & y; - - -- generate the stages for the full pipeline - pipeline_stages : for i in 0 to (t-1) generate - stage : sys_stage - generic map( - width => s - ) - port map( - core_clk => core_clk, - y => y_i((i+1)*s downto (i*s)+1), - m => m_i((i+1)*s downto (i*s)), - my_cin => my_cin_stage(i), - my_cout => my_cout_stage(i), - xin => xin_stage(i), - qin => qin_stage(i), - xout => xout_stage(i), - qout => qout_stage(i), - a_0 => a_0_stage(i), - a_msb => a_msb_stage(i), - cin => cin_stage(i), - cout => cout_stage(i), - red_cin => red_cin_stage(i), - red_cout => red_cout_stage(i), - start => start_stage(i), - reset => reset, - done => done_stage(i), - r_sel => r_sel_stage(i), - r => r(((i+1)*s)-1 downto (i*s)) - ); - end generate; - - -- first cell logic - -------------------- - first_cell : sys_first_cell_logic - port map ( - m0 => m_i(0), - y0 => y_i(0), - my_cout => my_cin_stage(0), - xi => xi, - xout => xin_stage(0), - qout => qin_stage(0), - cout => cin_stage(0), - a_0 => a_0_stage(0), - red_cout => red_cin_stage(0) - ); - - -- last cell logic - ------------------- - last_cell : sys_last_cell_logic - port map ( - core_clk => core_clk, - reset => reset, - a_0 => a_msb_stage(t-1), - cin => cout_stage(t-1), - red_cin => red_cout_stage(t-1), - r_sel => r_sel_end, - start => done_stage(t-1) - ); - ------------------------------------- --- SINGLE PART PIPELINE CONNECTIONS ------------------------------------- -single_pipeline : if split=false generate - -- link stages to eachother - stage_connect : for i in 1 to (t-1) generate - my_cin_stage(i) <= my_cout_stage(i-1); - cin_stage(i) <= cout_stage(i-1); - xin_stage(i) <= xout_stage(i-1); - qin_stage(i) <= qout_stage(i-1); - red_cin_stage(i) <= red_cout_stage(i-1); - start_stage(i) <= done_stage(i-1); - a_msb_stage(i-1) <= a_0_stage(i); - r_sel_stage(i) <= r_sel_end; - end generate; - r_sel_stage(0) <= r_sel_end; - - start_stage(0) <= start; - next_x <= done_stage(0); -end generate; - ----------------------------------------- --- SPLIT PIPELINE CONNECTIONS AND LOGIC ----------------------------------------- -split_pipeline : if split=true generate - -- only start first stage if lower part is used - with p_sel select - start_stage(0) <= '0' when "10", - start when others; - - -- select start or midstart stage for requesting new xi bit - with p_sel select - next_x <= done_stage(tl) when "10", - done_stage(0) when others; - - -- link lower stages to eachother - stage_connect_l : for i in 1 to (tl-1) generate - my_cin_stage(i) <= my_cout_stage(i-1); - cin_stage(i) <= cout_stage(i-1); - xin_stage(i) <= xout_stage(i-1); - qin_stage(i) <= qout_stage(i-1); - red_cin_stage(i) <= red_cout_stage(i-1); - start_stage(i) <= done_stage(i-1); - a_msb_stage(i-1) <= a_0_stage(i); - r_sel_stage(i) <= r_sel_l; - end generate; - r_sel_stage(0) <= r_sel_l; - - -- mid end logic - ----------------- - mid_end_cell : sys_last_cell_logic - port map ( - core_clk => core_clk, - reset => reset, - a_0 => a_0_midend, - cin => cout_stage(tl-1), - red_cin => red_cout_stage(tl-1), - r_sel => r_sel_midend, - start => done_stage(tl-1) - ); - --muxes for midend signals - with p_sel select - a_msb_stage(tl-1) <= a_0_midend when "01", - a_0_stage(tl) when others; - - -- mid start logic - ------------------- - mid_start_logic : sys_first_cell_logic - port map ( - m0 => m_i(tl*s), - y0 => y_i(tl*s), - my_cout => my_cout_midstart, - xi => xi, - xout => xout_midstart, - qout => qout_midstart, - cout => cout_midstart, - a_0 => a_0_stage(tl), - red_cout => red_cout_midstart - ); - - -- only start stage tl if only higher part is used - with p_sel select - start_stage(tl) <= start when "10", - done_stage(tl-1) when "11", - '0' when others; - - with p_sel select - my_cin_stage(tl) <= my_cout_midstart when "10", - my_cout_stage(tl-1) when others; - with p_sel select - xin_stage(tl) <= xout_midstart when "10", - xout_stage(tl-1) when others; - with p_sel select - qin_stage(tl) <= qout_midstart when "10", - qout_stage(tl-1) when others; - with p_sel select - cin_stage(tl) <= cout_midstart when "10", - cout_stage(tl-1) when others; - with p_sel select - red_cin_stage(tl) <= red_cout_midstart when "10", - red_cout_stage(tl-1) when others; - - -- link higher stages to eachother - stage_connect_h : for i in (tl+1) to (t-1) generate - my_cin_stage(i) <= my_cout_stage(i-1); - cin_stage(i) <= cout_stage(i-1); - xin_stage(i) <= xout_stage(i-1); - qin_stage(i) <= qout_stage(i-1); - red_cin_stage(i) <= red_cout_stage(i-1); - start_stage(i) <= done_stage(i-1); - a_msb_stage(i-1) <= a_0_stage(i); - r_sel_stage(i) <= r_sel_h; - end generate; - r_sel_stage(tl) <= r_sel_h; - - with p_sel select - r_sel_l <= r_sel_midend when "01", - r_sel_end when "11", - '0' when others; - - with p_sel select - r_sel_h <= '0' when "01", - r_sel_end when others; -end generate; - -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_pkg.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_pkg.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_pkg.vhd (nonexistent) @@ -1,629 +0,0 @@ ----------------------------------------------------------------------- ----- mod_sim_exp_pkg ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- Package for the Modular Simultaneous Exponentiation Core ---- ----- Project. Contains the component declarations and used ---- ----- constants. ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -package mod_sim_exp_pkg is - -------------------------------------------------------------------- - ---------------------- COMPONENT DECLARATIONS ---------------------- - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- d_flip_flop - -------------------------------------------------------------------- - -- 1-bit D flip-flop with asynchronous active high reset - -- - component d_flip_flop is - port( - core_clk : in std_logic; -- clock signal - reset : in std_logic; -- active high reset - din : in std_logic; -- data in - dout : out std_logic -- data out - ); - end component d_flip_flop; - - -------------------------------------------------------------------- - -- register_1b - -------------------------------------------------------------------- - -- 1-bit register with asynchronous reset and clock enable - -- - component register_1b is - port( - core_clk : in std_logic; -- clock input - ce : in std_logic; -- clock enable (active high) - reset : in std_logic; -- reset (active high) - din : in std_logic; -- data in - dout : out std_logic -- data out - ); - end component register_1b; - - -------------------------------------------------------------------- - -- register_n - -------------------------------------------------------------------- - -- n-bit register with asynchronous reset and clock enable - -- - component register_n is - generic( - width : integer := 4 - ); - port( - core_clk : in std_logic; -- clock input - ce : in std_logic; -- clock enable (active high) - reset : in std_logic; -- reset (active high) - din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit - dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit - ); - end component register_n; - - -------------------------------------------------------------------- - -- cell_1b_adder - -------------------------------------------------------------------- - -- 1-bit full adder cell using combinatorial logic - -- - component cell_1b_adder is - port ( - -- input operands a, b - a : in std_logic; - b : in std_logic; - -- carry in, out - cin : in std_logic; - cout : out std_logic; - -- result out - r : out std_logic - ); - end component cell_1b_adder; - - -------------------------------------------------------------------- - -- cell_1b_mux - -------------------------------------------------------------------- - -- 1-bit mux for a standard cell in the montgommery multiplier - -- systolic array - -- - component cell_1b_mux is - port ( - -- input bits - my : in std_logic; - y : in std_logic; - m : in std_logic; - -- selection bits - x : in std_logic; - q : in std_logic; - -- mux out - result : out std_logic - ); - end component cell_1b_mux; - - -------------------------------------------------------------------- - -- cell_1b - -------------------------------------------------------------------- - -- 1-bit cell for the systolic array - -- - component cell_1b is - port ( - -- operand input bits (m+y, y and m) - my : in std_logic; - y : in std_logic; - m : in std_logic; - -- operand x input bit and q - x : in std_logic; - q : in std_logic; - -- previous result input bit - a : in std_logic; - -- carry's - cin : in std_logic; - cout : out std_logic; - -- cell result out - r : out std_logic - ); - end component cell_1b; - - -------------------------------------------------------------------- - -- adder_block - -------------------------------------------------------------------- - -- (width)-bit full adder block using cell_1b_adders with buffered - -- carry out - -- - component adder_block is - generic ( - width : integer := 32 --adder operand widths - ); - port ( - -- clock input - core_clk : in std_logic; - -- adder input operands a, b (width)-bit - a : in std_logic_vector((width-1) downto 0); - b : in std_logic_vector((width-1) downto 0); - -- carry in, out - cin : in std_logic; - cout : out std_logic; - -- adder result out (width)-bit - r : out std_logic_vector((width-1) downto 0) - ); - end component adder_block; - - -------------------------------------------------------------------- - -- standard_cell_block - -------------------------------------------------------------------- - -- a standard cell block of (width)-bit for the montgommery multiplier - -- systolic array - -- - component standard_cell_block is - generic ( - width : integer := 16 - ); - port ( - -- modulus and y operand input (width)-bit - my : in std_logic_vector((width-1) downto 0); - y : in std_logic_vector((width-1) downto 0); - m : in std_logic_vector((width-1) downto 0); - -- q and x operand input (serial input) - x : in std_logic; - q : in std_logic; - -- previous result in (width)-bit - a : in std_logic_vector((width-1) downto 0); - -- carry in and out - cin : in std_logic; - cout : out std_logic; - -- result out (width)-bit - r : out std_logic_vector((width-1) downto 0) - ); - end component standard_cell_block; - - -------------------------------------------------------------------- - -- counter_sync - -------------------------------------------------------------------- - -- counter with synchronous count enable. It generates an - -- overflow when max_value is reached - -- - component counter_sync is - generic( - max_value : integer := 1024 -- maximum value (constraints the nr bits for counter) - ); - port( - reset_value : in integer; -- value the counter counts to - core_clk : in std_logic; -- clock input - ce : in std_logic; -- count enable - reset : in std_logic; -- reset input - overflow : out std_logic -- gets high when counter reaches reset_value - ); - end component counter_sync; - - -------------------------------------------------------------------- - -- stepping_logic - -------------------------------------------------------------------- - -- stepping logic for the pipeline, generates the start pulses for the - -- first stage and keeps track of when the last stages are done - -- - component stepping_logic is - generic( - n : integer := 1536; -- max nr of steps required to complete a multiplication - t : integer := 192 -- total nr of steps in the pipeline - ); - port( - core_clk : in std_logic; -- clock input - start : in std_logic; -- start signal for pipeline (one multiplication) - reset : in std_logic; -- reset signal - t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece - n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication - start_first_stage : out std_logic; -- start pulse output for first stage - stepping_done : out std_logic -- done signal - ); - end component stepping_logic; - - -------------------------------------------------------------------- - -- x_shift_reg - -------------------------------------------------------------------- - -- shift register for the x operand of the multiplier - -- outputs the lsb of the register or bit at offset according to the - -- selected pipeline part - -- - component x_shift_reg is - generic( - n : integer := 1536; -- width of the operands (# bits) - t : integer := 48; -- total number of stages - tl : integer := 16 -- lower number of stages - ); - port( - -- clock input - clk : in std_logic; - -- x operand in (n-bit) - x_in : in std_logic_vector((n-1) downto 0); - -- control signals - reset : in std_logic; -- reset, clears register - load_x : in std_logic; -- load operand into shift register - next_x : in std_logic; -- next bit of x - p_sel : in std_logic_vector(1 downto 0); -- pipeline selection - -- x operand bit out (serial) - xi : out std_logic - ); - end component x_shift_reg; - - -------------------------------------------------------------------- - -- mod_sim_exp_core - -------------------------------------------------------------------- - -- toplevel of the modular simultaneous exponentiation core - -- contains an operand and modulus ram, multiplier, an exponent fifo - -- and control logic - -- - component mod_sim_exp_core is - generic( - C_NR_BITS_TOTAL : integer := 1536; - C_NR_STAGES_TOTAL : integer := 96; - C_NR_STAGES_LOW : integer := 32; - C_SPLIT_PIPELINE : boolean := true - ); - port( - clk : in std_logic; - reset : in std_logic; - -- operand memory interface (plb shared memory) - write_enable : in std_logic; -- write data to operand ram - data_in : in std_logic_vector (31 downto 0); -- operand ram data in - rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus - data_out : out std_logic_vector (31 downto 0); -- operand ram data out - collision : out std_logic; -- write collision - -- op_sel fifo interface - fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in - fifo_push : in std_logic; -- push data in exponent fifo - fifo_full : out std_logic; -- high if fifo is full - fifo_nopush : out std_logic; -- high if error during push - -- control signals - start : in std_logic; -- start multiplication/exponentiation - exp_m : in std_logic; -- single multiplication if low, exponentiation if high - ready : out std_logic; -- calculations done - x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection - y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection - dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection - p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection - calc_time : out std_logic - ); - end component mod_sim_exp_core; - - component autorun_cntrl is - port ( - clk : in std_logic; - reset : in std_logic; - start : in std_logic; - done : out std_logic; - op_sel : out std_logic_vector (1 downto 0); - start_multiplier : out std_logic; - multiplier_done : in std_logic; - read_buffer : out std_logic; - buffer_din : in std_logic_vector (31 downto 0); - buffer_empty : in std_logic - ); - end component autorun_cntrl; - - component fifo_primitive is - port ( - clk : in std_logic; - din : in std_logic_vector (31 downto 0); - dout : out std_logic_vector (31 downto 0); - empty : out std_logic; - full : out std_logic; - push : in std_logic; - pop : in std_logic; - reset : in std_logic; - nopop : out std_logic; - nopush : out std_logic - ); - end component fifo_primitive; - - -------------------------------------------------------------------- - -- fifo_generic - -------------------------------------------------------------------- - -- a behavorial implementation of a fifo - -- - component fifo_generic is - generic ( - depth : integer := 32 - ); - port ( - clk : in std_logic; -- clock input - din : in std_logic_vector (31 downto 0); -- 32 bit input data for push - dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop - empty : out std_logic; -- empty flag, 1 when FIFO is empty - full : out std_logic; -- full flag, 1 when FIFO is full - push : in std_logic; - pop : in std_logic; - reset : in std_logic; - nopop : out std_logic; - nopush : out std_logic - ); - end component fifo_generic; - - - component modulus_ram is - port( - clk : in std_logic; - modulus_addr : in std_logic_vector(5 downto 0); - write_modulus : in std_logic; - modulus_in : in std_logic_vector(31 downto 0); - modulus_out : out std_logic_vector(1535 downto 0) - ); - end component modulus_ram; - - -------------------------------------------------------------------- - -- mont_ctrl - -------------------------------------------------------------------- - -- This module controls the montgommery mutliplier and controls traffic between - -- RAM and multiplier. Also contains the autorun logic for exponentiations. - -- - component mont_ctrl is - port ( - clk : in std_logic; - reset : in std_logic; - -- bus side - start : in std_logic; - x_sel_single : in std_logic_vector(1 downto 0); - y_sel_single : in std_logic_vector(1 downto 0); - run_auto : in std_logic; - op_buffer_empty : in std_logic; - op_sel_buffer : in std_logic_vector(31 downto 0); - read_buffer : out std_logic; - done : out std_logic; - calc_time : out std_logic; - -- multiplier side - op_sel : out std_logic_vector(1 downto 0); - load_x : out std_logic; - load_result : out std_logic; - start_multiplier : out std_logic; - multiplier_ready : in std_logic - ); - end component mont_ctrl; - - component operand_dp is - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(5 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0); - clkb : in std_logic; - web : in std_logic_vector(0 downto 0); - addrb : in std_logic_vector(5 downto 0); - dinb : in std_logic_vector(511 downto 0); - doutb : out std_logic_vector(31 downto 0) - ); - end component operand_dp; - - component operand_mem is - generic( - n : integer := 1536 - ); - port( - -- data interface (plb side) - data_in : in std_logic_vector(31 downto 0); - data_out : out std_logic_vector(31 downto 0); - rw_address : in std_logic_vector(8 downto 0); - write_enable : in std_logic; - -- address structure: - -- bit: 8 -> '1': modulus - -- '0': operands - -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0' - -- don't care in case of modulus - -- bits: 5-0 -> modulus_addr / operand_addr resp. - - -- operand interface (multiplier side) - op_sel : in std_logic_vector(1 downto 0); - xy_out : out std_logic_vector((n-1) downto 0); - m : out std_logic_vector((n-1) downto 0); - result_in : in std_logic_vector((n-1) downto 0); - -- control signals - load_result : in std_logic; - result_dest_op : in std_logic_vector(1 downto 0); - collision : out std_logic; - -- system clock - clk : in std_logic - ); - end component operand_mem; - - component operand_ram is - port( -- write_operand_ack voorzien? - -- global ports - clk : in std_logic; - collision : out std_logic; - -- bus side connections (32-bit serial) - operand_addr : in std_logic_vector(5 downto 0); - operand_in : in std_logic_vector(31 downto 0); - operand_in_sel : in std_logic_vector(1 downto 0); - result_out : out std_logic_vector(31 downto 0); - write_operand : in std_logic; - -- multiplier side connections (1536 bit parallel) - result_dest_op : in std_logic_vector(1 downto 0); - operand_out : out std_logic_vector(1535 downto 0); - operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side - write_result : in std_logic; - result_in : in std_logic_vector(1535 downto 0) - ); - end component operand_ram; - - component operands_sp is - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(4 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0) - ); - end component operands_sp; - - - component sys_stage is - generic( - width : integer := 32 -- width of the stage - ); - port( - -- clock input - core_clk : in std_logic; - -- modulus and y operand input (width)-bit - y : in std_logic_vector((width-1) downto 0); - m : in std_logic_vector((width) downto 0); - my_cin : in std_logic; - my_cout : out std_logic; - -- q and x operand input (serial input) - xin : in std_logic; - qin : in std_logic; - -- q and x operand output (serial output) - xout : out std_logic; - qout : out std_logic; - -- msb input (lsb from next stage, for shift right operation) - a_msb : in std_logic; - a_0 : out std_logic; - -- carry out(clocked) and in - cin : in std_logic; - cout : out std_logic; - -- reduction adder carry's - red_cin : in std_logic; - red_cout : out std_logic; - -- control singals - start : in std_logic; - reset : in std_logic; - done : out std_logic; - -- result out - r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result - r : out std_logic_vector((width-1) downto 0) - ); - end component sys_stage; - - -------------------------------------------------------------------- - -- sys_last_cell_logic - -------------------------------------------------------------------- - -- logic needed as the last piece in the systolic array pipeline - -- calculates the last 2 bits of the cell_result and finishes the reduction - -- also generates the result selection signal - -- - component sys_last_cell_logic is - port ( - core_clk : in std_logic; -- clock input - reset : in std_logic; - a_0 : out std_logic; -- a_msb for last stage - cin : in std_logic; -- cout from last stage - red_cin : in std_logic; -- red_cout from last stage - r_sel : out std_logic; -- result selection bit - start : in std_logic -- done signal from last stage - ); - end component sys_last_cell_logic; - - -------------------------------------------------------------------- - -- sys_first_cell_logic - -------------------------------------------------------------------- - -- logic needed as the first piece in the systolic array pipeline - -- calculates the first my_cout and generates q signal - -- - component sys_first_cell_logic is - port ( - m0 : in std_logic; -- lsb from m operand - y0 : in std_logic; -- lsb from y operand - my_cout : out std_logic; -- my_cin for first stage - xi : in std_logic; -- xi operand input - xout : out std_logic; -- xin for first stage - qout : out std_logic; -- qin for first stage - cout : out std_logic; -- cin for first stage - a_0 : in std_logic; -- a_0 from first stage - red_cout : out std_logic -- red_cin for first stage - ); - end component sys_first_cell_logic; - - -------------------------------------------------------------------- - -- sys_pipeline - -------------------------------------------------------------------- - -- the pipelined systolic array for a montgommery multiplier - -- contains a structural description of the pipeline using the systolic stages - -- - component sys_pipeline is - generic( - n : integer := 1536; -- width of the operands (# bits) - t : integer := 192; -- total number of stages (minimum 2) - tl : integer := 64; -- lower number of stages (minimum 1) - split : boolean := true -- if true the pipeline wil be split in 2 parts, - -- if false there are no lower stages, only t counts - ); - port( - -- clock input - core_clk : in std_logic; - -- modulus and y opperand input (n)-bit - y : in std_logic_vector((n-1) downto 0); - m : in std_logic_vector((n-1) downto 0); - -- x operand input (serial) - xi : in std_logic; - next_x : out std_logic; -- next x operand bit - -- control signals - start : in std_logic; -- start multiplier - reset : in std_logic; - p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used - -- result out - r : out std_logic_vector((n-1) downto 0) - ); - end component sys_pipeline; - - component mont_multiplier is - generic ( - n : integer := 1536; -- width of the operands - t : integer := 96; -- total number of stages (minimum 2) - tl : integer := 32; -- lower number of stages (minimum 1) - split : boolean := true -- if true the pipeline wil be split in 2 parts, - -- if false there are no lower stages, only t counts - ); - port ( - -- clock input - core_clk : in std_logic; - -- operand inputs - xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand - m : in std_logic_vector((n-1) downto 0); -- modulus - -- result output - r : out std_logic_vector((n-1) downto 0); -- result - -- control signals - start : in std_logic; - reset : in std_logic; - p_sel : in std_logic_vector(1 downto 0); - load_x : in std_logic; - ready : out std_logic - ); - end component mont_multiplier; - -end package mod_sim_exp_pkg; \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/stepping_logic.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/stepping_logic.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/stepping_logic.vhd (nonexistent) @@ -1,166 +0,0 @@ ----------------------------------------------------------------------- ----- stepping_logic ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- stepping logic to control the pipeline for one ---- ----- montgommery multiplication ---- ----- ---- ----- Dependencies: ---- ----- - d_flip_flop ---- ----- - counter_sync ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - - --- stepping logic for the pipeline, generates the start pulses for the --- first stage and keeps track of when the last stages are done -entity stepping_logic is - generic( - n : integer := 1536; -- max nr of steps required to complete a multiplication - t : integer := 192 -- total nr of steps in the pipeline - ); - port( - core_clk : in std_logic; -- clock input - start : in std_logic; -- start signal for pipeline (one multiplication) - reset : in std_logic; -- reset signal - t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece - n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication - start_first_stage : out std_logic; -- start pulse output for first stage - stepping_done : out std_logic -- done signal - ); -end stepping_logic; - - -architecture Behavioral of stepping_logic is - - -- signals for the first stage control, pulses and counters - signal first_stage_done : std_logic; -- indicates the first stage is done running for this multiplication - signal first_stage_active : std_logic; -- indicates the first stage is active - signal first_stage_active_d : std_logic; -- delayed version of first_stage_active - signal start_first_stage_i : std_logic; -- internal version of start_first_stage output - - -- signals for the last stages control and counter - signal last_stages_done : std_logic; -- indicates the last stages are done running for this multiplication - signal last_stages_active : std_logic; -- indicates the last stages are active - signal last_stages_active_d : std_logic; -- delayed version of last_stages_active - -begin - - -- map outputs - stepping_done <= last_stages_done; - - -- internal signals - -------------------- - -- first_stage_active signal gets active from a start pulse - -- inactive from first_stage_done pulse - first_stage_active <= start or (first_stage_active_d and not first_stage_done); - - -- done signal gets active from a first_stage_done pulse - -- inactive from last_stages_done pulse - last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done); - - -- map start_first_stage_i to output, but also use the initial start pulse - start_first_stage <= start or start_first_stage_i; - - last_stages_active_delay : d_flip_flop - port map( - core_clk => core_clk, - reset => reset, - din => last_stages_active, - dout => last_stages_active_d - ); - - first_stage_active_delay : d_flip_flop - port map( - core_clk => core_clk, - reset => reset, - din => first_stage_active, - dout => first_stage_active_d - ); - - -- the counters - ---------------- - - -- for counting the last steps (waiting for the other stages to stop) - -- counter for keeping track of how many stages are done - laststeps_counter : counter_sync - generic map( - max_value => t - ) - port map( - reset_value => t_sel, - core_clk => core_clk, - ce => last_stages_active, - reset => reset, - overflow => last_stages_done - ); - - -- counter for keeping track of how many times the first stage is started - -- counts bits in operand x till operand width then generates pulse on first_stage_done - steps_counter : counter_sync - generic map( - max_value => n - ) - port map( - reset_value => (n_sel), - core_clk => core_clk, - ce => start_first_stage_i, - reset => reset, - overflow => first_stage_done - ); - - -- the output (overflow) of this counter starts the first stage every 2 clock cycles - substeps_counter : counter_sync - generic map( - max_value => 2 - ) - port map( - reset_value => 2, - core_clk => core_clk, - ce => first_stage_active, - reset => reset, - overflow => start_first_stage_i - ); - -end Behavioral; \ No newline at end of file Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_1b.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_1b.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/register_1b.vhd (nonexistent) @@ -1,79 +0,0 @@ ----------------------------------------------------------------------- ----- register_1b ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 1 bit register with active high asynchronious reset and ce---- ----- used in montgommery multiplier systolic array stages ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- 1-bit register with asynchronous reset and clock enable -entity register_1b is - port( - core_clk : in std_logic; -- clock input - ce : in std_logic; -- clock enable (active high) - reset : in std_logic; -- reset (active high) - din : in std_logic; -- data in - dout : out std_logic -- data out - ); -end register_1b; - - -architecture Behavorial of register_1b is -begin - - -- process for 1-bit register - reg_1b : process (reset, ce, core_clk, din) - begin - if reset='1' then -- asynchronous active high reset - dout <= '0'; - else - if rising_edge(core_clk) then -- clock in data on rising edge - if ce='1' then -- active high clock enable to clock in data - dout <= din; - end if; - end if; - end if; - end process; - -end Behavorial; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/standard_cell_block.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/standard_cell_block.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/standard_cell_block.vhd (nonexistent) @@ -1,105 +0,0 @@ ----------------------------------------------------------------------- ----- standard_cell_block ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- a block of (width) cell_1b cells for use in the ---- ----- montgommery multiplier systolic array ---- ----- ---- ----- Dependencies: ---- ----- - cell_1b ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- a standard cell block of (width)-bit for the montgommery multiplier --- systolic array -entity standard_cell_block is - generic ( - width : integer := 16 - ); - port ( - -- modulus and y operand input (width)-bit - my : in std_logic_vector((width-1) downto 0); - y : in std_logic_vector((width-1) downto 0); - m : in std_logic_vector((width-1) downto 0); - -- q and x operand input (serial input) - x : in std_logic; - q : in std_logic; - -- previous result in (width)-bit - a : in std_logic_vector((width-1) downto 0); - -- carry in and out - cin : in std_logic; - cout : out std_logic; - -- result out (width)-bit - r : out std_logic_vector((width-1) downto 0) - ); -end standard_cell_block; - - -architecture Structural of standard_cell_block is - -- vector for the carry bits - signal carry : std_logic_vector(width downto 0); -begin - - -- carry in - carry(0) <= cin; - - -- structure of (width) 1-bit cells - cell_block : for i in 0 to (width-1) generate - cells : cell_1b - port map( - my => my(i), - y => y(i), - m => m(i), - x => x, - q => q, - a => a(i), - cin => carry(i), - cout => carry(i+1), - r => r(i) - ); - end generate; - - -- carry out - cout <= carry(width); -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_primitive.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_primitive.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_primitive.vhd (nonexistent) @@ -1,143 +0,0 @@ ----------------------------------------------------------------------- ----- fifo_primitive ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 512 x 32 bit fifo ---- ----- ---- ----- Dependencies: ---- ----- - FIFO18E1 (xilinx primitive) ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- Xilinx primitives used in this code. -library UNISIM; -use UNISIM.VComponents.all; - - -entity fifo_primitive is - port ( - clk : in std_logic; - din : in std_logic_vector (31 downto 0); - dout : out std_logic_vector (31 downto 0); - empty : out std_logic; - full : out std_logic; - push : in std_logic; - pop : in std_logic; - reset : in std_logic; - nopop : out std_logic; - nopush : out std_logic - ); -end fifo_primitive; - - -architecture Behavioral of fifo_primitive is - signal rdcount : std_logic_vector(11 downto 0); -- debugging - signal wrcount : std_logic_vector(11 downto 0); -- debugging - - signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic; -begin - - empty <= empty_i; - full <= full_i; - - -- these logical equations need to be extended where necessary - nopop <= rderr_i or (pop and reset_i); - nopush <= wrerr_i or (push and reset_i); - - pop_i <= pop and (not reset_i); - push_i <= push and (not reset_i); - - -- makes the reset at least three clk_cycles long - RESET_PROC: process (reset, clk) - variable clk_counter : integer range 0 to 3 := 3; - begin - if reset = '1' then - reset_i <= '1'; - clk_counter := 3; - elsif rising_edge(clk) then - if clk_counter = 0 then - clk_counter := 0; - reset_i <= '0'; - else - clk_counter := clk_counter - 1; - reset_i <= '1'; - end if; - end if; - end process; - - FIFO18E1_inst : FIFO18E1 - generic map ( - ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold - ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold - DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36 - DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE" - EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE") - FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36 - FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE" - INIT => X"000000000", -- Initial values on output port - SRVAL => X"000000000" -- Set/Reset value for output port - ) - port map ( - -- ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag - -- ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag - DO => dout, -- 32-bit data output - -- DOP => DOP, -- 4-bit parity data output - EMPTY => empty_i, -- 1-bit empty output flag - FULL => full_i, -- 1-bit full output flag - -- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers - RDCOUNT => RDCOUNT, -- 12-bit read count output - WRCOUNT => WRCOUNT, -- 12-bit write count output - -- WRERR, RDERR: 1-bit (each) FIFO full or empty error - RDERR => rderr_i, -- 1-bit read error output - WRERR => wrerr_i, -- 1-bit write error - DI => din, -- 32-bit data input - DIP => "0000", -- 4-bit parity input - RDEN => pop_i, -- 1-bit read enable input - REGCE => '1', -- 1-bit clock enable input - RST => reset_i, -- 1-bit reset input - RSTREG => reset_i, -- 1-bit output register set/reset - -- WRCLK, RDCLK: 1-bit (each) Clocks - RDCLK => clk, -- 1-bit read clock input - WRCLK => clk, -- 1-bit write clock input - WREN => push_i -- 1-bit write enable input - ); - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_core.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_core.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_core.vhd (nonexistent) @@ -1,197 +0,0 @@ ----------------------------------------------------------------------- ----- mod_sim_exp_core ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- toplevel of a modular simultaneous exponentiation core ---- ----- using a pipelined montgommery multiplier with split ---- ----- pipeline and auto-run support ---- ----- ---- ----- Dependencies: ---- ----- - mont_mult_sys_pipeline ---- ----- - operand_mem ---- ----- - fifo_primitive ---- ----- - mont_ctrl ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- toplevel of the modular simultaneous exponentiation core --- contains an operand and modulus ram, multiplier, an exponent fifo --- and control logic -entity mod_sim_exp_core is - generic( - C_NR_BITS_TOTAL : integer := 1536; - C_NR_STAGES_TOTAL : integer := 96; - C_NR_STAGES_LOW : integer := 32; - C_SPLIT_PIPELINE : boolean := true - ); - port( - clk : in std_logic; - reset : in std_logic; - -- operand memory interface (plb shared memory) - write_enable : in std_logic; -- write data to operand ram - data_in : in std_logic_vector (31 downto 0); -- operand ram data in - rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus - data_out : out std_logic_vector (31 downto 0); -- operand ram data out - collision : out std_logic; -- write collision - -- op_sel fifo interface - fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in - fifo_push : in std_logic; -- push data in exponent fifo - fifo_full : out std_logic; -- high if fifo is full - fifo_nopush : out std_logic; -- high if error during push - -- control signals - start : in std_logic; -- start multiplication/exponentiation - exp_m : in std_logic; -- single multiplication if low, exponentiation if high - ready : out std_logic; -- calculations done - x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection - y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection - dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection - p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection - calc_time : out std_logic - ); -end mod_sim_exp_core; - - -architecture Structural of mod_sim_exp_core is - -- data busses - signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier - signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier - signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier - - -- control signals - signal op_sel : std_logic_vector(1 downto 0); -- operand selection - signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand - signal mult_ready : std_logic; - signal start_mult : std_logic; - signal load_x : std_logic; - signal load_result : std_logic; - - -- fifo signals - signal fifo_empty : std_logic; - signal fifo_pop : std_logic; - signal fifo_nopop : std_logic; - signal fifo_dout : std_logic_vector(31 downto 0); -begin - - -- The actual multiplier - the_multiplier : mont_multiplier - generic map( - n => C_NR_BITS_TOTAL, - t => C_NR_STAGES_TOTAL, - tl => C_NR_STAGES_LOW, - split => C_SPLIT_PIPELINE - ) - port map( - core_clk => clk, - xy => xy, - m => m, - r => r, - start => start_mult, - reset => reset, - p_sel => p_sel, - load_x => load_x, - ready => mult_ready - ); - - -- Block ram memory for storing the operands and the modulus - the_memory : operand_mem - generic map( - n => C_NR_BITS_TOTAL - ) - port map( - data_in => data_in, - data_out => data_out, - rw_address => rw_address, - write_enable => write_enable, - op_sel => op_sel, - xy_out => xy, - m => m, - result_in => r, - load_result => load_result, - result_dest_op => result_dest_op, - collision => collision, - clk => clk - ); - - result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3 - - -- A fifo for auto-run operand selection - the_exponent_fifo : fifo_generic - generic map( - depth => 8 -- depth needs to be at least C_NR_EXP_BITS_MAX/16 - ) - port map( - clk => clk, - din => fifo_din, - dout => fifo_dout, - empty => fifo_empty, - full => fifo_full, - push => fifo_push, - pop => fifo_pop, - reset => reset, - nopop => fifo_nopop, - nopush => fifo_nopush - ); - - -- The control logic for the core - the_control_unit : mont_ctrl - port map( - clk => clk, - reset => reset, - start => start, - x_sel_single => x_sel_single, - y_sel_single => y_sel_single, - run_auto => exp_m, - op_buffer_empty => fifo_empty, - op_sel_buffer => fifo_dout, - read_buffer => fifo_pop, - done => ready, - calc_time => calc_time, - op_sel => op_sel, - load_x => load_x, - load_result => load_result, - start_multiplier => start_mult, - multiplier_ready => mult_ready - ); - -end Structural; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/counter_sync.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/counter_sync.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/counter_sync.vhd (nonexistent) @@ -1,94 +0,0 @@ ----------------------------------------------------------------------- ----- counter_sync ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- counter with synchronous count enable. It generates an ---- ----- overflow when max_value is reached ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- counter with synchronous count enable. It generates an --- overflow when max_value is reached -entity counter_sync is - generic( - max_value : integer := 1024 -- maximum value (constraints the nr bits for counter) - ); - port( - reset_value : in integer; -- value the counter counts to - core_clk : in std_logic; -- clock input - ce : in std_logic; -- count enable - reset : in std_logic; -- reset input - overflow : out std_logic -- gets high when counter reaches reset_value - ); -end counter_sync; - - -architecture Behavioral of counter_sync is -begin - - -- counter process with asynchronous active high reset - count_proc: process(core_clk, reset) - variable steps_counter : integer range 0 to max_value-1; - begin - if reset = '1' then -- reset counter - steps_counter := 0; - overflow <= '0'; - elsif rising_edge(core_clk) then - -- counter is enabled, count till reset_value - if ce = '1' then - if steps_counter = (reset_value-1) then -- generate overflow and reset counter - steps_counter := 0; - overflow <= '1'; - else -- just count - steps_counter := steps_counter + 1; - overflow <= '0'; - end if; - else - --counter disabled, halt counter - overflow <= '0'; - steps_counter := steps_counter; - end if; - end if; - end process; - -end Behavioral; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_dp.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_dp.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operand_dp.vhd (nonexistent) @@ -1,195 +0,0 @@ ----------------------------------------------------------------------- ----- operand_dp ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 4 x 512 bit dual port ram for the operands ---- ----- 32 bit read and write for bus side and 512 bit read and ---- ----- write for multiplier side ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- ----------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2009 Xilinx, Inc. -- --- All rights reserved. -- ----------------------------------------------------------------------- --- You must compile the wrapper file operand_dp.vhd when simulating --- the core, operand_dp. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - - -library ieee; -use ieee.std_logic_1164.ALL; --- synthesis translate_off -library XilinxCoreLib; --- synthesis translate_on - - -entity operand_dp is - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(5 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0); - clkb : in std_logic; - web : in std_logic_vector(0 downto 0); - addrb : in std_logic_vector(5 downto 0); - dinb : in std_logic_vector(511 downto 0); - doutb : out std_logic_vector(31 downto 0) - ); -end operand_dp; - - -architecture operand_dp_a of operand_dp is --- synthesis translate_off - component wrapped_operand_dp - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(5 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0); - clkb : in std_logic; - web : in std_logic_vector(0 downto 0); - addrb : in std_logic_vector(5 downto 0); - dinb : in std_logic_vector(511 downto 0); - doutb : out std_logic_vector(31 downto 0) - ); - end component; - --- Configuration specification - for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) - generic map( - c_has_regceb => 0, - c_has_regcea => 0, - c_mem_type => 2, - c_rstram_b => 0, - c_rstram_a => 0, - c_has_injecterr => 0, - c_rst_type => "SYNC", - c_prim_type => 1, - c_read_width_b => 32, - c_initb_val => "0", - c_family => "virtex6", - c_read_width_a => 512, - c_disable_warn_bhv_coll => 0, - c_write_mode_b => "WRITE_FIRST", - c_init_file_name => "no_coe_file_loaded", - c_write_mode_a => "WRITE_FIRST", - c_mux_pipeline_stages => 0, - c_has_mem_output_regs_b => 0, - c_has_mem_output_regs_a => 0, - c_load_init_file => 0, - c_xdevicefamily => "virtex6", - c_write_depth_b => 4, - c_write_depth_a => 64, - c_has_rstb => 0, - c_has_rsta => 0, - c_has_mux_output_regs_b => 0, - c_inita_val => "0", - c_has_mux_output_regs_a => 0, - c_addra_width => 6, - c_addrb_width => 6, - c_default_data => "0", - c_use_ecc => 0, - c_algorithm => 1, - c_disable_warn_bhv_range => 0, - c_write_width_b => 512, - c_write_width_a => 32, - c_read_depth_b => 64, - c_read_depth_a => 4, - c_byte_size => 9, - c_sim_collision_check => "ALL", - c_common_clk => 0, - c_wea_width => 1, - c_has_enb => 0, - c_web_width => 1, - c_has_ena => 0, - c_use_byte_web => 0, - c_use_byte_wea => 0, - c_rst_priority_b => "CE", - c_rst_priority_a => "CE", - c_use_default_data => 0 - ); --- synthesis translate_on -begin --- synthesis translate_off - U0 : wrapped_operand_dp - port map ( - clka => clka, - wea => wea, - addra => addra, - dina => dina, - douta => douta, - clkb => clkb, - web => web, - addrb => addrb, - dinb => dinb, - doutb => doutb - ); --- synthesis translate_on - -end operand_dp_a; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operands_sp.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operands_sp.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/operands_sp.vhd (nonexistent) @@ -1,180 +0,0 @@ ----------------------------------------------------------------------- ----- operands_sp ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 512 bit single port ram for the modulus ---- ----- 32 write for bus side and 512 bit read for multplier side ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- ----------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2009 Xilinx, Inc. -- --- All rights reserved. -- ----------------------------------------------------------------------- --- You must compile the wrapper file operand_dp.vhd when simulating --- the core, operand_dp. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - - -library ieee; -use ieee.std_logic_1164.all; --- synthesis translate_off -library XilinxCoreLib; --- synthesis translate_on - - -entity operands_sp is - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(4 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0) - ); -end operands_sp; - - -architecture operands_sp_a of operands_sp is --- synthesis translate_off - component wrapped_operands_sp - port ( - clka : in std_logic; - wea : in std_logic_vector(0 downto 0); - addra : in std_logic_vector(4 downto 0); - dina : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(511 downto 0) - ); - end component; - --- Configuration specification - for all : wrapped_operands_sp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) - generic map( - c_has_regceb => 0, - c_has_regcea => 0, - c_mem_type => 0, - c_rstram_b => 0, - c_rstram_a => 0, - c_has_injecterr => 0, - c_rst_type => "SYNC", - c_prim_type => 1, - c_read_width_b => 32, - c_initb_val => "0", - c_family => "virtex6", - c_read_width_a => 512, - c_disable_warn_bhv_coll => 0, - c_write_mode_b => "WRITE_FIRST", - c_init_file_name => "no_coe_file_loaded", - c_write_mode_a => "WRITE_FIRST", - c_mux_pipeline_stages => 0, - c_has_mem_output_regs_b => 0, - c_has_mem_output_regs_a => 0, - c_load_init_file => 0, - c_xdevicefamily => "virtex6", - c_write_depth_b => 32, - c_write_depth_a => 32, - c_has_rstb => 0, - c_has_rsta => 0, - c_has_mux_output_regs_b => 0, - c_inita_val => "0", - c_has_mux_output_regs_a => 0, - c_addra_width => 5, - c_addrb_width => 5, - c_default_data => "0", - c_use_ecc => 0, - c_algorithm => 1, - c_disable_warn_bhv_range => 0, - c_write_width_b => 32, - c_write_width_a => 32, - c_read_depth_b => 32, - c_read_depth_a => 2, - c_byte_size => 9, - c_sim_collision_check => "ALL", - c_common_clk => 0, - c_wea_width => 1, - c_has_enb => 0, - c_web_width => 1, - c_has_ena => 0, - c_use_byte_web => 0, - c_use_byte_wea => 0, - c_rst_priority_b => "CE", - c_rst_priority_a => "CE", - c_use_default_data => 0 - ); --- synthesis translate_on - -begin --- synthesis translate_off - u0 : wrapped_operands_sp - port map ( - clka => clka, - wea => wea, - addra => addra, - dina => dina, - douta => douta - ); --- synthesis translate_on - -end operands_sp_a; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/d_flip_flop.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/d_flip_flop.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/d_flip_flop.vhd (nonexistent) @@ -1,76 +0,0 @@ ----------------------------------------------------------------------- ----- d_flip_flop ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- 1-bit D flip-flop implemented with behavorial (generic) ---- ----- description. With asynchronous active high reset. ---- ----- ---- ----- Dependencies: none ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- 1-bit D flip-flop with asynchronous active high reset -entity d_flip_flop is - port( - core_clk : in std_logic; -- clock signal - reset : in std_logic; -- active high reset - din : in std_logic; -- data in - dout : out std_logic -- data out - ); -end d_flip_flop; - - -architecture Behavorial of d_flip_flop is -begin - - -- process for 1-bit D flip-flop - d_FF : process (reset, core_clk, din) - begin - if reset='1' then -- asynchronous active high reset - dout <= '0'; - else - if rising_edge(core_clk) then -- clock in data on rising edge - dout <= din; - end if; - end if; - end process; - -end Behavorial; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_last_cell_logic.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_last_cell_logic.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/sys_last_cell_logic.vhd (nonexistent) @@ -1,94 +0,0 @@ ----------------------------------------------------------------------- ----- sys_last_cell_logic ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- last cell logic for use int the montogommery mulitplier ---- ----- pipelined systolic array ---- ----- ---- ----- Dependencies: ---- ----- - register_n ---- ----- - cell_1b_adder ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library mod_sim_exp; -use mod_sim_exp.mod_sim_exp_pkg.all; - --- logic needed as the last piece in the systolic array pipeline --- calculates the last 2 bits of the cell_result and finishes the reduction --- also generates the result selection signal -entity sys_last_cell_logic is - port ( - core_clk : in std_logic; -- clock input - reset : in std_logic; - a_0 : out std_logic; -- a_msb for last stage - cin : in std_logic; -- cout from last stage - red_cin : in std_logic; -- red_cout from last stage - r_sel : out std_logic; -- result selection bit - start : in std_logic -- done signal from last stage - ); -end sys_last_cell_logic; - - -architecture Behavorial of sys_last_cell_logic is - signal cin_reg : std_logic; -begin - - a_0 <= cin_reg; - - last_reg : register_1b - port map( - core_clk => core_clk, - ce => start, - reset => reset, - din => cin, - dout => cin_reg - ); - - -- reduction, finishing last bit - reduction_adder : cell_1b_adder - port map( - a => '1', -- for 2s complement of m - b => cin_reg, - cin => red_cin, - cout => r_sel - ); - -end Behavorial; Index: mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_generic.vhd =================================================================== --- mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_generic.vhd (revision 67) +++ mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/fifo_generic.vhd (nonexistent) @@ -1,149 +0,0 @@ ----------------------------------------------------------------------- ----- fifo_generic ---- ----- ---- ----- This file is part of the ---- ----- Modular Simultaneous Exponentiation Core project ---- ----- http://www.opencores.org/cores/mod_sim_exp/ ---- ----- ---- ----- Description ---- ----- behavorial description of a FIFO, correctly inferred by ---- ----- altera and xilinx. ---- ----- ---- ----- Resources needed (xilinx): ---- ----- - RAM: (depth+1 * 32) bits ---- ----- - 2 adders/substractors ---- ----- - 2 comparators ---- ----- - 2 registers: aw bits (for the address pointers) ---- ----- - 3 registers: 1 bit (for the flags) ---- ----- ---- ----- Authors: ---- ----- - Geoffrey Ottoy, DraMCo research group ---- ----- - Jonas De Craene, JonasDC@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -library mod_sim_exp; -use mod_sim_exp.std_functions.all; - -entity fifo_generic is - generic ( - depth : integer := 32 - ); - port ( - clk : in std_logic; -- clock input - din : in std_logic_vector (31 downto 0); -- 32 bit input data for push - dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop - empty : out std_logic; -- empty flag, 1 when FIFO is empty - full : out std_logic; -- full flag, 1 when FIFO is full - push : in std_logic; - pop : in std_logic; - reset : in std_logic; - nopop : out std_logic; - nopush : out std_logic - ); -end fifo_generic; - -architecture arch of fifo_generic is - -- calculate the width for the address-pointers - constant aw : integer := log2(depth+1); - - -- read and write pointer - signal rd_addr : std_logic_vector(aw-1 downto 0); - signal wr_addr : std_logic_vector(aw-1 downto 0); - - -- control signals - signal empty_i : std_logic; - signal full_i : std_logic; - signal push_i : std_logic; - signal push_i_d : std_logic; - signal pop_i : std_logic; - - -- the memory - type ram_type is array (depth downto 0) of std_logic_vector (31 downto 0); - signal RAM : ram_type; -begin - - empty <= empty_i; - full <= full_i; - -- full flag is 1 when read address is one below write address - full_i <= '1' when (wr_addr+'1'=rd_addr) or - (wr_addr=conv_std_logic_vector(depth, aw) and (rd_addr=conv_std_logic_vector(0, aw))) - else '0'; - -- empty flag is 1 when read and write address are the same - empty_i <= '1' when (wr_addr=rd_addr) else '0'; - - fifo_addr_proc : process (clk) - begin - if rising_edge(clk) then - if reset='1' then -- if reset, both read and write address point to the maximum address (depth) - wr_addr <= conv_std_logic_vector(depth, aw); - rd_addr <= conv_std_logic_vector(depth, aw); - else - if push_i='1' then -- push - if (wr_addr=conv_std_logic_vector(depth, aw)) then - wr_addr <= (others=>'0'); -- if overflow, set to zero - else - wr_addr <= wr_addr+'1'; -- else, increase address - end if; - end if; - - if pop_i='1' then -- pop - if (rd_addr=conv_std_logic_vector(depth, aw)) then - rd_addr <= (others=>'0'); -- if overflow, set to zero - else - rd_addr <= rd_addr+'1'; -- else, increase address - end if; - end if; - end if; - push_i_d <= push_i; -- delayed version of push signal - - nopop <= (pop and empty_i) or (pop and reset); - nopush <= (push and full_i) or (push and reset); - end if; - end process; - - push_i <= push and not full_i; - pop_i <= pop and not empty_i; - - -- Block RAM - process (clk) - begin - if (clk'event and clk = '1') then - if (push_i_d = '1') then - RAM(conv_integer(wr_addr)) <= din; - end if; - dout <= RAM(conv_integer(rd_addr)); - end if; - end process; - -end arch; Index: mod_sim_exp/branches/newRAMstyle =================================================================== --- mod_sim_exp/branches/newRAMstyle (revision 67) +++ mod_sim_exp/branches/newRAMstyle (nonexistent)
mod_sim_exp/branches/newRAMstyle Property changes : Deleted: svn:ignore ## -1 +0,0 ## -.project

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