URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- from Rev 68 to Rev 69
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Rev 68 → Rev 69
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd
File deleted
/mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd
52,7 → 52,8
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
library mod_sim_exp; |
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
use mod_sim_exp.std_functions.all; |
|
entity fifo_generic is |
132,7 → 133,7
pop_i <= pop and not empty_i; |
|
-- Block RAM |
ramblock: entity mod_sim_exp.dpram_generic |
ramblock: dpram_generic |
generic map( |
depth => depth+1 |
) |
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
171,7 → 171,7
doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth) |
); |
-- weA, weB |
process (write_operand_i, write_result, operand_addr) |
process (write_operand_i, operand_addr) |
begin |
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then |
weA_RAM(i) <= write_operand_i; |
220,7 → 220,7
doutB => operand_out(width-1 downto i*RAMblock_maxwidth) |
); |
-- weA, weB part |
process (write_operand_i, write_result, operand_addr) |
process (write_operand_i, operand_addr) |
begin |
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then |
weA_part <= write_operand_i; |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
467,6 → 467,7
|
------------------------------ MEMORY ------------------------------ |
|
-------------------------- xil_prim specific ----------------------- |
-------------------------------------------------------------------- |
-- operand_dp |
-------------------------------------------------------------------- |
503,6 → 504,70
end component operands_sp; |
|
-------------------------------------------------------------------- |
-- fifo_primitive |
-------------------------------------------------------------------- |
-- a xilinx fifo primitive wrapper |
-- |
component fifo_primitive is |
port ( |
clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
); |
end component fifo_primitive; |
|
-------------------------------------------------------------------- |
-- operand_ram |
-------------------------------------------------------------------- |
-- RAM for the operands, fixed width of 1536-bit and depth of 4 |
-- uses xilinx primitives |
-- |
component operand_ram is |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; |
-- bus side connections (32-bit serial) |
operand_addr : in std_logic_vector(5 downto 0); |
operand_in : in std_logic_vector(31 downto 0); |
operand_in_sel : in std_logic_vector(1 downto 0); |
result_out : out std_logic_vector(31 downto 0); |
write_operand : in std_logic; |
-- multiplier side connections (1536 bit parallel) |
result_dest_op : in std_logic_vector(1 downto 0); |
operand_out : out std_logic_vector(1535 downto 0); |
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side |
write_result : in std_logic; |
result_in : in std_logic_vector(1535 downto 0) |
); |
end component operand_ram; |
|
-------------------------------------------------------------------- |
-- modulus_ram |
-------------------------------------------------------------------- |
-- RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives |
-- |
component modulus_ram is |
port( |
clk : in std_logic; |
modulus_addr : in std_logic_vector(5 downto 0); |
write_modulus : in std_logic; |
modulus_in : in std_logic_vector(31 downto 0); |
modulus_out : out std_logic_vector(1535 downto 0) |
); |
end component modulus_ram; |
|
|
------------------------- generic modules -------------------------- |
|
-------------------------------------------------------------------- |
-- dpram_generic |
-------------------------------------------------------------------- |
-- behavorial description of a dual port ram with one 32-bit |
550,27 → 615,7
); |
end component tdpram_generic; |
|
-------------------------------------------------------------------- |
-- fifo_primitive |
-------------------------------------------------------------------- |
-- a xilinx fifo primitive wrapper |
-- |
component fifo_primitive is |
port ( |
clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
); |
end component fifo_primitive; |
|
-------------------------------------------------------------------- |
-- fifo_generic |
-------------------------------------------------------------------- |
-- a behavorial implementation of a fifo that is designed to |
595,24 → 640,9
end component fifo_generic; |
|
-------------------------------------------------------------------- |
-- modulus_ram |
-------------------------------------------------------------------- |
-- RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives |
-- |
component modulus_ram is |
port( |
clk : in std_logic; |
modulus_addr : in std_logic_vector(5 downto 0); |
write_modulus : in std_logic; |
modulus_in : in std_logic_vector(31 downto 0); |
modulus_out : out std_logic_vector(1535 downto 0) |
); |
end component modulus_ram; |
|
-------------------------------------------------------------------- |
-- modulus_ram_gen |
-------------------------------------------------------------------- |
-- behavorial description of a RAM to hold the modulus, with |
-- structural description of a RAM to hold the modulus, with |
-- adjustable width and depth(nr of moduluses) |
-- |
component modulus_ram_gen is |
663,82 → 693,204
); |
end component operand_ram_gen; |
|
|
|
------------------------ asymmetric modules ------------------------ |
|
-------------------------------------------------------------------- |
-- operand_ram |
-- dpram_asym |
-------------------------------------------------------------------- |
-- RAM for the operands, fixed width of 1536-bit and depth of 4 |
-- uses xilinx primitives |
-- behavorial description of an asymmetric dual port ram |
-- with one (wrwidth)-bit write port and one 32-bit read |
-- port. Made using the templates of xilinx and altera for |
-- asymmetric ram. |
-- |
component operand_ram is |
port( -- write_operand_ack voorzien? |
-- global ports |
clk : in std_logic; |
collision : out std_logic; |
-- bus side connections (32-bit serial) |
operand_addr : in std_logic_vector(5 downto 0); |
operand_in : in std_logic_vector(31 downto 0); |
operand_in_sel : in std_logic_vector(1 downto 0); |
result_out : out std_logic_vector(31 downto 0); |
write_operand : in std_logic; |
-- multiplier side connections (1536 bit parallel) |
result_dest_op : in std_logic_vector(1 downto 0); |
operand_out : out std_logic_vector(1535 downto 0); |
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side |
write_result : in std_logic; |
result_in : in std_logic_vector(1535 downto 0) |
component dpram_asym is |
generic( |
rddepth : integer := 4; -- nr of 32-bit words |
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32 |
device : string := "xilinx" -- device template to use |
); |
end component operand_ram; |
port( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(wrwidth-1 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(rddepth)-1 downto 0); |
dout : out std_logic_vector(31 downto 0) |
); |
end component dpram_asym; |
|
-------------------------------------------------------------------- |
-- dpramblock_asym |
-------------------------------------------------------------------- |
-- structural description of an asymmetric dual port ram |
-- with one 32-bit write port and one (width)-bit read |
-- port. |
-- |
component dpramblock_asym is |
generic( |
width : integer := 256; -- read width |
depth : integer := 2; -- nr of (width)-bit words |
device : string := "xilinx" |
); |
port( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(31 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(depth)-1 downto 0); |
dout : out std_logic_vector(width-1 downto 0) |
); |
end component dpramblock_asym; |
|
component operand_mem is |
-------------------------------------------------------------------- |
-- tdpram_asym |
-------------------------------------------------------------------- |
-- behavorial description of an asymmetric true dual port |
-- ram with one (widthA)-bit read/write port and one 32-bit |
-- read/write port. Made using the templates of xilinx and |
-- altera for asymmetric ram. |
-- |
component tdpram_asym is |
generic( |
n : integer := 1536 |
depthB : integer := 4; -- nr of 32-bit words |
widthA : integer := 2; -- port A width, must be smaller than or equal to 32 |
device : string := "xilinx" |
); |
port( |
-- data interface (plb side) |
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- address structure: |
-- bit: 8 -> '1': modulus |
-- '0': operands |
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0' |
-- don't care in case of modulus |
-- bits: 5-0 -> modulus_addr / operand_addr resp. |
clk : in std_logic; |
-- port A (widthA)-bit |
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(widthA-1 downto 0); |
doutA : out std_logic_vector(widthA-1 downto 0); |
-- port B 32-bit |
addrB : in std_logic_vector(log2(depthB)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(31 downto 0); |
doutB : out std_logic_vector(31 downto 0) |
); |
end component tdpram_asym; |
|
-- operand interface (multiplier side) |
op_sel : in std_logic_vector(1 downto 0); |
xy_out : out std_logic_vector((n-1) downto 0); |
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
-- control signals |
load_result : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
collision : out std_logic; |
-- system clock |
clk : in std_logic |
-------------------------------------------------------------------- |
-- tdpramblock_asym |
-------------------------------------------------------------------- |
-- structural description of an asymmetric true dual port |
-- ram with one 32-bit read/write port and one (width)-bit |
-- read/write port. |
-- |
component tdpramblock_asym is |
generic ( |
depth : integer := 4; -- nr of (width)-bit words |
width : integer := 512; -- width of portB |
device : string := "xilinx" |
); |
end component operand_mem; |
port ( |
clk : in std_logic; |
-- port A 32-bit |
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
doutA : out std_logic_vector(31 downto 0); |
-- port B (width)-bit |
addrB : in std_logic_vector(log2(depth)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(width-1 downto 0); |
doutB : out std_logic_vector(width-1 downto 0) |
); |
end component tdpramblock_asym; |
|
-------------------------------------------------------------------- |
-- operand_mem_gen |
-- modulus_ram_asym |
-------------------------------------------------------------------- |
-- generic description of the cores memory, places the modulus |
-- and operands in one addres and data bus |
-- BRAM memory and logic to store the modulus, due to the |
-- achitecture, a minimum depth of 2 is needed for this |
-- module to be inferred into blockram, this version is |
-- slightly more performant than modulus_ram_gen and uses |
-- less resources. but does not work on every fpga, only |
-- the ones that support asymmetric rams. |
-- |
component modulus_ram_asym is |
generic( |
width : integer := 1536; -- must be a multiple of 32 |
depth : integer := 2; -- nr of moduluses |
device : string := "xilinx" |
); |
port( |
clk : in std_logic; |
-- bus side |
write_modulus : in std_logic; -- write enable |
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to |
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address |
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in |
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications |
-- multiplier side |
modulus_out : out std_logic_vector(width-1 downto 0) |
); |
end component modulus_ram_asym; |
|
-------------------------------------------------------------------- |
-- operand_ram_asym |
-------------------------------------------------------------------- |
-- BRAM memory and logic to store the operands, due to the |
-- achitecture, a minimum depth of 2 is needed for this |
-- module to be inferred into blockram, this version is |
-- slightly more performant than operand_ram_gen and uses |
-- less resources. but does not work on every fpga, only |
-- the ones that support asymmetric rams. |
-- |
component operand_ram_asym is |
generic( |
width : integer := 1536; -- width of the operands |
depth : integer := 4; -- nr of operands |
device : string := "xilinx" |
); |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; -- 1 if simultaneous write on RAM |
-- bus side connections (32-bit serial) |
write_operand : in std_logic; -- write_enable |
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to |
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write |
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write |
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand |
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier |
-- multiplier side connections (width-bit parallel) |
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result |
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier |
write_result : in std_logic; -- write enable for multiplier side |
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier |
); |
end component operand_ram_asym; |
|
-------------------------------------------------------------------- |
-- operand_mem |
-------------------------------------------------------------------- |
-- RAM memory and logic to the store operands and the |
-- modulus for the montgomery multiplier, the user has a |
-- choise between 3 memory styles, more detail in the |
-- documentation. |
-- |
-- address structure: |
-- bit: highest -> '1': modulus |
-- '0': operands |
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0' |
-- modulus_in_sel in case of highest bit = '1' |
-- modulus_in_sel in case of highest bit = '1' |
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp. |
-- |
component operand_mem_gen is |
component operand_mem is |
generic( |
width : integer := 1536; -- width of the operands |
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m |
nr_m : integer := 2 -- nr of modulus storages |
width : integer := 1536; -- width of the operands |
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m |
nr_m : integer := 2; -- nr of modulus storages |
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options |
device : string := "altera" -- xilinx, altera are valid options |
); |
port( |
-- system clock |
759,9 → 911,10
collision : out std_logic; |
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0) |
); |
end component operand_mem_gen; |
end component operand_mem; |
|
|
|
---------------------------- TOP LEVEL ----------------------------- |
|
-------------------------------------------------------------------- |
779,7 → 932,9
C_SPLIT_PIPELINE : boolean := true; |
C_NR_OP : integer := 4; |
C_NR_M : integer := 2; |
C_FIFO_DEPTH : integer := 32 |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
787,7 → 942,7
-- operand memory interface (plb shared memory) |
write_enable : in std_logic; -- write data to operand ram |
data_in : in std_logic_vector (31 downto 0); -- operand ram data in |
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus |
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus |
data_out : out std_logic_vector (31 downto 0); -- operand ram data out |
collision : out std_logic; -- write collision |
-- op_sel fifo interface |
799,12 → 954,12
start : in std_logic; -- start multiplication/exponentiation |
exp_m : in std_logic; -- single multiplication if low, exponentiation if high |
ready : out std_logic; -- calculations done |
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection |
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection |
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection |
x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection |
y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection |
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection |
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection |
calc_time : out std_logic; |
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) |
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications |
); |
end component mod_sim_exp_core; |
|
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
67,7 → 67,9
C_SPLIT_PIPELINE : boolean := true; |
C_NR_OP : integer := 4; |
C_NR_M : integer := 2; |
C_FIFO_DEPTH : integer := 32 |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
75,7 → 77,7
-- operand memory interface (plb shared memory) |
write_enable : in std_logic; -- write data to operand ram |
data_in : in std_logic_vector (31 downto 0); -- operand ram data in |
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus |
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus |
data_out : out std_logic_vector (31 downto 0); -- operand ram data out |
collision : out std_logic; -- write collision |
-- op_sel fifo interface |
92,7 → 94,7
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection |
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection |
calc_time : out std_logic; |
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) |
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications |
); |
end mod_sim_exp_core; |
|
99,18 → 101,18
|
architecture Structural of mod_sim_exp_core is |
-- data busses |
signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier |
|
signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier |
|
-- control signals |
signal op_sel : std_logic_vector(1 downto 0); -- operand selection |
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand |
signal mult_ready : std_logic; |
signal start_mult : std_logic; |
signal op_sel : std_logic_vector(1 downto 0); -- operand selection |
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand |
signal mult_ready : std_logic; |
signal start_mult : std_logic; |
signal load_x : std_logic; |
signal load_result : std_logic; |
|
signal load_result : std_logic; |
|
-- fifo signals |
signal fifo_empty : std_logic; |
signal fifo_pop : std_logic; |
121,9 → 123,9
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
n => C_NR_BITS_TOTAL, |
t => C_NR_STAGES_TOTAL, |
tl => C_NR_STAGES_LOW, |
n => C_NR_BITS_TOTAL, |
t => C_NR_STAGES_TOTAL, |
tl => C_NR_STAGES_LOW, |
split => C_SPLIT_PIPELINE |
) |
port map( |
139,11 → 141,13
); |
|
-- Block ram memory for storing the operands and the modulus |
the_memory : operand_mem_gen |
the_memory : operand_mem |
generic map( |
width => C_NR_BITS_TOTAL, |
nr_op => C_NR_OP, |
nr_m => C_NR_M |
width => C_NR_BITS_TOTAL, |
nr_op => C_NR_OP, |
nr_m => C_NR_M, |
mem_style => C_MEM_STYLE, |
device => C_DEVICE |
) |
port map( |
data_in => data_in, |
163,24 → 167,41
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3 |
|
-- A fifo for auto-run operand selection |
the_exponent_fifo : fifo_generic |
generic map( |
depth => C_FIFO_DEPTH |
) |
port map( |
clk => clk, |
din => fifo_din, |
dout => fifo_dout, |
empty => fifo_empty, |
full => fifo_full, |
push => fifo_push, |
pop => fifo_pop, |
reset => reset, |
nopop => fifo_nopop, |
nopush => fifo_nopush |
); |
|
-- A fifo for exponentiation mode |
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate |
the_exponent_fifo : fifo_primitive |
port map( |
clk => clk, |
din => fifo_din, |
dout => fifo_dout, |
empty => fifo_empty, |
full => fifo_full, |
push => fifo_push, |
pop => fifo_pop, |
reset => reset, |
nopop => fifo_nopop, |
nopush => fifo_nopush |
); |
end generate; |
gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate |
the_exponent_fifo : fifo_generic |
generic map( |
depth => C_FIFO_DEPTH |
) |
port map( |
clk => clk, |
din => fifo_din, |
dout => fifo_dout, |
empty => fifo_empty, |
full => fifo_full, |
push => fifo_push, |
pop => fifo_pop, |
reset => reset, |
nopop => fifo_nopop, |
nopush => fifo_nopush |
); |
end generate; |
|
-- The control logic for the core |
the_control_unit : mont_ctrl |
port map( |
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
6,12 → 6,18
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- BRAM memory and logic to the store 4 (1536-bit) operands ---- |
---- and the modulus for the montgomery multiplier ---- |
---- ---- |
---- RAM memory and logic to the store operands and the ---- |
---- modulus for the montgomery multiplier, the user has a ---- |
---- choise between 3 memory styles, more detail in the ---- |
---- documentation ---- |
---- ---- |
---- Dependencies: ---- |
---- - operand_ram ---- |
---- - modulus_ram ---- |
---- - operand_ram_gen ---- |
---- - modulus_ram_gen ---- |
---- - operand_ram_asym ---- |
---- - modulus_ram_asym ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
51,98 → 57,184
|
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
use mod_sim_exp.std_functions.all; |
|
|
-- address structure: |
-- bit: highest -> '1': modulus |
-- '0': operands |
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0' |
-- modulus_in_sel in case of highest bit = '1' |
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp. |
-- |
entity operand_mem is |
generic( |
n : integer := 1536 |
width : integer := 1536; -- width of the operands |
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m |
nr_m : integer := 2; -- nr of modulus storages |
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options |
device : string := "altera" -- xilinx, altera are valid options |
); |
port( |
-- data interface (plb side) |
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- address structure: |
-- bit: 8 -> '1': modulus |
-- '0': operands |
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0' |
-- don't care in case of modulus |
-- bits: 5-0 -> modulus_addr / operand_addr resp. |
|
-- operand interface (multiplier side) |
op_sel : in std_logic_vector(1 downto 0); |
xy_out : out std_logic_vector((n-1) downto 0); |
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
-- control signals |
-- system clock |
clk : in std_logic; |
-- data interface (plb side) |
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0); |
write_enable : in std_logic; |
-- operand interface (multiplier side) |
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0); |
xy_out : out std_logic_vector((width-1) downto 0); |
m : out std_logic_vector((width-1) downto 0); |
result_in : in std_logic_vector((width-1) downto 0); |
-- control signals |
load_result : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0); |
collision : out std_logic; |
-- system clock |
clk : in std_logic |
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0) |
); |
end operand_mem; |
|
architecture structural of operand_mem is |
-- constants |
constant wordaddr_aw : integer := log2(width/32); |
constant opaddr_aw : integer := log2(nr_op); |
constant maddr_aw : integer := log2(nr_m); |
constant total_aw : integer := 1+opaddr_aw+wordaddr_aw; |
|
architecture Behavioral of operand_mem is |
-- internal signals |
signal xy_data_i : std_logic_vector(31 downto 0); |
signal xy_addr_i : std_logic_vector(5 downto 0); |
signal operand_in_sel_i : std_logic_vector(1 downto 0); |
signal collision_i : std_logic; |
signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0); |
signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0); |
signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0); |
|
signal xy_out_i : std_logic_vector(1535 downto 0); |
signal m_i : std_logic_vector(1535 downto 0); |
signal result_in_i : std_logic_vector(1535 downto 0); |
signal load_op : std_logic; |
|
signal m_addr_i : std_logic_vector(5 downto 0); |
signal load_m : std_logic; |
signal m_data_i : std_logic_vector(31 downto 0); |
signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0); |
signal load_m : std_logic; |
signal m_data_i : std_logic_vector(31 downto 0); |
|
begin |
|
-- map outputs |
xy_out <= xy_out_i((n-1) downto 0); |
m <= m_i((n-1) downto 0); |
result_in_i((n-1) downto 0) <= result_in; |
collision <= collision_i; |
|
-- map inputs |
xy_addr_i <= rw_address(5 downto 0); |
m_addr_i <= rw_address(5 downto 0); |
operand_in_sel_i <= rw_address(7 downto 6); |
xy_addr_i <= rw_address(wordaddr_aw-1 downto 0); |
m_addr_i <= rw_address(wordaddr_aw-1 downto 0); |
operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw); |
modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw); |
xy_data_i <= data_in; |
m_data_i <= data_in; |
|
load_op <= write_enable when (rw_address(8) = '0') else '0'; |
load_m <= write_enable when (rw_address(8) = '1') else '0'; |
-- select right memory with highest address bit |
load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0'; |
load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0'; |
|
-- xy operand storage |
xy_ram : operand_ram |
port map( |
clk => clk, |
collision => collision_i, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
result_out => data_out, |
write_operand => load_op, |
operand_out => xy_out_i, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
write_result => load_result, |
result_in => result_in_i |
); |
xil_prim_RAM : if mem_style="xil_prim" generate |
-- xy operand storage |
xy_ram_xil : operand_ram |
port map( |
clk => clk, |
collision => collision, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
result_out => data_out, |
write_operand => load_op, |
operand_out => xy_out, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
write_result => load_result, |
result_in => result_in |
); |
|
-- modulus storage |
m_ram_xil : modulus_ram |
port map( |
clk => clk, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
modulus_out => m |
); |
end generate; |
|
-- modulus storage |
m_ram : modulus_ram |
port map( |
clk => clk, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
modulus_out => m_i |
); |
|
end Behavioral; |
gen_RAM : if mem_style="generic" generate |
-- xy operand storage |
xy_ram_gen : operand_ram_gen |
generic map( |
width => width, |
depth => nr_op |
) |
port map( |
clk => clk, |
collision => collision, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
result_out => data_out, |
write_operand => load_op, |
operand_out => xy_out, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
write_result => load_result, |
result_in => result_in |
); |
|
-- modulus storage |
m_ram_gen : modulus_ram_gen |
generic map( |
width => width, |
depth => nr_m |
) |
port map( |
clk => clk, |
modulus_in_sel => modulus_in_sel_i, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
modulus_out => m, |
modulus_sel => modulus_sel |
); |
end generate; |
|
asym_RAM : if mem_style="asym" generate |
-- xy operand storage |
xy_ram_asym : operand_ram_asym |
generic map( |
width => width, |
depth => nr_op, |
device => device |
) |
port map( |
clk => clk, |
collision => collision, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
result_out => data_out, |
write_operand => load_op, |
operand_out => xy_out, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
write_result => load_result, |
result_in => result_in |
); |
|
-- modulus storage |
m_ram_asym : modulus_ram_asym |
generic map( |
width => width, |
depth => nr_m, |
device => device |
) |
port map( |
clk => clk, |
modulus_in_sel => modulus_in_sel_i, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
modulus_out => m, |
modulus_sel => modulus_sel |
); |
end generate; |
|
end structural; |