OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk/rtl/vhdl/ram
    from Rev 83 to Rev 89
    ↔ Reverse comparison
  •

Rev 83 → Rev 89

/dpram_generic.vhd
56,14 → 56,15
depth : integer := 2
);
port (
clk : in std_logic;
-- write port
waddr : in std_logic_vector(log2(depth)-1 downto 0);
we : in std_logic;
din : in std_logic_vector(31 downto 0);
-- read port
raddr : in std_logic_vector(log2(depth)-1 downto 0);
dout : out std_logic_vector(31 downto 0)
-- write port A
clkA : in std_logic;
waddrA : in std_logic_vector(log2(depth)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
-- read port B
clkB : in std_logic;
raddrB : in std_logic_vector(log2(depth)-1 downto 0);
doutB : out std_logic_vector(31 downto 0)
);
end dpram_generic;
 
70,11 → 71,11
architecture behavorial of dpram_generic is
-- the memory
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
signal RAM : ram_type := (others => (others => '0'));
shared variable RAM : ram_type := (others => (others => '0'));
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of ram:signal is "block";
attribute ram_style of ram:variable is "block";
-- altera constraints:
-- for smal depths:
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
81,16 → 82,23
-- may be left commented.
-- uncomment this attribute if that option is off and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
--attribute ramstyle of RAM : variable is "M9K, no_rw_check";
begin
process (clk)
process (clkA)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(waddr)) <= din;
if rising_edge(clkA) then
if (weA = '1') then
RAM(conv_integer(waddrA)) := dinA;
end if;
dout <= RAM(conv_integer(raddr));
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
doutB <= RAM(conv_integer(raddrB));
end if;
end process;
end behavorial;
 
/tdpram_asym.vhd
62,13 → 62,14
device : string := "xilinx"
);
port (
clk : in std_logic;
-- port A (widthA)-bit
clkA : in std_logic;
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(widthA-1 downto 0);
doutA : out std_logic_vector(widthA-1 downto 0);
-- port B 32-bit
clkB : in std_logic;
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
weB : in std_logic;
dinB : in std_logic_vector(31 downto 0);
91,12 → 92,9
-- - the RAM has two write ports,
-- - the RAM has only one write port whose data width is maxWIDTH
-- In all other cases, ram can be a signal.
shared variable ram : ramType := (others => (others => '0'));
signal clkA : std_logic;
signal clkB : std_logic;
shared variable ram : ramType := (others => (others => '0'));
begin
clkA <= clk;
process (clkA)
begin
if rising_edge(clkA) then
107,7 → 105,6
end if;
end process;
clkB <= clk;
process (clkB)
begin
if rising_edge(clkB) then
149,9 → 146,9
end generate unpack;
--port B
process(clk)
process(clkB)
begin
if(rising_edge(clk)) then
if(rising_edge(clkB)) then
if(weB = '1') then
ram(conv_integer(addrB)) <= wB_local;
end if;
160,9 → 157,9
end process;
-- port A
process(clk)
process(clkA)
begin
if(rising_edge(clk)) then
if(rising_edge(clkA)) then
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
if(weA ='1') then
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
/dpramblock_asym.vhd
62,14 → 62,15
device : string := "xilinx"
);
port (
clk : in std_logic;
-- write port
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
we : in std_logic;
din : in std_logic_vector(31 downto 0);
-- read port
raddr : in std_logic_vector(log2(depth)-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
-- write port A
clkA : in std_logic;
waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
-- read port B
clkB : in std_logic;
raddrB : in std_logic_vector(log2(depth)-1 downto 0);
doutB : out std_logic_vector(width-1 downto 0)
);
end dpramblock_asym;
 
92,18 → 93,20
device => device
)
port map(
clk => clk,
-- write port
waddr => waddr,
we => we,
din => din((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
clkA => clkA,
waddrA => waddrA,
weA => weA,
dinA => dinA((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
-- read port
raddr => raddr,
dout => dout_RAM(i)
clkB => clkB,
raddrB => raddrB,
doutB => dout_RAM(i)
);
map_output : for j in 0 to nrRAMs-1 generate
dout(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
doutB(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
<= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth);
end generate;
end generate;
/tdpramblock_asym.vhd
61,14 → 61,15
width : integer := 512; -- width of portB
device : string := "xilinx"
);
port (
clk : in std_logic;
port (
-- port A 32-bit
clkA : in std_logic;
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
-- port B (width)-bit
clkB : in std_logic;
addrB : in std_logic_vector(log2(depth)-1 downto 0);
weB : in std_logic;
dinB : in std_logic_vector(width-1 downto 0);
95,13 → 96,14
device => device
)
port map(
clk => clk,
-- port A (widthA)-bit
clkA => clkA,
addrA => addrA,
weA => weA,
dinA => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
-- port B 32-bit
clkB => clkB,
addrB => addrB,
weB => weB,
dinB => dinB_RAM(i),
/dpram_asym.vhd
61,15 → 61,16
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
device : string := "xilinx" -- device template to use
);
port (
clk : in std_logic;
port (
-- write port
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
we : in std_logic;
din : in std_logic_vector(wrwidth-1 downto 0);
clkA : in std_logic;
waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(wrwidth-1 downto 0);
-- read port
raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
dout : out std_logic_vector(31 downto 0)
clkB : in std_logic;
raddrB : in std_logic_vector(log2(rddepth)-1 downto 0);
doutB : out std_logic_vector(31 downto 0)
);
end dpram_asym;
 
82,21 → 83,29
xilinx_device : if device="xilinx" generate
-- the memory
type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
shared variable RAM : ram_type := (others => (others => '0'));
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of ram:signal is "block";
attribute ram_style of RAM:variable is "block";
begin
process (clk)
-- Write port A
process (clkA)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(waddr)) <= din;
if rising_edge(clkA) then
if (weA = '1') then
RAM(conv_integer(waddrA)) := dinA;
end if;
end if;
end process;
-- Read port B
process (clkB)
begin
if rising_edge(clkB) then
for i in 0 to R-1 loop
dout((i+1)*wrwidth-1 downto i*wrwidth)
<= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R))));
doutB((i+1)*wrwidth-1 downto i*wrwidth)
<= RAM(conv_integer(raddrB & conv_std_logic_vector(i,log2(R))));
end loop;
end if;
end process;
107,7 → 116,7
type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
type ram_t is array (0 to rddepth-1) of word_t;
signal ram : ram_t;
shared variable ram : ram_t;
signal q_local : word_t;
-- altera constraints:
-- for smal depths:
118,18 → 127,24
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
begin
unpack: for i in 0 to R - 1 generate
dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
doutB(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
end generate unpack;
process(clk, we)
process(clkA)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din;
if(rising_edge(clkA)) then
if(weA = '1') then
ram(conv_integer(waddrA)/R)(conv_integer(waddrA) mod R) := dinA;
end if;
q_local <= ram(conv_integer(raddr));
end if;
end process;
process(clkB)
begin
if(rising_edge(clkB)) then
q_local <= ram(conv_integer(raddrB));
end if;
end process;
end generate;
end behavorial;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.