URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/trunk/rtl/vhdl/core/register_n.vhd
50,14 → 50,14
-- n-bit register with asynchronous reset and clock enable |
entity register_n is |
generic( |
n : integer := 4 |
width : integer := 4 |
); |
port( |
core_clk : in std_logic; -- clock input |
ce : in std_logic; -- clock enable (active high) |
reset : in std_logic; -- reset (active high) |
din : in std_logic_vector((n-1) downto 0); -- data in (n-bit) |
dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit) |
din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit |
dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit |
); |
end register_n; |
|
64,7 → 64,7
|
architecture Behavorial of register_n is |
begin |
-- process for n-bit register |
-- process for (width)-bit register |
reg_nb : process (reset, ce, core_clk, din) |
begin |
if reset='1' then -- asynchronous active high reset |
/trunk/rtl/vhdl/core/first_stage.vhd
155,7 → 155,7
-- output registers |
RESULT_REG : register_n |
generic map( |
n => width |
width => width |
) |
port map( |
core_clk => core_clk, |
/trunk/rtl/vhdl/core/standard_stage.vhd
143,7 → 143,7
-- output registers |
RESULT_REG : register_n |
generic map( |
n => width |
width => width |
) |
port map( |
core_clk => core_clk, |
/trunk/rtl/vhdl/core/last_stage.vhd
136,7 → 136,7
-- output registers |
RESULT_REG : register_n |
generic map( |
n => (width+2) |
width => (width+2) |
) |
port map( |
core_clk => core_clk, |