OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/trunk/bench/vhdl/tb_multiplier_core.vhd
1,10 → 1,50
--------------------------------------------------------------------------------
-- Entity: tb_multiplier_core
-- Date:2012-10-02
-- Author: Dinghe
--
-- Description ${cursor}
--------------------------------------------------------------------------------
----------------------------------------------------------------------
---- testbenchtrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- testbench for the modular simultaneous exponentiation ----
---- core. Performs some exponentiations to verify the design ----
---- Takes input parameters from sim_input.txt en writes ----
---- result and output to sim_output.txt ----
---- ----
---- Dependencies: ----
---- - multiplier_core ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
16,6 → 56,9
library ieee;
use ieee.std_logic_textio.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
entity tb_multiplier_core is
end tb_multiplier_core;
 
24,8 → 67,8
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
file input : text open read_mode is "sim_input.txt";
file output : text open write_mode is "sim_output.txt";
file input : text open read_mode is "src/sim_input.txt";
file output : text open write_mode is "out/sim_output.txt";
------------------------------------------------------------------
-- Signals for multiplier core memory space
54,34 → 97,6
signal core_ready : std_logic;
signal core_mem_collision : std_logic;
 
component multiplier_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
end component;
 
 
begin
 
------------------------------------------
138,7 → 153,6
wait until rising_edge(clk);
end loadOp;
procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
variable op_data : out std_logic_vector(2047 downto 0);
variable op_width : integer) is
537,7 → 551,7
wait until rising_edge(clk);
end loop;
waitclk(10);
write(Lw, string'(" Done"));
write(Lw, string'(" => Done"));
writeline(output, Lw);
-- start exponentiation
641,7 → 655,7
------------------------------------------
-- Multiplier core instance
------------------------------------------
the_multiplier : multiplier_core
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.multiplier_core
port map(
clk => clk,
reset => reset,
667,6 → 681,4
calc_time => calc_time
);
 
 
end test;
 
/trunk/rtl/vhdl/core/std_logic_textio.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/core/autorun_cntrl.vhd
1,83 → 1,99
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: autorun_cntrl.vhd / entity autorun_cntrl
--
-- Last Modified: 25/04/2012
--
-- Description: autorun control unit for a pipelined montgomery multiplier
--
--
-- Dependencies: none
--
-- Revision 2.00 - Major bug fix: bit_counter should count from 15 downto 0.
-- Revision 1.00 - Architecture created
-- Revision 0.01 - File Created
-- Additional Comments:
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- autorun_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- autorun control unit for a pipelined montgomery ----
---- multiplier ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity autorun_cntrl is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
op_sel : out STD_LOGIC_VECTOR (1 downto 0);
start_multiplier : out STD_LOGIC;
multiplier_done : in STD_LOGIC;
read_buffer : out STD_LOGIC;
buffer_din : in STD_LOGIC_VECTOR (31 downto 0);
buffer_empty : in STD_LOGIC);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end autorun_cntrl;
 
 
architecture Behavioral of autorun_cntrl is
 
signal bit_counter_i : integer range 0 to 15 := 0;
signal bit_counter_0_i : std_logic;
signal bit_counter_15_i : std_logic;
signal next_bit_i : std_logic := '0';
signal next_bit_del_i : std_logic;
signal start_cycle_i : std_logic := '0';
signal start_cycle_del_i : std_logic;
signal bit_counter_i : integer range 0 to 15 := 0;
signal bit_counter_0_i : std_logic;
signal bit_counter_15_i : std_logic;
signal next_bit_i : std_logic := '0';
signal next_bit_del_i : std_logic;
signal start_cycle_i : std_logic := '0';
signal start_cycle_del_i : std_logic;
signal done_i : std_logic;
signal start_i : std_logic;
signal running_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_multiplier_del_i : std_logic;
signal mult_done_del_i : std_logic;
signal e0_i : std_logic_vector(15 downto 0);
signal e1_i : std_logic_vector(15 downto 0);
signal e0_bit_i : std_logic;
signal e1_bit_i : std_logic;
signal e_bits_i : std_logic_vector(1 downto 0);
signal e_bits_0_i : std_logic;
signal cycle_counter_i : std_logic;
signal op_sel_sel_i : std_logic;
signal op_sel_i : std_logic_vector(1 downto 0);
begin
 
signal done_i : std_logic;
signal start_i : std_logic;
signal running_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_multiplier_del_i : std_logic;
signal mult_done_del_i : std_logic;
signal e0_i : std_logic_vector(15 downto 0);
signal e1_i : std_logic_vector(15 downto 0);
signal e0_bit_i : std_logic;
signal e1_bit_i : std_logic;
signal e_bits_i : std_logic_vector(1 downto 0);
signal e_bits_0_i : std_logic;
signal cycle_counter_i : std_logic;
signal op_sel_sel_i : std_logic;
signal op_sel_i : std_logic_vector(1 downto 0);
begin
--done <= (multiplier_done and (not running_i)) or (start and buffer_empty);
done <= done_i;
-- the two exponents
/trunk/rtl/vhdl/core/cell_1b_adder.vhd
1,54 → 1,69
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: cell_1b_adder.vhd / entity cell_1b_adder
--
-- Last Modified: 18/11/2011
--
-- Description: full adder for use in the montgommery multiplier systolic array
-- currently a behavioral description
--
--
-- Dependencies: none
--
-- Revision:
-- Revision 2.00 - Major error resolved (carry & sum output were switched)
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- cell_1b_adder ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- This file contains the implementation of a 1-bit full ----
---- adder cell using logic gates ----
---- used in adder_block ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity cell_1b_adder is
Port ( a : in STD_LOGIC;
mux_result : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
port (
a : in std_logic;
mux_result : in std_logic;
cin : in std_logic;
cout : out std_logic;
r : out std_logic
);
end cell_1b_adder;
 
 
architecture Behavioral of cell_1b_adder is
signal a_xor_mux_result: std_logic;
signal a_xor_mux_result : std_logic;
begin
a_xor_mux_result <= a xor mux_result;
r <= a_xor_mux_result xor cin;
cout <= (a and mux_result) or (cin and a_xor_mux_result);
a_xor_mux_result <= a xor mux_result;
r <= a_xor_mux_result xor cin;
cout <= (a and mux_result) or (cin and a_xor_mux_result);
end Behavioral;
 
/trunk/rtl/vhdl/core/x_shift_reg.vhd
1,60 → 1,76
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: x_shift_reg.vhd / entity x_shift_reg
--
-- Last Modified: 18/06/2012
--
-- Description: n-bit shift register with lsb output
--
--
-- Dependencies: none
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- x_shift_reg ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1536 bit shift register with lsb output ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity x_shift_reg is
generic( n : integer := 1536;
t : integer := 48;
tl : integer := 16
);
port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
x_in : in STD_LOGIC_VECTOR((n-1) downto 0);
load_x : in STD_LOGIC;
next_x : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0);
x_i : out STD_LOGIC
);
generic(
n : integer := 1536;
t : integer := 48;
tl : integer := 16
);
port(
clk : in std_logic;
reset : in std_logic;
x_in : in std_logic_vector((n-1) downto 0);
load_x : in std_logic;
next_x : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
x_i : out std_logic
);
end x_shift_reg;
 
 
architecture Behavioral of x_shift_reg is
signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- nr of stages
constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- nr of stages
constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
begin
 
REG_PROC: process(reset, clk)
begin
if reset = '1' then -- Reset, clear the register
71,8 → 87,7
end process;
 
with p_sel select -- pipeline select
x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
x_reg_i(0) when others; -- use LS bit for lower part of pipeline
x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
x_reg_i(0) when others; -- use LS bit for lower part of pipeline
 
end Behavioral;
 
/trunk/rtl/vhdl/core/register_n.vhd
1,53 → 1,71
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: register_n.vhd / entity register_n
--
-- Last Modified: 24/11/2011
--
-- Description: n bit register
--
--
-- Dependencies: FDCE
--
-- Revision:
-- Revision 3.00 - Replaced LDCE primitive with FDCE primitive
-- Revision 2.00 - Replaced behavioral architecture with structural using FPGA
-- primitives.
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- register_n ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n bit register ----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Xilinx primitives used
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity register_n is
generic( n : integer := 4
);
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR((n-1) downto 0);
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
);
generic(
n : integer := 4
);
port(
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
din : in std_logic_vector((n-1) downto 0);
dout : out std_logic_vector((n-1) downto 0)
);
end register_n;
 
 
architecture Structural of register_n is
signal dout_i : std_logic_vector((n-1) downto 0) := (others => '0');
begin
54,18 → 72,18
dout <= dout_i;
N_REGS: for i in 0 to n-1 generate
FDCE_inst : FDCE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => dout_i(i), -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din(i), -- Data input
C => core_clk, -- Gate input
CE => ce -- Gate enable input
);
end generate;
N_REGS : for i in 0 to n-1 generate
FDCE_inst : FDCE
generic map (
INIT => '0' -- Initial value of latch ('0' or '1')
)
port map (
Q => dout_i(i), -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din(i), -- Data input
C => core_clk, -- Gate input
CE => ce -- Gate enable input
);
end generate;
end Structural;
end Structural;
/trunk/rtl/vhdl/core/cell_1b.vhd
1,88 → 1,94
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: cell_1b.vhd / entity cell_1b
--
-- Last Modified: 14/11/2011
--
-- Description: cell for use in the montgommery multiplier systolic array
--
--
-- Dependencies: cell_1b_adder
-- cell_1b_mux
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- cel_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1 bit cell for use in the montgommery multiplier systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - cell_1bit_adder ----
---- - cell_1bit_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity cell_1b is
Port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
port (
my : in std_logic;
y : in std_logic;
m : in std_logic;
x : in std_logic;
q : in std_logic;
a : in std_logic;
cin : in std_logic;
cout : out std_logic;
r : out std_logic
);
end cell_1b;
 
 
architecture Structural of cell_1b is
component cell_1b_mux
Port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
result : out STD_LOGIC);
end component;
component cell_1b_adder
Port ( a : in STD_LOGIC;
mux_result : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
end component;
 
signal mux2adder : std_logic;
signal mux2adder : std_logic;
begin
cell_mux: cell_1b_mux
port map( my => my,
y => y,
m => m,
x => x,
q => q,
result => mux2adder
);
 
cell_adder: cell_1b_adder
port map(a => a,
mux_result => mux2adder,
cin => cin,
cout => cout,
r => r
);
cell_mux : cell_1b_mux
port map(
my => my,
y => y,
m => m,
x => x,
q => q,
result => mux2adder
);
 
end Structural;
cell_adder : cell_1b_adder
port map(
a => a,
mux_result => mux2adder,
cin => cin,
cout => cout,
r => r
);
 
end Structural;
/trunk/rtl/vhdl/core/mont_ctrl.vhd
1,110 → 1,112
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: mont_ctrl.vhd / entity mont_ctrl
--
-- Last Modified: 25/04/2012
--
-- Description: control unit for a pipelined montgomery multiplier, with split
-- pipeline operation and "auto-run" support
--
--
-- Dependencies: autorun_cntrl
--
-- Revision:
-- Revision 2.00 - Added autorun_control_logic
-- Revision 1.00 - Architecture with support for single multiplication
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- mont_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- control unit for a pipelined montgomery multiplier, with ----
---- split pipeline operation and "auto-run" support ----
---- ----
---- Dependencies: ----
---- - autorun_cntrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity mont_ctrl is
port ( clk : in std_logic; --v
reset : in std_logic; --v
-- bus side
start : in std_logic; --v
--p_sel : in std_logic_vector(1 downto 0);
x_sel_single : in std_logic_vector(1 downto 0); --v
y_sel_single : in std_logic_vector(1 downto 0); --v
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic; -- v
-- multiplier side
op_sel : out std_logic_vector(1 downto 0); --v
load_x : out std_logic; -- v
load_result : out std_logic; --v
start_multiplier : out std_logic; -- v
multiplier_ready : in std_logic
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end mont_ctrl;
 
 
architecture Behavioral of mont_ctrl is
signal start_delayed_i : std_logic; -- delayed version of start input
signal start_pulse_i : std_logic;
signal auto_start_pulse_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_up_counter_i : std_logic_vector(2 downto 0):= "100"; -- used in op_sel at multiplier start
signal auto_start_i : std_logic := '0';
signal store_autorun_i : std_logic;
signal run_auto_i : std_logic;
signal run_auto_stored_i : std_logic := '0';
signal single_start_pulse_i : std_logic;
signal calc_time_i : std_logic; -- high ('1') during multiplication
signal x_sel_i : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel_i : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer_i : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
signal start_delayed_i : std_logic; -- delayed version of start input
signal start_pulse_i : std_logic;
signal auto_start_pulse_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_up_counter_i : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
signal auto_start_i : std_logic := '0';
signal store_autorun_i : std_logic;
signal run_auto_i : std_logic;
signal run_auto_stored_i : std_logic := '0';
signal single_start_pulse_i : std_logic;
 
signal auto_done_i : std_logic;
signal start_auto_i : std_logic;
signal new_buf_part_i : std_logic;
signal new_buf_word_i : std_logic;
signal buf_part_i : std_logic_vector(3 downto 0);
signal pop_i : std_logic;
signal start_autorun_cycle_i : std_logic;
signal start_autorun_cycle_1_i : std_logic;
signal autorun_counter_i : std_logic_vector(1 downto 0);
signal part_counter_i : std_logic_vector(2 downto 0);
signal auto_multiplier_done_i : std_logic;
signal calc_time_i : std_logic; -- high ('1') during multiplication
 
signal x_sel_i : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel_i : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer_i : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
 
signal auto_done_i : std_logic;
signal start_auto_i : std_logic;
signal new_buf_part_i : std_logic;
signal new_buf_word_i : std_logic;
signal buf_part_i : std_logic_vector(3 downto 0);
signal pop_i : std_logic;
signal start_autorun_cycle_i : std_logic;
signal start_autorun_cycle_1_i : std_logic;
signal autorun_counter_i : std_logic_vector(1 downto 0);
signal part_counter_i : std_logic_vector(2 downto 0);
signal auto_multiplier_done_i : std_logic;
COMPONENT autorun_cntrl
PORT(
clk : IN std_logic;
reset : IN std_logic;
start : IN std_logic;
multiplier_done : IN std_logic;
buffer_din : IN std_logic_vector(31 downto 0);
buffer_empty : IN std_logic;
done : OUT std_logic;
op_sel : OUT std_logic_vector(1 downto 0);
start_multiplier : OUT std_logic;
read_buffer : OUT std_logic
);
END COMPONENT;
begin
 
-----------------------------------------------------------------------------------
117,11 → 119,8
start_delayed_i <= start;
end if;
end process START_PULSE_PROC;
--start_pulse_i <= store_autorun_i and (not run_auto_i);
start_pulse_i <= start and (not start_delayed_i);
single_start_pulse_i <= start_pulse_i and (not run_auto_i);
--store_autorun_i <= (start and (not start_delayed_i));
--start_auto_i <= store_autorun_i and run_auto_i;
start_auto_i <= start_pulse_i and run_auto_i;
 
-- to start the multiplier we first need to select the y_operand and
203,22 → 202,21
-- end if;
-- end process STORE_AUTORUN_PROC;
run_auto_i <= run_auto;
--run_auto_i <= run_auto or run_auto_stored_i;
-- multiplier_ready is only passed to autorun control when in autorun mode
auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
autorun_control_logic: autorun_cntrl PORT MAP(
clk => clk,
reset => reset,
start => start_auto_i,
done => auto_done_i,
op_sel => x_sel_buffer_i,
start_multiplier => auto_start_pulse_i,
multiplier_done => auto_multiplier_done_i,
read_buffer => read_buffer,
buffer_din => op_sel_buffer,
buffer_empty => op_buffer_empty
);
autorun_control_logic : autorun_cntrl port map(
clk => clk,
reset => reset,
start => start_auto_i,
done => auto_done_i,
op_sel => x_sel_buffer_i,
start_multiplier => auto_start_pulse_i,
multiplier_done => auto_multiplier_done_i,
read_buffer => read_buffer,
buffer_din => op_sel_buffer,
buffer_empty => op_buffer_empty
);
 
end Behavioral;
 
/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd
1,278 → 1,251
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: mont_mult_sys_pipeline.vhd / entity mont_mult_sys_pipeline
--
-- Last Modified: 18/06/2012
--
-- Description: n-bit montgomery multiplier with a pipelined systolic array
--
--
-- Dependencies: systolic_pipeline
-- adder_n
-- cell_1b_adder
-- x_shift_register
--
-- Revision:
-- Revision 3.00 - shift register for x selection in stead of decoding logic
-- Revision 2.01 - Bug fix of the bug fix
-- Revision 2.00 - Major bug fix in reduction logic (carry in upper part)
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- mont_mult_sys_pipline ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n-bit montgomery multiplier with a pipelined systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - x_shift_reg ----
---- - adder_n ----
---- - d_flip_flop ----
---- - systolic_pipeline ----
---- - cell_1b_adder ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity mont_mult_sys_pipeline is
generic ( n : integer := 1536;
nr_stages : integer := 96; --(divides n, bits_low & (n-bits_low))
stages_low : integer := 32
);
Port ( core_clk : in STD_LOGIC;
xy : in STD_LOGIC_VECTOR((n-1) downto 0);
m : in STD_LOGIC_VECTOR((n-1) downto 0);
r : out STD_LOGIC_VECTOR((n-1) downto 0);
start : in STD_LOGIC;
reset : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0);
load_x : in std_logic;
ready : out STD_LOGIC
);
generic (
n : integer := 1536;
nr_stages : integer := 96; --(divides n, bits_low & (n-bits_low))
stages_low : integer := 32
);
port (
core_clk : in std_logic;
xy : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
r : out std_logic_vector((n-1) downto 0);
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end mont_mult_sys_pipeline;
 
 
architecture Structural of mont_mult_sys_pipeline is
component adder_n
generic ( width : integer := 16;
block_width : integer := 4
);
Port ( core_clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
b : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR((width-1) downto 0)
);
end component;
component systolic_pipeline
generic( n : integer := 1536; -- width of the operands (# bits)
t : integer := 96; -- number of stages (divider of n) >= 2
tl: integer := 32
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((n) downto 0);
y : in STD_LOGIC_VECTOR((n-1) downto 0);
m : in STD_LOGIC_VECTOR((n-1) downto 0);
xi : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0);
ready : out STD_LOGIC;
next_x : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((n+1) downto 0)
);
end component;
component x_shift_reg
generic( n : integer := 32;
t : integer := 8;
tl : integer := 3
);
port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
x_in : in STD_LOGIC_VECTOR((n-1) downto 0);
load_x : in STD_LOGIC;
next_x : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0);
x_i : out STD_LOGIC
);
end component;
component cell_1b_adder
Port ( a : in STD_LOGIC;
mux_result : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
end component;
constant stage_width : integer := n/nr_stages;
constant bits_l : integer := stage_width * stages_low;
constant bits_h : integer := n - bits_l;
 
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
signal my : std_logic_vector(n downto 0);
signal my_h_cin : std_logic;
signal my_l_cout : std_logic;
signal r_pipeline : std_logic_vector(n+1 downto 0);
signal r_red : std_logic_vector(n-1 downto 0);
signal r_i : std_logic_vector(n-1 downto 0);
signal c_red_l : std_logic_vector(2 downto 0);
signal c_red_h : std_logic_vector(2 downto 0);
signal cin_red_h : std_logic;
signal r_sel : std_logic;
signal reset_multiplier : std_logic;
signal start_multiplier : std_logic;
signal m_inv : std_logic_vector(n-1 downto 0);
 
constant stage_width : integer := n/nr_stages;
constant bits_l : integer := stage_width * stages_low;
constant bits_h : integer := n - bits_l;
signal my : std_logic_vector(n downto 0);
signal my_h_cin : std_logic;
signal my_l_cout : std_logic;
signal r_pipeline : std_logic_vector(n+1 downto 0);
signal r_red : std_logic_vector(n-1 downto 0);
signal r_i : std_logic_vector(n-1 downto 0);
signal c_red_l : std_logic_vector(2 downto 0);
signal c_red_h : std_logic_vector(2 downto 0);
signal cin_red_h : std_logic;
signal r_sel : std_logic;
signal reset_multiplier : std_logic;
signal start_multiplier : std_logic;
signal m_inv : std_logic_vector(n-1 downto 0);
signal next_x_i : std_logic;
signal x_i : std_logic;
signal next_x_i : std_logic;
signal x_i : std_logic;
begin
-- x selection
x_selection: x_shift_reg
generic map( n => n,
t => nr_stages,
tl => stages_low
)
port map(clk => core_clk,
reset => reset,
x_in => xy,
load_x => load_x,
next_x => next_x_i,
p_sel => p_sel,
x_i => x_i
);
 
-- precomputation of my (m+y)
my_adder_l: adder_n
generic map( width => bits_l,
block_width => stage_width
)
port map( core_clk => core_clk,
a => m((bits_l-1) downto 0),
b => xy((bits_l-1) downto 0),
cin => '0',
cout => my_l_cout,
s => my((bits_l-1) downto 0)
);
-- x selection
x_selection : x_shift_reg
generic map(
n => n,
t => nr_stages,
tl => stages_low
)
port map(
clk => core_clk,
reset => reset,
x_in => xy,
load_x => load_x,
next_x => next_x_i,
p_sel => p_sel,
x_i => x_i
);
 
-- precomputation of my (m+y)
my_adder_l : adder_n
generic map(
width => bits_l,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m((bits_l-1) downto 0),
b => xy((bits_l-1) downto 0),
cin => '0',
cout => my_l_cout,
s => my((bits_l-1) downto 0)
);
my_adder_h: adder_n
generic map( width => bits_h,
block_width => stage_width
)
port map( core_clk => core_clk,
a => m((n-1) downto bits_l),
b => xy((n-1) downto bits_l),
cin => my_h_cin,
cout => my(n),
s => my((n-1) downto bits_l)
);
my_adder_h : adder_n
generic map(
width => bits_h,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m((n-1) downto bits_l),
b => xy((n-1) downto bits_l),
cin => my_h_cin,
cout => my(n),
s => my((n-1) downto bits_l)
);
 
my_h_cin <= '0' when (p_sel(1) and (not p_sel(0)))='1' else my_l_cout;
-- multiplication
reset_multiplier <= reset or start;
 
delay_1_cycle: d_flip_flop
port map(core_clk => core_clk,
reset => reset,
din => start,
dout => start_multiplier
);
delay_1_cycle : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => start_multiplier
);
 
the_multiplier: systolic_pipeline
generic map( n => n, -- width of the operands (# bits)
t => nr_stages, -- number of stages (divider of n) >= 2
tl => stages_low
)
port map(core_clk => core_clk,
my => my,
y => xy,
m => m,
xi => x_i,
start => start_multiplier,
reset => reset_multiplier,
p_sel => p_sel,
ready => ready, -- misschien net iets te vroeg?
next_x => next_x_i,
r => r_pipeline
);
the_multiplier : systolic_pipeline
generic map(
n => n, -- width of the operands (# bits)
t => nr_stages, -- number of stages (divider of n) >= 2
tl => stages_low
)
port map(
core_clk => core_clk,
my => my,
y => xy,
m => m,
xi => x_i,
start => start_multiplier,
reset => reset_multiplier,
p_sel => p_sel,
ready => ready, -- misschien net iets te vroeg?
next_x => next_x_i,
r => r_pipeline
);
-- post-computation (reduction)
m_inv <= not(m);
reduction_adder_l: adder_n
generic map( width => bits_l,
block_width => stage_width
)
port map( core_clk => core_clk,
a => m_inv((bits_l-1) downto 0),
b => r_pipeline((bits_l-1) downto 0),
cin => '1',
cout => c_red_l(0),
s => r_red((bits_l-1) downto 0)
);
reduction_adder_l : adder_n
generic map(
width => bits_l,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m_inv((bits_l-1) downto 0),
b => r_pipeline((bits_l-1) downto 0),
cin => '1',
cout => c_red_l(0),
s => r_red((bits_l-1) downto 0)
);
 
reduction_adder_l_a : cell_1b_adder
port map(
a => '1',
mux_result => r_pipeline(bits_l),
cin => c_red_l(0),
cout => c_red_l(1)
--r =>
);
 
reduction_adder_l_b : cell_1b_adder
port map(
a => '1',
mux_result => r_pipeline(bits_l+1),
cin => c_red_l(1),
cout => c_red_l(2)
-- r =>
);
reduction_adder_l_a: cell_1b_adder
port map(a => '1',
mux_result => r_pipeline(bits_l),
cin => c_red_l(0),
cout => c_red_l(1)
--r =>
);
reduction_adder_l_b: cell_1b_adder
port map(a => '1',
mux_result => r_pipeline(bits_l+1),
cin => c_red_l(1),
cout => c_red_l(2)
-- r =>
);
--cin_red_h <= p_sel(1) and (not p_sel(0));
cin_red_h <= c_red_l(0) when p_sel(0) = '1' else '1';
reduction_adder_h: adder_n
generic map( width => bits_h,
block_width => stage_width
)
port map( core_clk => core_clk,
a => m_inv((n-1) downto bits_l),
b => r_pipeline((n-1) downto bits_l),
cin => cin_red_h,
cout => c_red_h(0),
s => r_red((n-1) downto bits_l)
);
reduction_adder_h_a: cell_1b_adder
port map(a => '1',
mux_result => r_pipeline(n),
cin => c_red_h(0),
cout => c_red_h(1)
);
reduction_adder_h_b: cell_1b_adder
port map(a => '1',
mux_result => r_pipeline(n+1),
cin => c_red_h(1),
cout => c_red_h(2)
);
reduction_adder_h : adder_n
generic map(
width => bits_h,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m_inv((n-1) downto bits_l),
b => r_pipeline((n-1) downto bits_l),
cin => cin_red_h,
cout => c_red_h(0),
s => r_red((n-1) downto bits_l)
);
 
reduction_adder_h_a : cell_1b_adder
port map(
a => '1',
mux_result => r_pipeline(n),
cin => c_red_h(0),
cout => c_red_h(1)
);
 
reduction_adder_h_b : cell_1b_adder
port map(
a => '1',
mux_result => r_pipeline(n+1),
cin => c_red_h(1),
cout => c_red_h(2)
);
 
r_sel <= (c_red_h(2) and p_sel(1)) or (c_red_l(2) and (p_sel(0) and (not p_sel(1))));
r_i <= r_red when r_sel = '1' else r_pipeline((n-1) downto 0);
/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
0,0 → 1,436
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
package mod_sim_exp_pkg is
component adder_n is
generic (
width : integer := 1536;
block_width : integer := 8
);
port (
core_clk : in std_logic;
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
s : out std_logic_vector((width-1) downto 0)
);
end component adder_n;
component adder_block is
generic (
width : integer := 32
);
port (
core_clk : in std_logic;
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
s : out std_logic_vector((width-1) downto 0)
);
end component adder_block;
component autorun_cntrl is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end component autorun_cntrl;
component cell_1b_adder is
port (
a : in std_logic;
mux_result : in std_logic;
cin : in std_logic;
cout : out std_logic;
r : out std_logic
);
end component cell_1b_adder;
component cell_1b_mux is
port (
my : in std_logic;
y : in std_logic;
m : in std_logic;
x : in std_logic;
q : in std_logic;
result : out std_logic
);
end component cell_1b_mux;
component cell_1b is
port (
my : in std_logic;
y : in std_logic;
m : in std_logic;
x : in std_logic;
q : in std_logic;
a : in std_logic;
cin : in std_logic;
cout : out std_logic;
r : out std_logic
);
end component cell_1b;
component counter_sync is
generic(
max_value : integer := 1024
);
port(
reset_value : in integer;
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
overflow : out std_logic
);
end component counter_sync;
component d_flip_flop is
port(
core_clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component d_flip_flop;
component fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_primitive;
component first_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width) downto 0);
y : in std_logic_vector((width) downto 0);
m : in std_logic_vector((width) downto 0);
xin : in std_logic;
xout : out std_logic;
qout : out std_logic;
a_msb : in std_logic;
cout : out std_logic;
start : in std_logic;
reset : in std_logic;
done : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end component first_stage;
component last_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-2) downto 0);
m : in std_logic_vector((width-2) downto 0);
xin : in std_logic;
qin : in std_logic;
cin : in std_logic;
start : in std_logic;
reset : in std_logic;
r : out std_logic_vector((width+1) downto 0)
);
end component last_stage;
component modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component modulus_ram;
component mont_ctrl is
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end component mont_ctrl;
component mont_mult_sys_pipeline is
generic (
n : integer := 1536;
nr_stages : integer := 96; --(divides n, bits_low & (n-bits_low))
stages_low : integer := 32
);
port (
core_clk : in std_logic;
xy : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
r : out std_logic_vector((n-1) downto 0);
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end component mont_mult_sys_pipeline;
component multiplier_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
end component multiplier_core;
component operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component operand_dp;
component operand_mem is
generic(n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end component operand_mem;
component operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end component operand_ram;
component operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component operands_sp;
component register_1b is
port(
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component register_1b;
component register_n is
generic(
n : integer := 4
);
port(
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
din : in std_logic_vector((n-1) downto 0);
dout : out std_logic_vector((n-1) downto 0)
);
end component register_n;
component standard_cell_block is
generic (
width : integer := 16
);
port (
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
x : in std_logic;
q : in std_logic;
a : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end component standard_cell_block;
component standard_stage is
generic(
width : integer := 32
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
xin : in std_logic;
qin : in std_logic;
xout : out std_logic;
qout : out std_logic;
a_msb : in std_logic;
cin : in std_logic;
cout : out std_logic;
start : in std_logic;
reset : in std_logic;
done : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end component standard_stage;
component stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic;
start : in std_logic;
reset : in std_logic;
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out std_logic;
stepping_done : out std_logic
);
end component stepping_logic;
component systolic_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- number of stages (divider of n) >= 2
tl : integer := 64 -- best take t = sqrt(n)
);
port(
core_clk : in std_logic;
my : in std_logic_vector((n) downto 0);
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
xi : in std_logic;
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
ready : out std_logic;
next_x : out std_logic;
r : out std_logic_vector((n+1) downto 0)
);
end component systolic_pipeline;
component x_shift_reg is
generic(
n : integer := 1536;
t : integer := 48;
tl : integer := 16
);
port(
clk : in std_logic;
reset : in std_logic;
x_in : in std_logic_vector((n-1) downto 0);
load_x : in std_logic;
next_x : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
x_i : out std_logic
);
end component x_shift_reg;
end package mod_sim_exp_pkg;
/trunk/rtl/vhdl/core/stepping_logic.vhd
1,95 → 1,88
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: stepping_logic.vhd / entity stepping_logic
--
-- Last Modified: 23/01/2012
--
-- Description: stepping logic for the pipelined montgomery multiplier
--
--
-- Dependencies: counter_sync
--
-- Revision:
-- Revision 5.01 - defined integer range for t_sel and n_sel resulting in less LUTs
-- Revision 5.00 - made the reset value changeable in runtime
-- Revision 4.01 - Delayed ready pulse with 1 clk cylce. This delay is necessary
-- for the reduction to complete.
-- Revision 4.00 - Changed design to fit new pipeline-architecture
-- (i.e. 1 clock cycle / stage)
-- Revision 3.00 - Removed second delay on next_x
-- Revision 2.00 - Changed operation to give a pulse on stepping_done when pipeline
-- operation has finished
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- stepping_logic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- stepping logic for the pipelined montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - d_flip_flop ----
---- - counter_sync ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity stepping_logic is
generic( n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port( core_clk : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out STD_LOGIC;
stepping_done : out STD_LOGIC
);
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic;
start : in std_logic;
reset : in std_logic;
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out std_logic;
stepping_done : out std_logic
);
end stepping_logic;
 
 
architecture Behavioral of stepping_logic is
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
component counter_sync
generic(max_value : integer := 16
);
port(reset_value : in integer;
core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
overflow : out STD_LOGIC
);
end component;
signal laststeps_in_i : std_logic := '0';
signal laststeps_out_i : std_logic := '0';
signal start_stop_in_i : std_logic := '0';
signal start_stop_out_i : std_logic := '0';
signal steps_in_i : std_logic := '0';
signal steps_out_i : std_logic := '0';
signal substeps_in_i : std_logic := '0';
signal substeps_out_i : std_logic := '0';
signal done_reg_in_i : std_logic := '0';
signal done_reg_out_i : std_logic := '0';
signal start_first_stage_i : std_logic := '0';
signal start_i : std_logic := '0';
 
signal laststeps_in_i : std_logic := '0';
signal laststeps_out_i : std_logic := '0';
signal start_stop_in_i : std_logic := '0';
signal start_stop_out_i : std_logic := '0';
signal steps_in_i : std_logic := '0';
signal steps_out_i : std_logic := '0';
signal substeps_in_i : std_logic := '0';
signal substeps_out_i : std_logic := '0';
signal done_reg_in_i : std_logic := '0';
signal done_reg_out_i : std_logic := '0';
signal start_first_stage_i : std_logic := '0';
signal start_i : std_logic := '0';
 
begin
start_i <= start;
 
106,51 → 99,59
start_first_stage_i <= start_i or steps_in_i;
--start_first_stage_i <= steps_in_i;
done_reg: d_flip_flop
port map(core_clk => core_clk,
reset => reset,
din => done_reg_in_i,
dout => done_reg_out_i
);
start_stop_reg: d_flip_flop
port map(core_clk => core_clk,
reset => reset,
din => start_stop_in_i,
dout => start_stop_out_i
);
-- for counting the last steps
laststeps_counter: counter_sync
generic map(max_value => t
)
port map(reset_value => t_sel,
core_clk => core_clk,
ce => laststeps_in_i,
reset => reset,
overflow => laststeps_out_i
);
-- counter for keeping track of the steps
steps_counter: counter_sync
generic map(max_value => n
)
port map(reset_value => (n_sel),
core_clk => core_clk,
ce => steps_in_i,
reset => reset,
overflow => steps_out_i
);
-- makes sure we don't start too early with a new step
substeps_counter: counter_sync
generic map(max_value => 2
)
port map(reset_value => 2,
core_clk => core_clk,
ce => substeps_in_i,
reset => reset,
overflow => substeps_out_i
);
done_reg : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => done_reg_in_i,
dout => done_reg_out_i
);
 
start_stop_reg : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start_stop_in_i,
dout => start_stop_out_i
);
 
-- for counting the last steps
laststeps_counter : counter_sync
generic map(
max_value => t
)
port map(
reset_value => t_sel,
core_clk => core_clk,
ce => laststeps_in_i,
reset => reset,
overflow => laststeps_out_i
);
 
-- counter for keeping track of the steps
steps_counter : counter_sync
generic map(
max_value => n
)
port map(
reset_value => (n_sel),
core_clk => core_clk,
ce => steps_in_i,
reset => reset,
overflow => steps_out_i
);
 
-- makes sure we don't start too early with a new step
substeps_counter : counter_sync
generic map(
max_value => 2
)
port map(
reset_value => 2,
core_clk => core_clk,
ce => substeps_in_i,
reset => reset,
overflow => substeps_out_i
);
 
end Behavioral;
/trunk/rtl/vhdl/core/register_1b.vhd
1,48 → 1,68
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: register_1b.vhd / entity register_1b
--
-- Last Modified: 24/11/2011
--
-- Description: 1 bit register
--
--
-- Dependencies: LDCE
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- register_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1 bit register ----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Xilinx primitives used
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity register_1b is
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
port(
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end register_1b;
 
 
architecture Structural of register_1b is
signal dout_i : std_logic;
begin
49,15 → 69,16
dout <= dout_i;
FDCE_inst : FDCE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => dout_i, -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din, -- Data input
C => core_clk, -- Gate input
CE => ce -- Gate enable input
);
FDCE_inst : FDCE
generic map (
INIT => '0' -- Initial value of latch ('0' or '1')
)
port map (
Q => dout_i, -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din, -- Data input
C => core_clk, -- Gate input
CE => ce -- Gate enable input
);
end Structural;
/trunk/rtl/vhdl/core/standard_cell_block.vhd
1,84 → 1,95
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: standard_cell_block.vhd / entity standard_cell_block
--
-- Last Modified: 14/11/2011
--
-- Description: cell_block for use in the montgommery multiplier systolic array
--
--
-- Dependencies: none
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- standard_cell_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- a block of [width] cell_1b cells for use in the ----
---- montgommery multiplier systolic array ----
---- ----
---- Dependencies: ----
---- - cell_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity standard_cell_block is
generic ( width : integer := 16
);
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0));
generic (
width : integer := 16
);
port (
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
x : in std_logic;
q : in std_logic;
a : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end standard_cell_block;
 
 
architecture Structural of standard_cell_block is
component cell_1b
Port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
end component;
 
signal carry : std_logic_vector(width downto 0);
begin
carry(0) <= cin;
cell_block: for i in 0 to (width-1) generate
cells: cell_1b
port map( my => my(i),
y => y(i),
m => m(i),
x => x,
q => q,
a => a(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
cell_block : for i in 0 to (width-1) generate
cells : cell_1b
port map(
my => my(i),
y => y(i),
m => m(i),
x => x,
q => q,
a => a(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
 
cout <= carry(width);
end Structural;
end Structural;
/trunk/rtl/vhdl/core/first_stage.vhd
1,152 → 1,104
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: first_stage.vhd / entity first_stage
--
-- Last Modified: 24/11/2011
--
-- Description: first stage for use in the montgommery multiplier systolic
-- array pipeline
--
--
-- Dependencies: standard_cell_block
-- cell_mux_1b
-- register_n,
-- register_1b,
-- d_flip_flop
--
-- Revision:
-- Revision 4.00 - Removed input registers and used start signal as load_out_regs
-- Revision 3.00 - Removed "a" input and replaced with "a_msb" (which is the only one
-- that matters.
-- Revision 2.02 - removed "ready" output signal
-- Revision 2.01 - replaced the behavioral description of the registers with a
-- component instantiation
-- Revision 2.00 - added register to store input value xin (because this
-- can change during operation)
-- Revision 1.03 - added done pulse
-- Revision 1.02 - appended "_i" to name of all internal signals
-- Revision 1.01 - ready is '1' after reset
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- first_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- first stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - d_flip_flop ----
---- - register_n ----
---- - register_1b ----
---- - cell_1b_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity first_stage is
generic(width : integer := 16 -- must be the same as width of the standard stage
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width) downto 0);
y : in STD_LOGIC_VECTOR((width) downto 0);
m : in STD_LOGIC_VECTOR((width) downto 0);
xin : in STD_LOGIC;
xout : out STD_LOGIC;
qout : out STD_LOGIC;
a_msb : in STD_LOGIC;
cout : out STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
-- ready : out STD_LOGIC;
done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0)
);
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width) downto 0);
y : in std_logic_vector((width) downto 0);
m : in std_logic_vector((width) downto 0);
xin : in std_logic;
xout : out std_logic;
qout : out std_logic;
a_msb : in std_logic;
cout : out std_logic;
start : in std_logic;
reset : in std_logic;
done : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end first_stage;
 
 
architecture Structural of first_stage is
-- input
signal xin_i : std_logic;
signal a_msb_i : std_logic;
 
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal cout_reg_i : std_logic;
signal xout_reg_i : std_logic;
signal qout_reg_i : std_logic;
signal r_reg_i : std_logic_vector((width-1) downto 0);
 
component register_1b
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
component register_n
generic( n : integer := 4
);
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR((n-1) downto 0);
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
);
end component;
-- interconnection
signal q_i : std_logic;
signal c_i : std_logic;
signal first_res_i : std_logic;
signal a_i : std_logic_vector((width) downto 0);
 
component standard_cell_block
generic ( width : integer := 32
);
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0));
end component;
 
component cell_1b_mux
port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
result : out STD_LOGIC);
end component;
 
-- input
signal xin_i : std_logic;
signal a_msb_i : std_logic;
-- signal xin_reg_i : std_logic;
-- signal a_msb_reg_i : std_logic;
 
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal cout_reg_i : std_logic;
signal xout_reg_i : std_logic;
signal qout_reg_i : std_logic;
signal r_reg_i : std_logic_vector((width-1) downto 0);
 
-- interconnection
signal q_i : std_logic;
signal c_i : std_logic;
signal first_res_i : std_logic;
signal a_i : std_logic_vector((width) downto 0);
-- control signals
signal done_i : std_logic := '1';
--signal ready_del_i : std_logic := '1';
-- signal load_out_regs_i : std_logic;
-- control signals
signal done_i : std_logic := '1';
begin
-- map inputs to internal signals
159,113 → 111,86
cout <= cout_reg_i;
qout <= qout_reg_i;
xout <= xout_reg_i;
-- two posibilities:
--done <= ready_i and (not ready_del_i); -- slow
--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
-- a_i <= a_msb_reg_i & r_reg_i;
a_i <= a_msb_i & r_reg_i;
 
-- -- input registers
-- A_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => a_msb_i,
-- dout => a_msb_reg_i
-- );
--
-- XIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => xin_i,
-- dout => xin_reg_i
-- );
-- compute first q_i and carry
-- q_i <= a_i(0) xor (y(0) and xin_reg_i);
q_i <= a_i(0) xor (y(0) and xin_i);
c_i <= a_i(0) and first_res_i;
first_cell: cell_1b_mux
port map( my => my(0),
y => y(0),
m => m(0),
-- x => xin_reg_i,
x => xin_i,
q => q_i,
result => first_res_i
);
cell_block: standard_cell_block
generic map( width => width
)
port map( my => my(width downto 1),
y => y(width downto 1),
m => m(width downto 1),
-- x => xin_reg_i,
x => xin_i,
q => q_i,
a => a_i(width downto 1),
cin => c_i,
cout => cout_i,
r => r_i((width-1) downto 0)
);
-- delay_1_cycle: d_flip_flop
-- port map(core_clk => core_clk,
-- reset => reset,
-- din => start,
-- dout => load_out_regs_i
-- );
done_signal: d_flip_flop
port map(core_clk => core_clk,
reset => reset,
-- din => load_out_regs_i,
din => start,
dout => done_i
);
-- output registers
RESULT_REG: register_n
generic map( n => width
)
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
XOUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
-- din => xin_reg_i,
din => xin_i,
dout => xout_reg_i
);
QOUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => q_i,
dout => qout_reg_i
);
COUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => cout_i,
dout => cout_reg_i
);
first_cell : cell_1b_mux
port map(
my => my(0),
y => y(0),
m => m(0),
x => xin_i,
q => q_i,
result => first_res_i
);
 
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my(width downto 1),
y => y(width downto 1),
m => m(width downto 1),
x => xin_i,
q => q_i,
a => a_i(width downto 1),
cin => c_i,
cout => cout_i,
r => r_i((width-1) downto 0)
);
 
done_signal : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => done_i
);
 
-- output registers
RESULT_REG : register_n
generic map(
n => width
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
 
XOUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => xin_i,
dout => xout_reg_i
);
 
QOUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => q_i,
dout => qout_reg_i
);
 
COUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cout_i,
dout => cout_reg_i
);
 
 
end Structural;
/trunk/rtl/vhdl/core/counter_sync.vhd
1,52 → 1,67
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: counter_sync.vhd / entity counter_sync
--
-- Last Modified: 23/01/2012
--
-- Description: counter with synchronous count enable. It generates an
-- overflow when max_value is reached
--
--
-- Dependencies: none
--
-- Revision:
-- Revision 2.00 - moved max_value from generic to port so it is changeable in runtime
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- counter_sync ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- counter with synchronous count enable. It generates an ----
---- overflow when max_value is reached ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity counter_sync is
generic(max_value : integer := 1024
);
port(reset_value : in integer;
core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
overflow : out STD_LOGIC
);
generic(
max_value : integer := 1024
);
port(
reset_value : in integer;
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
overflow : out std_logic
);
end counter_sync;
 
 
architecture Behavioral of counter_sync is
signal overflow_i : std_logic := '0';
/trunk/rtl/vhdl/core/fifo_primitive.vhd
1,53 → 1,73
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: adder_n.vhd / entity adder_n
--
-- Last Modified: 04/04/2012
--
-- Description: 512x32-bit fifo
--
--
-- Dependencies: FIFO18E1 primitive
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- fifo_primitive ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 x 32 bit fifo ----
---- ----
---- Dependencies: ----
---- - FIFO18E1 (xilinx primitive) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Xilinx primitives used in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity fifo_primitive is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
reset : in STD_LOGIC;
nopop : out STD_LOGIC;
nopush : out STD_LOGIC
);
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end fifo_primitive;
 
 
architecture Behavioral of fifo_primitive is
signal rdcount : std_logic_vector(11 downto 0); -- debugging
signal wrcount : std_logic_vector(11 downto 0); -- debugging
90,7 → 110,7
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
INIT => X"000000000", -- Initial values on output port
SRVAL => X"000000000" -- Set/Reset value for output port
103,22 → 123,21
EMPTY => empty_i, -- 1-bit empty output flag
FULL => full_i, -- 1-bit full output flag
-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers
RDCOUNT => RDCOUNT, -- 12-bit read count output
WRCOUNT => WRCOUNT, -- 12-bit write count output
RDCOUNT => RDCOUNT, -- 12-bit read count output
WRCOUNT => WRCOUNT, -- 12-bit write count output
-- WRERR, RDERR: 1-bit (each) FIFO full or empty error
RDERR => rderr_i, -- 1-bit read error output
WRERR => wrerr_i, -- 1-bit write error
DI => din, -- 32-bit data input
DIP => "0000", -- 4-bit parity input
RDEN => pop_i, -- 1-bit read enable input
REGCE => '1', -- 1-bit clock enable input
RST => reset_i, -- 1-bit reset input
RSTREG => reset_i, -- 1-bit output register set/reset
DI => din, -- 32-bit data input
DIP => "0000", -- 4-bit parity input
RDEN => pop_i, -- 1-bit read enable input
REGCE => '1', -- 1-bit clock enable input
RST => reset_i, -- 1-bit reset input
RSTREG => reset_i, -- 1-bit output register set/reset
-- WRCLK, RDCLK: 1-bit (each) Clocks
RDCLK => clk, -- 1-bit read clock input
WRCLK => clk, -- 1-bit write clock input
RDCLK => clk, -- 1-bit read clock input
WRCLK => clk, -- 1-bit write clock input
WREN => push_i -- 1-bit write enable input
);
 
end Behavioral;
 
/trunk/rtl/vhdl/core/operand_dp.vhd
1,31 → 1,75
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
----------------------------------------------------------------------
---- operand_dp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 4 x 512 bit dual port ram for the operands ----
---- 32 bit read and write for bus side and 512 bit read and ----
---- write for multiplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
35,40 → 79,46
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
library ieee;
use ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
library XilinxCoreLib;
-- synthesis translate_on
ENTITY operand_dp IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(5 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(511 downto 0);
clkb: IN std_logic;
web: IN std_logic_VECTOR(0 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
dinb: IN std_logic_VECTOR(511 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0));
END operand_dp;
 
ARCHITECTURE operand_dp_a OF operand_dp IS
 
entity operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end operand_dp;
 
 
architecture operand_dp_a of operand_dp is
-- synthesis translate_off
component wrapped_operand_dp
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(5 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(511 downto 0);
clkb: IN std_logic;
web: IN std_logic_VECTOR(0 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
dinb: IN std_logic_VECTOR(511 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0));
end component;
component wrapped_operand_dp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
122,23 → 172,24
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
c_use_default_data => 0
);
-- synthesis translate_on
BEGIN
begin
-- synthesis translate_off
U0 : wrapped_operand_dp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb);
U0 : wrapped_operand_dp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
 
END operand_dp_a;
 
end operand_dp_a;
/trunk/rtl/vhdl/core/d_flip_flop.vhd
1,62 → 1,80
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: d_flip_flop.vhd / entity d_flip_flop
--
-- Last Modified: 24/11/2011
--
-- Description: 1 bit D flip-flop
--
--
-- Dependencies: LDCE
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- d_flip_flop ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1 bit D flip-flop currently still uses primitives ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Xilinx primitives used
library unisim;
use unisim.vcomponents.all;
 
 
entity d_flip_flop is
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
port(
core_clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end d_flip_flop;
 
 
architecture Structural of d_flip_flop is
signal dout_i : std_logic;
signal dout_i : std_logic;
begin
dout <= dout_i;
FDCE_inst : FDCE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => dout_i, -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din, -- Data input
C => core_clk, -- Gate input
CE => '1' -- Gate enable input
);
end Structural;
 
dout <= dout_i;
 
FDCE_inst : FDCE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => dout_i, -- Data output
CLR => reset, -- Asynchronous clear/reset input
D => din, -- Data input
C => core_clk, -- Gate input
CE => '1' -- Gate enable input
);
 
end Structural;
/trunk/rtl/vhdl/core/operands_sp.vhd
1,33 → 1,76
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file operands_sp.vhd when simulating
-- the core, operands_sp. When compiling the wrapper file, be sure to
----------------------------------------------------------------------
---- operands_sp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 bit single port ram for the modulus ----
---- 32 write for bus side and 512 bit read for multplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
35,30 → 78,36
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
library ieee;
use ieee.std_logic_1164.all;
-- synthesis translate_off
Library XilinxCoreLib;
library XilinxCoreLib;
-- synthesis translate_on
ENTITY operands_sp IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(511 downto 0));
END operands_sp;
 
ARCHITECTURE operands_sp_a OF operands_sp IS
 
entity operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end operands_sp;
 
 
architecture operands_sp_a of operands_sp is
-- synthesis translate_off
component wrapped_operands_sp
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(511 downto 0));
end component;
component wrapped_operands_sp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operands_sp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
112,18 → 161,20
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
c_use_default_data => 0
);
-- synthesis translate_on
BEGIN
 
begin
-- synthesis translate_off
U0 : wrapped_operands_sp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
u0 : wrapped_operands_sp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
 
END operands_sp_a;
 
end operands_sp_a;
/trunk/rtl/vhdl/core/standard_stage.vhd
1,145 → 1,106
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: standard_stage.vhd / entity standard_stage
--
-- Last Modified: 24/11/2011
--
-- Description: standard stage for use in the montgommery multiplier systolic
-- array pipeline
--
--
-- Dependencies: standard_cell_block,
-- register_n,
-- register_1b,
-- d_flip_flop
--
-- Revision:
-- Revision 4.00 - Removed input registers and used start signal as load_out_regs
-- Revision 3.00 - Removed "a" input and replaced with "a_msb" (which is the only one
-- that matters.
-- Revision 2.02 - removed "ready" output signal
-- Revision 2.01 - replaced the behavioral description of the registers with a
-- component instantiation
-- Revision 2.00 - added registers to store input values xin, cin, qin (because they
-- can change during operation)
-- Revision 1.03 - added done pulse
-- Revision 1.02 - appended "_i" to name of all internal signals
-- Revision 1.01 - ready is '1' after reset
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- standard_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- standard stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - d_flip_flop ----
---- - register_n ----
---- - register_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity standard_stage is
generic(width : integer := 32
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
xin : in STD_LOGIC;
qin : in STD_LOGIC;
xout : out STD_LOGIC;
qout : out STD_LOGIC;
a_msb : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
-- ready : out STD_LOGIC;
done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0)
);
generic(
width : integer := 32
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
xin : in std_logic;
qin : in std_logic;
xout : out std_logic;
qout : out std_logic;
a_msb : in std_logic;
cin : in std_logic;
cout : out std_logic;
start : in std_logic;
reset : in std_logic;
done : out std_logic;
r : out std_logic_vector((width-1) downto 0)
);
end standard_stage;
 
 
architecture Structural of standard_stage is
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
-- input
signal cin_i : std_logic;
signal xin_i : std_logic;
signal qin_i : std_logic;
signal a_msb_i : std_logic;
 
component register_1b
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
component register_n
generic( n : integer := 4
);
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR((n-1) downto 0);
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
);
end component;
component standard_cell_block
generic ( width : integer := 32
);
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0));
end component;
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal cout_reg_i : std_logic;
signal xout_reg_i : std_logic;
signal qout_reg_i : std_logic;
signal r_reg_i : std_logic_vector((width-1) downto 0);
 
-- input
signal cin_i : std_logic;
signal xin_i : std_logic;
signal qin_i : std_logic;
signal a_msb_i : std_logic;
-- signal cin_reg_i : std_logic;
-- signal xin_reg_i : std_logic;
-- signal qin_reg_i : std_logic;
-- signal a_msb_reg_i : std_logic;
-- interconnect
signal a_i : std_logic_vector((width-1) downto 0);
 
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal cout_reg_i : std_logic;
signal xout_reg_i : std_logic;
signal qout_reg_i : std_logic;
signal r_reg_i : std_logic_vector((width-1) downto 0);
-- control
signal done_i : std_logic := '1';
begin
 
-- interconnect
signal a_i : std_logic_vector((width-1) downto 0);
 
-- control
-- signal load_out_regs_i : std_logic;
signal done_i : std_logic := '1';
--signal ready_del_i : std_logic := '1';
begin
-- map internal signals to outputs
done <= done_i;
r <= r_reg_i;
146,9 → 107,6
cout <= cout_reg_i;
qout <= qout_reg_i;
xout <= xout_reg_i;
-- two posibilities:
--done <= ready_i and (not ready_del_i); -- slow
--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
-- map inputs to internal signals
xin_i <= xin;
156,113 → 114,71
cin_i <= cin;
a_msb_i <= a_msb;
-- a_i <= a_msb_reg_i & r_reg_i((width-1) downto 1);
a_i <= a_msb_i & r_reg_i((width-1) downto 1);
-- input registers
-- A_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => a_msb_i,
-- dout => a_msb_reg_i
-- );
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my,
y => y,
m => m,
x => xin_i,
q => qin_i,
a => a_i,
cin => cin_i,
cout => cout_i,
r => r_i
);
-- XIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => xin_i,
-- dout => xin_reg_i
-- );
done_signal : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => done_i
);
 
-- output registers
RESULT_REG : register_n
generic map(
n => width
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
 
XOUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => xin_i,
dout => xout_reg_i
);
 
QOUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => qin_i,
dout => qout_reg_i
);
 
COUT_REG : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cout_i,
dout => cout_reg_i
);
 
-- QIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => qin_i,
-- dout => qin_reg_i
-- );
-- CIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => cin_i,
-- dout => cin_reg_i
-- );
cell_block: standard_cell_block
generic map( width => width
)
Port map( my => my,
y => y,
m => m,
-- x => xin_reg_i,
-- q => qin_reg_i,
x => xin_i,
q => qin_i,
a => a_i,
-- cin => cin_reg_i,
cin => cin_i,
cout => cout_i,
r => r_i
);
-- delay_1_cycle: d_flip_flop
-- port map(core_clk => core_clk,
-- reset => reset,
-- din => start,
-- dout => load_out_regs_i
-- );
done_signal: d_flip_flop
port map(core_clk => core_clk,
reset => reset,
-- din => load_out_regs_i,
din => start,
dout => done_i
);
-- output registers
RESULT_REG: register_n
generic map( n => width
)
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
XOUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
-- din => xin_reg_i,
din => xin_i,
dout => xout_reg_i
);
QOUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
-- din => qin_reg_i,
din => qin_i,
dout => qout_reg_i
);
COUT_REG: register_1b
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => cout_i,
dout => cout_reg_i
);
end Structural;
/trunk/rtl/vhdl/core/last_stage.vhd
1,160 → 1,98
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: last_stage.vhd / entity last_stage
--
-- Last Modified: 24/11/2011
--
-- Description: last stage for use in the montgommery multiplier systolic
-- array pipeline
--
--
-- Dependencies: standard_cell_block
-- cell_1b
--
-- Revision:
-- Revision 5.00 - Removed input registers and used start signal as load_out_regs
-- Revision 4.01 - Remove "done" input
-- Revision 4.00 - Removed "a" input with internal feedback
-- Revision 3.03 - fixed switched last two bits
-- Revision 3.02 - removed "ready" output signal
-- Revision 3.01 - replaced the behavioral description of the registers with a
-- component instantiation
-- Revision 3.00 - added registers to store input values xin, cin, qin (because they
-- can change during operation)
-- Revision 2.00 - changed indices in signals my, y and m
-- Revision 1.03 - added done pulse
-- Revision 1.02 - appended "_i" to name of all internal signals
-- Revision 1.01 - ready is '1' after reset
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- first_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- last stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - register_n ----
---- - cell_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity last_stage is
generic(width : integer := 16 -- must be the same as width of the standard stage
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-2) downto 0);
m : in STD_LOGIC_VECTOR((width-2) downto 0);
xin : in STD_LOGIC;
qin : in STD_LOGIC;
cin : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
-- ready : out STD_LOGIC;
-- done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width+1) downto 0)
);
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
core_clk : in std_logic;
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-2) downto 0);
m : in std_logic_vector((width-2) downto 0);
xin : in std_logic;
qin : in std_logic;
cin : in std_logic;
start : in std_logic;
reset : in std_logic;
r : out std_logic_vector((width+1) downto 0)
);
end last_stage;
 
 
architecture Structural of last_stage is
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
-- input
signal my_i : std_logic_vector(width downto 0);
signal m_i : std_logic_vector(width downto 0);
signal y_i : std_logic_vector(width downto 0);
signal cin_i : std_logic;
signal xin_i : std_logic;
signal qin_i : std_logic;
signal a_i : std_logic_vector((width) downto 0);
 
component register_1b
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
component register_n
generic( n : integer := 4
);
port(core_clk : in STD_LOGIC;
ce : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR((n-1) downto 0);
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
);
end component;
component standard_cell_block
generic ( width : integer := 32
);
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0));
end component;
-- output
signal r_i : std_logic_vector((width+1) downto 0);
signal r_reg_i : std_logic_vector((width+1) downto 0);
 
component cell_1b
port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
a : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
end component;
 
-- input
signal my_i : std_logic_vector(width downto 0);
signal m_i : std_logic_vector(width downto 0);
signal y_i : std_logic_vector(width downto 0);
signal cin_i : std_logic;
signal xin_i : std_logic;
signal qin_i : std_logic;
signal a_i : std_logic_vector((width) downto 0);
-- signal cin_reg_i : std_logic;
-- signal xin_reg_i : std_logic;
-- signal qin_reg_i : std_logic;
-- signal a_reg_i : std_logic_vector((width) downto 0);
-- interconnection
signal cout_i : std_logic;
-- output
signal r_i : std_logic_vector((width+1) downto 0);
signal r_reg_i : std_logic_vector((width+1) downto 0);
 
-- interconnection
signal cout_i : std_logic;
-- control signals
-- signal load_out_regs_i : std_logic;
-- signal done_i : std_logic := '1';
--signal ready_del_i : std_logic := '1';
begin
-- map internal signals to outputs
-- done <= done_i;
r <= r_reg_i;
-- two posibilities:
--done <= ready_i and (not ready_del_i); -- slow
--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
-- map inputs to internal signals
my_i <= '0' & my;
166,86 → 104,46
 
a_i <= r_reg_i((width+1) downto 1);
cell_block: standard_cell_block
generic map( width => width
)
Port map( my => my_i(width-1 downto 0),
y => y_i(width-1 downto 0),
m => m_i(width-1 downto 0),
-- x => xin_reg_i,
-- q => qin_reg_i,
x => xin_i,
q => qin_i,
a => a_i((width-1) downto 0),
-- cin => cin_reg_i,
cin => cin_i,
cout => cout_i,
r => r_i((width-1) downto 0)
);
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my_i(width-1 downto 0),
y => y_i(width-1 downto 0),
m => m_i(width-1 downto 0),
x => xin_i,
q => qin_i,
a => a_i((width-1) downto 0),
cin => cin_i,
cout => cout_i,
r => r_i((width-1) downto 0)
);
 
last_cell : cell_1b
port map(
my => my_i(width),
y => y_i(width),
m => m_i(width),
x => xin_i,
q => qin_i,
a => a_i(width),
cin => cout_i,
cout => r_i(width+1),
r => r_i(width)
);
 
-- output registers
RESULT_REG : register_n
generic map(
n => (width+2)
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
last_cell: cell_1b
port map( my => my_i(width),
y => y_i(width),
m => m_i(width),
-- x => xin_reg_i,
-- q => qin_reg_i,
x => xin_i,
q => qin_i,
a => a_i(width),
cin => cout_i,
cout => r_i(width+1),
r => r_i(width)
);
-- XIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => xin_i,
-- dout => xin_reg_i
-- );
-- QIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => qin_i,
-- dout => qin_reg_i
-- );
-- CIN_REG: register_1b
-- port map(core_clk => core_clk,
-- ce => start,
-- reset => reset,
-- din => cin_i,
-- dout => cin_reg_i
-- );
-- control
-- delay_1_cycle: d_flip_flop
-- port map(core_clk => core_clk,
-- reset => reset,
-- din => start,
-- dout => load_out_regs_i
-- );
-- done_signal: d_flip_flop
-- port map(core_clk => core_clk,
-- reset => reset,
-- din => load_out_regs_i,
-- dout => done_i
-- );
-- output registers
RESULT_REG: register_n
generic map( n => (width+2)
)
port map(core_clk => core_clk,
-- ce => load_out_regs_i,
ce => start,
reset => reset,
din => r_i,
dout => r_reg_i
);
end Structural;
/trunk/rtl/vhdl/core/operand_mem.vhd
1,112 → 1,102
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: operand_mem.vhd / entity operand_mem
--
-- Last Modified: 18/06/2012
--
-- Description: BRAM memory and logic to the store 4 (1536-bit) operands and the
-- modulus for the montgomery multiplier
--
--
-- Dependencies: modulus_ram, operand_ram
--
-- Revision:
-- Revision 2.00 - Removed y_register -> seperate module
-- Revision 1.01 - Added "result_dest_op" input
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- operand_mem ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- and the modulus for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_ram ----
---- - modulus_ram ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_mem is
generic(n : integer := 1536
);
port(-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
generic(n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
 
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end operand_mem;
 
 
architecture Behavioral of operand_mem is
-- single port (32-bit -> 1536-bit) block ram
component modulus_ram
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component;
signal xy_data_i : std_logic_vector(31 downto 0);
signal xy_addr_i : std_logic_vector(5 downto 0);
signal operand_in_sel_i : std_logic_vector(1 downto 0);
signal collision_i : std_logic;
 
-- dual port block ram
component operand_ram
port(
clk : in std_logic;
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
write_operand : in std_logic;
operand_out_sel : in std_logic_vector(1 downto 0);
result_dest_op : in std_logic_vector(1 downto 0);
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0);
collision : out std_logic;
result_out : out std_logic_vector(31 downto 0);
operand_out : out std_logic_vector(1535 downto 0)
);
end component;
signal xy_op_i : std_logic_vector(1535 downto 0);
 
signal xy_data_i : std_logic_vector(31 downto 0);
signal xy_addr_i : std_logic_vector(5 downto 0);
signal operand_in_sel_i : std_logic_vector(1 downto 0);
signal collision_i : std_logic;
signal m_addr_i : std_logic_vector(5 downto 0);
signal write_m_i : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
 
signal xy_op_i : std_logic_vector(1535 downto 0);
signal m_addr_i : std_logic_vector(5 downto 0);
signal write_m_i : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
begin
 
-- map outputs
121,31 → 111,31
m_data_i <= data_in;
write_m_i <= load_m;
 
-- xy operand storage
xy_ram: operand_ram port map(
clk => clk,
collision => collision_i,
operand_addr => xy_addr_i,
operand_in => xy_data_i,
operand_in_sel => operand_in_sel_i,
result_out => data_out,
write_operand => load_op,
operand_out => xy_op_i,
operand_out_sel => op_sel,
result_dest_op => result_dest_op,
write_result => load_result,
result_in => result_in
);
-- xy operand storage
xy_ram : operand_ram
port map(
clk => clk,
collision => collision_i,
operand_addr => xy_addr_i,
operand_in => xy_data_i,
operand_in_sel => operand_in_sel_i,
result_out => data_out,
write_operand => load_op,
operand_out => xy_op_i,
operand_out_sel => op_sel,
result_dest_op => result_dest_op,
write_result => load_result,
result_in => result_in
);
 
-- modulus storage
m_ram : modulus_ram
port map(
clk => clk,
modulus_addr => m_addr_i,
write_modulus => write_m_i,
modulus_in => m_data_i,
modulus_out => m
);
-- modulus storage
m_ram : modulus_ram
port map(
clk => clk,
modulus_addr => m_addr_i,
write_modulus => write_m_i,
modulus_in => m_data_i,
modulus_out => m
);
end Behavioral;
 
/trunk/rtl/vhdl/core/modulus_ram.vhd
1,57 → 1,71
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:57:21 03/08/2012
-- Design Name:
-- Module Name: modulus_ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- modulus_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to store the 1536-bit modulus ----
---- ----
---- Dependencies: ----
---- - operands_sp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end modulus_ram;
 
 
architecture Behavioral of modulus_ram is
-- single port blockram to store modulus
component operands_sp
port(
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(4 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(511 downto 0)
);
end component;
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(4 downto 0);
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(4 downto 0);
begin
 
-- the blockram has a write depth of 2 but we only use the lower half
59,10 → 73,10
-- the two highest bits of the address are used to select the bloc
with modulus_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_modulus select
wea <= part_enable when '1',
69,41 → 83,31
"0000" when others;
-- 4 instances of 512 bits blockram
modulus_0 : operands_sp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => modulus_in,
douta => modulus_out(511 downto 0)
);
modulus_1 : operands_sp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => modulus_in,
douta => modulus_out(1023 downto 512)
);
modulus_2 : operands_sp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => modulus_in,
douta => modulus_out(1535 downto 1024)
);
-- modulus_3 : operands_sp
-- port map (
-- clka => clk,
-- wea => wea(3 downto 3),
-- addra => addra,
-- dina => modulus_in,
-- douta => modulus_out(2047 downto 1536)
-- );
modulus_0 : operands_sp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => modulus_in,
douta => modulus_out(511 downto 0)
);
 
modulus_1 : operands_sp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => modulus_in,
douta => modulus_out(1023 downto 512)
);
 
modulus_2 : operands_sp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => modulus_in,
douta => modulus_out(1535 downto 1024)
);
 
end Behavioral;
 
/trunk/rtl/vhdl/core/operand_ram.vhd
1,93 → 1,95
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: operand_mem.vhd / entity operand_mem
--
-- Last Modified: 25/04/2012
--
-- Description: BRAM memory and logic to the store 4 (1536-bit) operands and the
-- modulus for the montgomery multiplier
--
--
-- Dependencies: operand_dp (coregen)
--
-- Revision:
-- Revision 1.01 - added "result_dest_op" input
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
-- Additional Comments:
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- operand_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_dp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (+1024 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side :)
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end operand_ram;
 
 
architecture Behavioral of operand_ram is
-- dual port blockram to store and update operands
component operand_dp
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(5 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(511 downto 0);
clkb: in std_logic;
web: IN std_logic_VECTOR(0 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
dinb: IN std_logic_VECTOR(511 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0));
end component;
-- port a signals
signal addra : std_logic_vector(5 downto 0);
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal write_operand_i : std_logic;
-- port b signals
signal addrb : std_logic_vector(5 downto 0);
signal web : std_logic_vector(0 downto 0);
signal doutb0 : std_logic_vector(31 downto 0);
signal doutb1 : std_logic_vector(31 downto 0);
signal doutb2 : std_logic_vector(31 downto 0);
signal doutb3 : std_logic_vector(31 downto 0);
-- port a signals
signal addra : std_logic_vector(5 downto 0);
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal write_operand_i : std_logic;
 
-- port b signals
signal addrb : std_logic_vector(5 downto 0);
signal web : std_logic_vector(0 downto 0);
signal doutb0 : std_logic_vector(31 downto 0);
signal doutb1 : std_logic_vector(31 downto 0);
signal doutb2 : std_logic_vector(31 downto 0);
signal doutb3 : std_logic_vector(31 downto 0);
 
begin
 
-- WARNING: Very Important!
-- wea & web signals must never be high at the same time !!
-- web has priority
103,10 → 105,10
operand_out_sel & "0000" when others;
with operand_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_operand_i select
wea <= part_enable when '1',
115,83 → 117,54
-- we can only read back from the result (stored in result_dest_op)
addrb <= result_dest_op & operand_addr(3 downto 0);
-- register_output_proc: process(clk)
-- begin
-- if rising_edge(clk) then
-- case operand_addr(5 downto 4) is
-- when "00" =>
-- result_out <= doutb0;
-- when "01" =>
-- result_out <= doutb1;
-- when "10" =>
-- result_out <= doutb2;
-- when others =>
-- result_out <= doutb3;
-- end case;
-- end if;
-- end process;
with operand_addr(5 downto 4) select
result_out <= doutb0 when "00",
doutb1 when "01",
doutb2 when "10",
doutb3 when others;
doutb2 when "10",
doutb3 when others;
-- 4 instances of a dual port ram to store the parts of the operand
op_0 : operand_dp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => operand_in,
douta => operand_out(511 downto 0),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(511 downto 0),
doutb => doutb0
);
op_1 : operand_dp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => operand_in,
douta => operand_out(1023 downto 512),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1023 downto 512),
doutb => doutb1
);
op_2 : operand_dp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => operand_in,
douta => operand_out(1535 downto 1024),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1535 downto 1024),
doutb => doutb2
);
-- op_3 : operand_dp
-- port map (
-- clka => clk,
-- wea => wea(3 downto 3),
-- addra => addra,
-- dina => operand_in,
-- douta => operand_out(2047 downto 1536),
-- clkb => clk,
-- web => web,
-- addrb => addrb,
-- dinb => result_in(2047 downto 1536),
-- doutb => doutb3
-- );
-- 3 instances of a dual port ram to store the parts of the operand
op_0 : operand_dp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => operand_in,
douta => operand_out(511 downto 0),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(511 downto 0),
doutb => doutb0
);
 
op_1 : operand_dp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => operand_in,
douta => operand_out(1023 downto 512),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1023 downto 512),
doutb => doutb1
);
 
op_2 : operand_dp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => operand_in,
douta => operand_out(1535 downto 1024),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1535 downto 1024),
doutb => doutb2
);
 
end Behavioral;
 
/trunk/rtl/vhdl/core/adder_block.vhd
1,90 → 1,96
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: adder_block.vhd / entity adder_block
--
-- Last Modified: 25/11/2011
--
-- Description: adder block for use in the montgommery multiplier pre- and post-
-- computation adders
--
--
-- Dependencies: cell_1b_adder,
-- d_flip_flop
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- adder_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- Adder block with a flipflop for the carry out ----
---- for use in the montgommery multiplier pre and post ----
---- computation adders ----
---- ----
---- Dependencies: ----
---- - cell_1b_adder ----
---- - d_flip_flop ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
entity adder_block is
generic ( width : integer := 32
);
Port ( core_clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
b : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR((width-1) downto 0)
);
generic (
width : integer := 32
);
port (
core_clk : in std_logic;
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
s : out std_logic_vector((width-1) downto 0)
);
end adder_block;
 
 
architecture Structural of adder_block is
component cell_1b_adder
Port ( a : in STD_LOGIC;
mux_result : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
r : out STD_LOGIC);
end component;
component d_flip_flop
port(core_clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
signal carry : std_logic_vector(width downto 0);
signal carry : std_logic_vector(width downto 0);
begin
carry(0) <= cin;
adder_chain: for i in 0 to (width-1) generate
adders: cell_1b_adder
port map(a => a(i),
mux_result => b(i),
cin => carry(i),
cout => carry(i+1),
r => s(i)
);
end generate;
delay_1_cycle: d_flip_flop
port map(core_clk => core_clk,
reset => '0',
din => carry(width),
dout => cout
);
end Structural;
 
carry(0) <= cin;
 
adder_chain : for i in 0 to (width-1) generate
adders : cell_1b_adder
port map(
a => a(i),
mux_result => b(i),
cin => carry(i),
cout => carry(i+1),
r => s(i)
);
end generate;
 
delay_1_cycle : d_flip_flop
port map(
core_clk => core_clk,
reset => '0',
din => carry(width),
dout => cout
);
 
end Structural;
/trunk/rtl/vhdl/core/cell_1b_mux.vhd
1,60 → 1,74
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: cell_1b_mux.vhd / entity cell_1b_mux
--
-- Last Modified: 14/11/2011
--
-- Description: mux for use in the montgommery multiplier systolic array
-- currently a behavioral description
--
--
-- Dependencies: none
--
-- Revision:
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- cel_1b_mux ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- mux for use in the montgommery multiplier systolic array ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity cell_1b_mux is
Port ( my : in STD_LOGIC;
y : in STD_LOGIC;
m : in STD_LOGIC;
x : in STD_LOGIC;
q : in STD_LOGIC;
result : out STD_LOGIC);
port (
my : in std_logic;
y : in std_logic;
m : in std_logic;
x : in std_logic;
q : in std_logic;
result : out std_logic
);
end cell_1b_mux;
 
 
architecture Behavioral of cell_1b_mux is
signal sel : std_logic_vector(1 downto 0);
signal sel : std_logic_vector(1 downto 0);
begin
sel <= x & q;
with sel select
result <= my when "11",
y when "10",
m when "01",
'0' when others;
 
sel <= x & q;
 
with sel select
result <= my when "11",
y when "10",
m when "01",
'0' when others;
 
end Behavioral;
 
/trunk/rtl/vhdl/core/adder_n.vhd
1,7 → 1,6
----------------------------------------------------------------------
----------------------------------------------------------------------
---- adder_n ----
---- ----
---- adder_n.vhd ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
8,8 → 7,8
---- ----
---- Description ----
---- This file contains the implementation of a n-bit adder ----
---- using the adder blocks. ----
---- used as the montgommery multiplier pre- and post- ----
---- using adder_blocks ----
---- used for the montgommery multiplier pre- and post- ----
---- computation adder ----
---- ----
---- Dependencies: ----
46,61 → 45,53
---- ----
----------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity adder_n is
generic ( width : integer := 1536;
block_width : integer := 8
);
Port ( core_clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
b : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR((width-1) downto 0)
);
generic (
width : integer := 1536;
block_width : integer := 8
);
port (
core_clk : in std_logic;
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
cin : in std_logic;
cout : out std_logic;
s : out std_logic_vector((width-1) downto 0)
);
end adder_n;
 
 
architecture Structural of adder_n is
component adder_block
generic ( width : integer := 32
);
Port ( core_clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR((width-1) downto 0);
b : in STD_LOGIC_VECTOR((width-1) downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR((width-1) downto 0)
);
end component;
constant nr_of_blocks : integer := width/block_width;
signal carry : std_logic_vector(nr_of_blocks downto 0);
constant nr_of_blocks : integer := width/block_width;
signal carry : std_logic_vector(nr_of_blocks downto 0);
begin
carry(0) <= cin;
adder_block_chain: for i in 0 to (nr_of_blocks-1) generate
adder_blocks: adder_block
generic map( width => block_width
)
port map( core_clk => core_clk,
a => a((((i+1)*block_width)-1) downto (i*block_width)),
b => b((((i+1)*block_width)-1) downto (i*block_width)),
cin => carry(i),
cout => carry(i+1),
s => s((((i+1)*block_width)-1) downto (i*block_width))
);
end generate;
cout <= carry(nr_of_blocks);
 
carry(0) <= cin;
 
adder_block_chain : for i in 0 to (nr_of_blocks-1) generate
adder_blocks : adder_block
generic map(
width => block_width
)
port map(
core_clk => core_clk,
a => a((((i+1)*block_width)-1) downto (i*block_width)),
b => b((((i+1)*block_width)-1) downto (i*block_width)),
cin => carry(i),
cout => carry(i+1),
s => s((((i+1)*block_width)-1) downto (i*block_width))
);
end generate;
 
cout <= carry(nr_of_blocks);
 
end Structural;
/trunk/rtl/vhdl/core/multiplier_core.vhd
1,244 → 1,188
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: multiplier_core.vhd / entity multiplier_core
--
-- Last Modified: 18/06/2012
--
-- Description: a pipelined montgomery multiplier, with split
-- pipeline operation and "auto-run" support
--
--
-- Dependencies: mont_mult_sys_pipeline, operand_mem, fifo_primitive, mont_cntrl
--
-- Revision:
-- Revision 6.00 - created seperate module for x-operand (x_shift_reg)
-- Revision 5.00 - moved fifo interface to shared memory
-- Revision 4.00 - added dest_op_single input
-- Revision 3.00 - added auto-run control
-- Revision 2.01 - Split ctrl_reg input to separate inputs with more descriptive
-- names
-- Revision 2.00 - Control logic moved to separate design module and added fifo
-- Revision 1.00 - Architecture based on multiplier IP core "mont_mult1536_v1_00_a"
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- multiplier_core ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- toplevel of a modular simultaneous exponentiation core ----
---- using a pipelined montgommery multiplier with split ----
---- pipeline support and auto-run support ----
---- ----
---- Dependencies: ----
---- - mont_mult_sys_pipeline ----
---- - operand_mem ----
---- - fifo_primitive ----
---- - mont_ctrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity multiplier_core is
port( clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
end multiplier_core;
 
 
architecture Behavioral of multiplier_core is
component mont_mult_sys_pipeline
generic ( n : integer := 32;
nr_stages : integer := 8; --(divides n, bits_low & (n-bits_low))
stages_low : integer := 3
);
Port ( core_clk : in STD_LOGIC;
xy : in STD_LOGIC_VECTOR((n-1) downto 0);
m : in STD_LOGIC_VECTOR((n-1) downto 0);
r : out STD_LOGIC_VECTOR((n-1) downto 0);
start : in STD_LOGIC;
reset : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0);
load_x : in std_logic;
ready : out STD_LOGIC
);
end component;
component operand_mem
port(
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
clk : in std_logic
);
end component;
component fifo_primitive
port(
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
dout : out std_logic_vector(31 downto 0);
empty : out std_logic;
full : out std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component;
component mont_ctrl
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
multiplier_ready : in std_logic;
op_buffer_empty : in std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic
);
end component;
signal xy_i : std_logic_vector(1535 downto 0);
signal x_i : std_logic;
signal m : std_logic_vector(1535 downto 0);
signal r : std_logic_vector(1535 downto 0);
signal op_sel : std_logic_vector(1 downto 0);
signal result_dest_op_i : std_logic_vector(1 downto 0);
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_op : std_logic;
signal load_x_i : std_logic;
signal load_m : std_logic;
signal load_result : std_logic;
signal fifo_empty : std_logic;
signal fifo_pop : std_logic;
signal fifo_nopop : std_logic;
signal fifo_dout : std_logic_vector(31 downto 0);
--signal fifo_push : std_logic;
constant n : integer := 1536;
constant t : integer := 96;
constant tl : integer := 32;
signal xy_i : std_logic_vector(1535 downto 0);
signal x_i : std_logic;
signal m : std_logic_vector(1535 downto 0);
signal r : std_logic_vector(1535 downto 0);
 
signal op_sel : std_logic_vector(1 downto 0);
signal result_dest_op_i : std_logic_vector(1 downto 0);
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_op : std_logic;
signal load_x_i : std_logic;
signal load_m : std_logic;
signal load_result : std_logic;
 
signal fifo_empty : std_logic;
signal fifo_pop : std_logic;
signal fifo_nopop : std_logic;
signal fifo_dout : std_logic_vector(31 downto 0);
--signal fifo_push : std_logic;
 
constant n : integer := 1536;
constant t : integer := 96;
constant tl : integer := 32;
 
begin
 
-- The actual multiplier
the_multiplier: mont_mult_sys_pipeline generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
stages_low => tl
)
port map(
core_clk => clk,
xy => xy_i,
m => m,
r => r,
start => start_mult,
reset => reset,
p_sel => p_sel,
load_x => load_x_i,
ready => mult_ready
);
-- Block ram memory for storing the operands and the modulus
the_memory: operand_mem port map(
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
op_sel => op_sel,
xy_out => xy_i,
m => m,
result_in => r,
load_op => load_op,
load_m => load_m,
load_result => load_result,
result_dest_op => result_dest_op_i,
collision => collision,
clk => clk
);
-- The actual multiplier
the_multiplier : mont_mult_sys_pipeline generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
stages_low => tl
)
port map(
core_clk => clk,
xy => xy_i,
m => m,
r => r,
start => start_mult,
reset => reset,
p_sel => p_sel,
load_x => load_x_i,
ready => mult_ready
);
 
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem port map(
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
op_sel => op_sel,
xy_out => xy_i,
m => m,
result_in => r,
load_op => load_op,
load_m => load_m,
load_result => load_result,
result_dest_op => result_dest_op_i,
collision => collision,
clk => clk
);
 
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
result_dest_op_i <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo: fifo_primitive port map(
clk => clk,
din => fifo_din,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
push => fifo_push,
pop => fifo_pop,
reset => reset,
nopop => fifo_nopop,
nopush => fifo_nopush
);
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive port map(
clk => clk,
din => fifo_din,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
push => fifo_push,
pop => fifo_pop,
reset => reset,
nopop => fifo_nopop,
nopush => fifo_nopush
);
-- The control logic for the core
the_control_unit: mont_ctrl port map(
clk => clk,
reset => reset,
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => run_auto,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
buffer_noread => fifo_nopop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
load_x => load_x_i,
load_result => load_result,
start_multiplier => start_mult,
multiplier_ready => mult_ready
);
-- The control logic for the core
the_control_unit : mont_ctrl port map(
clk => clk,
reset => reset,
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => run_auto,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
buffer_noread => fifo_nopop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
load_x => load_x_i,
load_result => load_result,
start_multiplier => start_mult,
multiplier_ready => mult_ready
);
 
end Behavioral;
 
/trunk/rtl/vhdl/core/systolic_pipeline.vhd
1,47 → 1,60
------------------------------------------------------------------------------------
--
-- Geoffrey Ottoy - DraMCo research group
--
-- Module Name: systolic_pipeline.vhd / entity systolic_pipeline
--
-- Last Modified: 05/01/2012
--
-- Description: pipelined systolic array implementation of a montgomery multiplier
--
--
-- Dependencies: first_stage,
-- standard_stage,
-- last_stage,
-- stepping_control
--
-- Revision:
-- Revision 3.00 - Made x_selection external
-- Revision 2.02 - Changed design to cope with new stepping_control (next_x)
-- Revision 2.01 - Created an extra contant s (step size = n/t) to fix a problem
-- that occured when t not = sqrt(n).
-- Revision 2.00 - Moved stepping logic and x_selection to seperate submodules
-- Revision 1.00 - Architecture
-- Revision 0.01 - File Created
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
-- by other third parties!
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------
---- systolic_pipeline ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- pipelined systolic array implementation of a montgomery ----
---- multiplier ----
---- ----
---- Dependencies: ----
---- - stepping_logic ----
---- - first_stage ----
---- - standard_stage ----
---- - last_stage ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- p_sel:
-- 01 = lower part
-- 10 = upper part
48,134 → 61,62
-- 11 = full range
 
entity systolic_pipeline is
generic( n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- number of stages (divider of n) >= 2
tl: integer := 64
-- best take t = sqrt(n)
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((n) downto 0);
y : in STD_LOGIC_VECTOR((n-1) downto 0);
m : in STD_LOGIC_VECTOR((n-1) downto 0);
xi : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
p_sel : in STD_LOGIC_VECTOR(1 downto 0); -- select which piece of the multiplier will be used
ready : out STD_LOGIC;
next_x : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((n+1) downto 0)
);
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- number of stages (divider of n) >= 2
tl : integer := 64 -- best take t = sqrt(n)
);
port(
core_clk : in std_logic;
my : in std_logic_vector((n) downto 0);
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
xi : in std_logic;
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
ready : out std_logic;
next_x : out std_logic;
r : out std_logic_vector((n+1) downto 0)
);
end systolic_pipeline;
 
 
architecture Structural of systolic_pipeline is
constant s : integer := n/t; -- defines the size of the stages (# bits)
constant size_l : integer := s*tl;
constant size_h : integer := n - size_l;
 
constant s : integer := n/t; -- defines the size of the stages (# bits)
constant size_l : integer := s*tl;
constant size_h : integer := n - size_l;
component first_stage
generic(width : integer := 4 -- must be the same as width of the standard stage
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width) downto 0);
y : in STD_LOGIC_VECTOR((width) downto 0);
m : in STD_LOGIC_VECTOR((width) downto 0);
xin : in STD_LOGIC;
xout : out STD_LOGIC;
qout : out STD_LOGIC;
a_msb : in STD_LOGIC;
cout : out STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
--ready : out STD_LOGIC;
done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0)
);
end component;
component standard_stage
generic(width : integer := 4
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-1) downto 0);
m : in STD_LOGIC_VECTOR((width-1) downto 0);
xin : in STD_LOGIC;
qin : in STD_LOGIC;
xout : out STD_LOGIC;
qout : out STD_LOGIC;
a_msb : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
-- ready : out STD_LOGIC;
done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width-1) downto 0)
);
end component;
component last_stage
generic(width : integer := 4 -- must be the same as width of the standard stage
);
port(core_clk : in STD_LOGIC;
my : in STD_LOGIC_VECTOR((width-1) downto 0);
y : in STD_LOGIC_VECTOR((width-2) downto 0);
m : in STD_LOGIC_VECTOR((width-2) downto 0);
xin : in STD_LOGIC;
qin : in STD_LOGIC;
cin : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
-- ready : out STD_LOGIC;
-- done : out STD_LOGIC;
r : out STD_LOGIC_VECTOR((width+1) downto 0)
);
end component;
component stepping_logic
generic( n : integer := 16; -- max nr of steps required to complete a multiplication
t : integer := 4 -- total nr of steps in the pipeline
);
port(core_clk : in STD_LOGIC;
start : in STD_LOGIC;
reset : in STD_LOGIC;
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out STD_LOGIC;
stepping_done : out STD_LOGIC
);
end component;
signal start_stage_i : std_logic_vector((t-1) downto 0);
--signal stage_ready_i : std_logic_vector((t-1) downto 0);
signal stage_done_i : std_logic_vector((t-2) downto 0);
 
signal start_stage_i : std_logic_vector((t-1) downto 0);
--signal stage_ready_i : std_logic_vector((t-1) downto 0);
signal stage_done_i : std_logic_vector((t-2) downto 0);
signal x_i : std_logic_vector((t-1) downto 0) := (others=>'0');
signal q_i : std_logic_vector((t-2) downto 0) := (others=>'0');
signal c_i : std_logic_vector((t-2) downto 0) := (others=>'0');
signal a_i : std_logic_vector((n+1) downto 0) := (others=>'0');
signal r_tot : std_logic_vector((n+1) downto 0) := (others=>'0');
signal r_h : std_logic_vector(s-1 downto 0) := (others=>'0');
signal r_l : std_logic_vector((s+1) downto 0) := (others=>'0');
signal a_h : std_logic_vector((s*2)-1 downto 0) := (others=>'0');
signal a_l : std_logic_vector((s*2)-1 downto 0) := (others=>'0');
--signal ready_i : std_logic;
signal stepping_done_i : std_logic;
signal t_sel : integer range 0 to t := t;
signal n_sel : integer range 0 to n := n;
signal split : std_logic := '0';
signal lower_e_i : std_logic := '0';
signal higher_e_i : std_logic := '0';
signal start_pulses_i : std_logic := '0';
signal start_higher_i : std_logic := '0';
signal higher_0_done_i : std_logic := '0';
signal h_x_0, h_x_1 : std_logic := '0';
signal h_q_0, h_q_1 : std_logic := '0';
signal h_c_0, h_c_1 : std_logic := '0';
signal x_offset_i : integer range 0 to tl*s := 0;
signal next_x_i : std_logic := '0';
signal x_i : std_logic_vector((t-1) downto 0) := (others => '0');
signal q_i : std_logic_vector((t-2) downto 0) := (others => '0');
signal c_i : std_logic_vector((t-2) downto 0) := (others => '0');
signal a_i : std_logic_vector((n+1) downto 0) := (others => '0');
signal r_tot : std_logic_vector((n+1) downto 0) := (others => '0');
signal r_h : std_logic_vector(s-1 downto 0) := (others => '0');
signal r_l : std_logic_vector((s+1) downto 0) := (others => '0');
signal a_h : std_logic_vector((s*2)-1 downto 0) := (others => '0');
signal a_l : std_logic_vector((s*2)-1 downto 0) := (others => '0');
 
--signal ready_i : std_logic;
signal stepping_done_i : std_logic;
signal t_sel : integer range 0 to t := t;
signal n_sel : integer range 0 to n := n;
signal split : std_logic := '0';
signal lower_e_i : std_logic := '0';
signal higher_e_i : std_logic := '0';
signal start_pulses_i : std_logic := '0';
signal start_higher_i : std_logic := '0';
signal higher_0_done_i : std_logic := '0';
signal h_x_0, h_x_1 : std_logic := '0';
signal h_q_0, h_q_1 : std_logic := '0';
signal h_c_0, h_c_1 : std_logic := '0';
signal x_offset_i : integer range 0 to tl*s := 0;
signal next_x_i : std_logic := '0';
 
begin
 
-- output mapping
190,10 → 131,9
a_h((s*2)-1 downto s) <= r_h;
with p_sel select
a_i(((tl+1)*s-1) downto ((tl-1)*s)) <= a_l when "01",
a_h when "10",
r_tot(((tl+1)*s-1) downto ((tl-1)*s)) when others;
a_h when "10",
r_tot(((tl+1)*s-1) downto ((tl-1)*s)) when others;
 
 
-- signals from x_selection
next_x_i <= start_stage_i(1) or (start_stage_i(tl+1) and higher_e_i);
--
202,38 → 142,40
-- this module controls the pipeline operation
with p_sel select
t_sel <= tl when "01",
t-tl when "10",
t when others;
t_sel <= tl when "01",
t-tl when "10",
t when others;
with p_sel select
n_sel <= size_l-1 when "01",
size_h-1 when "10",
n-1 when others;
size_h-1 when "10",
n-1 when others;
with p_sel select
lower_e_i <= '0' when "10",
'1' when others;
lower_e_i <= '0' when "10",
'1' when others;
with p_sel select
higher_e_i <= '1' when "10",
'0' when others;
'0' when others;
split <= p_sel(0) and p_sel(1);
stepping_control: stepping_logic
generic map( n => n, -- max nr of steps required to complete a multiplication
t => t -- total nr of steps in the pipeline
)
port map(core_clk => core_clk,
start => start,
reset => reset,
t_sel => t_sel,
n_sel => n_sel,
start_first_stage => start_pulses_i,
stepping_done => stepping_done_i
);
stepping_control : stepping_logic
generic map(
n => n, -- max nr of steps required to complete a multiplication
t => t -- total nr of steps in the pipeline
)
port map(
core_clk => core_clk,
start => start,
reset => reset,
t_sel => t_sel,
n_sel => n_sel,
start_first_stage => start_pulses_i,
stepping_done => stepping_done_i
);
-- start signals for first stage of lower and higher part
start_stage_i(0) <= start_pulses_i and lower_e_i;
245,154 → 187,169
-- nothing special here, previous stages starts the next
start_signals_l: for i in 1 to tl-1 generate
start_stage_i(i) <= stage_done_i(i-1);
start_stage_i(i) <= stage_done_i(i-1);
end generate;
start_signals_h: for i in tl+2 to t-1 generate
start_stage_i(i) <= stage_done_i(i-1);
start_stage_i(i) <= stage_done_i(i-1);
end generate;
 
stage_0 : first_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(s downto 0),
y => y(s downto 0),
m => m(s downto 0),
xin => x_i(0),
xout => x_i(1),
qout => q_i(0),
a_msb => a_i(s),
cout => c_i(0),
start => start_stage_i(0),
reset => reset,
--ready => stage_ready_i(0),
done => stage_done_i(0),
r => r_tot((s-1) downto 0)
);
stage_0: first_stage
generic map(width => s
)
port map(core_clk => core_clk,
my => my(s downto 0),
y => y(s downto 0),
m => m(s downto 0),
xin => x_i(0),
xout => x_i(1),
qout => q_i(0),
a_msb => a_i(s),
cout => c_i(0),
start => start_stage_i(0),
reset => reset,
--ready => stage_ready_i(0),
done => stage_done_i(0),
r => r_tot((s-1) downto 0)
);
stages_l : for i in 1 to (tl) generate
standard_stages : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => x_i(i),
qin => q_i(i-1),
xout => x_i(i+1),
qout => q_i(i),
a_msb => a_i((i+1)*s),
cin => c_i(i-1),
cout => c_i(i),
start => start_stage_i(i),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
stages_l: for i in 1 to (tl) generate
standard_stages: standard_stage
generic map(width => s
)
port map(core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => x_i(i),
qin => q_i(i-1),
xout => x_i(i+1),
qout => q_i(i),
a_msb => a_i((i+1)*s),
cin => c_i(i-1),
cout => c_i(i),
start => start_stage_i(i),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
h_c_1 <= h_c_0 or c_i(tl);
h_q_1 <= h_q_0 or q_i(tl);
h_x_1 <= h_x_0 or x_i(tl+1);
stage_tl_1: standard_stage
generic map(width => s
)
port map(core_clk => core_clk,
my => my(((tl+2)*s) downto ((s*(tl+1))+1)),
y => y(((tl+2)*s) downto ((s*(tl+1))+1)),
m => m(((tl+2)*s) downto ((s*(tl+1))+1)),
--xin => x_i(tl+1),
xin => h_x_1,
--qin => q_i(tl),
qin => h_q_1,
xout => x_i(tl+2),
qout => q_i(tl+1),
a_msb => a_i((tl+2)*s),
--cin => c_i(tl),
cin => h_c_1,
cout => c_i(tl+1),
start => start_stage_i(tl+1),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(tl+1),
r => r_tot((((tl+2)*s)-1) downto (s*(tl+1)))
);
stage_tl_1 : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((tl+2)*s) downto ((s*(tl+1))+1)),
y => y(((tl+2)*s) downto ((s*(tl+1))+1)),
m => m(((tl+2)*s) downto ((s*(tl+1))+1)),
--xin => x_i(tl+1),
xin => h_x_1,
--qin => q_i(tl),
qin => h_q_1,
xout => x_i(tl+2),
qout => q_i(tl+1),
a_msb => a_i((tl+2)*s),
--cin => c_i(tl),
cin => h_c_1,
cout => c_i(tl+1),
start => start_stage_i(tl+1),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(tl+1),
r => r_tot((((tl+2)*s)-1) downto (s*(tl+1)))
);
stages_h: for i in (tl+2) to (t-2) generate
standard_stages: standard_stage
generic map(width => s
)
port map(core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => x_i(i),
qin => q_i(i-1),
xout => x_i(i+1),
qout => q_i(i),
a_msb => a_i((i+1)*s),
cin => c_i(i-1),
cout => c_i(i),
start => start_stage_i(i),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
stage_t: last_stage
generic map(width => s -- must be the same as width of the standard stage
)
port map(core_clk => core_clk,
my => my(n downto ((n-s)+1)), --width-1
y => y((n-1) downto ((n-s)+1)), --width-2
m => m((n-1) downto ((n-s)+1)), --width-2
xin => x_i(t-1),
qin => q_i(t-2),
cin => c_i(t-2),
start => start_stage_i(t-1),
reset => reset,
--ready => stage_ready_i(t-1),
r => r_tot((n+1) downto (n-s)) --width+1
);
stages_h : for i in (tl+2) to (t-2) generate
standard_stages : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => x_i(i),
qin => q_i(i-1),
xout => x_i(i+1),
qout => q_i(i),
a_msb => a_i((i+1)*s),
cin => c_i(i-1),
cout => c_i(i),
start => start_stage_i(i),
reset => reset,
--ready => stage_ready_i(i),
done => stage_done_i(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
 
mid_start: first_stage
generic map(width => s
)
port map(core_clk => core_clk,
my => my((tl*s+s) downto tl*s),
y => y((tl*s+s) downto tl*s),
m => m((tl*s+s) downto tl*s),
xin => x_i(0),
xout => h_x_0,
qout => h_q_0,
a_msb => a_i((tl+1)*s),
cout => h_c_0,
start => start_higher_i,
reset => reset,
--ready => stage_ready_i(0),
done => higher_0_done_i,
r => r_h
);
mid_end: last_stage
generic map(width => s -- must be the same as width of the standard stage
)
port map(core_clk => core_clk,
my => my((tl*s) downto ((tl-1)*s)+1), --width-1
y => y(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
m => m(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
xin => x_i(tl-1),
qin => q_i(tl-2),
cin => c_i(tl-2),
start => start_stage_i(tl-1),
reset => reset,
--ready => stage_ready_i(t-1),
r => r_l --width+1
);
stage_t : last_stage
generic map(
width => s -- must be the same as width of the standard stage
)
port map(
core_clk => core_clk,
my => my(n downto ((n-s)+1)), --width-1
y => y((n-1) downto ((n-s)+1)), --width-2
m => m((n-1) downto ((n-s)+1)), --width-2
xin => x_i(t-1),
qin => q_i(t-2),
cin => c_i(t-2),
start => start_stage_i(t-1),
reset => reset,
--ready => stage_ready_i(t-1),
r => r_tot((n+1) downto (n-s)) --width+1
);
 
end Structural;
mid_start : first_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my((tl*s+s) downto tl*s),
y => y((tl*s+s) downto tl*s),
m => m((tl*s+s) downto tl*s),
xin => x_i(0),
xout => h_x_0,
qout => h_q_0,
a_msb => a_i((tl+1)*s),
cout => h_c_0,
start => start_higher_i,
reset => reset,
--ready => stage_ready_i(0),
done => higher_0_done_i,
r => r_h
);
 
mid_end : last_stage
generic map(
width => s -- must be the same as width of the standard stage
)
port map(
core_clk => core_clk,
my => my((tl*s) downto ((tl-1)*s)+1), --width-1
y => y(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
m => m(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
xin => x_i(tl-1),
qin => q_i(tl-2),
cin => c_i(tl-2),
start => start_stage_i(tl-1),
reset => reset,
--ready => stage_ready_i(t-1),
r => r_l --width+1
);
 
end Structural;
/trunk/sim/mod_sim_exp.do
0,0 → 1,2
nolog -all
run -all
/trunk/sim/out/sim_output.txt
0,0 → 1,192
----------------------------------------------
-- EXPONENTIATION --
----------------------------------------------
----- Variables used:
base width: 512
exponent width: 32
g0: DE0BBADE38204E63359A46E672A8D0A2FD5300692AB48F9EF732F5C3FA212B90C98229BBB79BECE734A622154C904DCE9A0F53D4A88B3E558EF7612F6694CE75
g1: 2E5D3FEA7D9D0D33AC553EECD5C3F27A310115D283E49377820195C8E67781B6F112A625B14B747FA4CC13D06EBA0917246C775F5C732865701AE9349EA8729C
e0: 64150A6D
e1: 8593F0D7
m: 18F204FE6846AEB6F58174D57A3372363C0D9FCFAA3DC18B1EFF7E89BF7678636580D17DD84A873B14B9C0E1680BBDC87647F3C382902D2F58D2754B39BCA875
R2: 098EB081ECFA53F3F90E7DBF1E10B6E29EE45D6B02BFF85403B335C0C6D5E1AB6EEC5D670AFB95713ED15F9723E5FAEDD6A42D95EFFAFA771CB0C72D3A73C905
 
----- Selecting pipeline:
Lower pipeline selected
 
----- Writing operands:
m written
g0 written in operand_0
g1 written in operand_1
R^2 written in operand_2
1 written in operand_3
 
----- Pre-computations:
Computed gt0: 14026CDDA1794A94D7FA3CC76C69F6E43B5DA0597C4040C6EB5CF65F677CAC9BD85B08AF0C998241ED365DECD2D1CF2A62CCB6138A409224F7F03184D2CD77B5
Read gt0: 14026CDDA1794A94D7FA3CC76C69F6E43B5DA0597C4040C6EB5CF65F677CAC9BD85B08AF0C998241ED365DECD2D1CF2A62CCB6138A409224F7F03184D2CD77B5
=> calc time is 10600 ns
=> expected time is 11180 ns
=> gt0 is correct!
Computed gt1: 047D6C7653ECA32D15971BE88EBA38526FEA6BBB9F991AD6C8D9EDE11BB11DC888444923C5732D57D31A4AEEA397179007927BA14CFDD1078664DCBBFCC3AAF4
Read gt1: 047D6C7653ECA32D15971BE88EBA38526FEA6BBB9F991AD6C8D9EDE11BB11DC888444923C5732D57D31A4AEEA397179007927BA14CFDD1078664DCBBFCC3AAF4
=> calc time is 10600 ns
=> expected time is 11180 ns
=> gt1 is correct!
Computed a=(R)mod m: 068BCE0FED3D2CDA68F16FA939FD89E1A777C1E359967090CA050E9E855F4C1E08F7D1158D16B7B130BE7731EF8A962B61307A5CE65E3C2687C76B0FBEA16B6E
Read (R)mod m: 068BCE0FED3D2CDA68F16FA939FD89E1A777C1E359967090CA050E9E855F4C1E08F7D1158D16B7B130BE7731EF8A962B61307A5CE65E3C2687C76B0FBEA16B6E
=> calc time is 10600 ns
=> expected time is 11180 ns
=> (R)mod m is correct!
Computed gt01: 00A84956047B71ED15148F0FC4BE161C3FE4FE03650DFF8E239982C0EBBBDBFBEA2087F0C2F725A023E1E568E56E980E36524CBC29190B698BCB62534AA47C3B
Read gt01: 00A84956047B71ED15148F0FC4BE161C3FE4FE03650DFF8E239982C0EBBBDBFBEA2087F0C2F725A023E1E568E56E980E36524CBC29190B698BCB62534AA47C3B
=> calc time is 10600 ns
=> expected time is 11180 ns
=> gt01 is correct!
 
----- Loading exponent fifo:
=> Done
 
----- Starting exponentiation:
=> calc time is 595040 ns
=> expected time is 626080 ns
=> Done
 
----- Post-computations:
1 written in operand_2
Computed result: 0AE33423C12184905FB44E34AE955AC5A502C9983910135AE22AE1F477C7E4532CF1134DDE48CCC4126124F91085D64D6106C503B6E71B0CE5333D679B0F016F
=> calc time is 10600 ns
=> expected time is 11180 ns
 
----- verifying result:
Read result: 0AE33423C12184905FB44E34AE955AC5A502C9983910135AE22AE1F477C7E4532CF1134DDE48CCC4126124F91085D64D6106C503B6E71B0CE5333D679B0F016F
Computed result: 0AE33423C12184905FB44E34AE955AC5A502C9983910135AE22AE1F477C7E4532CF1134DDE48CCC4126124F91085D64D6106C503B6E71B0CE5333D679B0F016F
=> Result is correct!
 
----------------------------------------------
-- EXPONENTIATION --
----------------------------------------------
----- Variables used:
base width: 1024
exponent width: 16
g0: 895F783FAB56A353B58A8C4316EACF3012C77E6FBFDB4BE7ED3CD27FC1C72A98F7733050AE2A4BD8C2B356F3F81DE6F56258F69355B9321117B905723DB3FE533FF94C12502B145C53E61608834634EAE18E60C5B991B9F8D71B2D971CBE5AC9E09F4814ADDAB421EFDCC2870D2C92C87003FCFF55CCBA1D4F22F5AB90950FB0
g1: 2A46626CF17C40BC08E57582F9852AD12CF0EE16F2440678D35A31147278A27658A66182B41C8327A559D058A9E9DF5A55FE9EECCD16FD651C2D7F13A9942E7418052B4AE1B98F8CA3F3E828532A453289BD47B363738F866DEBF04222ABEECAC1E11F980B6F115F097F4540AA7735B993F17F55083CAEB6A80F80D092C59D2F
e0: 7C1F
e1: 5EB8
m: 20F8BE80BA9B4C7CA011F74C2D41581F0036D233B5E8E58B6DD5CA6DB0625D764B927A43FE78844090C6843F29A331B76F8ECE93E7E313ECCB9BCB6ED2330923899AAE43A0FD2430CB6772793755E74862E61E2AC376CFAB9D61827E646421B28E9E0E2ACA4625731AEBBB69EA37E0FA859E499B8A186C8EE6196954170EB807
R2: 06412C26297124BA58188BC306FA67D5E2349D33C677CB3701084AB808780E2D89F5D0B912E4866F37F4FEC043A08C1991C2EF1A4D9F81B6BD6E8449CF2DFA510A0417DB84EC15BEA71C17B483852B918137926002C232D2ADFD304C7A1BEEF79B83544BC405D714A10E1B2ED02E33CFBF25B0DFFDDA16E76D92E84D778DCC27
 
----- Selecting pipeline:
Upper pipeline selected
 
----- Writing operands:
m written
g0 written in operand_0
g1 written in operand_1
R^2 written in operand_2
1 written in operand_3
 
----- Pre-computations:
Computed gt0: 1563CCE47758B785CFD5BF169F156B4E4328B02221FAA51D65CC5E819ABD176948D3262A5F54A3DD960D1AEABA079BB8AD3D9926D0B5F3FF3DADA08F6219E932FF858E754EF7CCC3F3B63CB0BE8D2B346EF8054ED96A1BFCB6AB110F52D2C601F4CCA7149A7A3AE60AAE54611266844562F93A152656D6C857BB8E41209E2904
Read gt0: 1563CCE47758B785CFD5BF169F156B4E4328B02221FAA51D65CC5E819ABD176948D3262A5F54A3DD960D1AEABA079BB8AD3D9926D0B5F3FF3DADA08F6219E932FF858E754EF7CCC3F3B63CB0BE8D2B346EF8054ED96A1BFCB6AB110F52D2C601F4CCA7149A7A3AE60AAE54611266844562F93A152656D6C857BB8E41209E2904
=> calc time is 21160 ns
=> expected time is 21420 ns
=> gt0 is correct!
Computed gt1: 19D524C74C54446433FD52E430BC5AB765AFCDFF9F13CFE2B81958BAF4C1804E6F0DED2B6E39A37D59A9D6F9F833C6225920C7700A06F308074DF8027B47EE5B4E0E3A96BCF2F44F74E5FF4B9EDA59538C88E9E86F321F28584BE5A4738EB56925CD464B980CBCA2F78C2D456FC9C46BB58D34425DFA4B12AD486A7B79982E7F
Read gt1: 19D524C74C54446433FD52E430BC5AB765AFCDFF9F13CFE2B81958BAF4C1804E6F0DED2B6E39A37D59A9D6F9F833C6225920C7700A06F308074DF8027B47EE5B4E0E3A96BCF2F44F74E5FF4B9EDA59538C88E9E86F321F28584BE5A4738EB56925CD464B980CBCA2F78C2D456FC9C46BB58D34425DFA4B12AD486A7B79982E7F
=> calc time is 21160 ns
=> expected time is 21420 ns
=> gt1 is correct!
Computed a=(R)mod m: 1932CA7AE5C0E8979F823CEAC3369726FE80409606A1B92FFF2777002D4F71C3EEFEA8240AB4623C0A926245DC89A3FBF31859F4A8CA74866EBD6FF8409AC0073CC53C26991402AA702BDEAF7CA6AD054BB52CD4A7C0524EB2556E8B4143141E19AD9CD47814F9DA438DE01A9878D92658ABFCBF39550817B54E1EB35E98F7CF
Read (R)mod m: 1932CA7AE5C0E8979F823CEAC3369726FE80409606A1B92FFF2777002D4F71C3EEFEA8240AB4623C0A926245DC89A3FBF31859F4A8CA74866EBD6FF8409AC0073CC53C26991402AA702BDEAF7CA6AD054BB52CD4A7C0524EB2556E8B4143141E19AD9CD47814F9DA438DE01A9878D92658ABFCBF39550817B54E1EB35E98F7CF
=> calc time is 21160 ns
=> expected time is 21420 ns
=> (R)mod m is correct!
Computed gt01: 1544B14914333391B50DDC809FDD3B372F607292A3677AC566448683B734BA6FEECB8AE791E6BA01DFDF37441676459F27343E727C5CE647E4E5F3FD5CEA23E891525229306DB57A0DF7ABF72D167A09CF3DAF35E24628A39CD85B824DD548C516A36586E77A844677F3889A58FF57E80734C70D37E403EB0BC122825C36585C
Read gt01: 1544B14914333391B50DDC809FDD3B372F607292A3677AC566448683B734BA6FEECB8AE791E6BA01DFDF37441676459F27343E727C5CE647E4E5F3FD5CEA23E891525229306DB57A0DF7ABF72D167A09CF3DAF35E24628A39CD85B824DD548C516A36586E77A844677F3889A58FF57E80734C70D37E403EB0BC122825C36585C
=> calc time is 21160 ns
=> expected time is 21420 ns
=> gt01 is correct!
 
----- Loading exponent fifo:
=> Done
 
----- Starting exponentiation:
=> calc time is 614380 ns
=> expected time is 599760 ns
=> Done
 
----- Post-computations:
1 written in operand_2
Computed result: 1324646BFB0BAD60A82843AE9B47E64D4FB298550061B01755AED16BA0448AFC9CAC7557640DE2E8EDA59E5C9E29483ED5181D997D9F73E8EDCFD671A724CC1F2EC976ED97B392148D8F1156F0CB4CAB35A2B378C7A63B539DAA0588260AA6FB2AB3F8AD497C96305A0FA081EE6AB4BB7067D3EA85C6455BF6F9AF37DEB38EB3
=> calc time is 21160 ns
=> expected time is 21420 ns
 
----- verifying result:
Read result: 1324646BFB0BAD60A82843AE9B47E64D4FB298550061B01755AED16BA0448AFC9CAC7557640DE2E8EDA59E5C9E29483ED5181D997D9F73E8EDCFD671A724CC1F2EC976ED97B392148D8F1156F0CB4CAB35A2B378C7A63B539DAA0588260AA6FB2AB3F8AD497C96305A0FA081EE6AB4BB7067D3EA85C6455BF6F9AF37DEB38EB3
Computed result: 1324646BFB0BAD60A82843AE9B47E64D4FB298550061B01755AED16BA0448AFC9CAC7557640DE2E8EDA59E5C9E29483ED5181D997D9F73E8EDCFD671A724CC1F2EC976ED97B392148D8F1156F0CB4CAB35A2B378C7A63B539DAA0588260AA6FB2AB3F8AD497C96305A0FA081EE6AB4BB7067D3EA85C6455BF6F9AF37DEB38EB3
=> Result is correct!
 
----------------------------------------------
-- EXPONENTIATION --
----------------------------------------------
----- Variables used:
base width: 1536
exponent width: 16
g0: B2C5BDFAF2BA8F23D35F13F9F77A1B8EFD364518248B0AB2010D3260A3445F5A0A8AA4198B0C3207D3458A2E1539A16F8D4AE39B8913A951884085DCF22F2FB08291D7363204E5335E697F7398A9ECEB1CAFBCD348517674F15BBCBEA90537CA2C8E6364D67421F29B9AE1C2E5F17872C08B122DD36A9965916287D08D8E2ECE0500D4F1E37B45E29CB056EFCD1449220D602E7CF13EC97B6C4F17A7E57AF9C8EC65CB9864B7A4C83290855C8FFC55BC1DA64E43B9EC4E9F266DCE489D14AA8C
g1: C7A679C71DCAA96A8401DD62D7E71F68532C71819B8FE7AB721FB04B4DCED1DF8486000094AE3410622CD598ED3E74AB64952EEE06659E1A891CCBD3702155BCBD3931224694FAA89B4055C056E0AA844139FBBFE3D9B568B58387F1A955EE2E0043E5ADBEA47BEACE8589DD09BD98826DB084EC7172C76B92D315D164F26C049784ED73AE654E5CA1C1D1FAF227CE981B624EA7F57AAB0A06B88D2B3105B957B1A19D1899B8E544F05C6DE4756B8B095D2E346DA3ECDB386B33FBE48F5254B1
e0: ED01
e1: 611E
m: DA67CD50B638D8454A6854741126C4A07CC716330A37576E5021CA2FD2F24B31E027C0B9BC2929F2A2A38C9D003AE5B45D153957D2D0FE1CD05A87F375D050F6341D1E83F0583276902503259190AA7B0353E99A8B404DA6FEABE3A3B4A54263523A3619AEDFFE301DB8BE0AA07B04B8D8C1210CBB3034856D6F46DEC94CF866558439083E26BD03DC4C11A81239654B516B2F891D20D0F7FC98547FAC560AB315DE74E6EB71DCCEF15A3AC85D3DAA6072603A608A1D9201D5F09AD67ED8CE95
R2: 27D738BE5B0CCB62AEC64623ADFEC2FB3FBDC26BE7040817F764250D3F8F324AC468575A3953CFA8EA853097D17B71E3ED7A81255688A155C1F84C81F8288019A364E4A267A828AB90919F1D034743F88B81AECEF510EF66DC7C45971EC384C4433BD9377CF72C97AF9AF5B36EA8522DEA929D219819BD178B910C8C54365D5071AD39C2527B64D878D3DF051B0FC82C71155571F9EA89F9A16B1EC77A05D39FD6840328958DA9BB19C637D3952D0B704FF176B4CE18D782030310527785F8B6
 
----- Selecting pipeline:
Full pipeline selected
 
----- Writing operands:
m written
g0 written in operand_0
g1 written in operand_1
R^2 written in operand_2
1 written in operand_3
 
----- Pre-computations:
Computed gt0: BF4E8A2AFF25F970DB92A08206B2662FADE7E2DEE533FC585F0EBF85280F8760A45A7AF38AEC082A8BF07B380A3814E52B38147B7E92CDE28CB7D0500BACBA0E79A7D9752BC3F6B4A8CE7E9091D8F614FE8B970135D27E63F81FAA587F35871ABD5B3A8D4BD84E6AB717D1E49C5F92470547D4BF977A07EEFCBDEBE1754278AFC06505E4058C099DA4632614DB98D9E3D7447E2A48403BD9CDA0EFB7FBC4E43A9E962CC9ABE24F6312893A165927614519CCF6897D3F17F3D9FF5CA3ABB00117
Read gt0: BF4E8A2AFF25F970DB92A08206B2662FADE7E2DEE533FC585F0EBF85280F8760A45A7AF38AEC082A8BF07B380A3814E52B38147B7E92CDE28CB7D0500BACBA0E79A7D9752BC3F6B4A8CE7E9091D8F614FE8B970135D27E63F81FAA587F35871ABD5B3A8D4BD84E6AB717D1E49C5F92470547D4BF977A07EEFCBDEBE1754278AFC06505E4058C099DA4632614DB98D9E3D7447E2A48403BD9CDA0EFB7FBC4E43A9E962CC9ABE24F6312893A165927614519CCF6897D3F17F3D9FF5CA3ABB00117
=> calc time is 31720 ns
=> expected time is 31660 ns
=> gt0 is correct!
Computed gt1: 4505CC0EB73A76E09AF6C512B4B3611D7C3B3108A68AD4D08ACA6CA13756E553EFE6ADE8C7A0AE6B5BBAD04BA0A281824DE0A13763C3ACA96930C4F9AEC2E9ED52E9F329DB58EC6ACC4D1A86DF706F3E74B2E088F9064CAEF6A0074D63E726243779721517848124EA65C1CCD3E8A1471AFA3F25811A577757AA2807577A7C6A77C3634813F92CDAADE697CB17FA0555918D53A75E05C263E807F107437A5C4032C68F18B8CA54A61CAFF215DEBC1A0988933E6E442501A8FBC497403631D543
Read gt1: 4505CC0EB73A76E09AF6C512B4B3611D7C3B3108A68AD4D08ACA6CA13756E553EFE6ADE8C7A0AE6B5BBAD04BA0A281824DE0A13763C3ACA96930C4F9AEC2E9ED52E9F329DB58EC6ACC4D1A86DF706F3E74B2E088F9064CAEF6A0074D63E726243779721517848124EA65C1CCD3E8A1471AFA3F25811A577757AA2807577A7C6A77C3634813F92CDAADE697CB17FA0555918D53A75E05C263E807F107437A5C4032C68F18B8CA54A61CAFF215DEBC1A0988933E6E442501A8FBC497403631D543
=> calc time is 31720 ns
=> expected time is 31660 ns
=> gt1 is correct!
Computed a=(R)mod m: 259832AF49C727BAB597AB8BEED93B5F8338E9CCF5C8A891AFDE35D02D0DB4CE1FD83F4643D6D60D5D5C7362FFC51A4BA2EAC6A82D2F01E32FA5780C8A2FAF09CBE2E17C0FA7CD896FDAFCDA6E6F5584FCAC166574BFB25901541C5C4B5ABD9CADC5C9E6512001CFE24741F55F84FB47273EDEF344CFCB7A9290B92136B30799AA7BC6F7C1D942FC23B3EE57EDC69AB4AE94D076E2DF2F080367AB8053A9F54CEA218B19148E23310EA5C537A2C2559F8D9FC59F75E26DFE2A0F65298127316B
Read (R)mod m: 259832AF49C727BAB597AB8BEED93B5F8338E9CCF5C8A891AFDE35D02D0DB4CE1FD83F4643D6D60D5D5C7362FFC51A4BA2EAC6A82D2F01E32FA5780C8A2FAF09CBE2E17C0FA7CD896FDAFCDA6E6F5584FCAC166574BFB25901541C5C4B5ABD9CADC5C9E6512001CFE24741F55F84FB47273EDEF344CFCB7A9290B92136B30799AA7BC6F7C1D942FC23B3EE57EDC69AB4AE94D076E2DF2F080367AB8053A9F54CEA218B19148E23310EA5C537A2C2559F8D9FC59F75E26DFE2A0F65298127316B
=> calc time is 31720 ns
=> expected time is 31660 ns
=> (R)mod m is correct!
Computed gt01: 51FE92E79CF87E206A6A1D6192CC670090A20AD3FCC36F13CE25FC7CA15F7C0CF5FC1F466BEB949C01AF87520731B63699900F0D4BBC21D2FC13B30A66FD767D76B6D391FB1418EDC2E07057D9FA124C99DFE154E46F98A718A09CCFD01862EBBFF0221CDFE9039851872526AEE09BE7EFE4F1FE3D2FDF747E0AB0FCE0F5062E7379E19FBE8F25647A081A90E5A8C9C28FA7A2D600C9072B139C901236EC3E04AB2E67C684348D07C0857B7D85DABE1E232EEB63675C63D6732F2BFEA20DCD6B
Read gt01: 51FE92E79CF87E206A6A1D6192CC670090A20AD3FCC36F13CE25FC7CA15F7C0CF5FC1F466BEB949C01AF87520731B63699900F0D4BBC21D2FC13B30A66FD767D76B6D391FB1418EDC2E07057D9FA124C99DFE154E46F98A718A09CCFD01862EBBFF0221CDFE9039851872526AEE09BE7EFE4F1FE3D2FDF747E0AB0FCE0F5062E7379E19FBE8F25647A081A90E5A8C9C28FA7A2D600C9072B139C901236EC3E04AB2E67C684348D07C0857B7D85DABE1E232EEB63675C63D6732F2BFEA20DCD6B
=> calc time is 31720 ns
=> expected time is 31660 ns
=> gt01 is correct!
 
----- Loading exponent fifo:
=> Done
 
----- Starting exponentiation:
=> calc time is 857140 ns
=> expected time is 886480 ns
=> Done
 
----- Post-computations:
1 written in operand_2
Computed result: 5ED841EDA3B8C955FE433D971816C55F290735FD5C60AA5C0021F441172383463E18835FF4962FCC76C9B59894A8A11C5748183A3453C9E9D3CAACE2834A285F326D49742B2E56FF7D1DCCB91BB2F3059F6A3C509C7FB62D929B8002619BB70676B5EC0617B3D36FD2FABB2701FF9C0B94B3942673DE0FE22E4D13969398F8DA5563959C05328EF7767B6E4E11E4E31A3196F35919B29464E45E5A8A461BD9533A11A3BDF9C1F57EC911B496B05072F45427293234F8189D0649F8A05B91FFB5
=> calc time is 31720 ns
=> expected time is 31660 ns
 
----- verifying result:
Read result: 5ED841EDA3B8C955FE433D971816C55F290735FD5C60AA5C0021F441172383463E18835FF4962FCC76C9B59894A8A11C5748183A3453C9E9D3CAACE2834A285F326D49742B2E56FF7D1DCCB91BB2F3059F6A3C509C7FB62D929B8002619BB70676B5EC0617B3D36FD2FABB2701FF9C0B94B3942673DE0FE22E4D13969398F8DA5563959C05328EF7767B6E4E11E4E31A3196F35919B29464E45E5A8A461BD9533A11A3BDF9C1F57EC911B496B05072F45427293234F8189D0649F8A05B91FFB5
Computed result: 5ED841EDA3B8C955FE433D971816C55F290735FD5C60AA5C0021F441172383463E18835FF4962FCC76C9B59894A8A11C5748183A3453C9E9D3CAACE2834A285F326D49742B2E56FF7D1DCCB91BB2F3059F6A3C509C7FB62D929B8002619BB70676B5EC0617B3D36FD2FABB2701FF9C0B94B3942673DE0FE22E4D13969398F8DA5563959C05328EF7767B6E4E11E4E31A3196F35919B29464E45E5A8A461BD9533A11A3BDF9C1F57EC911B496B05072F45427293234F8189D0649F8A05B91FFB5
=> Result is correct!
 
/trunk/sim/src/sim_input.txt
0,0 → 1,44
-- input generator program
-- generates test values per bit input pair
-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
512
32
de0bbade38204e63359a46e672a8d0a2fd5300692ab48f9ef732f5c3fa212b90c98229bbb79bece734a622154c904dce9a0f53d4a88b3e558ef7612f6694ce75
2e5d3fea7d9d0d33ac553eecd5c3f27a310115d283e49377820195c8e67781b6f112a625b14b747fa4cc13d06eba0917246c775f5c732865701ae9349ea8729c
64150a6d
8593f0d7
18f204fe6846aeb6f58174d57a3372363c0d9fcfaa3dc18b1eff7e89bf7678636580d17dd84a873b14b9c0e1680bbdc87647f3c382902d2f58d2754b39bca875
098eb081ecfa53f3f90e7dbf1e10b6e29ee45d6b02bff85403b335c0c6d5e1ab6eec5d670afb95713ed15f9723e5faedd6a42d95effafa771cb0c72d3a73c905
068bce0fed3d2cda68f16fa939fd89e1a777c1e359967090ca050e9e855f4c1e08f7d1158d16b7b130be7731ef8a962b61307a5ce65e3c2687c76b0fbea16b6e
14026cdda1794a94d7fa3cc76c69f6e43b5da0597c4040c6eb5cf65f677cac9bd85b08af0c998241ed365decd2d1cf2a62ccb6138a409224f7f03184d2cd77b5
047d6c7653eca32d15971be88eba38526fea6bbb9f991ad6c8d9ede11bb11dc888444923c5732d57d31a4aeea397179007927ba14cfdd1078664dcbbfcc3aaf4
00a84956047b71ed15148f0fc4be161c3fe4fe03650dff8e239982c0ebbbdbfbea2087f0c2f725a023e1e568e56e980e36524cbc29190b698bcb62534aa47c3b
0ae33423c12184905fb44e34ae955ac5a502c9983910135ae22ae1f477c7e4532cf1134dde48ccc4126124f91085d64d6106c503b6e71b0ce5333d679b0f016f
-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
1024
16
895f783fab56a353b58a8c4316eacf3012c77e6fbfdb4be7ed3cd27fc1c72a98f7733050ae2a4bd8c2b356f3f81de6f56258f69355b9321117b905723db3fe533ff94c12502b145c53e61608834634eae18e60c5b991b9f8d71b2d971cbe5ac9e09f4814addab421efdcc2870d2c92c87003fcff55ccba1d4f22f5ab90950fb0
2a46626cf17c40bc08e57582f9852ad12cf0ee16f2440678d35a31147278a27658a66182b41c8327a559d058a9e9df5a55fe9eeccd16fd651c2d7f13a9942e7418052b4ae1b98f8ca3f3e828532a453289bd47b363738f866debf04222abeecac1e11f980b6f115f097f4540aa7735b993f17f55083caeb6a80f80d092c59d2f
7c1f
5eb8
20f8be80ba9b4c7ca011f74c2d41581f0036d233b5e8e58b6dd5ca6db0625d764b927a43fe78844090c6843f29a331b76f8ece93e7e313eccb9bcb6ed2330923899aae43a0fd2430cb6772793755e74862e61e2ac376cfab9d61827e646421b28e9e0e2aca4625731aebbb69ea37e0fa859e499b8a186c8ee6196954170eb807
06412c26297124ba58188bc306fa67d5e2349d33c677cb3701084ab808780e2d89f5d0b912e4866f37f4fec043a08c1991c2ef1a4d9f81b6bd6e8449cf2dfa510a0417db84ec15bea71c17b483852b918137926002c232d2adfd304c7a1beef79b83544bc405d714a10e1b2ed02e33cfbf25b0dffdda16e76d92e84d778dcc27
1932ca7ae5c0e8979f823ceac3369726fe80409606a1b92fff2777002d4f71c3eefea8240ab4623c0a926245dc89a3fbf31859f4a8ca74866ebd6ff8409ac0073cc53c26991402aa702bdeaf7ca6ad054bb52cd4a7c0524eb2556e8b4143141e19ad9cd47814f9da438de01a9878d92658abfcbf39550817b54e1eb35e98f7cf
1563cce47758b785cfd5bf169f156b4e4328b02221faa51d65cc5e819abd176948d3262a5f54a3dd960d1aeaba079bb8ad3d9926d0b5f3ff3dada08f6219e932ff858e754ef7ccc3f3b63cb0be8d2b346ef8054ed96a1bfcb6ab110f52d2c601f4cca7149a7a3ae60aae54611266844562f93a152656d6c857bb8e41209e2904
19d524c74c54446433fd52e430bc5ab765afcdff9f13cfe2b81958baf4c1804e6f0ded2b6e39a37d59a9d6f9f833c6225920c7700a06f308074df8027b47ee5b4e0e3a96bcf2f44f74e5ff4b9eda59538c88e9e86f321f28584be5a4738eb56925cd464b980cbca2f78c2d456fc9c46bb58d34425dfa4b12ad486a7b79982e7f
1544b14914333391b50ddc809fdd3b372f607292a3677ac566448683b734ba6feecb8ae791e6ba01dfdf37441676459f27343e727c5ce647e4e5f3fd5cea23e891525229306db57a0df7abf72d167a09cf3daf35e24628a39cd85b824dd548c516a36586e77a844677f3889a58ff57e80734c70d37e403eb0bc122825c36585c
1324646bfb0bad60a82843ae9b47e64d4fb298550061b01755aed16ba0448afc9cac7557640de2e8eda59e5c9e29483ed5181d997d9f73e8edcfd671a724cc1f2ec976ed97b392148d8f1156f0cb4cab35a2b378c7a63b539daa0588260aa6fb2ab3f8ad497c96305a0fa081ee6ab4bb7067d3ea85c6455bf6f9af37deb38eb3
-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
1536
16
b2c5bdfaf2ba8f23d35f13f9f77a1b8efd364518248b0ab2010d3260a3445f5a0a8aa4198b0c3207d3458a2e1539a16f8d4ae39b8913a951884085dcf22f2fb08291d7363204e5335e697f7398a9eceb1cafbcd348517674f15bbcbea90537ca2c8e6364d67421f29b9ae1c2e5f17872c08b122dd36a9965916287d08d8e2ece0500d4f1e37b45e29cb056efcd1449220d602e7cf13ec97b6c4f17a7e57af9c8ec65cb9864b7a4c83290855c8ffc55bc1da64e43b9ec4e9f266dce489d14aa8c
c7a679c71dcaa96a8401dd62d7e71f68532c71819b8fe7ab721fb04b4dced1df8486000094ae3410622cd598ed3e74ab64952eee06659e1a891ccbd3702155bcbd3931224694faa89b4055c056e0aa844139fbbfe3d9b568b58387f1a955ee2e0043e5adbea47beace8589dd09bd98826db084ec7172c76b92d315d164f26c049784ed73ae654e5ca1c1d1faf227ce981b624ea7f57aab0a06b88d2b3105b957b1a19d1899b8e544f05c6de4756b8b095d2e346da3ecdb386b33fbe48f5254b1
ed01
611e
da67cd50b638d8454a6854741126c4a07cc716330a37576e5021ca2fd2f24b31e027c0b9bc2929f2a2a38c9d003ae5b45d153957d2d0fe1cd05a87f375d050f6341d1e83f0583276902503259190aa7b0353e99a8b404da6feabe3a3b4a54263523a3619aedffe301db8be0aa07b04b8d8c1210cbb3034856d6f46dec94cf866558439083e26bd03dc4c11a81239654b516b2f891d20d0f7fc98547fac560ab315de74e6eb71dccef15a3ac85d3daa6072603a608a1d9201d5f09ad67ed8ce95
27d738be5b0ccb62aec64623adfec2fb3fbdc26be7040817f764250d3f8f324ac468575a3953cfa8ea853097d17b71e3ed7a81255688a155c1f84c81f8288019a364e4a267a828ab90919f1d034743f88b81aecef510ef66dc7c45971ec384c4433bd9377cf72c97af9af5b36ea8522dea929d219819bd178b910c8c54365d5071ad39c2527b64d878d3df051b0fc82c71155571f9ea89f9a16b1ec77a05d39fd6840328958da9bb19c637d3952d0b704ff176b4ce18d782030310527785f8b6
259832af49c727bab597ab8beed93b5f8338e9ccf5c8a891afde35d02d0db4ce1fd83f4643d6d60d5d5c7362ffc51a4ba2eac6a82d2f01e32fa5780c8a2faf09cbe2e17c0fa7cd896fdafcda6e6f5584fcac166574bfb25901541c5c4b5abd9cadc5c9e6512001cfe24741f55f84fb47273edef344cfcb7a9290b92136b30799aa7bc6f7c1d942fc23b3ee57edc69ab4ae94d076e2df2f080367ab8053a9f54cea218b19148e23310ea5c537a2c2559f8d9fc59f75e26dfe2a0f65298127316b
bf4e8a2aff25f970db92a08206b2662fade7e2dee533fc585f0ebf85280f8760a45a7af38aec082a8bf07b380a3814e52b38147b7e92cde28cb7d0500bacba0e79a7d9752bc3f6b4a8ce7e9091d8f614fe8b970135d27e63f81faa587f35871abd5b3a8d4bd84e6ab717d1e49c5f92470547d4bf977a07eefcbdebe1754278afc06505e4058c099da4632614db98d9e3d7447e2a48403bd9cda0efb7fbc4e43a9e962cc9abe24f6312893a165927614519ccf6897d3f17f3d9ff5ca3abb00117
4505cc0eb73a76e09af6c512b4b3611d7c3b3108a68ad4d08aca6ca13756e553efe6ade8c7a0ae6b5bbad04ba0a281824de0a13763c3aca96930c4f9aec2e9ed52e9f329db58ec6acc4d1a86df706f3e74b2e088f9064caef6a0074d63e726243779721517848124ea65c1ccd3e8a1471afa3f25811a577757aa2807577a7c6a77c3634813f92cdaade697cb17fa0555918d53a75e05c263e807f107437a5c4032c68f18b8ca54a61caff215debc1a0988933e6e442501a8fbc497403631d543
51fe92e79cf87e206a6a1d6192cc670090a20ad3fcc36f13ce25fc7ca15f7c0cf5fc1f466beb949c01af87520731b63699900f0d4bbc21d2fc13b30a66fd767d76b6d391fb1418edc2e07057d9fa124c99dfe154e46f98a718a09ccfd01862ebbff0221cdfe9039851872526aee09be7efe4f1fe3d2fdf747e0ab0fce0f5062e7379e19fbe8f25647a081a90e5a8c9c28fa7a2d600c9072b139c901236ec3e04ab2e67c684348d07c0857b7d85dabe1e232eeb63675c63d6732f2bfea20dcd6b
5ed841eda3b8c955fe433d971816c55f290735fd5c60aa5c0021f441172383463e18835ff4962fcc76c9b59894a8a11c5748183a3453c9e9d3caace2834a285f326d49742b2e56ff7d1dccb91bb2f3059f6a3c509c7fb62d929b8002619bb70676b5ec0617b3d36fd2fabb2701ff9c0b94b3942673de0fe22e4d13969398f8da5563959c05328ef7767b6e4e11e4e31a3196f35919b29464e45e5a8a461bd9533a11a3bdf9c1f57ec911b496b05072f45427293234f8189d0649f8a05b91ffb5
/trunk/sim/Makefile
0,0 → 1,72
#VCOM = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
 
 
##
# avs_aes hdl files
##
CORE_SRC =$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
$(HDL_DIR)/core/adder_block.vhd \
$(HDL_DIR)/core/adder_n.vhd \
$(HDL_DIR)/core/autorun_cntrl.vhd \
$(HDL_DIR)/core/cell_1b_adder.vhd \
$(HDL_DIR)/core/cell_1b_mux.vhd \
$(HDL_DIR)/core/cell_1b.vhd \
$(HDL_DIR)/core/counter_sync.vhd \
$(HDL_DIR)/core/d_flip_flop.vhd \
$(HDL_DIR)/core/fifo_primitive.vhd \
$(HDL_DIR)/core/first_stage.vhd \
$(HDL_DIR)/core/last_stage.vhd \
$(HDL_DIR)/core/modulus_ram.vhd \
$(HDL_DIR)/core/mont_ctrl.vhd \
$(HDL_DIR)/core/mont_mult_sys_pipeline.vhd \
$(HDL_DIR)/core/multiplier_core.vhd \
$(HDL_DIR)/core/operand_dp.vhd \
$(HDL_DIR)/core/operand_mem.vhd \
$(HDL_DIR)/core/operand_ram.vhd \
$(HDL_DIR)/core/operands_sp.vhd \
$(HDL_DIR)/core/register_1b.vhd \
$(HDL_DIR)/core/register_n.vhd \
$(HDL_DIR)/core/standard_cell_block.vhd \
$(HDL_DIR)/core/standard_stage.vhd \
$(HDL_DIR)/core/stepping_logic.vhd \
$(HDL_DIR)/core/systolic_pipeline.vhd \
$(HDL_DIR)/core/x_shift_reg.vhd \
 
 
##
# Testbench HDL file
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC = $(TB_SRC_DIR)tb_multiplier_core.vhd
 
#######################################
all: mod_sim_exp
 
clean:
rm -rf *_lib
 
mod_sim_exp_lib:
vlib mod_sim_exp
 
work_lib:
vlib work
 
libs: mod_sim_exp work_lib
 
mod_sim_exp_com: mod_sim_exp_lib
#echo --
#echo building Modular Exponentiation Core
#echo --
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
 
mod_sim_exp_tb: work_lib
#echo --
#echo building Modular Exponentiation Core Testbench
#echo --
vcom $(VCOMOPS) -work work $(TB_SRC)
 
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
vsim -c -do mod_sim_exp.do -lib work tb_multiplier_core

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.