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URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

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    /mpmc8/trunk
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Rev 6 → Rev 7

/rtl/mpmc10/mpcm10_cache_wb.sv
91,7 → 91,7
reg [31:0] radrr [0:8];
reg wchi_stb, wchi_stb_r;
reg [15:0] wchi_sel, wchi_sel_r;
reg [31:0] wchi_adr;
reg [31:0] wchi_adr, wchi_adr1;
reg [127:0] wchi_dat;
 
mpmc10_quad_cache_line_t doutb [0:8];
98,6 → 98,8
mpmc10_quad_cache_line_t wrdata, wdata;
 
reg [31:0] wadr;
reg [127:0] lddat1, lddat2;
reg [31:0] wadr2;
reg wstrb;
reg [$clog2(CACHE_ASSOC)-1:0] wway;
 
140,7 → 142,8
always_ff @(posedge ch6clk) radrr[6] <= ch6i.adr;
always_ff @(posedge ch7clk) radrr[7] <= ch7i.adr;
always_ff @(posedge wclk) radrr[8] <= ld.cyc ? ld.adr : wchi.adr;
always_ff @(posedge wclk) wchi_adr <= radrr[8];
always_ff @(posedge wclk) wchi_adr1 <= wchi.adr;
always_ff @(posedge wclk) wchi_adr <= wchi_adr1;
 
always_ff @(posedge ch0clk) stb0 <= ch0i.stb;
always_ff @(posedge ch1clk) stb1 <= ch1i.stb;
159,7 → 162,7
always_comb rstb[5] <= ch5i.stb & ~ch5i.we;
always_comb rstb[6] <= ch6i.stb & ~ch6i.we;
always_comb rstb[7] <= ch7i.stb & ~ch7i.we;
always_comb rstb[8] <= ld.stb | wchi.stb;
always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
 
always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
388,7 → 391,7
b1 <= vbit[1][wadr[HIBIT:LOBIT]];
b2 <= vbit[2][wadr[HIBIT:LOBIT]];
end
if (|wchi_sel & wchi_stb & ~(ld.cyc|ldcycd1|ldcycd2))
if (|hit8a & |wchi_sel & wchi_stb & wchi.we & ~(ld.cyc|ldcycd1|ldcycd2))
vbit[wway][wadr[HIBIT:LOBIT]] <= 1'b1;
else if (inv)
vbit[wway][wadr[HIBIT:LOBIT]] <= 1'b0;
403,10 → 406,8
wadr <= ld.adr;
else if (wchi_stb)
wadr <= wchi_adr;
wstrb <= ldcycd2 | (wchi_stb & |hit8a);
wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
end
reg [127:0] lddat1, lddat2;
reg [31:0] wadr2;
always_ff @(posedge wclk)
wadr2 <= wadr;
always_ff @(posedge wclk)
443,22 → 444,22
m2 <= wrdata.lines[2].modified;
end
if (!(ld.cyc|ldcycd1|ldcycd2)) begin
if (wchi_stb & hit8a[0])
if (wchi_stb & hit8a[0] & wchi.we)
wdata.lines[0].modified <= 1'b1;
else
wdata.lines[0].modified <= wrdata.lines[0].modified;
if (wchi_stb & hit8a[1])
if (wchi_stb & hit8a[1] & wchi.we)
wdata.lines[1].modified <= 1'b1;
else
wdata.lines[1].modified <= wrdata.lines[0].modified;
if (wchi_stb & hit8a[2])
wdata.lines[1].modified <= wrdata.lines[1].modified;
if (wchi_stb & hit8a[2] & wchi.we)
wdata.lines[2].modified <= 1'b1;
else
wdata.lines[2].modified <= wrdata.lines[0].modified;
if (wchi_stb & hit8a[3])
wdata.lines[2].modified <= wrdata.lines[2].modified;
if (wchi_stb & hit8a[3] & wchi.we)
wdata.lines[3].modified <= 1'b1;
else
wdata.lines[3].modified <= wrdata.lines[0].modified;
wdata.lines[3].modified <= wrdata.lines[3].modified;
// Tag stays the same, it was hit
wdata.lines[0].tag <= wrdata.lines[0].tag;
wdata.lines[1].tag <= wrdata.lines[1].tag;
477,22 → 478,22
wdata.lines[3].data[g*8+7:g*8] <= wrdata.lines[2].data[g*8+7:g*8];
end
if (!(ld.cyc|ldcycd1|ldcycd2)) begin
if (wchi_stb & hit8a[0])
if (wchi_stb & hit8a[0] & wchi.we)
wdata.lines[0].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[0].data[g*8+7:g*8];
else
wdata.lines[0].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
if (wchi_stb & hit8a[1])
if (wchi_stb & hit8a[1] & wchi.we)
wdata.lines[1].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[1].data[g*8+7:g*8];
else
wdata.lines[1].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
if (wchi_stb & hit8a[2])
wdata.lines[1].data[g*8+7:g*8] <= wrdata.lines[1].data[g*8+7:g*8];
if (wchi_stb & hit8a[2] & wchi.we)
wdata.lines[2].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[2].data[g*8+7:g*8];
else
wdata.lines[2].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
if (wchi_stb & hit8a[3])
wdata.lines[2].data[g*8+7:g*8] <= wrdata.lines[2].data[g*8+7:g*8];
if (wchi_stb & hit8a[3] & wchi.we)
wdata.lines[3].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[3].data[g*8+7:g*8];
else
wdata.lines[3].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
wdata.lines[3].data[g*8+7:g*8] <= wrdata.lines[3].data[g*8+7:g*8];
end
end
end
507,7 → 508,7
wack <= 1'b0;
else begin
wack <= 1'b0;
if (wchi.stb & ~ld.stb)
if (wchi.stb & ~ld.stb & wchi.we)
wack <= 1'b1;
end
assign wcho.ack = wack & wchi.stb;
/rtl/mpmc10/mpmc10_app_en_gen.sv
38,7 → 38,7
 
module mpmc10_app_en_gen(clk, state, rdy, strip_cnt, num_strips, en);
input clk;
input [3:0] state;
input mpmc10_state_t state;
input rdy;
input [5:0] strip_cnt;
input [5:0] num_strips;
49,14 → 49,14
always_ff @(posedge clk)
begin
en <= mpmc10_pkg::FALSE;
if (state==mpmc10_pkg::WRITE_DATA1)
en <= mpmc10_pkg::TRUE;
else if (state==mpmc10_pkg::WRITE_DATA2 && !rdy)
en <= mpmc10_pkg::TRUE;
else if (state==mpmc10_pkg::READ_DATA0)
en <= mpmc10_pkg::TRUE;
else if (state==mpmc10_pkg::READ_DATA1 && !(rdy && strip_cnt==num_strips))
en <= mpmc10_pkg::TRUE;
if (state==WRITE_DATA1)
en <= TRUE;
else if (state==WRITE_DATA2 && !en)
en <= TRUE;
else if (state==READ_DATA0)
en <= TRUE;
else if (state==READ_DATA1 && !(rdy && strip_cnt==num_strips))
en <= TRUE;
end
 
endmodule
/rtl/mpmc10/mpmc10_app_wdf_wren_gen.sv
38,16 → 38,16
 
module mpmc10_app_wdf_wren_gen(clk, state, rdy, wren);
input clk;
input [3:0] state;
input mpmc10_state_t state;
input rdy;
output reg wren;
 
// app_wdf_wren is used to strobe data into the data fifo when app_wdf_rdy is
// true.
// true. It must be after en is asserted to set the command and address.
always_ff @(posedge clk)
begin
wren <= mpmc10_pkg::FALSE;
if (state==mpmc10_pkg::WRITE_DATA0 && rdy)
if (state==WRITE_DATA3)// WRITE_DATA0 && rdy)
wren <= mpmc10_pkg::TRUE;
end
 
/rtl/mpmc10/mpmc10_data_select.sv
39,13 → 39,13
module mpmc10_data_select(clk, state, dati, dato);
parameter WID=256;
input clk;
input [3:0] state;
input mpmc10_state_t state;
input [WID-1:0] dati;
output reg [WID-1:0] dato;
 
// Setting the write data
always_ff @(posedge clk)
if (state==mpmc10_pkg::IDLE) begin
if (state==PRESET2) begin
dato <= dati;
end
 
/rtl/mpmc10/mpmc10_mask_select.sv
39,7 → 39,7
module mpmc10_mask_select(rst, clk, state, wmask, mask, mask2);
input rst;
input clk;
input [3:0] state;
input mpmc10_state_t state;
input [15:0] wmask;
output reg [15:0] mask;
output reg [15:0] mask2;
49,7 → 49,7
if (rst)
mask2 <= 16'h0000;
else begin
if (state==PRESET1)
if (state==PRESET2)
mask2 <= wmask;
// For RMW cycle all bytes are writtten.
else if (state==WRITE_TRAMP1)
59,7 → 59,7
if (rst)
mask <= 16'h0000;
else begin
if (state==PRESET2)
if (state==PRESET3)
mask <= mask2;
end
 
/rtl/mpmc10/mpmc10_set_write_mask.sv
54,7 → 54,7
input [4:0] adri;
output [15:0] masko;
begin
if (state==IDLE)
if (state==PRESET2)
if (wei)
masko <= ~seli >> {adri[4],4'h0};
else
/rtl/mpmc10/mpmc10_set_write_mask_wb.sv
39,7 → 39,7
module mpmc10_set_write_mask_wb(clk, state, we, sel, adr, mask);
parameter WID=16;
input clk;
input [3:0] state;
input mpmc10_state_t state;
input we;
input [WID-1:0] sel;
input [31:0] adr;
55,7 → 55,7
input [4:0] adri;
output [15:0] masko;
begin
if (state==IDLE)
if (state==PRESET1)
if (wei)
masko <= ~seli;
else
/rtl/mpmc10/mpmc10_state_machine_wb.sv
36,115 → 36,99
//
import mpmc10_pkg::*;
 
module mpmc10_state_machine_wb(rst, clk, to, rdy, wdf_rdy, fifo_empty, rd_fifo,
module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
rd_rst_busy, fifo_out, state,
num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid, wway);
num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid);
input rst;
input clk;
input calib_complete;
input to; // state machine time-out
input rdy;
input wdf_rdy;
input fifo_empty;
input rd_rst_busy;
output reg rd_fifo;
input wb_write_request128_t fifo_out;
output reg [3:0] state;
output mpmc10_state_t state;
input [5:0] num_strips;
input [5:0] req_strip_cnt;
input [5:0] resp_strip_cnt;
input rd_data_valid;
output reg [1:0] wway;
 
reg [3:0] next_state;
reg next_rd_fifo;
mpmc10_state_t next_state;
 
always_ff @(posedge clk)
state <= next_state;
always_ff @(posedge clk)
rd_fifo <= next_rd_fifo;
always_ff @(posedge clk)
if (rst)
wway <= 2'd0;
else begin
if (state==mpmc10_pkg::PRESET1)
wway <= wway + 2'd1;
end
 
always_comb
if (rst) begin
next_state <= mpmc10_pkg::IDLE;
next_rd_fifo <= 1'b0;
end
if (rst)
next_state <= IDLE;
else begin
next_rd_fifo <= 1'b0;
case(state)
mpmc10_pkg::IDLE:
if (!fifo_empty && !rd_rst_busy) begin
next_rd_fifo <= 1'b1;
next_state <= mpmc10_pkg::PRESET1;
end
IDLE:
if (!fifo_empty && !rd_rst_busy && calib_complete)
next_state <= PRESET1;
else
next_state <= mpmc10_pkg::IDLE;
mpmc10_pkg::PRESET1:
next_state <= mpmc10_pkg::PRESET2;
mpmc10_pkg::PRESET2:
next_state <= mpmc10_pkg::PRESET3;
mpmc10_pkg::PRESET3:
next_state <= IDLE;
PRESET1:
next_state <= PRESET2;
PRESET2:
next_state <= PRESET3;
PRESET3:
if (fifo_out.stb & fifo_out.we)
next_state <= mpmc10_pkg::WRITE_DATA0;
next_state <= WRITE_DATA0;
else
next_state <= mpmc10_pkg::READ_DATA0;
next_state <= READ_DATA0;
// Write data to the data fifo
// Write occurs when app_wdf_wren is true and app_wdf_rdy is true
mpmc10_pkg::WRITE_DATA0:
WRITE_DATA0:
// Issue a write command if the fifo is full.
// if (!app_wdf_rdy)
// next_state <= WRITE_DATA1;
// else
if (wdf_rdy)// && req_strip_cnt==num_strips)
next_state <= mpmc10_pkg::WRITE_DATA1;
next_state <= WRITE_DATA1;
else
next_state <= mpmc10_pkg::WRITE_DATA0;
mpmc10_pkg::WRITE_DATA1:
next_state <= mpmc10_pkg::WRITE_DATA2;
mpmc10_pkg::WRITE_DATA2:
next_state <= WRITE_DATA0;
WRITE_DATA1:
next_state <= WRITE_DATA2;
WRITE_DATA2:
if (rdy)
next_state <= mpmc10_pkg::WRITE_DATA3;
next_state <= WRITE_DATA3;
else
next_state <= mpmc10_pkg::WRITE_DATA2;
mpmc10_pkg::WRITE_DATA3:
next_state <= mpmc10_pkg::IDLE;
next_state <= WRITE_DATA2;
WRITE_DATA3:
next_state <= IDLE;
 
// There could be multiple read requests submitted before any response occurs.
// Stay in the SET_CMD_RD until all requested strips have been processed.
mpmc10_pkg::READ_DATA0:
next_state <= mpmc10_pkg::READ_DATA1;
READ_DATA0:
next_state <= READ_DATA1;
// Could it take so long to do the request that we start getting responses
// back?
mpmc10_pkg::READ_DATA1:
READ_DATA1:
if (rdy && req_strip_cnt==num_strips)
next_state <= mpmc10_pkg::READ_DATA2;
next_state <= READ_DATA2;
else
next_state <= mpmc10_pkg::READ_DATA1;
next_state <= READ_DATA1;
// Wait for incoming responses, but only for so long to prevent a hang.
mpmc10_pkg::READ_DATA2:
READ_DATA2:
if (rd_data_valid && resp_strip_cnt==num_strips)
next_state <= mpmc10_pkg::WAIT_NACK;
next_state <= WAIT_NACK;
else
next_state <= mpmc10_pkg::READ_DATA2;
next_state <= READ_DATA2;
 
mpmc10_pkg::WAIT_NACK:
WAIT_NACK:
// If we're not seeing a nack and there is a channel selected, then the
// cache tag must not have updated correctly.
// For writes, assume a nack by now.
next_state <= mpmc10_pkg::IDLE;
next_state <= IDLE;
default: next_state <= mpmc10_pkg::IDLE;
default: next_state <= IDLE;
endcase
 
// Is the state machine hung?
// if (to)
// next_state <= mpmc10_pkg::IDLE;
// Is the state machine hung? Do not time out during calibration.
if (to && calib_complete)
next_state <= IDLE;
end
 
endmodule
/rtl/mpmc10/mpmc10_wb.sv
47,6 → 47,7
input clk100MHz,
input mem_ui_rst,
input mem_ui_clk,
input calib_complete,
output reg rstn,
output [31:0] app_waddr,
input app_rdy,
78,7 → 79,7
output wb_read_response128_t ch6o,
input wb_write_request128_t ch7i,
output wb_read_response128_t ch7o,
output [3:0] state
output mpmc10_state_t state
);
parameter NAR = 2; // Number of address reservations
parameter CL = 3'd4; // Cache read latency
129,14 → 130,15
wb_write_request128_t req_fifoi;
wb_write_request128_t req_fifoo;
wb_write_request128_t ld;
wb_write_request128_t fifo_mask;
wb_write_request128_t fifoo = req_fifoo & fifo_mask;
 
genvar g;
integer n1,n2;
integer n1,n2,n3;
wire almost_full;
wire [4:0] cnt;
reg wr_fifo;
wire [3:0] prev_state;
wire [3:0] state;
mpmc10_state_t prev_state;
wire rd_fifo; // from state machine
reg [5:0] num_strips; // from fifo
wire [5:0] req_strip_cnt;
148,12 → 150,11
wire [15:0] wmask;
wire [15:0] mem_wdf_mask2;
reg [127:0] dat128;
wire [255:0] dat256;
wire [127:0] dat256;
wire [3:0] resv_ch [0:NAR-1];
wire [31:0] resv_adr [0:NAR-1];
wire rb1;
reg [7:0] req;
wire [1:0] wway;
reg [127:0] rd_data_r;
reg rd_data_valid_r;
 
202,7 → 203,7
chcnt[n2] <= 'd0;
end
 
reg [7:0] pe_req;
wire [7:0] pe_req;
reg [7:0] chack;
always_comb chack[0] = ch0o.ack;
always_comb chack[1] = ch1o.ack;
213,8 → 214,14
always_comb chack[6] = ch6o.ack;
always_comb chack[7] = ch7o.ack;
 
reg [7:0] reqa;
always_comb reqa[1] = (!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb);
always_comb reqa[5] = (!ch5o.ack && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb);
 
wire rste = mem_ui_rst||rst||!calib_complete;
 
edge_det edch0 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch0o.ack && ch0is.stb && !ch0is.we && chcnt[0]==CL) || (ch0is.we && ch0is.stb)),
223,16 → 230,16
.ee()
);
edge_det edch1 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb)),
.i(reqa[1]),
.pe(pe_req[1]),
.ne(),
.ee()
);
edge_det edch2 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch2o.ack && ch2is.stb && !ch2is.we && chcnt[2]==CL) || (ch2is.we && ch2is.stb)),
241,7 → 248,7
.ee()
);
edge_det edch3 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch3o.ack && ch3is.stb && !ch3is.we && chcnt[3]==CL) || (ch3is.we && ch3is.stb)),
250,7 → 257,7
.ee()
);
edge_det edch4 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch4o.ack && ch4is.stb && !ch4is.we && chcnt[4]==CL) || (ch4is.we && ch4is.stb)),
259,16 → 266,16
.ee()
);
edge_det edch5 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch5_hit_s && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb)),
.i(reqa[5]),
.pe(pe_req[5]),
.ne(),
.ee()
);
edge_det edch6 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch6o.ack && ch6is.stb && !ch6is.we && chcnt[6]==CL) || (ch6is.we && ch6is.stb)),
277,7 → 284,7
.ee()
);
edge_det edch7 (
.rst(mem_ui_rst),
.rst(rste),
.clk(mem_ui_clk),
.ce(1'b1),
.i((!ch7o.ack && ch7is.stb && !ch7is.we && chcnt[7]==CL) || (ch7is.we && ch7is.stb)),
286,15 → 293,12
.ee()
);
wire [3:0] req_sel;
generate begin : gReq
for (g = 0; g < 8; g = g + 1)
always_ff @(posedge mem_ui_clk)
if (pe_req[g])
req[g] <= 1'b1;
else if (req_sel==g[3:0] || chack[g])
req[g] <= 1'b0;
end
endgenerate
always_ff @(posedge mem_ui_clk)
for (n3 = 0; n3 < 8; n3 = n3 + 1)
if (pe_req[n3])
req[n3] <= 1'b1;
else if ((req_sel==n3[3:0]) || chack[n3])
req[n3] <= 1'b0;
 
// Register signals onto mem_ui_clk domain
mpmc10_sync128_wb usyn0
394,8 → 398,8
ld.bte <= wishbone_pkg::LINEAR;
ld.cti <= wishbone_pkg::CLASSIC;
ld.blen <= 'd0;
ld.cyc <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
ld.stb <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
ld.cyc <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
ld.we <= 1'b0;
ld.adr <= {app_waddr[31:4],4'h0};
ld.dat <= {app_waddr[31:14],8'h00,rd_data_r}; // modified=false,tag = high order address bits
439,8 → 443,8
(
.rst(mem_ui_rst),
.wclk(mem_ui_clk),
.inv(),
.wchi(req_fifoo),
.inv(1'b0),
.wchi(fifoo),
.wcho(),
.ld(ld),
.ch0clk(STREAM0 ? 1'b0 : ch0clk),
610,7 → 614,7
wire rd_rst_busy;
wire wr_rst_busy;
wire cd_sel;
change_det #(.WID(8)) ucdsel (.rst(rst), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
change_det #(.WID(8)) ucdsel (.rst(rst), .ce(1'b1), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
 
always_comb //ff @(posedge mem_ui_clk)
wr_fifo = |sel & ~almost_full & ~wr_rst_busy & cd_sel;
636,7 → 640,11
4'd5: req_fifoi <= STREAM5 ? ch5is2 : ch5is;
4'd6: req_fifoi <= STREAM6 ? ch6is2 : ch6is;
4'd7: req_fifoi <= STREAM7 ? ch7is2 : ch7is;
default: req_fifoi <= 'd0;
default:
begin
req_fifoi <= 'd0;
req_fifoi.cid <= 4'd15;
end
endcase
 
mpmc10_fifo ufifo1
657,11 → 665,11
);
 
always_comb
uch <= req_fifoo.cid;
uch <= fifoo.cid;
always_comb
num_strips <= req_fifoo.blen;
num_strips <= fifoo.blen;
always_comb
adr <= req_fifoo.adr;
adr <= fifoo.adr;
 
wire [2:0] app_addr3; // dummy to make up 32-bits
 
693,7 → 701,7
(
.clk(mem_ui_clk),
.state(state),
.we(req_fifoo.we),
.we(fifoo.we),
.sel(req_fifoo.sel[15:0]),
.adr(adr|{req_strip_cnt[0],4'h0}),
.mask(wmask)
737,23 → 745,43
if (mem_ui_rst)
app_wdf_data <= 128'd0;
else begin
if (state==PRESET2)
if (state==PRESET3)
app_wdf_data <= dat128x;
// else if (state==WRITE_TRAMP1)
// app_wdf_data <= rmw_data;
end
 
mpmc10_rd_fifo_gen urdf1
(
.rst(rst|mem_ui_rst),
.clk(mem_ui_clk),
.state(state),
.empty(empty),
.rd_rst_busy(rd_rst_busy),
.calib_complete(calib_complete),
.rd(rd_fifo)
);
 
always_ff @(posedge mem_ui_clk)
if (rst)
fifo_mask <= 'd0;
else begin
if (rd_fifo)
fifo_mask <= {$bits(fifo_mask){1'b1}};
else if (state==IDLE)
fifo_mask <= 'd0;
end
 
mpmc10_state_machine_wb usm1
(
.rst(rst|mem_ui_rst),
.clk(mem_ui_clk),
.calib_complete(calib_complete),
.to(tocnt[9]),
.rdy(app_rdy),
.wdf_rdy(app_wdf_rdy),
.fifo_empty(empty),
.rd_rst_busy(rd_rst_busy),
.rd_fifo(rd_fifo),
.fifo_out(req_fifoo),
.state(state),
.num_strips(num_strips),
836,10 → 864,10
(
.clk(mem_ui_clk),
.state(state),
.wch(req_fifoo.cid),
.we(req_fifoo.stb & req_fifoo.we),
.cr(req_fifoo.csr & req_fifoo.we),
.adr(req_fifoo.adr),
.wch(fifoo.cid),
.we(fifoo.stb & fifoo.we),
.cr(fifoo.csr & fifoo.we),
.adr(fifoo.adr),
.resv_ch(resv_ch),
.resv_adr(resv_adr),
.rb(rb1)
866,10 → 894,10
.sr5(1'b0),
.sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
.sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
.wch(req_fifoo.stb ? req_fifoo.cid : 4'd15),
.we(req_fifoo.stb & req_fifoo.we),
.wadr(req_fifoo.adr),
.cr(req_fifoo.csr & req_fifoo.stb & req_fifoo.we),
.wch(fifoo.stb ? fifoo.cid : 4'd15),
.we(fifoo.stb & fifoo.we),
.wadr(fifoo.adr),
.cr(fifoo.csr & fifoo.stb & fifoo.we),
.resv_ch(resv_ch),
.resv_adr(resv_adr)
);

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