URL
https://opencores.org/ocsvn/mpx/mpx/trunk
Subversion Repositories mpx
Compare Revisions
- This comparison shows the changes necessary to convert path
/mpx
- from Rev 4 to Rev 3
- ↔ Reverse comparison
Rev 4 → Rev 3
/trunk/fpga_papilio_xc3/program.vhd
File deleted
/trunk/fpga_papilio_xc3/fpga.ucf
File deleted
/trunk/fpga_papilio_xc3/ClockDCM.vhd
File deleted
/trunk/fpga_papilio_xc3/top.vhd
File deleted
/trunk/fpga_papilio_xc3/fpga_papilio_xc3s250e.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/fpga_papilio_xc3/fpga_papilio_xc3s250e.bit
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/fpga_papilio_xc3/Memory Map.txt
===================================================================
--- trunk/fpga_papilio_xc3/Memory Map.txt (revision 4)
+++ trunk/fpga_papilio_xc3/Memory Map.txt (nonexistent)
@@ -1,13 +0,0 @@
-
-Memory Map
-----------
-
-The XC3S250E has around 24KB of BlockRAM which has been instantiated as 'BootRAM'.
-This memory is pre-initialised with a bootloader image which can be used to load new code via the serial port using X-Modem file transfer protocol.
-
-Map:
-0x0000 - 0x2000 = Bootloader
-0x2000 - 0x6000 = Application space
-
-
-The bootloader section 0x0000 - 0x2000 (8KBytes) can be re-used for BSS & Data sections for the application (thus overwriting the bootloader post boot).
Index: trunk/fpga_papilio_xc3/components.vhd
===================================================================
--- trunk/fpga_papilio_xc3/components.vhd (revision 4)
+++ trunk/fpga_papilio_xc3/components.vhd (nonexistent)
@@ -1,133 +0,0 @@
--------------------------------------------------------------------
--- MPX 32-bit Soft-Core Processor
--- V0.1
--- Ultra-Embedded.com
--- Copyright 2011 - 2012
---
--- Email: admin@ultra-embedded.com
---
--- License: LGPL
---
--- If you would like a version with a different license for use
--- in commercial projects please contact the above email address
--- for more details.
--------------------------------------------------------------------
---
--- Copyright (C) 2011 - 2012 Ultra-Embedded.com
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, write to the
--- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
--- Boston, MA 02111-1307 USA
--------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package peripherals is
-
--------------------------------------------------------------------
--- Components:
--------------------------------------------------------------------
-component mpx_soc
-generic
-(
- CLK_KHZ : integer := 12288;
- UART_BAUD : integer := 115200;
- EXTERNAL_INTERRUPTS : integer := 1;
- CORE_ID : std_logic_vector := X"00000000";
- BOOT_VECTOR : std_logic_vector := X"00000000";
- ISR_VECTOR : std_logic_vector := X"0000003C"
-);
-port
-(
- -- General - clocking & rst_i
- clk_i : in std_logic;
- rst_i : in std_logic;
- en_i : in std_logic;
- ext_intr_i : in std_logic_vector(EXTERNAL_INTERRUPTS-1 downto 0);
- fault_o : out std_logic;
-
- -- UART
- uart_tx_o : out std_logic;
- uart_rx_i : in std_logic;
-
- -- BootRAM
- int_mem_addr_o : out std_logic_vector(32-1 downto 0);
- int_mem_data_o : out std_logic_vector(32-1 downto 0);
- int_mem_data_i : in std_logic_vector(32-1 downto 0);
- int_mem_wr_o : out std_logic_vector(3 downto 0);
- int_mem_rd_o : out std_logic;
-
- -- External IO
- ext_io_addr_o : out std_logic_vector(32-1 downto 0);
- ext_io_data_o : out std_logic_vector(32-1 downto 0);
- ext_io_data_i : in std_logic_vector(32-1 downto 0);
- ext_io_wr_o : out std_logic_vector(3 downto 0);
- ext_io_rd_o : out std_logic;
- ext_io_pause_i : in std_logic;
-
- -- Debug Register Access
- dbg_reg_addr_i : in std_logic_vector(8 downto 0);
- dbg_reg_out_o : out std_logic_vector(31 downto 0);
- dbg_pc_o : out std_logic_vector(31 downto 0);
-
- -- Debug UART Output
- dbg_uart_data_o : out std_logic_vector(7 downto 0);
- dbg_uart_wr_o : out std_logic
-);
-end component;
-
-component ClockDCM is
-generic
-(
- CLK_IN_MHZ : integer := 32;
- CLK_OUT_MHZ : integer := 64
-);
-port
-(
- CLKIN_IN : in std_logic;
- CLKFX_OUT : out std_logic;
- CLKIN_IBUFG_OUT : out std_logic
-);
-end component;
-
-component ram
-generic
-(
- memory_type : string := "DEFAULT";
- --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
- block_count : integer := 1
-);
-port(clk : in std_logic;
- enable : in std_logic;
- write_byte_enable : in std_logic_vector(3 downto 0);
- address : in std_logic_vector(31 downto 2);
- data_write : in std_logic_vector(31 downto 0);
- data_read : out std_logic_vector(31 downto 0));
-end component;
-
-
-end peripherals;
-
-package body peripherals is
-
-end; --package body
Index: trunk/fpga_papilio_xc3
===================================================================
--- trunk/fpga_papilio_xc3 (revision 4)
+++ trunk/fpga_papilio_xc3 (nonexistent)
trunk/fpga_papilio_xc3
Property changes :
Deleted: bugtraq:number
## -1 +0,0 ##
-true
\ No newline at end of property
Index: trunk/soc/mpx_soc_defs.v
===================================================================
--- trunk/soc/mpx_soc_defs.v (revision 4)
+++ trunk/soc/mpx_soc_defs.v (revision 3)
@@ -41,9 +41,9 @@
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
-`define MEM_REGION_INTERNAL 3'b000
+`define MEM_REGION_INTERNAL 3'b001
`define MEM_REGION_CORE_IO 3'b010
-`define MEM_REGION_EXT_IO 3'b011
+`define MEM_REGION_EXT_IO 3'b011
//-----------------------------------------------------------------
// I/O
/trunk/sim/mpx_top.v
117,8 → 117,8
.UART_BAUD(115200), |
.EXTERNAL_INTERRUPTS(1), |
.CORE_ID(32'h00000000), |
.BOOT_VECTOR(32'h00002000), |
.ISR_VECTOR(32'h0000203C) |
.BOOT_VECTOR(32'h10000000), |
.ISR_VECTOR(32'h1000003C) |
) |
u1_cpu |
( |
/trunk/sim/mpx_top.cpp
57,9 → 57,6
//----------------------------------------------------------------- |
// Defines |
//----------------------------------------------------------------- |
// Memory start offset (set to 0x2000 to match FPGA version where |
// bootloader exists in first 8K) |
#define MEMORY_START 0x2000 |
#define MEMORY_SIZE (512 * 1024) |
|
//----------------------------------------------------------------- |
113,11 → 110,9
//----------------------------------------------------------------- |
int mpx_test_load(unsigned int addr, unsigned char val) |
{ |
if (addr >= (MEMORY_SIZE - MEMORY_START)) |
if (addr >= MEMORY_SIZE) |
return -1; |
|
addr += MEMORY_START; |
|
switch (addr & 0x3) |
{ |
case 0: |
/trunk/sim/test_image.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/sim/Readme.txt
9,7 → 9,7
To run applications: |
./run_mpx image.bin |
|
Where image.bin is your compiled source which has a starting address of 0x00002000. |
Where image.bin is your compiled source which has a starting address of 0x10000000. |
|
Example Image: |
./run_mpx test_image.bin |
29,5 → 29,4
10. SYSCALL return PC check |
11. Comparision |
Correct comparision |
Total test clock cycles: 1180442 |
DONE! |
Total test clock cycles: 1679037 |