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/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_101.vhd
0,0 → 1,53
-- File: generated/lfsr_101.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_101 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(100 downto 0)
);
end entity lfsr_101;
 
 
architecture MyHDL of lfsr_101 is
 
 
 
 
 
signal reg_internal: unsigned(100 downto 0);
 
begin
 
 
 
 
 
LFSR_101_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00000110110110000110100000110100111001000000011101111100000011111100010001101010100010111100111000000";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("11000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_101_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_1024.vhd
0,0 → 1,53
-- File: generated/lfsr_1024.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_1024 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(1023 downto 0)
);
end entity lfsr_1024;
 
 
architecture MyHDL of lfsr_1024 is
 
 
 
 
 
signal reg_internal: unsigned(1023 downto 0);
 
begin
 
 
 
 
 
LFSR_1024_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0010101001100110010111000110010110001000111011111000011010001110000111011011010010100011100001110100000111101001110110010000010111110110001010011001111001111111011101010110011001011101100111110011000000100011100111111010010010011110110011000001101100110100110000010101111001110010100110111001001011101101110111010100111010001110110101101010010011011111010011010001101001011110110010100100010001011010001001110110011001011001011111101011100001000000111011110001110111111110111111111000100011110110100011000000101110110001100000101111000101111010010100000001011100001100110010101000100001100110011001011101010011110100011001101110101100111101100110101010011110100111100001110001100001100110010000000111001100001011101101011000100111010000001010110000000011001000111010000001110001000100010110111000100011001101011100111000000101000010010010100011110001001001010011010110000001111000001100101010111101010111010101000100101001001111100000101110111111011000000011010010001010011011001001011101110010011010001001111001111000111110";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1000000001000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_1024_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_12.vhd
0,0 → 1,54
-- File: generated/lfsr_12.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_12 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(11 downto 0)
);
end entity lfsr_12;
 
 
architecture MyHDL of lfsr_12 is
 
 
constant tap_const__val: integer := 3232;
 
 
 
signal reg_internal: unsigned(11 downto 0);
 
begin
 
 
 
 
 
LFSR_12_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(675, 12);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 12));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_12_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_128.vhd
0,0 → 1,53
-- File: generated/lfsr_128.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_128 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(127 downto 0)
);
end entity lfsr_128;
 
 
architecture MyHDL of lfsr_128 is
 
 
 
 
 
signal reg_internal: unsigned(127 downto 0);
 
begin
 
 
 
 
 
LFSR_128_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00100111011001101010111000000101110001011101111100011001000011011110011111000010011110110101001101010010111110010000001111111010";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("11100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_128_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_129.vhd
0,0 → 1,53
-- File: generated/lfsr_129.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_129 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(128 downto 0)
);
end entity lfsr_129;
 
 
architecture MyHDL of lfsr_129 is
 
 
 
 
 
signal reg_internal: unsigned(128 downto 0);
 
begin
 
 
 
 
 
LFSR_129_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"000110100001011010010101001101110100000111000111100010101011000110011001001110110111000010010001010001000011010100111010101100101";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_129_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_16.vhd
0,0 → 1,54
-- File: generated/lfsr_16.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_16 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(15 downto 0)
);
end entity lfsr_16;
 
 
architecture MyHDL of lfsr_16 is
 
 
constant tap_const__val: integer := 46080;
 
 
 
signal reg_internal: unsigned(15 downto 0);
 
begin
 
 
 
 
 
LFSR_16_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(10566, 16);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 16));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_16_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_17.vhd
0,0 → 1,54
-- File: generated/lfsr_17.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_17 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(16 downto 0)
);
end entity lfsr_17;
 
 
architecture MyHDL of lfsr_17 is
 
 
constant tap_const__val: integer := 73728;
 
 
 
signal reg_internal: unsigned(16 downto 0);
 
begin
 
 
 
 
 
LFSR_17_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(3728, 17);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 17));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_17_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_2.vhd
0,0 → 1,54
-- File: generated/lfsr_2.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_2 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(1 downto 0)
);
end entity lfsr_2;
 
 
architecture MyHDL of lfsr_2 is
 
 
constant tap_const__val: integer := 3;
 
 
 
signal reg_internal: unsigned(1 downto 0);
 
begin
 
 
 
 
 
LFSR_2_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(1, 2);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 2));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_2_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_2048.vhd
0,0 → 1,53
-- File: generated/lfsr_2048.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_2048 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(2047 downto 0)
);
end entity lfsr_2048;
 
 
architecture MyHDL of lfsr_2048 is
 
 
 
 
 
signal reg_internal: unsigned(2047 downto 0);
 
begin
 
 
 
 
 
LFSR_2048_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00010110110110011001111110000111000110000001111101110011011100100001001011110001001011000000111010110100110001001100101100100100110000111110011111111001000011010011000100101001101001101000101011100000110011010011011010111111000100101100100101011001001101110100110100100010110110101110011101011010111010111001111111110101110000100110100101110101011101101011111111011000011100101100111100100000100101000010001000010000110111111001110111000001110100010001001111111101011111101101110000000111000100101011010000101110110111001100111100011111110011000011111100101001111100110100110100111011101010011001000011101100010001101101011101011111011000100001100010011000010101010101110100101111101011000111101101101110011101110101001001010010001100000100110100000110100000101001100101011101010011001110101001100000000101011000011101101110110110110100000110101010001111110010000011111101010010110001001101111000001111011011001111010000000000110001101101100110010101001101100110001110100000000111001110111110010000101110010011100111000100100111010100111100000111111100110011110101100111100011000010000111000001010111010011001011110001010011111011101101101001100111110011011011011010111100111000111101111010101011111000111001110101110110110011111111011010100111101011001100110001010111000111000011110010011101000010001111111111000100101111101101110101111101010011110001100011100101010001110011011000010110110010110001011010011100001110010010111010101111110100011111111000011100101100000011110010100011111110001111010010010100101100101010111100100011011100100111010111000111001100110011110011011100011010111000011001010100000101110101000111100010011101111000111011000000100001000000010110011011110101100011011001111110100001111000011101110000101111001000010111010010001011110101101010100000010111110111011110100111011010111110001100011111111010110011001000111011111000100101100111101111000111010011010100000010111011011000010101000001110100111110110010011100101100010101111011001000001111100000111001110100000000011111011110111110110101010110101000000011101111101101";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10000000000001100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_2048_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_24.vhd
0,0 → 1,54
-- File: generated/lfsr_24.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_24 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(23 downto 0)
);
end entity lfsr_24;
 
 
architecture MyHDL of lfsr_24 is
 
 
constant tap_const__val: integer := 14155776;
 
 
 
signal reg_internal: unsigned(23 downto 0);
 
begin
 
 
 
 
 
LFSR_24_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(1992386, 24);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 24));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_24_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_256.vhd
0,0 → 1,53
-- File: generated/lfsr_256.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_256 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(255 downto 0)
);
end entity lfsr_256;
 
 
architecture MyHDL of lfsr_256 is
 
 
 
 
 
signal reg_internal: unsigned(255 downto 0);
 
begin
 
 
 
 
 
LFSR_256_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0011111000011111111101011111001101001110110101011000110001110111110000011100011001110100010010010110101000111010010101000000101000011001000101101100111010001101001001111000101111001011101000001100100100111111100100010001100101101111110111000011101111100000";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1010010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_256_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_257.vhd
0,0 → 1,53
-- File: generated/lfsr_257.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_257 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(256 downto 0)
);
end entity lfsr_257;
 
 
architecture MyHDL of lfsr_257 is
 
 
 
 
 
signal reg_internal: unsigned(256 downto 0);
 
begin
 
 
 
 
 
LFSR_257_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00111111011010001001010011100011010011110101110001111101010011101110011101110111010011001110110110100011111100010010110101100110010101000101111100011101110101110001101011110111001000110001110111010100110010011100011110010011001101010011010100011110010110000";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_257_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_29.vhd
0,0 → 1,54
-- File: generated/lfsr_29.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_29 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(28 downto 0)
);
end entity lfsr_29;
 
 
architecture MyHDL of lfsr_29 is
 
 
constant tap_const__val: integer := 335544320;
 
 
 
signal reg_internal: unsigned(28 downto 0);
 
begin
 
 
 
 
 
LFSR_29_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(128420263, 29);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 29));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_29_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_3.vhd
0,0 → 1,54
-- File: generated/lfsr_3.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_3 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(2 downto 0)
);
end entity lfsr_3;
 
 
architecture MyHDL of lfsr_3 is
 
 
constant tap_const__val: integer := 6;
 
 
 
signal reg_internal: unsigned(2 downto 0);
 
begin
 
 
 
 
 
LFSR_3_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(2, 3);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 3));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_3_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_31.vhd
0,0 → 1,54
-- File: generated/lfsr_31.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_31 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(30 downto 0)
);
end entity lfsr_31;
 
 
architecture MyHDL of lfsr_31 is
 
 
constant tap_const__val: integer := 1207959552;
 
 
 
signal reg_internal: unsigned(30 downto 0);
 
begin
 
 
 
 
 
LFSR_31_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(7804784, 31);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 31));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_31_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_32.vhd
0,0 → 1,53
-- File: generated/lfsr_32.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_32 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(31 downto 0)
);
end entity lfsr_32;
 
 
architecture MyHDL of lfsr_32 is
 
 
 
 
 
signal reg_internal: unsigned(31 downto 0);
 
begin
 
 
 
 
 
LFSR_32_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(120947654, 32);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10100011000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_32_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_33.vhd
0,0 → 1,53
-- File: generated/lfsr_33.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_33 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(32 downto 0)
);
end entity lfsr_33;
 
 
architecture MyHDL of lfsr_33 is
 
 
 
 
 
signal reg_internal: unsigned(32 downto 0);
 
begin
 
 
 
 
 
LFSR_33_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(781674530, 33);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000000000010000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_33_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_37.vhd
0,0 → 1,53
-- File: generated/lfsr_37.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_37 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(36 downto 0)
);
end entity lfsr_37;
 
 
architecture MyHDL of lfsr_37 is
 
 
 
 
 
signal reg_internal: unsigned(36 downto 0);
 
begin
 
 
 
 
 
LFSR_37_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0010101000011111100110111001110110001";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1100101000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_37_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_384.vhd
0,0 → 1,53
-- File: generated/lfsr_384.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_384 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(383 downto 0)
);
end entity lfsr_384;
 
 
architecture MyHDL of lfsr_384 is
 
 
 
 
 
signal reg_internal: unsigned(383 downto 0);
 
begin
 
 
 
 
 
LFSR_384_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"001100011111001101101111110100001001110101011011011111110010111001100100110100011101100010000000100111101011010110100101011100101110001100110101100011101010000100010100110000010010010001011101011010010111110101000010000101010111101110101101010011101110100100000101010101010011111111001011011111001001011100010100101111100111001101110110010001110101111110111100011001111111101111101111";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000100000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_384_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_4.vhd
0,0 → 1,54
-- File: generated/lfsr_4.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_4 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(3 downto 0)
);
end entity lfsr_4;
 
 
architecture MyHDL of lfsr_4 is
 
 
constant tap_const__val: integer := 12;
 
 
 
signal reg_internal: unsigned(3 downto 0);
 
begin
 
 
 
 
 
LFSR_4_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(3, 4);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 4));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_4_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_4096.vhd
0,0 → 1,53
-- File: generated/lfsr_4096.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_4096 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(4095 downto 0)
);
end entity lfsr_4096;
 
 
architecture MyHDL of lfsr_4096 is
 
 
 
 
 
signal reg_internal: unsigned(4095 downto 0);
 
begin
 
 
 
 
 
LFSR_4096_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0011111001011010101111011011000000010011001011010011101110001111110011010011110010111000110110101100101010111000100001111100110011101111100110110011010101010001010111011101100000011101010011100001101011101111111101010011110010011010101100110010010011011010010101011010110001000010000100111010000100100110110100110011110101000101010101100101110100011110001011000111011110001110101110111010100010001001110000001111010001100001001010001111111000110101110010110110010100100100100001001011010110100111001010010010111011000111010011110101000001111011010011100100011110110011000101111001101111000110010011100100110111001110001011111110101000110011011100111111011110110010011011110101010100001100110110111111000000010000100100110000101110111011000011001010101010101000001011001111101001100111000000101001001010011000101111101101100110011100010101000011100100100001111011000101110010100100111011011010000010000010011100111101000101110000101101110000011111010011110100101110001110001100110001110000101110100100000101110001111011100110101100001001100111101010001000010001001010000101111110011101001101010011010101011001010001110010011010111111100111100100110010110011101101110001111111010000101011000011111101000111100111111001101100100000011001110100011010000010101110011000110010010001111001111101100010011001011110111010011001100110011110111011100000000110110010101100111010101100000100110100110000010111111101000010010001110110100101111010000010011101111011010101011001011010010011111101110000101111111110100110111101101001111111001101000110101001110001110010010001100010001101000111110111010101110011101011011110000001011101000110101101010101111010000101100100001100110100001000010011001110001011111001110110101000100110010100010010110001101010101001110111101000011101011010111101111111010100111101100011000011001000110001000000010011011010000000010110110001101001100101000101010101111010000111001010100001001011010001110110010000111110111110000111110100010011100010010011101100100110010111011110101010010010100001001101001111010111010111100101101001101101010110111000101000001000110101101110101101000100010011110000010110001100101101101010001010010011011010110000111010000100111010011010100001010011001010111000110001101111101010000010111010101110010011100011100000110001011010100101111010111011101011100010100100000000011101110111111100110101100100100011001000101000011011100010111111010100100010100010001110011101011101011110000110100011101000001010100001010110110011111101000111011011011010011010111100100101111111110010010001100101011110000111110011110101000011010011001101000100011011100000011110011000110001010101000001101000011000011101101101010110000110010000110011010101001001011000100000010111111000000010011101010111111100001010010100100010110010111101000111011000111001011110110000000011111110110100000001100101111100000110110001100010101000100101011001011000011010010001011000011000100010110010110010100100011011101100010010111110000000000101000101011100000100111011011110110010011000000100010101001001110010000010111110001110001101100000101110001011100111010011010100011101100101110010001010001011001110010011001000010000110110011110100111010101100110001110000011101100001110010010101111010010100100010000110101011100001011010010101010110111001100001100001111010000110101100001001100000000101100111101010000010000010111001101001110100010011000001101010011101111001101100100110011000111110000011000110101100000111011011110100011000111100100110001111111110111100010100101110000010100001000010111010110011011010010111001100110010010101100110111011110010001011110001101100100111001110101010010101001100001100010001111011010011100111111000010111010100111110000010101101100000000000011011111010111001010010010000001100110110001100111111101000100010000100110010011011000110001100010011010110100110011110011000010011000101100100111110111011011000001011000110111011011010010101111101110010001111010000001010110000111101011111110100111100100000110100110011110110101100100001010010100010000100011101101110010101111111011000101001001100011100010011010100000101000000111001001100101110111111000111010";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1100000000000001000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_4096_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_43.vhd
0,0 → 1,53
-- File: generated/lfsr_43.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_43 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(42 downto 0)
);
end entity lfsr_43;
 
 
architecture MyHDL of lfsr_43 is
 
 
 
 
 
signal reg_internal: unsigned(42 downto 0);
 
begin
 
 
 
 
 
LFSR_43_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0010111100101000010100010100000111101010000";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1100011000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_43_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_47.vhd
0,0 → 1,53
-- File: generated/lfsr_47.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_47 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(46 downto 0)
);
end entity lfsr_47;
 
 
architecture MyHDL of lfsr_47 is
 
 
 
 
 
signal reg_internal: unsigned(46 downto 0);
 
begin
 
 
 
 
 
LFSR_47_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00010011111110010000110001010010101111110111000";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10000100000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_47_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_512.vhd
0,0 → 1,53
-- File: generated/lfsr_512.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_512 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(511 downto 0)
);
end entity lfsr_512;
 
 
architecture MyHDL of lfsr_512 is
 
 
 
 
 
signal reg_internal: unsigned(511 downto 0);
 
begin
 
 
 
 
 
LFSR_512_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00101010110110000010001111101100010011010110111101101000111000111100100100010010010011101110010100110001100111010101110101100100100110000111101000000101110001101001011010101001010011011111100011101010100011110111111110111010001001000100010000000111001111111111101100111110000011010110101111111100010101000110110001100000101000011100010010101011110101011100110011010010111100010010001100110000000011011011011010100000111100010100011100100110110100010000100000101001101100010110111100000010001000010110001001010001";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_512_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_513.vhd
0,0 → 1,53
-- File: generated/lfsr_513.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_513 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(512 downto 0)
);
end entity lfsr_513;
 
 
architecture MyHDL of lfsr_513 is
 
 
 
 
 
signal reg_internal: unsigned(512 downto 0);
 
begin
 
 
 
 
 
LFSR_513_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"000111001001101111000110110000101111001101110001101011000000100111000100000110000000101001011000100100100111111101100000010010110101001010111000111010110110010110011011010111111010010001001011100100010110011101101111010000100001010101100010101100011111101100011010100011101001101001100010010100100011000000000000110111000111110100000111000010001101110100011100010011001111101000101101100111000000010010110000000010010001101000100000100010010100000110001111110111101011111001111100101010100110110001001111101001011";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_513_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_53.vhd
0,0 → 1,53
-- File: generated/lfsr_53.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_53 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(52 downto 0)
);
end entity lfsr_53;
 
 
architecture MyHDL of lfsr_53 is
 
 
 
 
 
signal reg_internal: unsigned(52 downto 0);
 
begin
 
 
 
 
 
LFSR_53_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00000110101011101111000001000011001011000000101100001";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("11100010000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_53_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_64.vhd
0,0 → 1,53
-- File: generated/lfsr_64.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_64 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(63 downto 0)
);
end entity lfsr_64;
 
 
architecture MyHDL of lfsr_64 is
 
 
 
 
 
signal reg_internal: unsigned(63 downto 0);
 
begin
 
 
 
 
 
LFSR_64_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"0010111101101010100000001011101111100101010110001010100011100101";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1101100000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_64_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_65.vhd
0,0 → 1,53
-- File: generated/lfsr_65.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_65 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(64 downto 0)
);
end entity lfsr_65;
 
 
architecture MyHDL of lfsr_65 is
 
 
 
 
 
signal reg_internal: unsigned(64 downto 0);
 
begin
 
 
 
 
 
LFSR_65_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"00110101100000010010100110101100101101011011011101111010001011101";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10000000000000000010000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_65_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_768.vhd
0,0 → 1,53
-- File: generated/lfsr_768.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_768 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(767 downto 0)
);
end entity lfsr_768;
 
 
architecture MyHDL of lfsr_768 is
 
 
 
 
 
signal reg_internal: unsigned(767 downto 0);
 
begin
 
 
 
 
 
LFSR_768_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"000111010100001110100000101001100101100100010101001001010000110011010101001111011110101110111000011110011100101100001000100100101101111111000101101100111011100011110001101000100011110101010001111011010011101100011101100110101111100110111111001000001011110000001111010100010101001101011111101010110011001011100100111111001110001000101000001010000010111011000010011001110110110111011000110100101010011011010110101101111010010011110011011110100100010000000110010000010101011000011011110000000011011010110010001101001001111100001111110001001000010000000111011001010000110111000001010011111011011101010011110111000010101101001110010111010010011100100001110100101101000101011000011001010101110111010000001000010010101010111010000101001110000011010111010010010111101111111001";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100010000000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_768_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_8.vhd
0,0 → 1,54
-- File: generated/lfsr_8.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_8 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(7 downto 0)
);
end entity lfsr_8;
 
 
architecture MyHDL of lfsr_8 is
 
 
constant tap_const__val: integer := 184;
 
 
 
signal reg_internal: unsigned(7 downto 0);
 
begin
 
 
 
 
 
LFSR_8_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(1, 8);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 8));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_8_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_9.vhd
0,0 → 1,54
-- File: generated/lfsr_9.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_9 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(8 downto 0)
);
end entity lfsr_9;
 
 
architecture MyHDL of lfsr_9 is
 
 
constant tap_const__val: integer := 272;
 
 
 
signal reg_internal: unsigned(8 downto 0);
 
begin
 
 
 
 
 
LFSR_9_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= to_unsigned(53, 9);
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 9));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_9_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/lfsr_96.vhd
0,0 → 1,53
-- File: generated/lfsr_96.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_96 is
port (
reset: in std_logic;
clock: in std_logic;
lfsr_out: out unsigned(95 downto 0)
);
end entity lfsr_96;
 
 
architecture MyHDL of lfsr_96 is
 
 
 
 
 
signal reg_internal: unsigned(95 downto 0);
 
begin
 
 
 
 
 
LFSR_96_LFSR_LOGIC: process (clock, reset) is
begin
if (reset = '1') then
reg_internal <= unsigned'"000011010100110111100110010010001001100111101001101111110001011101101001110010111110111110001101";
elsif rising_edge(clock) then
if (reg_internal(0) = '1') then
reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
else
reg_internal <= shift_right(reg_internal, 1);
end if;
end if;
end process LFSR_96_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;
/myhdl_lfsr/trunk/sample_modules/VHDL/pck_myhdl_090.vhd
0,0 → 1,141
-- File: generated/pck_myhdl_090.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package pck_myhdl_090 is
 
attribute enum_encoding: string;
 
function stdl (arg: boolean) return std_logic;
 
function stdl (arg: integer) return std_logic;
 
function to_unsigned (arg: boolean; size: natural) return unsigned;
 
function to_signed (arg: boolean; size: natural) return signed;
 
function to_integer(arg: boolean) return integer;
 
function to_integer(arg: std_logic) return integer;
 
function to_unsigned (arg: std_logic; size: natural) return unsigned;
 
function to_signed (arg: std_logic; size: natural) return signed;
 
function bool (arg: std_logic) return boolean;
 
function bool (arg: unsigned) return boolean;
 
function bool (arg: signed) return boolean;
 
function bool (arg: integer) return boolean;
 
function "-" (arg: unsigned) return signed;
 
end pck_myhdl_090;
 
 
package body pck_myhdl_090 is
 
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
 
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
 
 
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
 
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
 
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
 
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
 
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
 
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
 
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
 
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
 
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
 
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
 
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
 
end pck_myhdl_090;
 
 
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_101.v
0,0 → 1,44
// File: generated/lfsr_101.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_101 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [100:0] out;
wire [100:0] out;
 
reg [100:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_101_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 587119219393369496968319599319;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 102'h18600000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_1024.v
0,0 → 1,44
// File: generated/lfsr_1024.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_1024 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [1023:0] out;
wire [1023:0] out;
 
reg [1023:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_1024_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 42082963438100842300011049632051513817286471381842424552588007902956694699216501563006494012496102355182406742128207496350734846251097969585360161454465559354154952828254567238737101599975418053047520322724235803065707102362869726195382228521523577556400186749615420832071378999503677442075829106239445563864;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 1025'h8040030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_12.v
0,0 → 1,44
// File: generated/lfsr_12.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_12 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [11:0] out;
wire [11:0] out;
 
reg [11:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_12_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 648;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 3232);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_128.v
0,0 → 1,44
// File: generated/lfsr_128.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_128 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [127:0] out;
wire [127:0] out;
 
reg [127:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_128_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 2898653946643625351297728272954579695;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 129'he1000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_129.v
0,0 → 1,44
// File: generated/lfsr_129.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_129 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [128:0] out;
wire [128:0] out;
 
reg [128:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_129_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 165771121328680894633511164402659574323;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 130'h108000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_16.v
0,0 → 1,44
// File: generated/lfsr_16.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_16 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [15:0] out;
wire [15:0] out;
 
reg [15:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_16_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 11765;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 46080);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_17.v
0,0 → 1,44
// File: generated/lfsr_17.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_17 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [16:0] out;
wire [16:0] out;
 
reg [16:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_17_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 11809;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 73728);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_2.v
0,0 → 1,44
// File: generated/lfsr_2.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_2 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [1:0] out;
wire [1:0] out;
 
reg [1:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_2_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 1;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 3);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_2048.v
0,0 → 1,44
// File: generated/lfsr_2048.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_2048 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [2047:0] out;
wire [2047:0] out;
 
reg [2047:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_2048_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 4246303789197548419185331987884540241389690098851414570675662745781788376768218864091557228342545852312810921124374667816852071497415220662108940562606332129909088463132885617274827012666521923582589600019829203454982095316269005018840235561887595280821654943773127825444913399239780432860703411839276679845735014013595924414195661025803497016865846613457839769104970817763974812015000598779692274272537226680742217527423882241542527888741595525040787476180701937094956572320251336475274772080315091155242806545112268637217216112977577772428192477014418382616962022175213167929655414095213294385845358744036379213820;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 2049'h80061000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_24.v
0,0 → 1,44
// File: generated/lfsr_24.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_24 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [23:0] out;
wire [23:0] out;
 
reg [23:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_24_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 3598147;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 14155776);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_256.v
0,0 → 1,44
// File: generated/lfsr_256.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_256 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [255:0] out;
wire [255:0] out;
 
reg [255:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_256_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 28143940933193749181955580878590174672837980096333821816012878967838641862250;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 257'ha420000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_257.v
0,0 → 1,44
// File: generated/lfsr_257.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_257 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [256:0] out;
wire [256:0] out;
 
reg [256:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_257_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 34678417597797179036570999341121534142151777972778728750797392528134662177427;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 258'h10010000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_29.v
0,0 → 1,44
// File: generated/lfsr_29.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_29 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [28:0] out;
wire [28:0] out;
 
reg [28:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_29_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 28997123;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 335544320);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_3.v
0,0 → 1,44
// File: generated/lfsr_3.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_3 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [2:0] out;
wire [2:0] out;
 
reg [2:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_3_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 2;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 6);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_31.v
0,0 → 1,44
// File: generated/lfsr_31.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_31 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [30:0] out;
wire [30:0] out;
 
reg [30:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_31_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 97699955;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 32'h48000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_32.v
0,0 → 1,44
// File: generated/lfsr_32.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_32 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [31:0] out;
wire [31:0] out;
 
reg [31:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_32_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 448929031;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 33'ha3000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_33.v
0,0 → 1,44
// File: generated/lfsr_33.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_33 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [32:0] out;
wire [32:0] out;
 
reg [32:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_33_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 1635071911;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 34'h100080000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_37.v
0,0 → 1,44
// File: generated/lfsr_37.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_37 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [36:0] out;
wire [36:0] out;
 
reg [36:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_37_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 4656803065;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 38'h1940000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_384.v
0,0 → 1,44
// File: generated/lfsr_384.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_384 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [383:0] out;
wire [383:0] out;
 
reg [383:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_384_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 2789258607346811508456138996505545746202102847997008145211868079990975134213712168816262838142949145765954712862718;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 385'h820180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_4.v
0,0 → 1,44
// File: generated/lfsr_4.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_4 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [3:0] out;
wire [3:0] out;
 
reg [3:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_4_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 2;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 12);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_4096.v
0,0 → 1,44
// File: generated/lfsr_4096.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_4096 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [4095:0] out;
wire [4095:0] out;
 
reg [4095:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_4096_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 19786675161995628253053705232380800434658328903343356998292168946225953300793428037302970239001677760674830651775720458054924624113772218183597842481803550241221926201302051357077082169684001162000391542241713558530993325110715578585056220014798535858831872320095339866102555545012563632419484678645827097610425793979077131047660127312937281104500077807400960953413761879297939986522597775734007944684446896806698610758088994121516152549551975816142446460287852052016035382610259674715296505118815256954008561537059435924191829957392653292735338793775825348571169542109110173815608076120516909416398007952657252748545884559225008708594565784888961800976910565684568840941403243854182355510625433409614815199672747427886477123407500490862234637255616250719756581490124585186324009961029669131193616236195521612407385558794986320847153744737470135592555900835390768869135014476170916738105711106594640827051502097149231471123450163917466463380125013674989973162313737068543138214243648049567522900487996882361768751528902372004869252628217941089295340413103832318139955702514974410255599983651884659567565662772007619911691847074985021593970569804605713114183957218309344702586742095663603213115685142237419519413524260476513654747525;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 4097'hc001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_43.v
0,0 → 1,44
// File: generated/lfsr_43.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_43 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [42:0] out;
wire [42:0] out;
 
reg [42:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_43_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 1744831545637;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 44'h63000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_47.v
0,0 → 1,44
// File: generated/lfsr_47.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_47 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [46:0] out;
wire [46:0] out;
 
reg [46:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_47_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 23173814600026;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 48'h420000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_512.v
0,0 → 1,44
// File: generated/lfsr_512.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_512 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [511:0] out;
wire [511:0] out;
 
reg [511:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_512_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 1077464999328904514268994939791857112907323971295498971432741416055282860267721700160839252331050492744467747950578919719063147178890486843751567300024824;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 513'ha4800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_513.v
0,0 → 1,44
// File: generated/lfsr_513.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_513 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [512:0] out;
wire [512:0] out;
 
reg [512:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_513_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 3083268499313128972540140338587670786118869819889307359452932521473045760757004826593814056464993797010481499347298095949174773122340895422833688772174454;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 513'h100000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_53.v
0,0 → 1,44
// File: generated/lfsr_53.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_53 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [52:0] out;
wire [52:0] out;
 
reg [52:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_53_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 465079130429073;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 54'h1c400000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_64.v
0,0 → 1,44
// File: generated/lfsr_64.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_64 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [63:0] out;
wire [63:0] out;
 
reg [63:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_64_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 3737405319821307317;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 65'hd800000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_65.v
0,0 → 1,44
// File: generated/lfsr_65.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_65 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [64:0] out;
wire [64:0] out;
 
reg [64:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_65_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 7530551304113312932;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 66'h10000400000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_768.v
0,0 → 1,44
// File: generated/lfsr_768.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_768 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [767:0] out;
wire [767:0] out;
 
reg [767:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_768_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 291143584868681772471303593185392365086698651189288315740359449674211451644149266507835960236242873226233363457348348077181486946179549007244965206177640157865466997687371991268069128700722368070295529878987798774955141357885005915;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 769'h880050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_8.v
0,0 → 1,44
// File: generated/lfsr_8.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_8 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [7:0] out;
wire [7:0] out;
 
reg [7:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_8_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 30;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 184);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_9.v
0,0 → 1,44
// File: generated/lfsr_9.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_9 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [8:0] out;
wire [8:0] out;
 
reg [8:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_9_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 16;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 272);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/lfsr_96.v
0,0 → 1,44
// File: generated/lfsr_96.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_96 (
reset,
clock,
out
);
 
 
input reset;
input clock;
output [95:0] out;
wire [95:0] out;
 
reg [95:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_96_LFSR_LOGIC
if (reset == 1) begin
reg_internal <= 1591560094523176942740114271;
end
else begin
if ((reg_internal[0] == 1)) begin
reg_internal <= ((reg_internal >>> 1) ^ 97'h826000000000000000000000);
end
else begin
reg_internal <= (reg_internal >>> 1);
end
end
end
 
 
 
assign out = reg_internal;
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_101.v
0,0 → 1,23
module tb_lfsr_101;
 
reg reset;
reg clock;
wire [100:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_101 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_1024.v
0,0 → 1,23
module tb_lfsr_1024;
 
reg reset;
reg clock;
wire [1023:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_1024 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_12.v
0,0 → 1,23
module tb_lfsr_12;
 
reg reset;
reg clock;
wire [11:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_12 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_128.v
0,0 → 1,23
module tb_lfsr_128;
 
reg reset;
reg clock;
wire [127:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_128 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_129.v
0,0 → 1,23
module tb_lfsr_129;
 
reg reset;
reg clock;
wire [128:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_129 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_16.v
0,0 → 1,23
module tb_lfsr_16;
 
reg reset;
reg clock;
wire [15:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_16 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_17.v
0,0 → 1,23
module tb_lfsr_17;
 
reg reset;
reg clock;
wire [16:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_17 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_2.v
0,0 → 1,23
module tb_lfsr_2;
 
reg reset;
reg clock;
wire [1:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_2 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_2048.v
0,0 → 1,23
module tb_lfsr_2048;
 
reg reset;
reg clock;
wire [2047:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_2048 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_24.v
0,0 → 1,23
module tb_lfsr_24;
 
reg reset;
reg clock;
wire [23:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_24 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_256.v
0,0 → 1,23
module tb_lfsr_256;
 
reg reset;
reg clock;
wire [255:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_256 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_257.v
0,0 → 1,23
module tb_lfsr_257;
 
reg reset;
reg clock;
wire [256:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_257 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_29.v
0,0 → 1,23
module tb_lfsr_29;
 
reg reset;
reg clock;
wire [28:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_29 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_3.v
0,0 → 1,23
module tb_lfsr_3;
 
reg reset;
reg clock;
wire [2:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_3 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_31.v
0,0 → 1,23
module tb_lfsr_31;
 
reg reset;
reg clock;
wire [30:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_31 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_32.v
0,0 → 1,23
module tb_lfsr_32;
 
reg reset;
reg clock;
wire [31:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_32 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_33.v
0,0 → 1,23
module tb_lfsr_33;
 
reg reset;
reg clock;
wire [32:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_33 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_37.v
0,0 → 1,23
module tb_lfsr_37;
 
reg reset;
reg clock;
wire [36:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_37 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_384.v
0,0 → 1,23
module tb_lfsr_384;
 
reg reset;
reg clock;
wire [383:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_384 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_4.v
0,0 → 1,23
module tb_lfsr_4;
 
reg reset;
reg clock;
wire [3:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_4 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_4096.v
0,0 → 1,23
module tb_lfsr_4096;
 
reg reset;
reg clock;
wire [4095:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_4096 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_43.v
0,0 → 1,23
module tb_lfsr_43;
 
reg reset;
reg clock;
wire [42:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_43 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_47.v
0,0 → 1,23
module tb_lfsr_47;
 
reg reset;
reg clock;
wire [46:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_47 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_512.v
0,0 → 1,23
module tb_lfsr_512;
 
reg reset;
reg clock;
wire [511:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_512 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_513.v
0,0 → 1,23
module tb_lfsr_513;
 
reg reset;
reg clock;
wire [512:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_513 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_53.v
0,0 → 1,23
module tb_lfsr_53;
 
reg reset;
reg clock;
wire [52:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_53 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_64.v
0,0 → 1,23
module tb_lfsr_64;
 
reg reset;
reg clock;
wire [63:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_64 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_65.v
0,0 → 1,23
module tb_lfsr_65;
 
reg reset;
reg clock;
wire [64:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_65 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_768.v
0,0 → 1,23
module tb_lfsr_768;
 
reg reset;
reg clock;
wire [767:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_768 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_8.v
0,0 → 1,23
module tb_lfsr_8;
 
reg reset;
reg clock;
wire [7:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_8 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_9.v
0,0 → 1,23
module tb_lfsr_9;
 
reg reset;
reg clock;
wire [8:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_9 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/sample_modules/verilog/tb_lfsr_96.v
0,0 → 1,23
module tb_lfsr_96;
 
reg reset;
reg clock;
wire [95:0] out;
 
initial begin
$from_myhdl(
reset,
clock
);
$to_myhdl(
out
);
end
 
lfsr_96 dut(
reset,
clock,
out
);
 
endmodule
/myhdl_lfsr/trunk/Readme.txt
0,0 → 1,14
This project contains code which may be used to generate a synthesizable Verilog or VHDL module representing a Galois LFSR of a user-specified width.
 
Max-cycle tap positions are included for some selected register widths. These positions can be credited to Roy Ward and Tim Molteno, whose table of tap positions is currently available at http://courses.cse.tamu.edu/walker/csce680/lfsr_table.pdf
 
Tap positions may be added and modified by editing lfsr_tap_table.py
 
Sample LFSR modules are made available in the sample_modules/ directory.
 
To use:
MyHDL must be available to your python installation. Instructions are available at http://myhdl.org/start/installation.html
 
A module may be generated by running lfsr_gen.py.
 
In its current state, lfsr_gen.py will generate an LFSR module for each width available in the tap table. Generated LFSRs will have a randomized but constant starting value. Efforts are planned to make this a bit more customizable from an end-user perspective, but users familiar with python should find it easy to make any necessary modifications.
/myhdl_lfsr/trunk/lfsr_gen.py
0,0 → 1,73
from myhdl import *
from lfsr_tap_table import *
from lfsr_logic import *
import random
 
#Author: Shawn Rainey
# rainey.shawn@gmail.com
 
def lfsr_export(exportfn=toVerilog, directory=".", width=32, init_value=1):
 
reset = ResetSignal(0, active=1, async=True)
clock = Signal(bool(0))
word_sig = Signal(modbv(0)[width:])
 
lfsr_mod = get_lfsr(width, init_value)
 
exportfn.name = "lfsr_" + str(width)
exportfn.directory = directory
exportfn(lfsr_mod, reset, clock, word_sig)
 
def lfsr_sim(clocks, width=32, init_value = 1):
 
lfsr_mod = get_lfsr(width, init_value)
 
def lfsr_tb():
reset = ResetSignal(0, active=1, async=True)
clock = Signal(bool(0))
word_sig = Signal(modbv(0)[width:])
 
lfsr_inst = lfsr_mod(reset, clock, word_sig)
 
@always(delay(1))
def clock_toggle():
clock.next = not clock
 
return instances()
 
tb = traceSignals(lfsr_tb)
sim = Simulation(tb)
sim.run(clocks*2)
 
def generate_all_widths():
lfsr_start = 1
for width in lfsr_tap_table:
lfsr_width = width
if lfsr_width > 2:
lfsr_start = random.getrandbits(lfsr_width-2)+1
else:
lfsr_start = 1
 
lfsr_export(toVHDL, "generated", lfsr_width, lfsr_start)
#alternatively: But this has problems with large widths
#lfsr_export(toVHDL, lfsr_width, lfsr_start)
 
 
if __name__ == "__main__":
lfsr_width = 32
 
#start with a pseudo-random number that will fit in our register and be non-zero
lfsr_start = random.getrandbits(lfsr_width-2)+1
#may also start with a non-zero constant:
#lfsr_start = 1
 
 
generate_all_widths()
lfsr_width = 8
lfsr_start = 1
#Generate a simulation with 256 clocks
#lfsr_sim(256, lfsr_width, lfsr_start)
/myhdl_lfsr/trunk/lfsr_logic.py
0,0 → 1,41
from myhdl import *
from lfsr_tap_table import *
import random
 
#Author: Shawn Rainey
# rainey.shawn@gmail.com
 
#init_value must not be 0
def get_lfsr(width=32, init_value=1):
 
if init_value == 0:
raise SystemExit("LFSR May not be instantiated with initial zero value")
 
tap_const = intbv(0)[width:]
 
 
for i in lfsr_tap_table[width]:
tap_const[i-1] = 1
 
def lfsr_module(reset, clock, lfsr_out):
reg_internal = Signal(intbv(init_value)[width:])
 
@always_comb
def assign_out():
lfsr_out.next = reg_internal
 
@always_seq(clock.posedge, reset=reset)
def lfsr_logic():
if reg_internal[0] == 1:
#use of _val here may not be forward or backward compatible
#with other versions of MyHDL
#works with MyHDL 0.9.0
reg_internal.next = (reg_internal >> 1) ^ tap_const._val
else:
reg_internal.next = reg_internal >> 1
 
return instances()
return lfsr_module
 
/myhdl_lfsr/trunk/lfsr_tap_table.py
0,0 → 1,44
#dictionary of width:taps
#taken from table by Roy Ward, Tim Molteno currently available at
#http://courses.cse.tamu.edu/walker/csce680/lfsr_table.pdf
#More taps may be added in this fashion if needed. The table only lists
#2-tap and 4-tap entries, but any number of taps may potentially be
#used provided that they fit the width
 
#Powers of 2 and some prime numbers:
lfsr_tap_table = {
2:[2,1],
3:[3,2],
4:[4,3],
8:[8,6,5,4],
9:[9,5],
12:[12,11,8,6],
16:[16,14,13,11],
17:[17,14],
24:[24,23,21,20],
29:[29,27],
31:[31,28],
32:[32,30,26,25],
33:[33,20],
37:[37,36,33,31],
43:[43,42,38,37],
47:[47,42],
53:[53,52,51,47],
64:[64,63,61,60],
65:[65,47],
96:[96,90,87,86],
101:[101,100,95,94],
128:[128,127,126,121],
129:[129,124],
256:[256,254,251,246],
257:[257,245],
384:[384,378,369,368],
512:[512,510,507,504],
513:[513,428],
768:[768,764,751,749],
1024:[1024,1015,1002,1001],
2048:[2048,2035,2034,2029],
4096:[4096,4095,4081,4069],
}
 
 

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