OpenCores
URL https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk

Subversion Repositories mytwoqcache

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 12 to Rev 13
    ↔ Reverse comparison
  •

Rev 12 → Rev 13

/mytwoqcache/trunk/2QCache.vhd
138,7 → 138,7
signal stateram: rType;
signal statequeue: fType;
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt: std_ulogic;
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
 
begin
204,6 → 204,7
statetag <= inittag;
writet <= '0';
enableram <= '0';
oldint <= '0';
found <= 15;
free <= 15;
done <= '0'; -- NEW
213,6 → 214,7
AddressInh <= ( others => '0');
else
oldint <= interrupt;
case statetag is
when inittag =>
for i in tagRAMIn'range loop
264,7 → 266,7
when tagwait =>
writet <= '0';
if interrupt = '1' then
if interrupt = '1' and oldint = '0' then
enableram <= '0';
AddressInt <= toFlush;
statetag <= stateget;
353,9 → 355,9
lastf <= ( others => '0');
counterf <= ( others => '0');
else
hi := accinterrupt or interrupt;
hi := accinterrupt or (interrupt and not oldint);
acc := accqueue or queuedone;
en := enablequeue and ( hi nor acc);
en := enablequeue and not acc;
if ldCachedWords = 0 then
index := 0;
545,8 → 547,6
when ramflush1 =>
if writesh = '0' then
if del /= 15 and hi = '1' then
doneh <= '1';
en := '1';
hi := '0';
stateram <= ramwait;
else
650,8 → 650,9
removeAm <= '0'; -- NEW
putA1 <= '0'; -- NEW
putAm <= '0'; -- NEW
serviced <= '0';
else
hi := '0';
hi := interrupt;
acc := accdone or doneh;
diff := firstA1 - unsigned( RecBuff.FiFoAddr);
687,7 → 688,7
statequeue <= queuewaitAm1;
end if;
elsif free /= 15 then
if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0') then
if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0' and serviced = '0') then
-- remove last entry from A1
if A1Out.valid = '1' then
del <= to_integer( A1Out.way);
694,9 → 695,10
toFlush <= A1Out.word;
getA1 <= '1';
hi := '1';
serviced <= '1';
statequeue <= queuewait;
end if;
elsif fullAm = '1' and emptyf = '1' then
elsif fullAm = '1' and emptyf = '1' and serviced = '0' then
-- remove last entry from Am
if AmOut.valid = '1' then
del <= to_integer( AmOut.way);
703,6 → 705,7
toFlush <= AmOut.word;
getAm <= '1';
hi := '1';
serviced <= '1';
statequeue <= queuewait;
end if;
else
710,6 → 713,7
A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
A1In.valid <= '1';
putA1 <= '1';
serviced <= '0';
statequeue <= queuewaitA11;
end if;
elsif elim /= 15 then
742,11 → 746,14
removeAm <= '0';
getAm <= '0';
getA1 <= '0';
queuedone <= '0';
if acc = '1' then
if hi = '1' then
hi := '0';
statequeue <= queuestart;
elsif acc = '1' then
acc := '0';
del <= 15;
queuedone <= '0';
statequeue <= queuestart;
end if;
when queuewaitAm1 =>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.