URL
https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk
Subversion Repositories mytwoqcache
Compare Revisions
- This comparison shows the changes necessary to convert path
/mytwoqcache/trunk
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/2QCache.vhd
63,7 → 63,7
|
type IOType is ( Start, busy); |
type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished); |
type rType is ( raminit, ramstart, ramstart1, ramcheck, ramcheck1, ramcheck2, ramread, ramread1, ramupdate, |
type rType is ( raminit, ramstart, ramstart1, ramread, ramread1, ramupdate, |
ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1); |
type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim); |
subtype myint is natural range 15 downto 0; |
139,6 → 139,7
signal statequeue: fType; |
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, |
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic; |
signal gal: std_ulogic_vector( 7 downto 0); |
|
begin |
|
212,8 → 213,9
AddressInt <= ( others => '0'); |
IOCodeh <= ( others => '0'); |
AddressInh <= ( others => '0'); |
gal <= ( others => '1'); |
else |
|
gal <= gal( 6 downto 4) & ( gal( 3) xor gal( 7)) & ( gal( 2) xor gal( 7)) & ( gal( 1) xor gal( 7)) & gal( 0) & gal( 7); |
oldint <= interrupt; |
case statetag is |
when inittag => |
258,6 → 260,12
|
found <= a; |
free <= b; |
|
if ways = 1 then |
elim <= 0; |
else |
elim <= to_integer( gal( ways - 1 downto 0)); |
end if; |
|
if stateram = ramstart then |
enableram <= '1'; |
346,7 → 354,6
getf <= '0'; |
putf <= '0'; -- NEW inserted |
doneh <= '0'; |
elim <= 15; |
accinterrupt <= '0'; |
accqueue <= '0'; |
initcount1 <= ( others => '0'); |
391,24 → 398,10
en := '1'; |
stateram <= ramwait; |
else |
elim <= 0; |
stateram <= ramcheck; |
cindex <= tagBuff( elim).cacheAddr; |
stateram <= ramupdate; |
end if; |
end if; |
when ramcheck => |
cindex <= tagBuff( elim).cacheAddr; |
stateram <= ramcheck1; |
when ramcheck1 => |
stateram <= ramcheck2; |
when ramcheck2 => |
if cacheOut.Am = '0' or elim = ways - 1 then |
RecBuff <= cacheOut; |
en := '1'; |
stateram <= ramwait; |
else |
elim <= elim + 1; |
stateram <= ramcheck; |
end if; |
when ramupdate => |
stateram <= ramupdate1; |
when ramupdate1 => |