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URL https://opencores.org/ocsvn/nand_controller/nand_controller/trunk

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  • This comparison shows the changes necessary to convert path 
    /nand_controller/trunk
    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/Doc/ONFI NAND Controller Avalon MM.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Doc/ONFI NAND Controller Avalon MM.pdf
Doc/ONFI NAND Controller Avalon MM.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: Doc/ONFI NAND Controller Avalon MM.docx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Doc/ONFI NAND Controller Avalon MM.docx =================================================================== --- Doc/ONFI NAND Controller Avalon MM.docx (nonexistent) +++ Doc/ONFI NAND Controller Avalon MM.docx (revision 16)
Doc/ONFI NAND Controller Avalon MM.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: VHDL/onfi_package.vhd =================================================================== --- VHDL/onfi_package.vhd (revision 15) +++ VHDL/onfi_package.vhd (revision 16) @@ -73,7 +73,12 @@ MI_GET_DATA_PAGE_BYTE, -- Gets page_data(page_idx) byte. MI_SET_DATA_PAGE_BYTE, -- Sets value at page_data(page_idx). MI_GET_CURRENT_ADDRESS_BYTE, -- Gets current_address(page_idx) byte. - MI_SET_CURRENT_ADDRESS_BYTE -- Sets value at current_address(page_idx). + MI_SET_CURRENT_ADDRESS_BYTE, -- Sets value at current_address(page_idx). + -- Command processor bypass commands + MI_BYPASS_ADDRESS, -- Send address byte directly to NAND chip + MI_BYPASS_COMMAND, -- Send command byte directly to NAND chip + MI_BYPASS_DATA_WR, -- Send data byte directly to NAND chip + MI_BYPASS_DATA_RD -- Read data byte directly from NAND chip ); type master_substate_t is
/VHDL/nand_master.vhd
146,6 → 146,10
17 => MI_SET_DATA_PAGE_BYTE,
18 => MI_GET_CURRENT_ADDRESS_BYTE,
19 => MI_SET_CURRENT_ADDRESS_BYTE,
20 => MI_BYPASS_ADDRESS,
21 => MI_BYPASS_COMMAND,
22 => MI_BYPASS_DATA_WR,
23 => MI_BYPASS_DATA_RD,
others => M_IDLE
);
249,7 → 253,8
(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND1) or -- initiate submission of READ command
(state = M_NAND_PAGE_PROGRAM and substate = MS_BEGIN) or -- initiate write mode for PAGE PROGRAM command
(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_COMMAND1) or -- initiate submission for PAGE PROGRAM command
(state = M_NAND_READ_ID and substate = MS_BEGIN) else -- initiate submission of READ ID command
(state = M_NAND_READ_ID and substate = MS_BEGIN) or -- initiate submission of READ ID command
(state = MI_BYPASS_COMMAND and substate = MS_BEGIN) else -- direct command byte submission
'0';
-- Activation of address latch unit
257,7 → 262,8
(state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for BLOCK ERASE command
(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ command
(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_ADDRESS) or -- initiate address submission for PAGE PROGRAM command
(state = M_NAND_READ_ID and substate = MS_SUBMIT_COMMAND) else -- initiate address submission for READ ID command
(state = M_NAND_READ_ID and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ ID command
(state = MI_BYPASS_ADDRESS and substate = MS_BEGIN) else -- direct address byte submission
'0';
-- Activation of read byte mechanism
264,11 → 270,13
io_rd_activate <= '1' when (state = M_NAND_READ_PARAM_PAGE and substate = MS_READ_DATA0) or -- initiate byte read for READ PARAMETER PAGE command
(state = M_NAND_READ_STATUS and substate = MS_READ_DATA0) or -- initiate byte read for READ STATUS command
(state = M_NAND_READ and substate = MS_READ_DATA0) or -- initiate byte read for READ command
(state = M_NAND_READ_ID and substate = MS_READ_DATA0) else -- initiate byte read for READ ID command
(state = M_NAND_READ_ID and substate = MS_READ_DATA0) or -- initiate byte read for READ ID command
(state = MI_BYPASS_DATA_RD and substate = MS_BEGIN) else -- reading byte directly from the chip
'0';
-- Activation of write byte mechanism
io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) else -- initiate byte write for PAGE_PROGRAM command
io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) or -- initiate byte write for PAGE_PROGRAM command
(state = MI_BYPASS_DATA_WR and substate = MS_WRITE_DATA0) else
'0';
MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)
546,6 → 554,7
elsif(substate = MS_SUBMIT_COMMAND1)then
cle_data_in <= x"0030";
-- delay <= t_wb;
substate <= MS_DELAY;
state <= M_WAIT;
n_state <= M_NAND_READ;
561,6 → 570,7
elsif(substate = MS_READ_DATA0)then
byte_count <= byte_count + 1;
n_state <= M_NAND_READ;
delay <= t_rr;
state <= M_WAIT;
substate <= MS_READ_DATA1;
756,16 → 766,30
status(1) <= page_param(6)(0);
-- Setup counters:
-- Number of bytes per page
tmp_int := page_param(83)&page_param(82)&page_param(81)&page_param(80);
data_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of spare bytes per page (OOB)
tmp_int := "0000000000000000" & page_param(85) & page_param(84);
oob_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of address cycles
addr_cycles <= to_integer(unsigned(page_param(101)(3 downto 0))) + to_integer(unsigned(page_param(101)(7 downto 4)));
-- Normal FLAsh
if(page_param(63) = x"20")then
-- Number of bytes per page
tmp_int := page_param(83)&page_param(82)&page_param(81)&page_param(80);
data_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of spare bytes per page (OOB)
tmp_int := "0000000000000000" & page_param(85) & page_param(84);
oob_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of address cycles
addr_cycles <= to_integer(unsigned(page_param(101)(3 downto 0))) + to_integer(unsigned(page_param(101)(7 downto 4)));
else
-- Number of bytes per page
tmp_int := page_param(82)&page_param(81)&page_param(80)&page_param(79);
data_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of spare bytes per page (OOB)
tmp_int := "0000000000000000" & page_param(84) & page_param(83);
oob_bytes_per_page <= to_integer(unsigned(tmp_int));
-- Number of address cycles
addr_cycles <= to_integer(unsigned(page_param(100)(3 downto 0))) + to_integer(unsigned(page_param(100)(7 downto 4)));
end if;
end if;
end if;
784,7 → 808,67
else
state <= n_state;
end if;
when MI_BYPASS_ADDRESS =>
if(substate = MS_BEGIN)then
ale_data_in <= x"00"&data_in(7 downto 0);
substate <= MS_SUBMIT_ADDRESS;
state <= M_WAIT;
n_state <= MI_BYPASS_ADDRESS;
elsif(substate = MS_SUBMIT_ADDRESS)then
delay <= t_wb + t_rr;
state <= M_WAIT;--M_DELAY;
n_state <= MI_BYPASS_ADDRESS;
substate <= MS_END;
elsif(substate = MS_END)then
substate <= MS_BEGIN;
state <= M_IDLE;
end if;
when MI_BYPASS_COMMAND =>
if(substate = MS_BEGIN)then
cle_data_in <= x"00"&data_in(7 downto 0);
substate <= MS_SUBMIT_COMMAND;
state <= M_WAIT;
n_state <= MI_BYPASS_COMMAND;
elsif(substate = MS_SUBMIT_COMMAND)then
delay <= t_wb + t_rr;
state <= M_WAIT;--M_DELAY;
n_state <= MI_BYPASS_COMMAND;
substate <= MS_END;
elsif(substate = MS_END)then
substate <= MS_BEGIN;
state <= M_IDLE;
end if;
when MI_BYPASS_DATA_WR =>
if(substate = MS_BEGIN)then
io_wr_data_in(15 downto 0) <= x"00"&data_in(7 downto 0); --page_data(page_idx);
substate <= MS_WRITE_DATA0;
state <= M_WAIT;
n_state <= MI_BYPASS_DATA_WR;
elsif(substate = MS_WRITE_DATA0)then
state <= M_WAIT;
n_state <= M_IDLE;
substate <= MS_BEGIN;
end if;
when MI_BYPASS_DATA_RD =>
if(substate = MS_BEGIN)then
substate <= MS_READ_DATA0;
elsif(substate = MS_READ_DATA0)then
--page_data(page_idx) <= io_rd_data_out(7 downto 0);
data_out(7 downto 0) <= io_rd_data_out(7 downto 0);
substate <= MS_BEGIN;
state <= M_IDLE;
end if;
-- For just in case ("Shit happens..." (C) Forrest Gump)
when others =>
state <= M_RESET;

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