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    /nand_controller/trunk
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/VHDL/nand_interface.vhd
81,10 → 81,21
'1';
-- NAND IO bidirectional "pin"
-- nand_io mapping to NAND device pins:
-- ========================================================================================================================
-- | Bits | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- ========================================================================================================================
-- | x8 | NC | NC | NC | NC | NC | NC | NC | NC | 44 | 43 | 42 | 41 | 32 | 31 | 30 | 29 |
-- ------------------------------------------------------------------------------------------------------------------------
-- | x16 | 47 | 45 | 43 | 41 | 33 | 31 | 29 | 27 | 46 | 44 | 42 | 40 | 32 | 30 | 28 | 26 |
-- ------------------------------------------------------------------------------------------------------------------------
--
-- nand_io and data_tx are muxed accordingly, so that we do not have to deal with this head ache outside this module.
nand_io <= nand_io_tx when nand_oe = '1' and is_x16 = '0' else
nand_io_tx(15)&nand_io_tx(14)&nand_io_tx(11)&nand_io_tx(8)&nand_io_tx(7)&nand_io_tx(4)&nand_io_tx(1)&nand_io_tx(0)&
nand_io_tx(6)&nand_io_tx(13)&nand_io_tx(5)&nand_io_tx(12)&nand_io_tx(3)&nand_io_tx(10)&nand_io_tx(2)&nand_io_tx(9) when nand_oe = '1' and is_x16 = '1'
else "ZZZZZZZZZZZZZZZZ";
data_tx <= nand_io_buffer when is_x16 = '0' else
nand_io_buffer(15)&nand_io_buffer(14)&nand_io_buffer(6)&nand_io_buffer(4)&nand_io_buffer(13)&nand_io_buffer(2)&nand_io_buffer(0)&nand_io_buffer(12)&
nand_io_buffer(11)&nand_io_buffer(7)&nand_io_buffer(5)&nand_io_buffer(10)&nand_io_buffer(3)&nand_io_buffer(1)&nand_io_buffer(9)&nand_io_buffer(8) when is_x16 = '1';

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