OpenCores
URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 169 to Rev 170
    ↔ Reverse comparison
  •

Rev 169 → Rev 170

/neo430/trunk/neo430/README.md
79,6 → 79,7
- Up to 48kB instruction memory and 12kB data memory
- Specific memory map – provided NEO430 linker script and compilation script required
- Custom binary executable format
- No default support of CPU's DADD instruction (btu can be enabled in package)
- Just 4 CPU interrupt channels
- Single clock domain for complete processor
- Different numbers of instruction execution cycles
89,28 → 90,58
 
## Implementation Results
 
Mapping results generated for HW version 0x0300. The full (default) configuration includes
all optional processor modules (excluding the CFU), an IMEM size of 4kB and a DMEM size of 2kB.
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes
all optional processor modules (excluding the CFU and DADD), an IMEM size of 4kB and a DMEM size of 2kB.
Results generated with Xilinx Vivado 2017.3, Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.0 (Synplify)
 
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|:----------------------------------------|:---------:|:--------:|:--------:|:------:|:-------:|
| Full (default) configuration: | 1006 (5%) | 952 (2%) | 2.5 (5%) | 0 (0%) | 100 MHz |
| Minimal configuration (CPU + GPIO): | 879 (4%) | 287 (1%) | 1 (2%) | 0 (0%) | 100 MHz |
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|:----------------------------------------|:----------:|:----------:|:--------:|:------:|:-------:|
| Full (default) configuration: | 941 (4.5%) | 960 (2.3%) | 2.5 (5%) | 0 (0%) | 100 MHz |
| Minimal configuration (CPU + GPIO): | 768 (3.6%) | 288 (0.7%) | 1 (2%) | 0 (0%) | 100 MHz |
 
| __Intel/Altera Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|:--------------------------------------------|:---------:|:--------:|:------------:|:------:|:-------:|
| Full (default) configuration: | 1676 (8%) | 940 (4%) | 65792 (11%) | 0 (0%) | 116 MHz |
| Minimal configuration (CPU + GPIO): | 602 (3%) | 228 (1%) | 49408 (8%) | 0 (0%) | 124 MHz |
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|:-------------------------------------|:---------:|:--------:|:------------:|:------:|:---------:|
| Full (default) configuration: | 1603 (7%) | 928 (4%) | 65792 (11%) | 0 (0%) | 119.6 MHz |
| Minimal configuration (CPU + GPIO): | 607 (3%) | 230 (1%) | 49408 (8%) | 0 (0%) | 119.6 MHz |
 
| __Lattice iCE40 UltraPlus (iCE40UP5K-SG48I)__ | LUTs | FFs | EBRs | DSPs | SRAMs | f_max* |
|:-----------------------------------------------|:----------:|:----------:|:--------:|:------:|:------:|:------:|
| Full (default) configuration: | 2843 (54%) | 1153 (22%) | 16 (53%) | 0 (0%) | 0 (0%) | 20 MHz |
| Minimal configuration (CPU + GPIO): | 1470 (28%) | 493 (9%) | 12 (40%) | 0 (0%) | 0 (0%) | 20 MHz |
| Full (default) configuration: | 2833 (54%) | 1131 (21%) | 16 (53%) | 0 (0%) | 0 (0%) | 20 MHz |
| Minimal configuration (CPU + GPIO): | 1464 (28%) | 498 (9%) | 12 (40%) | 0 (0%) | 0 (0%) | 20 MHz |
 
*) Constrained
 
 
### Device Utilization by Entity
 
The following table shows the required resources for each module of the NEO430 processor system. Note that the provided
numbers only represent a coarse overview as logic elements might be merged and optimized beyond module boundaries.
 
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes all optional
processor modules (excluding the CFU and DADD), an IMEM size of 4kB and a DMEM size of 2kB. Results were generated
using Intel Quartus Prime Lite 17.1.
 
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
|:------------------------------------|:----:|:---:|:------------|:----:|
| Bootloader Memory (Boot ROM, 2kB) | 2 | 1 | 16384 | 0 |
| Central Processing Unit (CPU) | 547 | 196 | 256 | 0 |
| Checksum Unit (CRC) | 111 | 94 | 0 | 0 |
| Custom Functions Unit (CFU) | - | - | - | - |
| Data Memory (DMEM, 2kB) | 5 | 1 | 16384 | 0 |
| IO Port Unit (GPIO) | 53 | 45 | 0 | 0 |
| Instruction Memory (IMEM, 4kB) | 6 | 1 | 32768 | 0 |
| Multiplier & Divider (MULDIV) | 186 | 131 | 0 | 0 |
| Pulse-Width Modulation Unit (PWM) | 80 | 67 | 0 | 0 |
| Serial Peripheral Interface (SPI) | 57 | 43 | 0 | 0 |
| System Info Memory (SYSCONFIG) | 16 | 14 | 0 | 0 |
| High-Precision Timer (TIMER) | 66 | 55 | 0 | 0 |
| Two Wire Interface (TWI) | 82 | 41 | 0 | 0 |
| Universal Asynchronous Rx/Tx (UART) | 129 | 89 | 0 | 0 |
| Wishbone Interface (WB32) | 130 | 117 | 0 | 0 |
| Watchdog TImer (WDT) | 51 | 34 | 0 | 0 |
 
 
 
## Let's Get It Started!
 
* At first, make sure to get the most recent version of this project from GitHub:
123,6 → 154,8
 
http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
 
* Make sure GNU Make and a native C compiler (GCC) are installed (double check for the newest version)
 
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary:
 
https://github.com/stnolting/neo430/blob/master/doc/NEO430.pdf
158,7 → 191,7
 
"Windows" is a trademark of Microsoft Corporation.
 
"Virtex", "Artix", "ISE" and "Vivado" are trademarks of Xilinx Inc.
"Virtex", "Artix" and "Vivado" are trademarks of Xilinx Inc.
 
"Cyclone", "Quartus" and "Avalon Bus" are trademarks of Intel Corporation.
 
/neo430/trunk/neo430/doc/NEO430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/rtl/core/neo430_addr_gen.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 10.01.2018 #
-- # Stephan Nolting, Hannover, Germany 14.11.2019 #
-- #################################################################################################
 
library ieee;
60,16 → 60,12
memory_addr_adder: process(ctrl_i, mem_i, imm_i, reg_i)
variable offset_v : std_ulogic_vector(15 downto 0);
begin
case ctrl_i(ctrl_adr_off1_c downto ctrl_adr_off0_c) is
when "00" =>
if (ctrl_i(ctrl_adr_imm_en_c) = '0') then
offset_v := mem_i;
else
offset_v := imm_i;
end if;
when "01" => offset_v := x"0001"; -- +1
when "10" => offset_v := x"0002"; -- +2
when others => offset_v := x"FFFE"; -- -2
case ctrl_i(ctrl_adr_off2_c downto ctrl_adr_off0_c) is
when "000" => offset_v := imm_i;
when "001" => offset_v := x"0001"; -- +1
when "010" => offset_v := x"0002"; -- +2
when "011" => offset_v := x"FFFE"; -- -2
when others => offset_v := mem_i;
end case;
addr_add <= std_ulogic_vector(unsigned(reg_i) + unsigned(offset_v));
end process memory_addr_adder;
100,10 → 96,10
begin
if (ctrl_i(ctrl_adr_bp_en_c) = '1') then
if (ctrl_i(ctrl_adr_ivec_oe_c) = '1') then -- interrupt handler call
mem_addr_o <= dmem_base_c; -- IRQ vectors are located at the beginning of the DMEM
mem_addr_o(2 downto 1) <= irq_sel_i; -- select according WORD entry
mem_addr_o <= dmem_base_c; -- IRQ vectors are located at the beginning of DMEM
mem_addr_o(2 downto 0) <= irq_sel_i & '0'; -- select according word-aligned entry
else -- direct output of reg file (for instruction fetch only)
mem_addr_o <= reg_i;
mem_addr_o <= reg_i(15 downto 1) & '0'; -- instructions have to be word-aligned
end if;
else
mem_addr_o <= mem_addr_reg;
/neo430/trunk/neo430/rtl/core/neo430_alu.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 22.06.2018 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
33,9 → 33,6
use neo430.neo430_package.all;
 
entity neo430_alu is
generic (
DADD_USE : boolean := true -- implement DADD instruction?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
172,7 → 169,7
end process dadd_pipe_reg;
 
-- implement DADD instruction? --
dadd_res_in <= dadd_res_ff when (DADD_USE = true) else (others => '0');
dadd_res_in <= dadd_res_ff when (use_dadd_cmd_c = true) else (others => '0');
 
 
-- ALU Core -----------------------------------------------------------------
/neo430/trunk/neo430/rtl/core/neo430_bootloader_image.vhd
13,994 → 13,1018
000002 => x"5211",
000003 => x"fffa",
000004 => x"8321",
000005 => x"3d1c",
000006 => x"4c4a",
000007 => x"403c",
000008 => x"f668",
000009 => x"12b0",
000010 => x"f53c",
000011 => x"4a4c",
000012 => x"12b0",
000013 => x"f58a",
000014 => x"4302",
000015 => x"435c",
000016 => x"12b0",
000017 => x"f622",
000018 => x"4030",
000019 => x"f024",
000020 => x"403c",
000021 => x"f66f",
000022 => x"12b0",
000023 => x"f53c",
000024 => x"403d",
000025 => x"ffa0",
000026 => x"4d2c",
000027 => x"930c",
000028 => x"3bfd",
000029 => x"4032",
000030 => x"4000",
000031 => x"4300",
000032 => x"4030",
000033 => x"f03e",
000034 => x"120a",
000035 => x"1209",
000036 => x"4c09",
000037 => x"434c",
000005 => x"3d9d",
000006 => x"120f",
000007 => x"120e",
000008 => x"120d",
000009 => x"120c",
000010 => x"120b",
000011 => x"5392",
000012 => x"c004",
000013 => x"435c",
000014 => x"12b0",
000015 => x"f658",
000016 => x"413b",
000017 => x"413c",
000018 => x"413d",
000019 => x"413e",
000020 => x"413f",
000021 => x"1300",
000022 => x"403c",
000023 => x"f698",
000024 => x"12b0",
000025 => x"f56c",
000026 => x"403d",
000027 => x"ffa0",
000028 => x"4d2c",
000029 => x"930c",
000030 => x"3bfd",
000031 => x"4032",
000032 => x"4000",
000033 => x"4300",
000034 => x"4030",
000035 => x"f042",
000036 => x"403c",
000037 => x"f6a5",
000038 => x"12b0",
000039 => x"f5da",
000040 => x"403a",
000041 => x"f608",
000042 => x"407c",
000043 => x"0003",
000044 => x"128a",
000045 => x"490c",
000046 => x"427d",
000047 => x"12b0",
000048 => x"f662",
000049 => x"128a",
000050 => x"494c",
000051 => x"128a",
000052 => x"434c",
000053 => x"128a",
000054 => x"4c4a",
000055 => x"434c",
000056 => x"12b0",
000057 => x"f600",
000058 => x"4a4c",
000059 => x"4030",
000060 => x"f656",
000061 => x"120a",
000062 => x"1209",
000063 => x"1208",
000064 => x"4c08",
000065 => x"934d",
000066 => x"200b",
000067 => x"4039",
000068 => x"f520",
000069 => x"1289",
000070 => x"4c4a",
000071 => x"1289",
000072 => x"4c4d",
000073 => x"4a4c",
000074 => x"12b0",
000075 => x"f63a",
000076 => x"4030",
000077 => x"f654",
000078 => x"4039",
000079 => x"f044",
000080 => x"1289",
000081 => x"4c4a",
000082 => x"480c",
000083 => x"531c",
000084 => x"1289",
000085 => x"4030",
000086 => x"f090",
000087 => x"120a",
000088 => x"1209",
000089 => x"1208",
000090 => x"1207",
000091 => x"1206",
000092 => x"1205",
000093 => x"1204",
000094 => x"8221",
000095 => x"4c47",
000096 => x"b0b2",
000097 => x"0100",
000098 => x"fff2",
000099 => x"2403",
000100 => x"435c",
000101 => x"12b0",
000102 => x"f00c",
000103 => x"4035",
000104 => x"f53c",
000105 => x"9307",
000106 => x"200e",
000107 => x"403c",
000108 => x"f67c",
000109 => x"1285",
000110 => x"4039",
000111 => x"f07a",
000112 => x"474d",
000113 => x"434c",
000114 => x"1289",
000115 => x"903c",
000116 => x"cafe",
000117 => x"2407",
000118 => x"436c",
000119 => x"4030",
000120 => x"f0ca",
000121 => x"403c",
000122 => x"f690",
000123 => x"4030",
000124 => x"f0da",
000125 => x"474d",
000126 => x"436c",
000127 => x"1289",
000128 => x"4c0a",
000129 => x"474d",
000130 => x"426c",
000131 => x"1289",
000132 => x"4c81",
000133 => x"0002",
000134 => x"421e",
000135 => x"fff6",
000136 => x"9a0e",
000137 => x"2815",
000138 => x"c312",
000139 => x"100a",
000140 => x"4a04",
000141 => x"5a04",
000142 => x"4346",
000143 => x"4608",
000144 => x"480c",
000145 => x"503c",
000146 => x"0006",
000147 => x"9408",
000148 => x"200d",
000149 => x"c312",
000150 => x"100e",
000151 => x"9e0a",
000152 => x"2814",
000153 => x"9116",
000154 => x"0002",
000155 => x"2419",
000156 => x"427c",
000157 => x"4030",
000158 => x"f0ca",
000159 => x"426c",
000160 => x"4030",
000161 => x"f0ca",
000162 => x"474d",
000163 => x"4e81",
000164 => x"0000",
000165 => x"1289",
000166 => x"ec06",
000167 => x"4c88",
000168 => x"0000",
000169 => x"5328",
000170 => x"412e",
000171 => x"4030",
000172 => x"f120",
000173 => x"4a0c",
000174 => x"5a0c",
000175 => x"540c",
000176 => x"438c",
000177 => x"0000",
000178 => x"531a",
000179 => x"4030",
000180 => x"f12e",
000181 => x"403c",
000182 => x"f69c",
000183 => x"1285",
000184 => x"5221",
000185 => x"4030",
000186 => x"f64c",
000187 => x"120a",
000188 => x"1209",
000189 => x"1208",
000190 => x"1207",
000191 => x"1206",
000192 => x"1205",
000193 => x"4c07",
000194 => x"4d46",
000195 => x"4038",
000196 => x"f5da",
000197 => x"434c",
000198 => x"1288",
000199 => x"403a",
000200 => x"f608",
000201 => x"407c",
000202 => x"0006",
000203 => x"128a",
000204 => x"4039",
000205 => x"f600",
000206 => x"434c",
000207 => x"1289",
000208 => x"434c",
000209 => x"1288",
000210 => x"436c",
000211 => x"128a",
000212 => x"470c",
000213 => x"427d",
000214 => x"12b0",
000215 => x"f662",
000216 => x"128a",
000217 => x"474c",
000218 => x"128a",
000219 => x"464c",
000220 => x"128a",
000221 => x"434c",
000222 => x"1289",
000223 => x"4807",
000224 => x"4348",
000225 => x"4075",
000226 => x"0005",
000227 => x"484c",
000228 => x"1287",
000229 => x"454c",
000230 => x"128a",
000231 => x"484c",
000232 => x"128a",
000233 => x"4c46",
000234 => x"484c",
000235 => x"1289",
000236 => x"b316",
000237 => x"23f5",
000238 => x"4030",
000239 => x"f64e",
000240 => x"120a",
000241 => x"1209",
000242 => x"1208",
000243 => x"4c09",
000244 => x"4d08",
000245 => x"4d0c",
000246 => x"427d",
000247 => x"12b0",
000248 => x"f662",
000249 => x"403a",
000250 => x"f176",
000251 => x"4c4d",
000252 => x"490c",
000253 => x"128a",
000254 => x"484d",
000255 => x"490c",
000256 => x"531c",
000257 => x"128a",
000258 => x"4030",
000259 => x"f654",
000260 => x"120f",
000261 => x"120e",
000262 => x"120d",
000263 => x"120c",
000264 => x"120b",
000265 => x"120a",
000266 => x"1209",
000267 => x"1208",
000268 => x"1207",
000269 => x"1206",
000270 => x"1205",
000271 => x"1204",
000272 => x"5392",
000273 => x"c004",
000274 => x"435c",
000275 => x"12b0",
000276 => x"f628",
000277 => x"4134",
000278 => x"4135",
000279 => x"4136",
000280 => x"4137",
000281 => x"4138",
000282 => x"4139",
000283 => x"413a",
000284 => x"413b",
000285 => x"413c",
000286 => x"413d",
000287 => x"413e",
000288 => x"413f",
000289 => x"1300",
000290 => x"120a",
000291 => x"1209",
000292 => x"1208",
000293 => x"1207",
000294 => x"1206",
000295 => x"1205",
000296 => x"1204",
000297 => x"8321",
000298 => x"12b0",
000299 => x"f644",
000300 => x"4032",
000301 => x"c000",
000302 => x"4382",
000303 => x"ff90",
000304 => x"4382",
000305 => x"ffe0",
000306 => x"4382",
000307 => x"ffe8",
000308 => x"40b2",
000309 => x"f208",
000310 => x"c000",
000311 => x"4382",
000312 => x"ffaa",
000313 => x"435c",
000314 => x"12b0",
000315 => x"f622",
000316 => x"403c",
000317 => x"4b00",
000318 => x"434d",
000319 => x"12b0",
000320 => x"f48c",
000321 => x"12b0",
000322 => x"f536",
000323 => x"426c",
000324 => x"12b0",
000325 => x"f5c0",
000326 => x"4038",
000327 => x"f608",
000328 => x"434c",
000329 => x"1288",
000330 => x"4382",
000331 => x"ffb0",
000332 => x"4037",
000333 => x"fffe",
000334 => x"472c",
000335 => x"5c0c",
000336 => x"5c0c",
000337 => x"533c",
000338 => x"4c82",
000339 => x"ffb4",
000340 => x"40b2",
000341 => x"007f",
000342 => x"ffb0",
000343 => x"4382",
000344 => x"ffb2",
000345 => x"4382",
000346 => x"c004",
000347 => x"12b0",
000348 => x"f634",
000349 => x"12b0",
000350 => x"f62e",
000351 => x"403a",
000352 => x"f53c",
000353 => x"403c",
000354 => x"f69f",
000355 => x"128a",
000356 => x"4039",
000357 => x"f5a6",
000358 => x"421c",
000359 => x"fff0",
000039 => x"f56c",
000040 => x"4130",
000041 => x"120a",
000042 => x"1209",
000043 => x"1208",
000044 => x"1207",
000045 => x"1206",
000046 => x"1205",
000047 => x"1204",
000048 => x"4079",
000049 => x"0020",
000050 => x"4348",
000051 => x"4037",
000052 => x"f56c",
000053 => x"4036",
000054 => x"f5d6",
000055 => x"4035",
000056 => x"f53c",
000057 => x"403c",
000058 => x"f707",
000059 => x"1287",
000060 => x"490a",
000061 => x"503a",
000062 => x"ffe0",
000063 => x"4a0c",
000064 => x"1286",
000065 => x"403c",
000066 => x"f709",
000067 => x"1287",
000068 => x"4074",
000069 => x"0020",
000070 => x"4a2c",
000071 => x"1286",
000072 => x"444c",
000073 => x"1285",
000074 => x"532a",
000075 => x"990a",
000076 => x"23f9",
000077 => x"12b0",
000078 => x"f55c",
000079 => x"930c",
000080 => x"2009",
000081 => x"5039",
000082 => x"0020",
000083 => x"9038",
000084 => x"ffe0",
000085 => x"2404",
000086 => x"5038",
000087 => x"0010",
000088 => x"4030",
000089 => x"f072",
000090 => x"4030",
000091 => x"f67c",
000092 => x"120a",
000093 => x"1209",
000094 => x"1208",
000095 => x"1207",
000096 => x"1206",
000097 => x"1205",
000098 => x"4c07",
000099 => x"4d46",
000100 => x"4038",
000101 => x"f60a",
000102 => x"434c",
000103 => x"1288",
000104 => x"403a",
000105 => x"f638",
000106 => x"407c",
000107 => x"0006",
000108 => x"128a",
000109 => x"4039",
000110 => x"f630",
000111 => x"1289",
000112 => x"434c",
000113 => x"1288",
000114 => x"436c",
000115 => x"128a",
000116 => x"470c",
000117 => x"427d",
000118 => x"12b0",
000119 => x"f692",
000120 => x"128a",
000121 => x"474c",
000122 => x"128a",
000123 => x"464c",
000124 => x"128a",
000125 => x"1289",
000126 => x"4347",
000127 => x"4075",
000128 => x"0005",
000129 => x"474c",
000130 => x"1288",
000131 => x"454c",
000132 => x"128a",
000133 => x"474c",
000134 => x"128a",
000135 => x"4c46",
000136 => x"1289",
000137 => x"b316",
000138 => x"23f6",
000139 => x"4030",
000140 => x"f67e",
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000822 => x"5f52",
000823 => x"4200",
000824 => x"6f6f",
000825 => x"6974",
000826 => x"676e",
000827 => x"2e2e",
000828 => x"0a2e",
000829 => x"000a",
000830 => x"7741",
000831 => x"6961",
000832 => x"6974",
000833 => x"676e",
000834 => x"4220",
000835 => x"4e49",
000836 => x"5845",
000837 => x"2e45",
000838 => x"2e2e",
000839 => x"0020",
000840 => x"6f4c",
000841 => x"6461",
000842 => x"6e69",
000843 => x"2e67",
000844 => x"2e2e",
000845 => x"0020",
000846 => x"4b4f",
000847 => x"0a00",
000848 => x"4e0a",
000849 => x"4f45",
000850 => x"3334",
000851 => x"2030",
000852 => x"6f42",
000853 => x"746f",
000854 => x"6f6c",
000855 => x"6461",
000856 => x"7265",
000857 => x"5620",
000858 => x"3032",
000859 => x"3931",
000860 => x"3930",
000861 => x"3931",
000862 => x"420a",
000863 => x"2079",
000864 => x"7453",
000865 => x"7065",
000866 => x"6168",
000867 => x"206e",
000868 => x"6f4e",
000869 => x"746c",
000870 => x"6e69",
000871 => x"0a67",
000872 => x"480a",
000873 => x"5657",
000874 => x"203a",
000875 => x"7830",
000876 => x"0a00",
000877 => x"5355",
000878 => x"3a52",
000879 => x"3020",
000880 => x"0078",
000881 => x"430a",
000882 => x"4b4c",
000883 => x"203a",
000884 => x"7830",
000885 => x"0a00",
000886 => x"4f52",
000887 => x"3a4d",
000888 => x"3020",
000889 => x"0078",
000890 => x"520a",
000891 => x"4d41",
000892 => x"203a",
000893 => x"7830",
000894 => x"0a00",
000895 => x"5953",
000896 => x"3a53",
000897 => x"3020",
000898 => x"0078",
000899 => x"0a0a",
000900 => x"7541",
000901 => x"6f74",
000902 => x"6f62",
000903 => x"746f",
000904 => x"6920",
000905 => x"206e",
000906 => x"7338",
000907 => x"202e",
000908 => x"7250",
000909 => x"7365",
000910 => x"2073",
000911 => x"656b",
000912 => x"2079",
000913 => x"6f74",
000914 => x"6120",
000915 => x"6f62",
000916 => x"7472",
000917 => x"0a2e",
000918 => x"0a00",
000919 => x"4300",
000920 => x"444d",
000921 => x"3a73",
000922 => x"200a",
000923 => x"3a64",
000924 => x"4420",
000925 => x"6d75",
000926 => x"2070",
000927 => x"454d",
000928 => x"0a4d",
000929 => x"6520",
000930 => x"203a",
000931 => x"6f4c",
000932 => x"6461",
000933 => x"4520",
000934 => x"5045",
000935 => x"4f52",
000936 => x"0a4d",
000937 => x"6820",
000938 => x"203a",
000939 => x"6548",
000940 => x"706c",
000941 => x"200a",
000942 => x"3a70",
000943 => x"5320",
000944 => x"6f74",
000945 => x"6572",
000946 => x"4520",
000947 => x"5045",
000948 => x"4f52",
000949 => x"0a4d",
000950 => x"7220",
000951 => x"203a",
000952 => x"6552",
000953 => x"7473",
000954 => x"7261",
000955 => x"0a74",
000956 => x"7320",
000957 => x"203a",
000958 => x"7453",
000959 => x"7261",
000960 => x"2074",
000961 => x"7061",
000962 => x"0a70",
000963 => x"7520",
000473 => x"f664",
000474 => x"12b0",
000475 => x"f65e",
000476 => x"403a",
000477 => x"f56c",
000478 => x"403c",
000479 => x"f753",
000480 => x"128a",
000481 => x"4039",
000482 => x"f5d6",
000483 => x"421c",
000484 => x"fff0",
000485 => x"1289",
000486 => x"403c",
000487 => x"f78d",
000488 => x"128a",
000489 => x"421c",
000490 => x"fff4",
000491 => x"1289",
000492 => x"403c",
000493 => x"f796",
000494 => x"128a",
000495 => x"482c",
000496 => x"1289",
000497 => x"421c",
000498 => x"fffc",
000499 => x"1289",
000500 => x"403c",
000501 => x"f79f",
000502 => x"128a",
000503 => x"421c",
000504 => x"fff6",
000505 => x"1289",
000506 => x"403c",
000507 => x"f7a8",
000508 => x"128a",
000509 => x"421c",
000510 => x"fffa",
000511 => x"1289",
000512 => x"403c",
000513 => x"f7b1",
000514 => x"128a",
000515 => x"421c",
000516 => x"fff2",
000517 => x"1289",
000518 => x"403c",
000519 => x"f7ba",
000520 => x"128a",
000521 => x"403e",
000522 => x"c004",
000523 => x"403d",
000524 => x"ffa2",
000525 => x"4e2c",
000526 => x"903c",
000527 => x"0020",
000528 => x"2008",
000529 => x"435c",
000530 => x"12b0",
000531 => x"f27c",
000532 => x"403c",
000533 => x"f707",
000534 => x"128a",
000535 => x"12b0",
000536 => x"f02c",
000537 => x"4d2c",
000538 => x"930c",
000539 => x"37f1",
000540 => x"4038",
000541 => x"f048",
000542 => x"1288",
000543 => x"4036",
000544 => x"f550",
000545 => x"4035",
000546 => x"f53c",
000547 => x"4037",
000548 => x"f27c",
000549 => x"403c",
000550 => x"f7e1",
000551 => x"128a",
000552 => x"1286",
000553 => x"4c49",
000554 => x"1285",
000555 => x"403c",
000556 => x"f707",
000557 => x"128a",
000558 => x"9079",
000559 => x"0072",
000560 => x"2004",
000561 => x"4030",
000562 => x"f000",
000563 => x"4030",
000564 => x"f44a",
000565 => x"9079",
000566 => x"0068",
000567 => x"2003",
000568 => x"1288",
000569 => x"4030",
000570 => x"f44a",
000571 => x"9079",
000572 => x"0064",
000573 => x"2004",
000574 => x"12b0",
000575 => x"f052",
000576 => x"4030",
000577 => x"f44a",
000578 => x"9079",
000579 => x"0075",
000580 => x"2004",
000581 => x"434c",
000582 => x"1287",
000583 => x"4030",
000584 => x"f44a",
000585 => x"9079",
000586 => x"0070",
000587 => x"2004",
000588 => x"12b0",
000589 => x"f1dc",
000590 => x"4030",
000591 => x"f44a",
000592 => x"9079",
000593 => x"0065",
000594 => x"2003",
000595 => x"435c",
000596 => x"4030",
000597 => x"f48c",
000598 => x"9079",
000599 => x"0073",
000600 => x"27be",
000601 => x"403c",
000602 => x"f7e9",
000603 => x"128a",
000604 => x"4030",
000605 => x"f44a",
000606 => x"120a",
000607 => x"1209",
000608 => x"421a",
000609 => x"fffc",
000610 => x"421b",
000611 => x"fffe",
000612 => x"4c0e",
000613 => x"5c0e",
000614 => x"4d0f",
000615 => x"6d0f",
000616 => x"434c",
000617 => x"4f09",
000618 => x"9f0b",
000619 => x"2804",
000620 => x"9b09",
000621 => x"201b",
000622 => x"9e0a",
000623 => x"2c19",
000624 => x"434a",
000625 => x"4079",
000626 => x"0003",
000627 => x"407d",
000628 => x"00ff",
000629 => x"9c0d",
000630 => x"2817",
000631 => x"4382",
000632 => x"ffa0",
000633 => x"4a0d",
000634 => x"5a0d",
000635 => x"5d0d",
000636 => x"5d0d",
000637 => x"5d0d",
000638 => x"5d0d",
000639 => x"5d0d",
000640 => x"5d0d",
000641 => x"5d0d",
000642 => x"dc0d",
000643 => x"d03d",
000644 => x"1000",
000645 => x"4d82",
000646 => x"ffa0",
000647 => x"4030",
000648 => x"f686",
000649 => x"8e0a",
000650 => x"7f0b",
000651 => x"531c",
000652 => x"4030",
000653 => x"f4d4",
000654 => x"936a",
000655 => x"2402",
000656 => x"926a",
000657 => x"2008",
000658 => x"490d",
000659 => x"12b0",
000660 => x"f692",
000661 => x"535a",
000662 => x"f03a",
000663 => x"00ff",
000664 => x"4030",
000665 => x"f4e6",
000666 => x"c312",
000667 => x"100c",
000668 => x"4030",
000669 => x"f52a",
000670 => x"f03c",
000671 => x"00ff",
000672 => x"403e",
000673 => x"ffa0",
000674 => x"4e2d",
000675 => x"930d",
000676 => x"3bfd",
000677 => x"4c82",
000678 => x"ffa2",
000679 => x"4130",
000680 => x"403d",
000681 => x"ffa2",
000682 => x"4d2c",
000683 => x"930c",
000684 => x"37fd",
000685 => x"4130",
000686 => x"421c",
000687 => x"ffa2",
000688 => x"f03c",
000689 => x"8000",
000690 => x"4130",
000691 => x"421c",
000692 => x"ffa2",
000693 => x"4130",
000694 => x"120a",
000695 => x"1209",
000696 => x"1208",
000697 => x"1207",
000698 => x"4c09",
000699 => x"4038",
000700 => x"f53c",
000701 => x"4077",
000702 => x"000d",
000703 => x"496a",
000704 => x"930a",
000705 => x"2002",
000706 => x"4030",
000707 => x"f682",
000708 => x"903a",
000709 => x"000a",
000710 => x"2002",
000711 => x"474c",
000712 => x"1288",
000713 => x"4a4c",
000714 => x"1288",
000715 => x"5319",
000716 => x"4030",
000717 => x"f57e",
000718 => x"f07c",
000719 => x"000f",
000720 => x"407d",
000721 => x"0009",
000722 => x"9c4d",
000723 => x"2805",
000724 => x"503c",
000725 => x"0030",
000726 => x"12b0",
000727 => x"f53c",
000728 => x"4130",
000729 => x"503c",
000730 => x"0037",
000731 => x"4030",
000732 => x"f5ac",
000733 => x"120a",
000734 => x"1209",
000735 => x"4c49",
000736 => x"490c",
000737 => x"426d",
000738 => x"12b0",
000739 => x"f692",
000740 => x"403a",
000741 => x"f59c",
000742 => x"128a",
000743 => x"494c",
000744 => x"128a",
000745 => x"4030",
000746 => x"f686",
000747 => x"120a",
000748 => x"1209",
000749 => x"4c09",
000750 => x"427d",
000751 => x"12b0",
000752 => x"f692",
000753 => x"403a",
000754 => x"f5ba",
000755 => x"128a",
000756 => x"494c",
000757 => x"128a",
000758 => x"4030",
000759 => x"f686",
000760 => x"f03c",
000761 => x"00ff",
000762 => x"403d",
000763 => x"ffa4",
000764 => x"438d",
000765 => x"0000",
000766 => x"5c0c",
000767 => x"5c0c",
000768 => x"5c0c",
000769 => x"d31c",
000770 => x"4c8d",
000771 => x"0000",
000772 => x"4130",
000773 => x"f03c",
000774 => x"00ff",
000775 => x"403d",
000776 => x"ffa4",
000777 => x"f0bd",
000778 => x"fc3f",
000779 => x"0000",
000780 => x"5c0c",
000781 => x"5c0c",
000782 => x"5c0c",
000783 => x"5c0c",
000784 => x"5c0c",
000785 => x"5c0c",
000786 => x"dd2c",
000787 => x"d03c",
000788 => x"0200",
000789 => x"4c8d",
000790 => x"0000",
000791 => x"4130",
000792 => x"f0b2",
000793 => x"fdff",
000794 => x"ffa4",
000795 => x"4130",
000796 => x"403d",
000797 => x"ffa6",
000798 => x"f03c",
000799 => x"00ff",
000800 => x"4c8d",
000801 => x"0000",
000802 => x"403e",
000803 => x"ffa4",
000804 => x"4e2c",
000805 => x"930c",
000806 => x"3bfd",
000807 => x"4d2c",
000808 => x"4130",
000809 => x"4c82",
000810 => x"ffae",
000811 => x"4130",
000812 => x"ec82",
000813 => x"ffae",
000814 => x"4130",
000815 => x"d232",
000816 => x"4303",
000817 => x"4130",
000818 => x"d032",
000819 => x"4000",
000820 => x"4130",
000821 => x"4c4e",
000822 => x"4d4c",
000823 => x"108e",
000824 => x"de0c",
000825 => x"4130",
000826 => x"40b2",
000827 => x"4700",
000828 => x"ffb8",
000829 => x"4130",
000830 => x"4134",
000831 => x"4135",
000832 => x"4136",
000833 => x"4137",
000834 => x"4138",
000835 => x"4139",
000836 => x"413a",
000837 => x"4130",
000838 => x"533d",
000839 => x"c312",
000840 => x"100c",
000841 => x"930d",
000842 => x"23fb",
000843 => x"4130",
000844 => x"6f42",
000845 => x"746f",
000846 => x"6e69",
000847 => x"2e67",
000848 => x"2e2e",
000849 => x"0a0a",
000850 => x"4300",
000851 => x"444d",
000852 => x"3a73",
000853 => x"200a",
000854 => x"3a64",
000855 => x"4420",
000856 => x"6d75",
000857 => x"2070",
000858 => x"454d",
000859 => x"0a4d",
000860 => x"6520",
000861 => x"203a",
000862 => x"6f4c",
000863 => x"6461",
000864 => x"4520",
000865 => x"5045",
000866 => x"4f52",
000867 => x"0a4d",
000868 => x"6820",
000869 => x"203a",
000870 => x"6548",
000871 => x"706c",
000872 => x"200a",
000873 => x"3a70",
000874 => x"5320",
000875 => x"6f74",
000876 => x"6572",
000877 => x"4520",
000878 => x"5045",
000879 => x"4f52",
000880 => x"0a4d",
000881 => x"7220",
000882 => x"203a",
000883 => x"6552",
000884 => x"7473",
000885 => x"7261",
000886 => x"0a74",
000887 => x"7320",
000888 => x"203a",
000889 => x"7453",
000890 => x"7261",
000891 => x"2074",
000892 => x"7061",
000893 => x"0a70",
000894 => x"7520",
000895 => x"203a",
000896 => x"7055",
000897 => x"6f6c",
000898 => x"6461",
000899 => x"0a00",
000900 => x"3a00",
000901 => x"2020",
000902 => x"0700",
000903 => x"450a",
000904 => x"5252",
000905 => x"005f",
000906 => x"7250",
000907 => x"636f",
000908 => x"6565",
000909 => x"2064",
000910 => x"7928",
000911 => x"6e2f",
000912 => x"3f29",
000913 => x"0a00",
000914 => x"7257",
000915 => x"7469",
000916 => x"6e69",
000917 => x"2e67",
000918 => x"2e2e",
000919 => x"0020",
000920 => x"4b4f",
000921 => x"4100",
000922 => x"6177",
000923 => x"7469",
000924 => x"6e69",
000925 => x"2067",
000926 => x"4942",
000927 => x"454e",
000928 => x"4558",
000929 => x"2e2e",
000930 => x"202e",
000931 => x"4c00",
000932 => x"616f",
000933 => x"6964",
000934 => x"676e",
000935 => x"2e2e",
000936 => x"202e",
000937 => x"0a00",
000938 => x"4e0a",
000939 => x"4f45",
000940 => x"3334",
000941 => x"2030",
000942 => x"6f42",
000943 => x"746f",
000944 => x"6f6c",
000945 => x"6461",
000946 => x"7265",
000947 => x"5620",
000948 => x"3032",
000949 => x"3931",
000950 => x"3131",
000951 => x"3331",
000952 => x"420a",
000953 => x"2079",
000954 => x"7453",
000955 => x"7065",
000956 => x"6168",
000957 => x"206e",
000958 => x"6f4e",
000959 => x"746c",
000960 => x"6e69",
000961 => x"0a67",
000962 => x"480a",
000963 => x"5657",
000964 => x"203a",
000965 => x"7055",
000966 => x"6f6c",
000967 => x"6461",
000968 => x"0a00",
000969 => x"4d43",
000970 => x"3a44",
000971 => x"203e",
000972 => x"3a00",
000973 => x"2020",
000974 => x"5000",
000975 => x"6f72",
000976 => x"6563",
000977 => x"6465",
000978 => x"2820",
000979 => x"2f79",
000980 => x"296e",
000981 => x"003f",
000982 => x"570a",
000983 => x"6972",
000984 => x"6974",
000985 => x"676e",
000986 => x"2e2e",
000987 => x"202e",
000988 => x"4200",
000989 => x"6461",
000990 => x"4320",
000991 => x"444d",
000992 => x"0021",
000965 => x"7830",
000966 => x"0a00",
000967 => x"5355",
000968 => x"3a52",
000969 => x"3020",
000970 => x"0078",
000971 => x"430a",
000972 => x"4b4c",
000973 => x"203a",
000974 => x"7830",
000975 => x"0a00",
000976 => x"4f52",
000977 => x"3a4d",
000978 => x"3020",
000979 => x"0078",
000980 => x"520a",
000981 => x"4d41",
000982 => x"203a",
000983 => x"7830",
000984 => x"0a00",
000985 => x"5953",
000986 => x"3a53",
000987 => x"3020",
000988 => x"0078",
000989 => x"0a0a",
000990 => x"7541",
000991 => x"6f74",
000992 => x"6f62",
000993 => x"746f",
000994 => x"6920",
000995 => x"206e",
000996 => x"7338",
000997 => x"202e",
000998 => x"7250",
000999 => x"7365",
001000 => x"2073",
001001 => x"656b",
001002 => x"2079",
001003 => x"6f74",
001004 => x"6120",
001005 => x"6f62",
001006 => x"7472",
001007 => x"0a2e",
001008 => x"0a00",
001009 => x"4d43",
001010 => x"3a44",
001011 => x"203e",
001012 => x"4200",
001013 => x"6461",
001014 => x"4320",
001015 => x"444d",
001016 => x"0021",
others => x"0000"
);
 
/neo430/trunk/neo430/rtl/core/neo430_control.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 28.05.2018 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
32,9 → 32,6
use neo430.neo430_package.all;
 
entity neo430_control is
generic (
DADD_USE : boolean := true -- implement DADD instruction?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
63,7 → 60,7
 
-- state machine --
type state_t is (RESET, IFETCH_0, IFETCH_1, DECODE,
TRANS_0, TRANS_1, TRANS_3, TRANS_4, TRANS_6, TRANS_7, TRANS_8, TRANS_9,
TRANS_0, TRANS_1, TRANS_2, TRANS_3, TRANS_4, TRANS_5, TRANS_6, TRANS_7,
PUSHCALL_0, PUSHCALL_1, PUSHCALL_2,
RETI_0, RETI_1, RETI_2, RETI_3, RETI_4,
IRQ_0, IRQ_1, IRQ_2, IRQ_3, IRQ_4, IRQ_5);
152,6 → 149,7
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source reg A
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c); -- keep ALU function
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default SRC addressing mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2 as address offset
ctrl_nxt(ctrl_mem_rd_c) <= mem_rd_ff; -- memory read
ctrl_nxt(ctrl_alu_bw_c) <= ctrl(ctrl_alu_bw_c); -- keep byte/word mode
 
187,7 → 185,7
ctrl_nxt(ctrl_rf_ad_c) <= '0'; -- DST address mode = REG
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output PC/IRQ vector
if (irq_start = '1') then -- execute IRQ
212,8 → 210,7
if (instr_i(13) = '1') then -- BRANCH INSTRUCTION
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "00"; -- add immediate offset
ctrl_nxt(ctrl_adr_imm_en_c) <= '1'; -- add immediate
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "000"; -- add immediate offset
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= branch_taken; -- valid RF write back if branch taken
state_nxt <= IFETCH_0;
235,10 → 232,10
when "100" => state_nxt <= TRANS_0; -- PUSH (via single ALU OP)
when "101" => state_nxt <= TRANS_0; -- CALL (via single ALU OP)
when "110" => state_nxt <= RETI_0; -- RETI
when "111" => state_nxt <= IFETCH_0; -- undefined
when "111" => state_nxt <= IFETCH_0; -- undefined (for detecting invalid opcodes)
when others => state_nxt <= TRANS_0; -- single ALU OP
end case;
else -- Undefined
else -- Undefined (for detecting invalid opcodes)
-- ------------------------------------------------------------
state_nxt <= IFETCH_0;
end if;
273,10 → 270,10
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_3;
state_nxt <= TRANS_2;
when "0010" | "0011" | "1010" | "1011" =>
-- "001-" = CLASS I, SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS II, SRC: indexed/symbolic/absolute, DST: register direct
284,7 → 281,7
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_1;
304,9 → 301,9
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
if (ir(6) = '0') or (src = reg_pc_c) then -- word mode (force if accessing PC)
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
else -- byte mode
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "01"; -- add +1
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "001"; -- add +1
end if;
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
326,7 → 323,7
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
state_nxt <= TRANS_8;
state_nxt <= TRANS_6;
end if;
when "0010" | "0011" | "1010" | "0100" | "0101" | "1100" | "0110" | "0111" | "1110" =>
-- "001-" = CLASS I, SRC/DST: indexed/symbolic/absolute
338,7 → 335,7
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= "00"; -- DST address mode = REG
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- source: reg B
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write OpB
state_nxt <= TRANS_3;
state_nxt <= TRANS_2;
when others =>
-- "1011" = CLASS II, SRC: indexed/symbolic/absolute, DST: indexed
-- "1101" = CLASS II, SRC: indirect, DST: indexed
346,13 → 343,13
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_3;
state_nxt <= TRANS_2;
end case;
 
when TRANS_3 => -- operand transfer cycle 3
when TRANS_2 => -- operand transfer cycle 3
-- ------------------------------------------------------------
case am is -- addressing mode
when "0000" | "0001" | "1000" | "1001" =>
361,17 → 358,17
-- "1001" = CLASS II, SRC: register direct, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
state_nxt <= TRANS_4;
state_nxt <= TRANS_3;
when "0010" | "0011" | "1010" | "1011" =>
-- "001-" = CLASS I: SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS II, SRC: indexed/symbolic/absolute, DST: register direct
-- "1011" = CLASS II, SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "00"; -- add memory data in
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
state_nxt <= TRANS_4;
state_nxt <= TRANS_3;
when "0100" | "0101" | "1100" | "0110" | "0111" | "1110" =>
-- "010-" = CLASS I: SRC/DST: indirect
-- "1100" = CLASS II, SRC: indirect, DST: register direct
382,7 → 379,7
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
state_nxt <= TRANS_8;
state_nxt <= TRANS_6;
end if;
when others =>
-- "1101" = CLASS II, SRC: indirect, DST: indexed
389,10 → 386,10
-- "1111" = CLASS II, SRC: indirect auto inc, DST: indexed
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
state_nxt <= TRANS_4;
state_nxt <= TRANS_3;
end case;
 
when TRANS_4 => -- operand transfer cycle 4
when TRANS_3 => -- operand transfer cycle 4
-- ------------------------------------------------------------
case am is -- addressing mode
when "1001" | "1011" | "1101" | "1111" =>
403,18 → 400,18
ctrl_nxt(ctrl_rf_as1_c) <= '0'; -- DST address mode = REG or INDEXED
ctrl_nxt(ctrl_rf_as0_c) <= ir(7); -- DST address mode = REG or INDEXED
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- source: reg B
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "00"; -- add memory data in
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) /= alu_mov_c) then -- no read for MOV
mem_rd <= '1'; -- Memory read
end if;
state_nxt <= TRANS_6;
state_nxt <= TRANS_4;
when others =>
state_nxt <= TRANS_6; -- NOP / DONT CARE
state_nxt <= TRANS_4; -- NOP / DONT CARE
end case;
 
when TRANS_6 => -- operand transfer cycle 6
when TRANS_4 => -- operand transfer cycle 6
-- ------------------------------------------------------------
case am is -- addressing mode
when "0010" | "0011" | "1010" =>
425,22 → 422,22
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
state_nxt <= TRANS_8;
state_nxt <= TRANS_6;
end if;
when "1011" =>
-- "1011" = CLASS II,SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
state_nxt <= TRANS_7;
state_nxt <= TRANS_5;
when others =>
-- "000-" = CLASS I, SRD/DST: CLASS II,
-- "1000" = CLASS II, SRC: register direct, DST: register direct = DONT CARE
-- "1001" = CLASS II, SRC: register direct, DST: indexed = NOP
-- others: NOP
state_nxt <= TRANS_7; -- NOP / DONT CARE
state_nxt <= TRANS_5; -- NOP / DONT CARE
end case;
 
when TRANS_7 => -- operand transfer cycle 7
when TRANS_5 => -- operand transfer cycle 7
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write to OpA
447,14 → 444,14
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
state_nxt <= TRANS_8; -- single/dual ALU operation
state_nxt <= TRANS_6; -- single/dual ALU operation
end if;
 
when TRANS_8 => -- operand transfer cycle 8
when TRANS_6 => -- operand transfer cycle 8
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- destination
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_dadd_c) and (DADD_USE = true) then
state_nxt <= TRANS_9;
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_dadd_c) and (use_dadd_cmd_c = true) then
state_nxt <= TRANS_7;
else
ctrl_nxt(ctrl_rf_fup_c) <= not spec_cmd_v; -- update ALU status flags
if (am(0) = '0') then -- DST: register direct
465,7 → 462,7
state_nxt <= IFETCH_0; -- done!
end if;
 
when TRANS_9 => -- operand transfer cycle 9
when TRANS_7 => -- operand transfer cycle 9
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- destination
ctrl_nxt(ctrl_rf_fup_c) <= not spec_cmd_v; -- update ALU status flags
480,7 → 477,7
when PUSHCALL_0 => -- PUSH/CALL cycle 0 (stack update)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "11"; -- add -2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
509,7 → 506,7
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_1;
519,7 → 516,7
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "10"; -- add +2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_2;
549,7 → 546,7
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "11"; -- add -2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
567,7 → 564,7
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- write memory request (store PC)
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off1_c downto ctrl_adr_off0_c) <= "11"; -- add -2
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
/neo430/trunk/neo430/rtl/core/neo430_cpu.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 30.05.2018 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
33,7 → 33,6
 
entity neo430_cpu is
generic (
DADD_USE : boolean := true; -- implement DADD instruction?
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
78,9 → 77,6
-- Control Unit -------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_control_inst: neo430_control
generic map (
DADD_USE => DADD_USE -- implement DADD instruction? (default=true)
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
124,9 → 120,6
-- ALU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_alu_inst: neo430_alu
generic map (
DADD_USE => DADD_USE -- implement DADD instruction? (default=true)
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
/neo430/trunk/neo430/rtl/core/neo430_package.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 05.10.2019 #
-- # Stephan Nolting, Hannover, Germany 14.11.2019 #
-- #################################################################################################
 
library ieee;
30,13 → 30,14
 
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0301"; -- no touchy!
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0304"; -- no touchy!
 
-- Advanced Hardware Configuration --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant use_dsp_mul_c : boolean := false; -- use DSP blocks for MULDIV's multiplication (default=false)
constant use_dadd_cmd_c : boolean := false; -- implement CPU's DADD instruction (default=false)
constant low_power_mode_c : boolean := false; -- reduces switching activity, but will also decrease f_max and might increase area (default=false)
constant awesome_mode_c : boolean := true; -- of course! (default=true)
constant awesome_mode_c : boolean := true; -- of course! (default=true)
 
-- Internal Functions ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
256,7 → 257,7
-- address generator --
constant ctrl_adr_off0_c : natural := 21; -- address offset selection bit 0
constant ctrl_adr_off1_c : natural := 22; -- address offset selection bit 1
constant ctrl_adr_imm_en_c : natural := 23; -- select immediate branch input
constant ctrl_adr_off2_c : natural := 23; -- address offset selection bit 2
constant ctrl_adr_mar_sel_c : natural := 24; -- select input for MAR
constant ctrl_adr_bp_en_c : natural := 25; -- mem addr output select, 0:MAR, 1:bypass
constant ctrl_adr_ivec_oe_c : natural := 26; -- output IRQ if 1, else output PC
309,7 → 310,6
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
361,9 → 361,6
-- Component: Control ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_control
generic (
DADD_USE : boolean := true -- implement DADD instruction?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
407,9 → 404,6
-- Component: Data ALU --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_alu
generic (
DADD_USE : boolean := true -- implement DADD instruction?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
448,7 → 442,6
-- -------------------------------------------------------------------------------------------
component neo430_cpu
generic (
DADD_USE : boolean := true; -- implement DADD instruction?
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
738,7 → 731,6
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction?
MULDIV_USE : boolean := true; -- implement multiplier/divider unit?
WB32_USE : boolean := true; -- implement WB32 unit?
WDT_USE : boolean := true; -- implement WDT?
/neo430/trunk/neo430/rtl/core/neo430_pwm.vhd
2,7 → 2,7
-- # << NEO430 - PWM Controller >> #
-- # ********************************************************************************************* #
-- # Simple 4-channel PWM controller with 8 bit resolution for the duty cycle and selectable #
--- # counter width (frequency resolution) from 1 to 8 bits. #
-- # counter width (frequency resolution) from 1 to 8 bits. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
131,14 → 131,14
mask_gen: process(size)
begin
case size is
when "000" => mask <= "00000001";
when "001" => mask <= "00000011";
when "010" => mask <= "00000111";
when "011" => mask <= "00001111";
when "100" => mask <= "00011111";
when "101" => mask <= "00111111";
when "110" => mask <= "01111111";
when "111" => mask <= "11111111";
when "000" => mask <= "00000001";
when "001" => mask <= "00000011";
when "010" => mask <= "00000111";
when "011" => mask <= "00001111";
when "100" => mask <= "00011111";
when "101" => mask <= "00111111";
when "110" => mask <= "01111111";
when "111" => mask <= "11111111";
when others => mask <= (others => '1');
end case;
end process mask_gen;
153,12 → 153,12
if (enable = '0') then
pwm_cnt <= (others => '0');
elsif (prsc_tick = '1') then
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1) and mask;
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
-- channels --
for i in 0 to num_pwm_channels_c-1 loop
-- constrain counter and duty cycle value to virtual size configured by SIZE register
if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
-- constrain counter to virtual size configured by SIZE register
if (unsigned(pwm_cnt and mask) >= unsigned(pwm_ch(i))) or (enable = '0') then
pwm_o(i) <= '0';
else
pwm_o(i) <= '1';
/neo430/trunk/neo430/rtl/core/neo430_spi.vhd
1,7 → 1,7
-- #################################################################################################
-- # << NEO430 - Serial Peripheral Interface >> #
-- # ********************************************************************************************* #
-- # Fixed frame: 8-bit, MSB first, 2 clock modes, 8 clock speeds, 8 dedicated CS lines. #
-- # Frame format: 8-bit, MSB or LSB first, 2 clock modes, 8 clock speeds, 8 dedicated CS lines. #
-- # Interrupt: SPI_transfer_done #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 17.11.2018 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
71,6 → 71,7
constant ctrl_spi_cs_sel1_c : natural := 7; -- r/w: spi CS select bit 0
constant ctrl_spi_cs_sel2_c : natural := 8; -- r/w: spi CS select bit 0
constant ctrl_spi_cs_set_c : natural := 9; -- r/w: spi CS select enable
constant ctrl_spi_dir_c : natural := 10; -- r/w: shift direction (0: MSB first, 1: LSB first)
-- ...
constant ctrl_spi_busy_c : natural := 15; -- r/-: spi transceiver is busy
 
153,11 → 154,19
else -- transmission in progress
if (spi_state1 = '0') then -- first half of transmission
spi_sclk_o <= ctrl(ctrl_spi_cpha_c);
spi_mosi_o <= spi_rtx_sreg(7); -- MSB first
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_mosi_o <= spi_rtx_sreg(7); -- MSB first
else
spi_mosi_o <= spi_rtx_sreg(0); -- LSB first
end if;
if (spi_clk = '1') then
spi_state1 <= '1';
if (ctrl(ctrl_spi_cpha_c) = '0') then
spi_rtx_sreg <= spi_rtx_sreg(6 downto 0) & spi_miso_ff1; -- MSB first
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_rtx_sreg <= spi_rtx_sreg(6 downto 0) & spi_miso_ff1; -- MSB first
else
spi_rtx_sreg <= spi_miso_ff1 & spi_rtx_sreg(7 downto 1); -- LSB first
end if;
end if;
spi_bitcnt <= std_ulogic_vector(unsigned(spi_bitcnt) - 1);
end if;
166,7 → 175,11
if (spi_clk = '1') then
spi_state1 <= '0';
if (ctrl(ctrl_spi_cpha_c) = '1') then
spi_rtx_sreg <= spi_rtx_sreg(6 downto 0) & spi_miso_ff1; -- MSB first
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_rtx_sreg <= spi_rtx_sreg(6 downto 0) & spi_miso_ff1; -- MSB first
else
spi_rtx_sreg <= spi_miso_ff1 & spi_rtx_sreg(7 downto 1); -- LSB first
end if;
end if;
if (spi_bitcnt = "0000") then
spi_state0 <= '0';
208,6 → 221,7
data_o(ctrl_spi_cs_sel1_c) <= ctrl(ctrl_spi_cs_sel1_c);
data_o(ctrl_spi_cs_sel2_c) <= ctrl(ctrl_spi_cs_sel2_c);
data_o(ctrl_spi_cs_set_c) <= ctrl(ctrl_spi_cs_set_c);
data_o(ctrl_spi_dir_c) <= ctrl(ctrl_spi_dir_c);
data_o(ctrl_spi_busy_c) <= spi_busy;
else -- spi_rtx_addr_c
data_o(7 downto 0) <= spi_rtx_sreg;
/neo430/trunk/neo430/rtl/core/neo430_sysconfig.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
41,7 → 41,6
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction?
MULDIV_USE : boolean := true; -- implement multiplier/divider unit?
WB32_USE : boolean := true; -- implement WB32 unit?
WDT_USE : boolean := true; -- implement WDT?
103,22 → 102,22
sysinfo_mem(0) <= hw_version_c; -- HW version
 
-- CPUID1: System setup (features) --
sysinfo_mem(1)(00) <= bool_to_ulogic_f(MULDIV_USE); -- MULDIV present?
sysinfo_mem(1)(01) <= bool_to_ulogic_f(WB32_USE); -- WB32 present?
sysinfo_mem(1)(02) <= bool_to_ulogic_f(WDT_USE); -- WDT present?
sysinfo_mem(1)(03) <= bool_to_ulogic_f(GPIO_USE); -- GPIO present?
sysinfo_mem(1)(04) <= bool_to_ulogic_f(TIMER_USE); -- TIMER present?
sysinfo_mem(1)(05) <= bool_to_ulogic_f(UART_USE); -- UART present?
sysinfo_mem(1)(06) <= bool_to_ulogic_f(DADD_USE); -- DADD instruction present?
sysinfo_mem(1)(07) <= bool_to_ulogic_f(BOOTLD_USE); -- bootloader present?
sysinfo_mem(1)(08) <= bool_to_ulogic_f(IMEM_AS_ROM); -- IMEM implemented as true ROM?
sysinfo_mem(1)(09) <= bool_to_ulogic_f(CRC_USE); -- CRC present?
sysinfo_mem(1)(10) <= bool_to_ulogic_f(CFU_USE); -- CFU present?
sysinfo_mem(1)(11) <= bool_to_ulogic_f(PWM_USE); -- PWM present?
sysinfo_mem(1)(12) <= bool_to_ulogic_f(TWI_USE); -- TWI present?
sysinfo_mem(1)(13) <= bool_to_ulogic_f(SPI_USE); -- SPI present?
sysinfo_mem(1)(14) <= '0'; -- reserved
sysinfo_mem(1)(15) <= '0'; -- reserved
sysinfo_mem(1)(00) <= bool_to_ulogic_f(MULDIV_USE); -- MULDIV present?
sysinfo_mem(1)(01) <= bool_to_ulogic_f(WB32_USE); -- WB32 present?
sysinfo_mem(1)(02) <= bool_to_ulogic_f(WDT_USE); -- WDT present?
sysinfo_mem(1)(03) <= bool_to_ulogic_f(GPIO_USE); -- GPIO present?
sysinfo_mem(1)(04) <= bool_to_ulogic_f(TIMER_USE); -- TIMER present?
sysinfo_mem(1)(05) <= bool_to_ulogic_f(UART_USE); -- UART present?
sysinfo_mem(1)(06) <= bool_to_ulogic_f(use_dadd_cmd_c); -- DADD instruction present?
sysinfo_mem(1)(07) <= bool_to_ulogic_f(BOOTLD_USE); -- bootloader present?
sysinfo_mem(1)(08) <= bool_to_ulogic_f(IMEM_AS_ROM); -- IMEM implemented as true ROM?
sysinfo_mem(1)(09) <= bool_to_ulogic_f(CRC_USE); -- CRC present?
sysinfo_mem(1)(10) <= bool_to_ulogic_f(CFU_USE); -- CFU present?
sysinfo_mem(1)(11) <= bool_to_ulogic_f(PWM_USE); -- PWM present?
sysinfo_mem(1)(12) <= bool_to_ulogic_f(TWI_USE); -- TWI present?
sysinfo_mem(1)(13) <= bool_to_ulogic_f(SPI_USE); -- SPI present?
sysinfo_mem(1)(14) <= '0'; -- reserved
sysinfo_mem(1)(15) <= '0'; -- reserved
 
-- CPUID2: User code --
sysinfo_mem(2) <= USER_CODE;
/neo430/trunk/neo430/rtl/core/neo430_timer.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # This timer uses a configurable prescaler to increment an internal 16-bit counter. When the #
-- # counter value reaches the programmable threshold an interrupt can be triggered. Optionally, #
-- # the counter can be automatically reset when reaching the threshold value. #
-- # the counter can be automatically reset when reaching the threshold value to restart counting. #
-- # Configure THRES before enabling the timer to prevent false interrupt requests. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
71,9 → 71,9
signal wr_en : std_ulogic; -- word write enable
 
-- timer regs --
signal cnt : std_ulogic_vector(15 downto 0);
signal thres : std_ulogic_vector(15 downto 0);
signal ctrl : std_ulogic_vector(05 downto 0);
signal cnt : std_ulogic_vector(15 downto 0); -- r/-: counter register
signal thres : std_ulogic_vector(15 downto 0); -- r/w: threshold register
signal ctrl : std_ulogic_vector(05 downto 0); -- r/w: control register
 
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
92,24 → 92,11
wr_en <= acc_en and wren_i;
 
 
-- Write access and timer update --------------------------------------------
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- edge detector --
irq_fire_ff <= irq_fire;
-- timer counter --
if (wr_en = '1') and (addr = timer_cnt_addr_c) then
cnt <= data_i;
elsif (ctrl(ctrl_en_bit_c) = '1') then -- timer enabled
if (match = '1') and (ctrl(ctrl_arst_bit_c) = '1') then -- match?
cnt <= (others => '0');
elsif (match = '0') and (prsc_tick = '1') then -- count++ if no match
cnt <= std_ulogic_vector(unsigned(cnt) + 1);
end if;
end if;
-- control & threshold --
if (wr_en = '1') then
if (addr = timer_thres_addr_c) then
thres <= data_i;
132,6 → 119,25
-- enable external clock generator --
clkgen_en_o <= ctrl(ctrl_en_bit_c);
 
 
-- Counter update -----------------------------------------------------------
-- -----------------------------------------------------------------------------
counter_update: process(clk_i)
begin
if rising_edge(clk_i) then
-- irq edge detector --
irq_fire_ff <= irq_fire;
-- counter update --
if (ctrl(ctrl_en_bit_c) = '0') then -- timer disabled
cnt <= (others => '0');
elsif (match = '1') and (ctrl(ctrl_arst_bit_c) = '1') then -- threshold match and auto reset?
cnt <= (others => '0');
elsif (match = '0') and (prsc_tick = '1') then -- count++
cnt <= std_ulogic_vector(unsigned(cnt) + 1);
end if;
end if;
end process counter_update;
 
-- match --
match <= '1' when (cnt = thres) else '0';
 
/neo430/trunk/neo430/rtl/core/neo430_top.vhd
43,7 → 43,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
63,7 → 63,6
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
240,7 → 239,6
-- -----------------------------------------------------------------------------
neo430_cpu_inst: neo430_cpu
generic map (
DADD_USE => DADD_USE, -- implement DADD instruction? (default=true)
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
)
676,7 → 674,6
-- additional configuration --
USER_CODE => USER_CODE, -- custom user code
-- module configuration --
DADD_USE => DADD_USE, -- implement DADD instruction?
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit?
WB32_USE => WB32_USE, -- implement WB32 unit?
WDT_USE => WDT_USE, -- implement WDT?
/neo430/trunk/neo430/rtl/core/neo430_twi.vhd
1,8 → 1,8
-- #################################################################################################
-- # << NEO430 - Two Wire Serial Interface (I2C) >> #
-- # << NEO430 - Two Wire Serial Interface Master (I2C) >> #
-- # ********************************************************************************************* #
-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
-- # No multi-master support yet! #
-- # No multi-master support and no slave mode support yet! #
-- # Interrupt: TWI_transfer_done #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
23,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 05.10.2019 #
-- # Stephan Nolting, Hannover, Germany 09.11.2019 #
-- #################################################################################################
 
library ieee;
60,16 → 60,16
constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit
 
-- control reg bits --
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI is busy
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI unit is busy
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
 
-- dta register flags --
-- data register flags --
constant data_twi_ack_c : natural := 15; -- r/-: Set if ACK received
 
-- access control --
130,24 → 130,22
-- main twi clock select --
twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
 
-- generate four non-overlapping clock ticks at twi_clk/4 each --
-- generate four non-overlapping clock ticks at twi_clk/4 --
clock_phase_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
twi_phase_gen <= "0001"; -- make sure to start with a new phase, 0,1,2,3 stepping
else
if (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
end if;
elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
end if;
end if;
end process clock_phase_gen;
 
twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk;
twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk;
twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
 
 
-- TWI transceiver ----------------------------------------------------------
155,7 → 153,7
twi_rtx_unit: process(clk_i)
begin
if rising_edge(clk_i) then
-- input synchronizer --
-- input synchronizer & sampler --
twi_sda_i_ff0 <= twi_sda_i;
twi_sda_i_ff1 <= twi_sda_i_ff0;
twi_scl_i_ff0 <= twi_scl_i;
162,14 → 160,14
twi_scl_i_ff1 <= twi_scl_i_ff0;
 
-- defaults --
twi_irq_o <= '0';
twi_irq_o <= '0';
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
 
-- arbiter FSM --
-- TWI bus signals are set/sampled using 4 clock phases
case arbiter is
 
when "100" => -- IDLE: waiting for requests, bus is still claimed by the master if no STOP condition was generated
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
when "100" => -- IDLE: waiting for requests, bus might be still claimed by this master if no STOP condition was generated
twi_bitcnt <= (others => '0');
if (wr_en = '1') then
if (addr = twi_ctrl_addr_c) then
178,7 → 176,7
elsif (data_i(ctrl_twi_stop_c) = '1') then -- issue STOP condition
arbiter(1 downto 0) <= "10";
end if;
elsif (addr = twi_rtx_addr_c) then -- start transmission
elsif (addr = twi_rtx_addr_c) then -- start a data transmission
twi_rtx_sreg <= data_i(7 downto 0) & '1'; -- one bit extra for stop condition
arbiter(1 downto 0) <= "11";
end if;
185,8 → 183,6
end if;
 
when "101" => -- START: generate START condition
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
 
if (twi_clk_phase(0) = '1') then
twi_sda_o <= '1';
elsif (twi_clk_phase(1) = '1') then
201,8 → 197,6
end if;
 
when "110" => -- STOP: generate STOP condition
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
 
if (twi_clk_phase(0) = '1') then
twi_sda_o <= '0';
elsif (twi_clk_phase(3) = '1') then
217,8 → 211,6
end if;
 
when "111" => -- TRANSMISSION: transmission in progress
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
 
if (twi_clk_phase(0) = '1') then
twi_bitcnt <= std_ulogic_vector(unsigned(twi_bitcnt) + 1);
twi_scl_o <= '0';
235,7 → 227,7
twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled
end if;
 
when others => -- "0--" OFFLINE: deactivated
when others => -- "0--" OFFLINE: TWI deactivated
twi_sda_o <= '1';
twi_scl_o <= '1';
arbiter <= ctrl(ctrl_twi_en_c) & "00"; -- stay here, go to idle when activated
249,8 → 241,7
-- -----------------------------------------------------------------------------
clock_stretching: process(arbiter, twi_scl_o, twi_scl_i_ff1)
begin
-- clock stretching can occur during data transmission and even during
-- a START or STOP condition
-- clock stretching by the slave can happen at "any time"
if (arbiter(2) = '1') and -- module enabled
(twi_scl_o = '1') and -- master wants to pull scl high
(twi_scl_i_ff1 = '0') then -- but scl is pulled low by slave
/neo430/trunk/neo430/rtl/core/neo430_wdt.vhd
107,6 → 107,7
clk_sel <= (others => '1'); -- slowest clock source
rst_gen <= (others => '1'); -- do NOT fire on reset!
elsif rising_edge(clk_i) then
-- control register write access --
if (wren = '1') then -- allow write if password is correct
enable <= data_i(ctrl_enable_c);
clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
/neo430/trunk/neo430/rtl/top_templates/neo430_test.vhd
23,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
67,7 → 67,6
-- additional configuration --
USER_CODE => x"CAFE", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => true, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
/neo430/trunk/neo430/rtl/top_templates/neo430_top_avm.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
38,7 → 38,6
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
147,7 → 146,6
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
DADD_USE => DADD_USE, -- implement DADD instruction? (default=true)
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
/neo430/trunk/neo430/rtl/top_templates/neo430_top_axi4lite.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
38,7 → 38,6
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
154,7 → 153,6
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
DADD_USE => DADD_USE, -- implement DADD instruction? (default=true)
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
/neo430/trunk/neo430/rtl/top_templates/neo430_top_std_logic.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 17.11.2018 #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- #################################################################################################
 
library ieee;
38,7 → 38,6
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
126,7 → 125,6
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
DADD_USE => DADD_USE, -- implement DADD instruction? (default=true)
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
/neo430/trunk/neo430/sim/ISIM/neo430_tb.wcfg
12,15 → 12,15
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="295936666667fs"></ZoomStartTime>
<ZoomEndTime time="301326666668fs"></ZoomEndTime>
<Cursor1Time time="298031667000fs"></Cursor1Time>
<ZoomStartTime time="335818933334fs"></ZoomStartTime>
<ZoomEndTime time="336035333335fs"></ZoomEndTime>
<Cursor1Time time="335860533000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="167"></NameColumnWidth>
<ValueColumnWidth column_width="77"></ValueColumnWidth>
<ValueColumnWidth column_width="73"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="119" />
<WVObjectSize size="120" />
<wvobject type="divider" fp_name="divider6">
<obj_property name="label">Global</obj_property>
<obj_property name="DisplayName">label</obj_property>
243,19 → 243,23
<obj_property name="label">IO: Timer</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_timer_inst_true/neo430_timer_inst/ctrl" type="array">
<obj_property name="ElementShortName">ctrl[5:0]</obj_property>
<obj_property name="ObjectShortName">ctrl[5:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_timer_inst_true/neo430_timer_inst/thres" type="array">
<obj_property name="ElementShortName">thres[15:0]</obj_property>
<obj_property name="ObjectShortName">thres[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_timer_inst_true/neo430_timer_inst/cnt" type="array">
<obj_property name="ElementShortName">cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">cnt[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_timer_inst_true/neo430_timer_inst/irq_o" type="logic">
<obj_property name="ElementShortName">irq_o</obj_property>
<obj_property name="ObjectShortName">irq_o</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_timer_inst_true/neo430_timer_inst/cnt" type="array">
<obj_property name="ElementShortName">cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">cnt[15:0]</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider22">
<obj_property name="label">IO: GPIO</obj_property>
<obj_property name="DisplayName">label</obj_property>
/neo430/trunk/neo430/sim/neo430_tb.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hanover, Germany 23.09.2019 #
-- # Stephan Nolting, Hannover, Germany 14.11.2019 #
-- #################################################################################################
 
library ieee;
96,7 → 96,6
-- additional configuration --
USER_CODE => x"4788", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => true, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WBT? (default=true)
153,14 → 152,14
-- -----------------------------------------------------------------------------
interrupt_gen: process
begin
irq <= '0';
wait for 20 ms;
wait until rising_edge(clk_gen);
irq <= '1';
wait for t_clock_c;
wait until rising_edge(irq_ack);
irq <= '0';
wait;
--irq <= '0';
--wait for 20 ms;
--wait until rising_edge(clk_gen);
--irq <= '1';
--wait for t_clock_c;
--wait until rising_edge(irq_ack);
--irq <= '0';
--wait;
end process interrupt_gen;
 
 
/neo430/trunk/neo430/sw/bootloader/Makefile
19,7 → 19,7
# You should have received a copy of the GNU Lesser General Public License along with this #
# source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
# ********************************************************************************************* #
# Stephan Nolting, Hannover, Germany 04.10.2019 #
# Stephan Nolting, Hannover, Germany 09.11.2019 #
#################################################################################################
 
 
89,6 → 89,7
 
# Compiler flags
CC_OPTS = -mcpu=msp430 -pipe -Wall -Xassembler --mY -mhwmult=none -fno-delete-null-pointer-checks
CC_OPTS += -Wl,-static -mrelax -minrt -nostartfiles -fdata-sections -ffunction-sections -Xlinker --gc-sections
 
# Linker flags
LD_OPTS = -mcpu=msp430 -mrelax -minrt -nostartfiles
/neo430/trunk/neo430/sw/bootloader/bootloader.c
29,7 → 29,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 19.09.2019 #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// #################################################################################################
 
// Libraries
45,7 → 45,7
#define AUTOBOOT_TIMEOUT 8 // countdown (seconds) to auto boot
#define STATUS_LED 0 // GPIO.out(0) is status LED
 
// 25LC512 EEPROM
// 25LC512 SPI EEPROM
#define BOOT_EEP_CS 0 // boot EEPROM CS (SPI.CS0)
#define EEP_IMAGE_BASE 0x00 // base address of NEO430 boot image
#define EEP_WRITE 0x02 // initialize start of write sequence
53,9 → 53,13
#define EEP_RDSR 0x05 // read status register
#define EEP_WREN 0x06 // write enable
 
// 24LC512 TWI EEPROM
#define TWI_BOOT_EEP_ADDR_READ 0b10100001 // READ address of TWI boot eeprom
 
// Image sources
#define UART_IMAGE 0x00
#define EEPROM_IMAGE 0x01
#define EEPROM_IMAGE_SPI 0x01
#define EEPROM_IMAGE_TWI 0x02
 
// Error codes
#define ERROR_EEPROM 0x00 // EEPROM access error
75,8 → 79,9
void core_dump(void);
void store_eeprom(void);
void eeprom_write_word(uint16_t a, uint16_t d);
void eeprom_write_byte(uint16_t a, uint8_t b);
uint8_t eeprom_read_byte(uint16_t a);
void spi_eeprom_write_byte(uint16_t a, uint8_t b);
uint8_t spi_eeprom_read_byte(uint16_t a);
uint8_t twi_eeprom_read_byte(uint16_t a);
void get_image(uint8_t src);
uint16_t get_image_word(uint16_t a, uint8_t src);
void __attribute__((__naked__)) system_error(uint8_t err_code);
122,8 → 127,8
neo430_uart_char_read(); // clear UART RX buffer
 
// set SPI config:
// enable SPI, no IRQs, SPI clock mode 0, 1/128 SPI speed, disable all 6 SPI CS lines (set high)
neo430_spi_enable(SPI_PRSC_128); // this also resets the SPI module
// enable SPI, no IRQs, MSB first, SPI clock mode 0, 1/128 SPI speed, disable all 6 SPI CS lines (set high)
neo430_spi_enable(SPI_PRSC_64); // this also resets the SPI module
neo430_spi_trans(0); // clear SPI RTX buffer
 
// Timeout counter: init timer, irq tick @ ~1Hz (prescaler = 4096)
133,8 → 138,7
TMR_THRES = (CLOCKSPEED_HI << 2) -1; // "fake" ;D
// enable timer, auto reset, enable IRQ, prsc = 1:2^16
TMR_CT = (1<<TMR_CT_EN) | (1<<TMR_CT_ARST) | (1<<TMR_CT_IRQ) | ((16-1)<<TMR_CT_PRSC0);
TMR_CNT = 0;
TIMEOUT_CNT = 0; // timeout ticker
TIMEOUT_CNT = 0; // console timeout ticker
 
neo430_clear_irq_buffer(); // clear all pending interrupts
neo430_eint(); // enable global interrupts
143,7 → 147,7
// ****************************************************************
// Show bootloader intro and system information
// ****************************************************************
neo430_uart_br_print("\n\nNEO430 Bootloader V20190919\nBy Stephan Nolting\n\n"
neo430_uart_br_print("\n\nNEO430 Bootloader V20191113\nBy Stephan Nolting\n\n"
"HWV: 0x");
neo430_uart_print_hex_word(HW_VERSION);
neo430_uart_br_print("\nUSR: 0x");
167,7 → 171,7
 
// timeout? start auto boot sequence
if (TIMEOUT_CNT == 4*AUTOBOOT_TIMEOUT) { // in 0.25 seconds
get_image(EEPROM_IMAGE); // try loading from EEPROM
get_image(EEPROM_IMAGE_SPI); // try loading from EEPROM
neo430_uart_br_print("\n");
start_app(); // start app if loading was successful
}
200,7 → 204,7
else if (c == 'p') // program EEPROM from RAM
store_eeprom();
else if (c == 'e') // copy program from EEPROM to RAM
get_image(EEPROM_IMAGE);
get_image(EEPROM_IMAGE_SPI);
else if (c == 's') // start program in RAM
start_app();
else // unknown command
263,18 → 267,18
 
uint16_t *pnt = (uint16_t*)0x0000;
uint16_t i = 0, j = 0;
 
while (1) {
neo430_uart_br_print("\n");
neo430_uart_print_hex_word((uint16_t)pnt); // print address
neo430_uart_br_print(": ");
 
// print hexadecimal data
for (i=0; i<16; i++) {
neo430_uart_print_hex_word(*pnt++);
neo430_uart_putc(' ');
}
 
// user abort or all done?
if ((neo430_uart_char_received() != 0) || (j == 0xFFE0))
return;
297,13 → 301,13
 
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_WREN); // write enable
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
// check if eeprom ready (or available at all)
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_RDSR); // read status register CMD
uint8_t b = neo430_spi_trans(0x00); // read status register data
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
if ((b & 0x8F) != 0x02)
system_error(ERROR_EEPROM);
344,21 → 348,21
uint8_t lo = (uint8_t)(d);
uint8_t hi = (uint8_t)(d >> 8);
eeprom_write_byte(a+0, hi);
eeprom_write_byte(a+1, lo);
spi_eeprom_write_byte(a+0, hi);
spi_eeprom_write_byte(a+1, lo);
}
 
 
/* ------------------------------------------------------------
* INFO EEPROM write single byte
* INFO SPI EEPROM write single byte
* PARAM a destination address (16 bit)
* PARAM b byte to be written
* ------------------------------------------------------------ */
void eeprom_write_byte(uint16_t a, uint8_t b) {
void spi_eeprom_write_byte(uint16_t a, uint8_t b) {
 
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_WREN); // write enable
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_WRITE); // byte write instruction
365,7 → 369,7
neo430_spi_trans((uint8_t)(a >> 8));
neo430_spi_trans((uint8_t)(a >> 0));
neo430_spi_trans(b);
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
// wait for write to finish
while(1) {
372,7 → 376,7
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_RDSR); // read status register CMD
uint8_t s = neo430_spi_trans(0x00);
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
if ((s & 0x01) == 0) { // check WIP flag
break; // done!
382,11 → 386,11
 
 
/* ------------------------------------------------------------
* INFO EEPROM read data
* INFO SPI EEPROM read data
* PARAM a destination address (16 bit)
* RETURN byte read data
* ------------------------------------------------------------ */
uint8_t eeprom_read_byte(uint16_t a) {
uint8_t spi_eeprom_read_byte(uint16_t a) {
 
neo430_spi_cs_en(BOOT_EEP_CS);
neo430_spi_trans(EEP_READ); // byte read instruction
393,7 → 397,7
neo430_spi_trans((uint8_t)(a >> 8));
neo430_spi_trans((uint8_t)(a >> 0));
uint8_t d = neo430_spi_trans(0);
neo430_spi_cs_dis(BOOT_EEP_CS);
neo430_spi_cs_dis();
 
return d;
}
400,8 → 404,30
 
 
/* ------------------------------------------------------------
* INFO TWI EEPROM read data
* PARAM a destination address (16 bit)
* RETURN byte read data
* ------------------------------------------------------------ */
uint8_t twi_eeprom_read_byte(uint16_t a) {
 
uint8_t twi_err = neo430_twi_start_trans(TWI_BOOT_EEP_ADDR_READ);
twi_err |= neo430_twi_trans((uint8_t)(a >> 8));
twi_err |= neo430_twi_trans((uint8_t)(a >> 0));
twi_err |= !neo430_twi_trans(0xFF); // read data
uint8_t d = neo430_twi_get_data();
neo430_twi_generate_stop();
 
//if (twi_err) {
//
//}
 
return d;
}
 
 
/* ------------------------------------------------------------
* INFO Get IMEM image from SPI EEPROM at SPI.CS0 or from UART
* PARAM src Image source 0: UART, 1: EEPROM
* PARAM src Image source 0: UART, 1: SPI_EEPROM
* RETURN error code (0 if successful)
* ------------------------------------------------------------ */
void get_image(uint8_t src) {
414,7 → 440,7
// print intro
if (src == UART_IMAGE) // boot via UART
neo430_uart_br_print("Awaiting BINEXE... ");
else //if (src == EEPROM_IMAGE)// boot from EEPROM
else //if (src == EEPROM_IMAGE_SPI)// boot from EEPROM
neo430_uart_br_print("Loading... ");
 
// check if valid image
456,9 → 482,9
 
 
/* ------------------------------------------------------------
* INFO Get image word from EEPROM or UART
* INFO Get image word from SPI_EEPROM or UART
* PARAM a source address (16 bit)
* PARAM src: 0: UART, 1: EEPROM
* PARAM src: 0: UART, 1: SPI_EEPROM
* RETURN accessed data word
* ------------------------------------------------------------ */
uint16_t get_image_word(uint16_t a, uint8_t src) {
470,10 → 496,14
c0 = (uint8_t)neo430_uart_getc();
c1 = (uint8_t)neo430_uart_getc();
}
else { //if (src == EEPROM_IMAGE) // get image data from EEPROM
c0 = eeprom_read_byte(a+0);
c1 = eeprom_read_byte(a+1);
else if (src == EEPROM_IMAGE_SPI) { // get image data from SPI EEPROM
c0 = spi_eeprom_read_byte(a+0);
c1 = spi_eeprom_read_byte(a+1);
}
else { // if (src == EEPROM_IMAGE_TWI) // get image data from TWI EEPROM
//c0 = twi_eeprom_read_byte(a+0);
//c1 = twi_eeprom_read_byte(a+1);
}
 
//uint16_t r = (((uint16_t)c0) << 8) | (((uint16_t)c1) << 0);
uint16_t r = neo430_combine_bytes(c0, c1);
489,7 → 519,7
* ------------------------------------------------------------ */
void __attribute__((__naked__)) system_error(uint8_t err_code){
 
neo430_uart_br_print("\a\nERR_");
neo430_uart_br_print("\a\nERR_"); // output error code with annoying bell sound
neo430_uart_print_hex_byte(err_code);
 
asm volatile ("mov #0, r2"); // deactivate IRQs, no more write access to IMEM
/neo430/trunk/neo430/sw/example/blink_led/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/cfu_test/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/crc_test/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/game_of_life/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/gpio_interrupt/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/hw_analysis/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/hw_analysis/main.c
21,7 → 21,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 23.09.2019 #
// # Stephan Nolting, Hannover, Germany 14.11.2019 #
// #################################################################################################
 
 
87,46 → 87,60
// System features
// --------------------------------------------
uint16_t ft = SYS_FEATURES;
neo430_printf("\n\nSystem features\n");
neo430_printf("\nSystem features\n");
 
// CFU
neo430_printf("- Multiplier/Divider: ");
print_state(ft & (1<<SYS_MULDIV_EN));
 
// WB32
neo430_printf("- Wishbone adapter: ");
neo430_printf("- Wishbone Adapter: ");
print_state(ft & (1<<SYS_WB32_EN));
 
// WDT
neo430_printf("- Watchdog timer: ");
neo430_printf("- Watchdog Timer: ");
print_state(ft & (1<<SYS_WDT_EN));
 
// GPIO
neo430_printf("- GPIO unit: ");
neo430_printf("- GPIO Unit: ");
print_state(ft & (1<<SYS_GPIO_EN));
 
// TIMER
neo430_printf("- High-precision timer: ");
neo430_printf("- High-Precision Timer: ");
print_state(ft & (1<<SYS_TIMER_EN));
 
// UART
neo430_printf("- UART: ");
print_state(ft & (1<<SYS_UART_EN));
 
// SPI
neo430_printf("- SPI: ");
print_state(ft & (1<<SYS_SPI_EN));
 
// DADD
neo430_printf("- DADD instruction: ");
neo430_printf("- DADD Instruction: ");
print_state(ft & (1<<SYS_DADD_EN));
 
// Bootloader installed
neo430_printf("- Internal bootloader: ");
neo430_printf("- Internal Bootloader: ");
print_state(ft & (1<<SYS_BTLD_EN));
 
// is IMEM true ROM?
neo430_printf("- IMEM as true ROM: ");
neo430_printf("- IMEM as True ROM: ");
print_state(ft & (1<<SYS_IROM_EN));
 
// CRC
neo430_printf("- CRC16/CRC32: ");
print_state(ft & (1<<SYS_CRC_EN));
 
// CFU
neo430_printf("- Custom Functions Unit: ");
print_state(ft & (1<<SYS_CFU_EN));
 
// PWM
neo430_printf("- PWM Controller: ");
print_state(ft & (1<<SYS_PWM_EN));
 
// TWI
neo430_printf("- Two Wire Interface: ");
print_state(ft & (1<<SYS_TWI_EN));
/neo430/trunk/neo430/sw/example/makefile
19,7 → 19,7
# You should have received a copy of the GNU Lesser General Public License along with this #
# source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
# ********************************************************************************************* #
# Stephan Nolting, Hannover, Germany 01.01.2019 #
# Stephan Nolting, Hannover, Germany 13.11.2019 #
#################################################################################################
 
 
29,7 → 29,7
.SUFFIXES:
.DEFAULT_GOAL := help
 
TOPTARGETS := all clean_all
TOPTARGETS := compile clean_all
 
SUBDIRS := $(wildcard */.)
# ignore dummy folders (starting with '~')
50,7 → 50,7
@echo "Compile / clean up ALL project folders in this directory"
@echo "Targets:"
@echo " help - show this text"
@echo " all - compile and install all projects"
@echo " compile - compile all projects"
@echo " clean_all - clean up everything"
 
/neo430/trunk/neo430/sw/example/morse_translator/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/muldiv_test/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/nested_irqs/main.c
22,7 → 22,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 20.04.2019 #
// # Stephan Nolting, Hannover, Germany 14.11.2019 #
// #################################################################################################
 
 
32,7 → 32,6
 
// Configuration
#define BAUD_RATE 19200
#define CLOCK_FREQ 1000 // in Hz
 
// Function prototypes
void __attribute__((__interrupt__)) timer_irq_handler(void);
39,7 → 38,7
void __attribute__((__interrupt__)) uart_irq_handler(void);
 
// Variable
volatile uint64_t time;
volatile uint64_t time_ms;
 
 
/* ------------------------------------------------------------
59,11 → 58,11
 
 
// reset time
time = 0;
time_ms = 0;
 
 
// intro text
neo430_uart_br_print("\nClock example. Press any key to show the current time.\n");
//neo430_uart_br_print("\nClock example. Press any key to show the current time.\n");
 
 
// init TIMER IRQ
73,10 → 72,13
IRQVEC_TIMER = (uint16_t)(&timer_irq_handler);
 
// configure timer frequency
if (neo430_config_timer_period(CLOCK_FREQ))
neo430_timer_disable();
if (neo430_timer_config_period(1000)) // 1kHz to increment every 1ms
neo430_uart_br_print("Invalid TIMER frequency!\n");
 
neo430_printf("THR: %x, CTR: %x\n", TMR_THRES, TMR_CT);
TMR_CT |= (1<<TMR_CT_EN) | (1<<TMR_CT_ARST) | (1<<TMR_CT_IRQ); // enable timer, auto-reset, irq enabled
neo430_printf("THR: %x, CTR: %x\n", TMR_THRES, TMR_CT);
 
 
// init UART RX IRQ
107,7 → 109,7
* ------------------------------------------------------------ */
void __attribute__((__interrupt__)) timer_irq_handler(void) {
 
time++;
time_ms++;
}
 
 
120,10 → 122,11
neo430_eint();
 
// show time
uint32_t current_time = time/CLOCK_FREQ; // in seconds
uint16_t hour = (uint16_t)( (current_time/3600)%24 );
uint16_t minute = (uint16_t)( (current_time/60)%60 );
uint16_t second = (uint16_t)( (current_time%60) );
neo430_printf("Current runtime: %u:%u:%u\n", hour, minute, second);
uint32_t current_time = time_ms; // in seconds
uint16_t hour = (uint16_t)( (((current_time/10000)/60)/3600)%24 );
uint16_t minute = (uint16_t)( ((current_time/1000)/60)%60 );
uint16_t second = (uint16_t)( (current_time/1000)%60 );
uint16_t m_second = (uint16_t)( (current_time%1000)%1000 );
neo430_printf("Current runtime: %u:%u:%u:%u\n", hour, minute, second, m_second);
}
 
/neo430/trunk/neo430/sw/example/nested_irqs/makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/prime_numbers/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/pwm_demo/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/timer_simple/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/timer_simple/main.c
21,7 → 21,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 17.11.2018 #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// #################################################################################################
 
 
65,7 → 65,8
IRQVEC_TIMER = (uint16_t)(&timer_irq_handler);
 
// configure timer frequency
if (neo430_config_timer_period(BLINK_FREQ))
neo430_timer_disable();
if (neo430_timer_config_period(BLINK_FREQ))
neo430_uart_br_print("Invalid TIMER frequency!\n");
 
TMR_CT |= (1<<TMR_CT_EN) | (1<<TMR_CT_ARST) | (1<<TMR_CT_IRQ); // enable timer, auto-reset, irq enabled
/neo430/trunk/neo430/sw/example/twi_test/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/twi_test/main.c
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 10.10.2019 #
// # Stephan Nolting, Hannover, Germany 14.11.2019 #
// #################################################################################################
 
 
36,7 → 36,10
// Configuration
#define BAUD_RATE 19200
 
// Global variables
uint16_t bus_claimed;
 
 
/* ------------------------------------------------------------
* INFO Main function
* ------------------------------------------------------------ */
64,6 → 67,7
// init TWI
// SCL clock speed = f_cpu / (4 * PRSC)
neo430_twi_enable(TWI_PRSC_2048); // second slowest
bus_claimed = 0; // no active bus session
 
// Main menu
for (;;) {
81,16 → 85,25
" scan - scan bus for devices\n"
" start - generate START condition\n"
" stop - generate STOP condition\n"
" send - write/read single byte to/from bus\n"
" send - write & read single byte to/from bus\n"
" speed - select bus clock\n"
" reset - perform soft-reset\n"
" exit - exit program and return to bootloader\n");
" exit - exit program and return to bootloader\n\n"
"Start a new transmission by generating a START condition. Next, transfer the 7-bit device address\n"
"and the R/W flag. After that, transfer your data to be written or send a 0xFF if you want to read\n"
"data from the bus. Finish the transmission by generating a STOP condition.\n");
}
else if (!strcmp(buffer, "start")) {
neo430_twi_generate_start(); // generate START condition
bus_claimed = 1;
}
else if (!strcmp(buffer, "stop")) {
if (bus_claimed == 0) {
neo430_uart_br_print("No active I2C transmission.\n");
continue;
}
neo430_twi_generate_stop(); // generate STOP condition
bus_claimed = 0;
}
else if (!strcmp(buffer, "scan")) {
scan_twi();
170,7 → 183,7
neo430_twi_generate_stop();
 
if (twi_ack == 0) {
neo430_uart_br_print(" * Found device at address (shifted left by 1 bit): 0x");
neo430_uart_br_print("+ Found device at write-address 0x");
neo430_uart_print_hex_byte(2*i);
neo430_uart_br_print("\n");
num_devices++;
190,6 → 203,11
 
char terminal_buffer[4];
 
if (bus_claimed == 0) {
neo430_uart_br_print("No active I2C transmission. Generate a START condition first.\n");
return;
}
 
// enter data
neo430_uart_br_print("Enter TX data (2 hex chars): ");
neo430_uart_scan(terminal_buffer, 3, 1); // 2 hex chars for address plus '\0'
/neo430/trunk/neo430/sw/example/uart_irq/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/uart_irq/main.c
22,7 → 22,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 17.11.2018 #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// #################################################################################################
 
 
82,9 → 82,8
UART_CT |= (1<<UART_CT_RX_IRQ);
 
// configure TIMER period
TMR_THRES = 1; // very high sample rate ;)
// clear timer counter
TMR_CNT = 0;
neo430_timer_disable();
TMR_THRES = 1;
 
// configure timer operation
TMR_CT = (1<<TMR_CT_EN) | // enable timer
/neo430/trunk/neo430/sw/example/wb_terminal/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/example/wdt_test/Makefile
140,7 → 140,7
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@ rm -f text.dat rodata.dat data.dat
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_aux.h File deleted
/neo430/trunk/neo430/sw/lib/neo430/include/neo430.h
23,7 → 23,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 23.09.2019 #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// #################################################################################################
 
#ifndef neo430_h
168,6 → 168,7
#define SPI_CT_CS_SEL1 7 // r/w: spi CS select 1
#define SPI_CT_CS_SEL2 8 // r/w: spi CS select 2
#define SPI_CT_CS_SET 9 // r/w: selected CS becomes active ('0') when set
#define SPI_CT_DIR 10 // r/w: shift direction (0: MSB first, 1: LSB first)
 
#define SPI_CT_BUSY 15 // r/-: spi transceiver is busy
 
195,7 → 196,7
// High-Precision Timer (TIMER)
// ----------------------------------------------------------------------------
#define TMR_CT (*(REG16 0xFFB0)) // r/w: control register
#define TMR_CNT (*(REG16 0xFFB2)) // r/w: counter register
#define TMR_CNT (*(ROM16 0xFFB2)) // r/-: counter register
#define TMR_THRES (*(REG16 0xFFB4)) // r/w: threshold register
//#define reserved (*(REG16 0xFFB6))
 
380,7 → 381,6
// ----------------------------------------------------------------------------
// Include all IO library headers
// ----------------------------------------------------------------------------
#include "neo430_aux.h"
#include "neo430_cpu.h"
#include "neo430_crc.h"
#include "neo430_gpio.h"
387,6 → 387,7
#include "neo430_muldiv.h"
#include "neo430_pwm.h"
#include "neo430_spi.h"
#include "neo430_timer.h"
#include "neo430_twi.h"
#include "neo430_uart.h"
#include "neo430_wdt.h"
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_timer.h
0,0 → 1,34
// #################################################################################################
// # < neo430_timer.h - Tim helper functions ;) > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// #################################################################################################
 
#ifndef neo430_timer_h
#define neo430_timer_h
 
// prototypes
void neo430_timer_enable(void);
void neo430_timer_disable(void);
void neo430_timer_reset(void);
uint8_t neo430_timer_config_period(uint32_t f_timer);
 
#endif // neo430_timer_h
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_aux.c File deleted
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_cpu.c
191,7 → 191,7
 
/* ------------------------------------------------------------
* INFO Binary-coded decimal addition
* WARNING Make sure the DADD unit is syntheszied!!!!
* WARNING MAKE SURE THE DADD UNIT IS SYNTHESIZED!!!
* PARAM 2x 16-bit BCD operands (4 digits)
* RETURN 16-bit BCD result (4 digits)
* ------------------------------------------------------------ */
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_timer.c
0,0 → 1,90
// #################################################################################################
// # < neo430_timer.h - Timer helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 14.11.2019 #
// #################################################################################################
 
#include "neo430.h"
#include "neo430_timer.h"
 
 
/* ------------------------------------------------------------
* INFO Activate Timer
* ------------------------------------------------------------ */
void neo430_timer_enable(void) {
 
TMR_CT |= (1<<TMR_CT_EN);
}
 
 
/* ------------------------------------------------------------
* INFO Dectivate Timer
* ------------------------------------------------------------ */
void neo430_timer_disable(void) {
 
TMR_CT &= ~(1<<TMR_CT_EN);
}
 
 
/* ------------------------------------------------------------
* INFO Reset Timer
* ------------------------------------------------------------ */
void neo430_timer_reset(void) {
 
neo430_timer_disable();
neo430_timer_enable();
}
 
 
/* ------------------------------------------------------------
* INFO Configure timer period
* PARAM Timer frequency in Hz (1Hz ... F_CPU/2)
* RETURN 0 if successful, !=0 if error
* ------------------------------------------------------------ */
uint8_t neo430_timer_config_period(uint32_t f_timer) {
 
uint32_t clock = CLOCKSPEED_32bit;
uint32_t ticks = (clock / f_timer) >> 1; // divide by lowest prescaler (= f/2)
 
uint8_t prsc = 0;
 
if (ticks == 0)
return 0xff; // frequency too high!
 
// find prescaler
while(prsc < 8) {
if (ticks <= 0x0000ffff)
break;
else {
if ((prsc == 2) || (prsc == 4))
ticks >>= 3;
else
ticks >>= 1;
prsc++;
}
}
 
TMR_THRES = (uint16_t)ticks;
TMR_CT &= ~(7<<TMR_CT_PRSC0); // clear prsc bits
TMR_CT |= (prsc<<TMR_CT_PRSC0);
 
return 0;
}

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