OpenCores
URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

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/neo430/trunk/neo430/README.md
14,44 → 14,41
Welcome to the __NEO430 Processor__ project!
 
You need a small but still powerful, customizable and microcontroller-like
processor system for your next FPGA design? Then the NEO430 is the perfect
choice for you!
processor system for your next FPGA project? Then the NEO430 is the right
choice for you.
 
This processor is based on the Texas Instruments MSP430(TM) ISA and provides 100%
This processor is based on the Texas Instruments MSP430(TM) ISA and provides full
compatibility with the original instruction set. The NEO430 is not an MSP430
clone – it is more a complete new implementation from the bottom up. The
clone – it is more like a complete new implementation from the bottom up. The
processor features a very small outline, already implementing standard
features like a timer, a watchdog, UART, TWI and SPI serial interfaces, general
purpose IO ports, an internal bootloader and of course internal memory for
program code and data. All of the peripheral modules are optional – so if you
do not need them, you can exclude them from implementation to reduce the size
program code and data. All of the implemented peripheral modules are optional – so if you
do not need them, you can exclude them from synthesis to reduce the size
of the system. Any additional modules, which make a more customized system,
can be connected via a Wishbone-compatible bus interface. By this, you can
built a system, that perfectly fits your needs.
can be connected via a Wishbone-compatible bus interface or directly implemented within the
processor. By this, you can built a system, that perfectly fits your needs.
 
It is up to you to use the NEO430 as stand-alone, configurable and extensible
microcontroller, or to include it as controller within a more complex SoC
design.
microcontroller, or to use it as controller within a more complex SoC design.
 
The high-level software development is based on the free TI msp430-gcc
compiler tool chain. You can either use Windows or Linux as build
environment for your applications – the project comes with build scripts
for both worlds. The sw\example folder of this project features several demo
programs from which you can start creating your own NEO430 applications.
compiler tool chain. You can either use Windows (PowerShell or Linux Subsystem) or
Linux as build environment for your applications – the project supports both worlds.
 
This project is intended to work "out of the box". Just synthesize the test
setup from this project, upload it to your FPGA board of choice (the NEO430 uses
a vendor-independent VHDL description) and start exploring the capabilities of
the NEO430 processor. Application program generation (and installation) works
by executing a single "make" command. Jump to the "Let’s Get It Started"
chapter, which provides a lot of guides and tutorials to make your first
NEO430 setup run:
a FPGA vendor-independent VHDL description) and start exploring the capabilities of
the NEO430 processor. Application program generation works by executing a single "make"
command. Jump to the "Let’s Get It Started" chapter in the NEO430 documentary, which provides
a lot of guides and tutorials to make your first NEO430 setup run:
https://github.com/stnolting/neo430/blob/master/doc/NEO430.pdf
 
 
## Processor Features
 
<img src="https://github.com/stnolting/neo430/blob/master/doc/figures/neo430_arch.png" width="500px"/>
![NEO430 Overview](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/neo430_arch.png)
 
(optional modules are marked using dashed lines in the figure above)
 
 
102,8 → 99,9
## Implementation Results
 
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes
all optional processor modules (excluding the CFU and DADD), an IMEM size of 4kB and a DMEM size of 2kB.
Results generated with Xilinx Vivado 2017.3, Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.0 (Synplify)
all optional processor modules (excluding the CFU and DADD instruction), an IMEM size of 4kB and a DMEM size of 2kB.
The minimal configuration only includes the CPU and the GPIO module. Results generated with Xilinx Vivado 2017.3,
Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.0 (Synplify)
 
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|:----------------------------------------|:----------:|:----------:|:--------:|:------:|:-------:|
129,7 → 127,7
numbers only represent a coarse overview as logic elements might be merged and optimized beyond module boundaries.
 
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes all optional
processor modules (excluding the CFU and DADD), an IMEM size of 4kB and a DMEM size of 2kB. Results were generated
processor modules (excluding the CFU and DADD instruction), an IMEM size of 4kB and a DMEM size of 2kB. Results were generated
using Intel Quartus Prime Lite 17.1.
 
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
160,23 → 158,23
git clone https://github.com/stnolting/neo430.git
~~~
 
* Next, install the compiler toolchain from the TI homepage (select the "compiler only" package):
* Next, install the compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):
 
http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
 
* Make sure GNU Make and a native C compiler (GCC) are installed (double check for the newest version)
* Make sure GNU Make and a native C compiler (GCC) are installed (double check for the newest versions)
 
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary:
 
https://github.com/stnolting/neo430/blob/master/doc/NEO430.pdf
https://github.com/stnolting/neo430/blob/master/doc/NEO430.pdf
 
* The NEO430 documentary will guide you to create a simple test setup, which serves as "hello world" FPGA demo:
 
<img src="https://github.com/stnolting/neo430/blob/master/doc/figures/test_setup.jpg" width="400px"/>
![NEO430 Test Example Setup](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/test_setup.jpg)
 
* This project also includes some example programs, from which you can start:
* The NEO430 project also includes some example programs from which you can start your own application:
 
https://github.com/stnolting/neo430/tree/master/sw/example
https://github.com/stnolting/neo430/tree/master/sw/example
 
* Have fun! =)
 
183,7 → 181,8
 
## Contact
 
If you have any questions, bug reports, ideas or if you are facing problems with the NEO430, feel free to drop me a line:
If you have any questions, bug reports, ideas or if you are facing problems with the NEO430, feel free to drop me a line.
I'm always happy to hear what cool projects you are realizing with this core :smiley:
 
stnolting@gmail.com
 
229,4 → 228,7
 
 
 
<img src="https://github.com/stnolting/neo430/blob/master/doc/figures/oshw_logo.png" width="100px"/>
![OpenHardware Logo](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/oshw_logo.png)
 
 
Made with :blue_heart: in Hannover, Germany.
/neo430/trunk/neo430/doc/figures/neo430_arch.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/doc/figures/oshw_logo.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/rtl/core/neo430_alu.vhd
1,7 → 1,7
-- #################################################################################################
-- # << NEO430 - Arithmetical/Logical Unit >> #
-- # ********************************************************************************************* #
-- # Main data processing ALU and temporary operand registers. #
-- # Main data processing ALU and operand registers. #
-- # BCD arithmetic operations need 2 cycles, all other operations only take one cycle. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 15.11.2019 #
-- #################################################################################################
 
library ieee;
139,9 → 139,9
end process binary_arithmetic_core;
 
 
-- Decimal Arithmetic Core --------------------------------------------------
-- Binary Coded Decimal Arithmetic Core -------------------------------------
-- -----------------------------------------------------------------------------
decimal_arithmetic_core: process(op_a_ff, op_b_ff, sreg_i)
bcd_arithmetic_core: process(op_a_ff, op_b_ff, sreg_i)
variable dsum_ll_v, dsum_lh_v, dsum_hl_v, dsum_hh_v : std_ulogic_vector(4 downto 0);
begin
-- four 4-bit BCD adders --
156,7 → 156,7
dadd_res(11 downto 08) <= dsum_hl_v(3 downto 0);
dadd_res(15 downto 12) <= dsum_hh_v(3 downto 0);
dadd_res(16) <= dsum_hh_v(4);
end process decimal_arithmetic_core;
end process bcd_arithmetic_core;
 
 
-- DADD Pipeline Register ---------------------------------------------------
169,7 → 169,7
end process dadd_pipe_reg;
 
-- implement DADD instruction? --
dadd_res_in <= dadd_res_ff when (use_dadd_cmd_c = true) else (others => '0');
dadd_res_in <= dadd_res_ff when (use_dadd_cmd_c = true) else (others => '-');
 
 
-- ALU Core -----------------------------------------------------------------
185,36 → 185,21
 
-- function selection --
case ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) is
when alu_add_c => -- r <= a + b
when alu_add_c | alu_addc_c | alu_sub_c | alu_subc_c | alu_cmp_c =>
-- alu_add_c : r <= a + b
-- alu_addc_c : r <= a + b + c
-- alu_sub_c : r <= b - a
-- alu_subc_c : r <= b - a - 1 + c
-- alu_cmp_c : b - a (no write back, done by ctrl arbiter)
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
 
when alu_addc_c => -- r <= a + b + c
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
 
when alu_sub_c => -- r <= b - a
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
 
when alu_subc_c => -- r <= b - a - 1 + c
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
 
when alu_dadd_c => -- r <= a + b + c (decimal)
alu_res <= dadd_res_in(15 downto 0);
flag_o(flag_c_c) <= dadd_res_in(16);
flag_o(flag_v_c) <= '0';
 
when alu_cmp_c => -- b - a (no write back, done by ctrl arbiter)
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
 
when alu_and_c => -- r <= a & b
alu_res <= op_a_ff and op_b_ff;
flag_o(flag_c_c) <= not zero;
247,22 → 232,23
flag_o(flag_c_c) <= not zero;
flag_o(flag_v_c) <= '0';
 
when alu_rra_c => -- r <= a >> 1, rotate right arithmetically
alu_res <= op_a_ff(15) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= op_a_ff(7);
when alu_rra_c | alu_rrc_c =>
-- alu_rra_c : r <= a >> 1, rotate right arithmetically
-- alu_rrc_c : r <= a >> 1, rotate right through carry
if (ctrl_i(ctrl_alu_cmd1_c) = alu_rra_c(1)) then -- alu_rra_c
alu_res <= op_a_ff(15) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= op_a_ff(7);
end if;
else -- alu_rrc_c
alu_res <= sreg_i(sreg_c_c) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= sreg_i(sreg_c_c);
end if;
end if;
flag_o(flag_c_c) <= op_a_ff(0);
flag_o(flag_v_c) <= '0';
 
when alu_rrc_c => -- r <= a >> 1, rotate right through carry
alu_res <= sreg_i(sreg_c_c) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= sreg_i(sreg_c_c);
end if;
flag_o(flag_c_c) <= op_a_ff(0);
flag_o(flag_v_c) <= '0';
 
when alu_sxt_c => -- r <= a, sign extend byte
for i in 8 to 15 loop
alu_res(i) <= op_a_ff(7);
278,19 → 264,12
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
 
when alu_mov_c => -- r <= a
when others => -- alu_mov_c : r <= a
alu_res <= op_a_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
 
when others => -- undefined
alu_res <= op_a_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
end case;
end process alu_core;
 
/neo430/trunk/neo430/rtl/core/neo430_bootloader_image.vhd
13,7 → 13,7
000002 => x"5211",
000003 => x"fffa",
000004 => x"8321",
000005 => x"3d9d",
000005 => x"3d98",
000006 => x"120f",
000007 => x"120e",
000008 => x"120d",
23,7 → 23,7
000012 => x"c004",
000013 => x"435c",
000014 => x"12b0",
000015 => x"f658",
000015 => x"f64e",
000016 => x"413b",
000017 => x"413c",
000018 => x"413d",
31,9 → 31,9
000020 => x"413f",
000021 => x"1300",
000022 => x"403c",
000023 => x"f698",
000023 => x"f68e",
000024 => x"12b0",
000025 => x"f56c",
000025 => x"f562",
000026 => x"403d",
000027 => x"ffa0",
000028 => x"4d2c",
45,9 → 45,9
000034 => x"4030",
000035 => x"f042",
000036 => x"403c",
000037 => x"f6a5",
000037 => x"f69b",
000038 => x"12b0",
000039 => x"f56c",
000039 => x"f562",
000040 => x"4130",
000041 => x"120a",
000042 => x"1209",
55,976 → 55,971
000044 => x"1207",
000045 => x"1206",
000046 => x"1205",
000047 => x"1204",
000048 => x"4079",
000049 => x"0020",
000050 => x"4348",
000047 => x"407a",
000048 => x"0020",
000049 => x"4038",
000050 => x"f562",
000051 => x"4037",
000052 => x"f56c",
000052 => x"f5cc",
000053 => x"4036",
000054 => x"f5d6",
000055 => x"4035",
000056 => x"f53c",
000057 => x"403c",
000058 => x"f707",
000059 => x"1287",
000060 => x"490a",
000061 => x"503a",
000062 => x"ffe0",
000063 => x"4a0c",
000064 => x"1286",
000065 => x"403c",
000066 => x"f709",
000067 => x"1287",
000068 => x"4074",
000069 => x"0020",
000070 => x"4a2c",
000054 => x"f532",
000055 => x"403c",
000056 => x"f6fd",
000057 => x"1288",
000058 => x"4a09",
000059 => x"5039",
000060 => x"ffe0",
000061 => x"490c",
000062 => x"1287",
000063 => x"403c",
000064 => x"f6ff",
000065 => x"1288",
000066 => x"4075",
000067 => x"0020",
000068 => x"492c",
000069 => x"1287",
000070 => x"454c",
000071 => x"1286",
000072 => x"444c",
000073 => x"1285",
000074 => x"532a",
000075 => x"990a",
000076 => x"23f9",
000077 => x"12b0",
000078 => x"f55c",
000079 => x"930c",
000080 => x"2009",
000081 => x"5039",
000072 => x"5329",
000073 => x"9a09",
000074 => x"23f9",
000075 => x"12b0",
000076 => x"f552",
000077 => x"930c",
000078 => x"2006",
000079 => x"930a",
000080 => x"2404",
000081 => x"503a",
000082 => x"0020",
000083 => x"9038",
000084 => x"ffe0",
000085 => x"2404",
000086 => x"5038",
000087 => x"0010",
000088 => x"4030",
000089 => x"f072",
000090 => x"4030",
000091 => x"f67c",
000092 => x"120a",
000093 => x"1209",
000094 => x"1208",
000095 => x"1207",
000096 => x"1206",
000097 => x"1205",
000098 => x"4c07",
000099 => x"4d46",
000100 => x"4038",
000101 => x"f60a",
000102 => x"434c",
000103 => x"1288",
000104 => x"403a",
000105 => x"f638",
000106 => x"407c",
000107 => x"0006",
000108 => x"128a",
000109 => x"4039",
000110 => x"f630",
000111 => x"1289",
000112 => x"434c",
000113 => x"1288",
000114 => x"436c",
000083 => x"4030",
000084 => x"f06e",
000085 => x"4030",
000086 => x"f674",
000087 => x"120a",
000088 => x"1209",
000089 => x"1208",
000090 => x"1207",
000091 => x"1206",
000092 => x"1205",
000093 => x"4c07",
000094 => x"4d46",
000095 => x"4038",
000096 => x"f600",
000097 => x"434c",
000098 => x"1288",
000099 => x"403a",
000100 => x"f62e",
000101 => x"407c",
000102 => x"0006",
000103 => x"128a",
000104 => x"4039",
000105 => x"f626",
000106 => x"1289",
000107 => x"434c",
000108 => x"1288",
000109 => x"436c",
000110 => x"128a",
000111 => x"470c",
000112 => x"427d",
000113 => x"12b0",
000114 => x"f688",
000115 => x"128a",
000116 => x"470c",
000117 => x"427d",
000118 => x"12b0",
000119 => x"f692",
000120 => x"128a",
000121 => x"474c",
000122 => x"128a",
000123 => x"464c",
000124 => x"128a",
000125 => x"1289",
000126 => x"4347",
000127 => x"4075",
000128 => x"0005",
000129 => x"474c",
000130 => x"1288",
000131 => x"454c",
000132 => x"128a",
000133 => x"474c",
000134 => x"128a",
000135 => x"4c46",
000136 => x"1289",
000137 => x"b316",
000138 => x"23f6",
000139 => x"4030",
000140 => x"f67e",
000141 => x"120a",
000142 => x"1209",
000143 => x"1208",
000144 => x"4c09",
000145 => x"4d08",
000146 => x"4d0c",
000147 => x"427d",
000148 => x"12b0",
000149 => x"f692",
000150 => x"403a",
000151 => x"f0b8",
000152 => x"4c4d",
000153 => x"490c",
000154 => x"128a",
000155 => x"484d",
000156 => x"490c",
000157 => x"531c",
000158 => x"128a",
000159 => x"4030",
000160 => x"f684",
000161 => x"120a",
000162 => x"1209",
000163 => x"8321",
000164 => x"4c09",
000165 => x"434c",
000166 => x"12b0",
000167 => x"f60a",
000168 => x"403a",
000169 => x"f638",
000170 => x"407c",
000171 => x"0003",
000116 => x"474c",
000117 => x"128a",
000118 => x"464c",
000119 => x"128a",
000120 => x"1289",
000121 => x"4347",
000122 => x"4075",
000123 => x"0005",
000124 => x"474c",
000125 => x"1288",
000126 => x"454c",
000127 => x"128a",
000128 => x"474c",
000129 => x"128a",
000130 => x"4c46",
000131 => x"1289",
000132 => x"b316",
000133 => x"23f6",
000134 => x"4030",
000135 => x"f674",
000136 => x"120a",
000137 => x"1209",
000138 => x"1208",
000139 => x"4c09",
000140 => x"4d08",
000141 => x"4d0c",
000142 => x"427d",
000143 => x"12b0",
000144 => x"f688",
000145 => x"403a",
000146 => x"f0ae",
000147 => x"4c4d",
000148 => x"490c",
000149 => x"128a",
000150 => x"484d",
000151 => x"490c",
000152 => x"531c",
000153 => x"128a",
000154 => x"4030",
000155 => x"f67a",
000156 => x"120a",
000157 => x"1209",
000158 => x"8321",
000159 => x"4c09",
000160 => x"434c",
000161 => x"12b0",
000162 => x"f600",
000163 => x"403a",
000164 => x"f62e",
000165 => x"407c",
000166 => x"0003",
000167 => x"128a",
000168 => x"490c",
000169 => x"427d",
000170 => x"12b0",
000171 => x"f688",
000172 => x"128a",
000173 => x"490c",
000174 => x"427d",
000175 => x"12b0",
000176 => x"f692",
000177 => x"128a",
000178 => x"494c",
000179 => x"128a",
000180 => x"434c",
000181 => x"128a",
000182 => x"4c81",
000183 => x"0000",
000184 => x"12b0",
000185 => x"f630",
000186 => x"412c",
000187 => x"5321",
000188 => x"4030",
000189 => x"f686",
000190 => x"120a",
000191 => x"1209",
000192 => x"1208",
000193 => x"4c08",
000194 => x"f03d",
000195 => x"00ff",
000196 => x"930d",
000197 => x"200b",
000198 => x"4039",
000199 => x"f550",
000200 => x"1289",
000201 => x"4c4a",
000202 => x"1289",
000203 => x"4c4d",
000204 => x"4a4c",
000205 => x"12b0",
000206 => x"f66a",
000207 => x"4030",
000208 => x"f684",
000209 => x"931d",
000210 => x"2009",
000211 => x"4039",
000212 => x"f142",
000213 => x"1289",
000214 => x"4c4a",
000215 => x"480c",
000216 => x"531c",
000217 => x"1289",
000218 => x"4030",
000219 => x"f196",
000220 => x"434d",
000221 => x"4d0a",
000222 => x"4030",
000223 => x"f198",
000224 => x"4c4a",
000225 => x"403c",
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000974 => x"0078",
000975 => x"520a",
000976 => x"4d41",
000977 => x"203a",
000978 => x"7830",
000979 => x"0a00",
000980 => x"5953",
000981 => x"3a53",
000982 => x"3020",
000983 => x"0078",
000984 => x"0a0a",
000985 => x"7541",
000986 => x"6f74",
000987 => x"6f62",
000988 => x"746f",
000989 => x"6920",
000990 => x"206e",
000991 => x"7338",
000992 => x"202e",
000993 => x"7250",
000994 => x"7365",
000995 => x"2073",
000996 => x"656b",
000997 => x"2079",
000998 => x"6f74",
000999 => x"6120",
001000 => x"6f62",
001001 => x"7472",
001002 => x"0a2e",
001003 => x"0a00",
001004 => x"4d43",
001005 => x"3a44",
001006 => x"203e",
001007 => x"4200",
001008 => x"6461",
001009 => x"4320",
001010 => x"444d",
001011 => x"0021",
others => x"0000"
);
 
/neo430/trunk/neo430/rtl/core/neo430_control.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 15.11.2019 #
-- #################################################################################################
 
library ieee;
148,7 → 148,7
ctrl_nxt <= (others => '0');
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source reg A
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c); -- keep ALU function
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default SRC addressing mode
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default: SRC addressing mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2 as address offset
ctrl_nxt(ctrl_mem_rd_c) <= mem_rd_ff; -- memory read
ctrl_nxt(ctrl_alu_bw_c) <= ctrl(ctrl_alu_bw_c); -- keep byte/word mode
638,15 → 638,17
-- interrupt priority encoder --
irq_priority: process(irq_buf)
begin
if (irq_buf(0) = '1') then
irq_vec_nxt <= "00";
elsif (irq_buf(1) = '1') then
irq_vec_nxt <= "01";
elsif (irq_buf(2) = '1') then
irq_vec_nxt <= "10";
else --if (irq_buf(3) = '1') then
irq_vec_nxt <= "11";
end if;
-- use "case" here to prevent a MUX chain
case irq_buf is
when "0001" | "0011" | "0101" | "0111" | "1001" | "1011" | "1101" | "1111" => -- "---1"
irq_vec_nxt <= "00";
when "0010" | "0110" | "1010" | "1110" => -- "--10"
irq_vec_nxt <= "01";
when "0100" | "1100" => -- "-100"
irq_vec_nxt <= "10";
when others => -- "1000"
irq_vec_nxt <= "11";
end case;
end process irq_priority;
 
-- interrupt vector output --
/neo430/trunk/neo430/rtl/core/neo430_package.vhd
30,7 → 30,7
 
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0304"; -- no touchy!
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0305"; -- no touchy!
 
-- Advanced Hardware Configuration --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
291,7 → 291,7
constant alu_subc_c : std_ulogic_vector(3 downto 0) := "0111"; -- r <= b - a - 1 + carry
constant alu_sub_c : std_ulogic_vector(3 downto 0) := "1000"; -- r <= b - a
constant alu_cmp_c : std_ulogic_vector(3 downto 0) := "1001"; -- b - a (no write back)
constant alu_dadd_c : std_ulogic_vector(3 downto 0) := "1010"; -- r <= a + b (BCD!)
constant alu_dadd_c : std_ulogic_vector(3 downto 0) := "1010"; -- r <= a + b (BCD)
constant alu_bit_c : std_ulogic_vector(3 downto 0) := "1011"; -- a & b (no write back)
constant alu_bic_c : std_ulogic_vector(3 downto 0) := "1100"; -- r <= !a & b
constant alu_bis_c : std_ulogic_vector(3 downto 0) := "1101"; -- r <= a | b
/neo430/trunk/neo430/rtl/core/neo430_reg_file.vhd
122,7 → 122,7
end if;
end process sreg_write;
 
-- construct logical SREG --
-- construct logical status register --
sreg_combine: process(sreg)
begin
sreg_int <= (others => '0');
139,7 → 139,7
-- status register output --
sreg_o <= sreg_int;
 
-- general purpose register file (including PC, dummy SR and dummy CG) --
-- general purpose register file (including PC, SP, dummy SR and dummy CG) --
rf_write: process(clk_i)
begin
if rising_edge(clk_i) then
153,7 → 153,7
-- Register File Read Access ------------------------------------------------
-- -----------------------------------------------------------------------------
rf_read: process(ctrl_i, reg_file, sreg_int)
variable const_sel_v : std_ulogic_vector(02 downto 0);
variable const_sel_v : std_ulogic_vector(2 downto 0);
begin
if ((ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) = reg_sr_c) or
(ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) = reg_cg_c)) then
168,10 → 168,9
when "101" => data_o <= x"0001"; -- +1
when "110" => data_o <= x"0002"; -- +2
when "111" => data_o <= x"FFFF"; -- -1
when others => data_o <= x"0000";
when others => data_o <= (others => '-');
end case;
else
-- gp register file read access --
else -- gp register file read access
data_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c))));
end if;
end process rf_read;
/neo430/trunk/neo430/sw/bootloader/bootloader.c
29,7 → 29,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 13.11.2019 #
// # Stephan Nolting, Hannover, Germany 15.11.2019 #
// #################################################################################################
 
// Libraries
147,7 → 147,7
// ****************************************************************
// Show bootloader intro and system information
// ****************************************************************
neo430_uart_br_print("\n\nNEO430 Bootloader V20191113\nBy Stephan Nolting\n\n"
neo430_uart_br_print("\n\nNEO430 Bootloader V20191115\nBy Stephan Nolting\n\n"
"HWV: 0x");
neo430_uart_print_hex_word(HW_VERSION);
neo430_uart_br_print("\nUSR: 0x");
283,7 → 283,7
if ((neo430_uart_char_received() != 0) || (j == 0xFFE0))
return;
j += 16;
j += 32;
}
}
 

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