OpenCores
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/neo430/trunk/neo430/README.md
5,13 → 5,15
* [Differences to the Original MSP430 Processors](#Differences-to-the-Original-MSP430-Processors)
* [Implementation Results](#Implementation-Results)
* [Quick Start](#Quick-Start)
* [Change Log](#Change-Log)
* [Contact](#Contact)
* [Disclaimer, Proprietary and Legal Notice](#Disclaimer-Proprietary-and-Legal-Notice)
 
 
 
## Introduction
 
Welcome to the __NEO430 Processor__ project!
Welcome to __[The NEO430 Processor](https://github.com/stnolting/neo430)__ project!
 
You need a small but still powerful, customizable and microcontroller-like
processor system for your next FPGA project? Then the NEO430 is the right
41,9 → 43,10
a FPGA vendor-independent VHDL description) and start exploring the capabilities of
the NEO430 processor. Application program generation works by executing a single "make"
command. Jump to the "Let’s Get It Started" chapter in the NEO430 documentary, which provides
a lot of guides and tutorials to make your first NEO430 setup run: ![NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/PDF_32.png)[NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
a lot of guides and tutorials to make your first NEO430 setup run: [![NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/PDF_32.png) NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
 
 
 
## Processor Features
 
![NEO430 Overview](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/neo430_arch.png)
52,41 → 55,47
 
 
- 16-bit open source soft-core microcontroller-like processor system
- Full support of the original [MSP430 instruction set architecture](https://raw.githubusercontent.com/stnolting/neo430/master/doc/instruction_set.pdf)
- Code-efficient CISC-like instruction capabilities
- Full support of the original MSP430 instruction set architecture
- Tool chain based on free TI msp430-gcc compiler
- Application compilation scripts for Windows Powershell / Windows Subsystem for Linux / native Linux
- Tool chain based on free [TI msp430-gcc compiler](http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html "TI `msp430-gcc` compiler")
- Application compilation scripts ([makefiles](https://github.com/stnolting/neo430/blob/master/sw/example/blink_led/Makefile)) for Windows Powershell / Windows Subsystem for Linux / native Linux
- Software requirements (regardless of platform):
- [TI `msp430-gcc` compiler](http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html "TI `msp430-gcc` compiler")
- native C compiler (`GCC`)
- TI `msp430-gcc` compiler
- native `GCC` compiler
- `GNU Make`
- Completely described in behavioral, platform-independent VHDL
- Completely described in behavioral, platform-independent VHDL (no macros, primitives, attributes, etc. used)
- Fully synchronous design, no latches, no gated clocks
- Very low resource requirements and high operating frequency
- Internal DMEN (RAM, for data) and IMEM (RAM or ROM, for code), configurable sizes
- Internal [DMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_dmem.vhd) (RAM, for data) and [IMEM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_imem.vhd) (RAM or ROM, for code), configurable sizes
- One external interrupt line
- Customizable processor hardware configuration:
- Optional multiplier/divider unit (MULDIV)
- Optional high-precision timer (TIMER)
- Optional universal asynchronous receiver and transmitter (UART)
- Optional serial peripheral interface (SPI)
- Optional I2C-compatible two wire serial interface (TWI) supporting clock stretching
- Optional general purpose parallel IO port (GPIO), 16 inputs & 16 outputs, with pin-change interrupt
- Optional 32-bit Wishbone bus interface adapter (WB32) - including bridges to Avalon(TM) bus and AXI4-Lite(TM)
- Optional watchdog timer (WDT)
- Optional cyclic redundancy check unit (CRC16/32)
- Optional custom functions unit (CFU) for user-defined processor extensions
- Optional 4 channel PWM controller with 1 to 8 bit resolution (PWM)
- Optional internal bootloader (2kB ROM) with serial user console and automatic boot from external SPI EEPROM
- Optional multiplier/divider unit ([MULDIV](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_muldiv.vhd))
- Optional high-precision timer ([TIMER](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_timer.vhd))
- Optional universal asynchronous receiver and transmitter ([UART](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_uart.vhd))
- Optional serial peripheral interface ([SPI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_spi.vhd))
- Optional I2C-compatible two wire serial interface ([TWI](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_twi.vhd)) supporting clock stretching
- Optional general purpose parallel IO port ([GPIO](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_gpio.vhd)), 16 inputs & 16 outputs, with pin-change interrupt and PWM option
- Optional 32-bit Wishbone bus interface adapter ([WB32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wb_interface.vhd)) - including bridges to [Avalon (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_avm.vhd)) bus and [AXI4-Lite (TM](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_top_axi4lite.vhd))
- Optional watchdog timer ([WDT](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_wdt.vhd))
- Optional cyclic redundancy check unit ([CRC16/32](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_crc.vhd))
- Optional custom functions unit ([CFU](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_cfu.vhd)) for user-defined processor extensions
- Optional 4 channel PWM controller with 1 to 8 bit resolution ([PWM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd))
- Optional Galois Ring Oscillator (GARO) based true random number generator ([TRNG](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd))
- Optional external interrupts controller with 8 independent channels ([EXIRQ](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd))
- Optional internal [bootloader](https://github.com/stnolting/neo430/blob/master/sw/bootloader/bootloader.c) (2kB ROM) with serial user console and automatic boot from external SPI EEPROM
 
 
 
## Differences to the Original MSP430 Processors
 
- Completely different processor modules with different functionality
- Up to 48kB instruction memory and 12kB data memory
- Specific memory map – provided NEO430 linker script and compilation script required
- NEO430 tool chain (makefiles, boot-code and linker script) required for application compilation
- Custom binary executable format
- No default support of CPU's DADD instruction (btu can be enabled in package)
- No hardware debugging interface
- No analog components
- No support of TI's Code Composer Studio
- No default support of CPU's DADD instruction (but can be enabled in package)
- Just 4 CPU interrupt channels
- Single clock domain for complete processor
- Different numbers of instruction execution cycles
93,29 → 102,31
- Only one power-down (sleep) mode
- Wishbone-compatible interface to attach custom IP
- Internal bootloader with text interface (via UART serial port)
- Extended ALU functions (if enabled)
 
 
 
## Implementation Results
 
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes
all optional processor modules (excluding the CFU and DADD instruction), an IMEM size of 4kB and a DMEM size of 2kB.
The minimal configuration only includes the CPU and the GPIO module. Results generated with Xilinx Vivado 2017.3,
Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.0 (Synplify)
Mapping results generated for HW version 0x0320. The full (default) hardware configuration includes
all optional processor modules (excluding the CFU, the TRNG and the DADD instruction), an IMEM size of 4kB and a DMEM
size of 2kB. The minimal configuration only includes the CPU and the GPIO module. Results generated with Xilinx Vivado 2017.3,
Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.1 (Synplify)
 
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|:----------------------------------------|:----------:|:----------:|:--------:|:------:|:-------:|
| Full (default) configuration: | 941 (4.5%) | 960 (2.3%) | 2.5 (5%) | 0 (0%) | 100 MHz |
| Minimal configuration (CPU + GPIO): | 768 (3.6%) | 288 (0.7%) | 1 (2%) | 0 (0%) | 100 MHz |
| __Xilinx Artix-7 (XC7A35TICSG324-1L)__ | LUTs | FFs | BRAMs | DSPs | f_max* |
|:----------------------------------------|:----------:|:-----------:|:--------:|:------:|:-------:|
| Full (default) configuration: | 983 (4.7%) | 1014 (2.5%) | 2.5 (5%) | 0 (0%) | 100 MHz |
| Minimal configuration (CPU + GPIO): | 685 (3.3%) | 290 (0.7%) | 1 (2%) | 0 (0%) | 100 MHz |
 
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|:-------------------------------------|:---------:|:--------:|:------------:|:------:|:---------:|
| Full (default) configuration: | 1603 (7%) | 928 (4%) | 65792 (11%) | 0 (0%) | 119.6 MHz |
| Minimal configuration (CPU + GPIO): | 607 (3%) | 230 (1%) | 49408 (8%) | 0 (0%) | 119.6 MHz |
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory bits | DSPs | f_max |
|:-------------------------------------|:---------:|:--------:|:-----------:|:------:|:-------:|
| Full (default) configuration: | 1648 (7%) | 990 (4%) | 65800 (11%) | 0 (0%) | 122 MHz |
| Minimal configuration (CPU + GPIO): | 596 (3%) | 233 (1%) | 49408 (8%) | 0 (0%) | 126 MHz |
 
| __Lattice iCE40 UltraPlus (iCE40UP5K-SG48I)__ | LUTs | FFs | EBRs | DSPs | SRAMs | f_max* |
|:-----------------------------------------------|:----------:|:----------:|:--------:|:------:|:------:|:------:|
| Full (default) configuration: | 2833 (54%) | 1131 (21%) | 16 (53%) | 0 (0%) | 0 (0%) | 20 MHz |
| Minimal configuration (CPU + GPIO): | 1464 (28%) | 498 (9%) | 12 (40%) | 0 (0%) | 0 (0%) | 20 MHz |
| Full (default) configuration: | 2600 (49%) | 1152 (21%) | 16 (53%) | 0 (0%) | 0 (0%) | 20 MHz |
| Minimal configuration (CPU + GPIO): | 1365 (25%) | 493 (9%) | 12 (40%) | 0 (0%) | 0 (0%) | 20 MHz |
 
*) Constrained
 
125,59 → 136,69
The following table shows the required resources for each module of the NEO430 processor system. Note that the provided
numbers only represent a coarse overview as logic elements might be merged and optimized beyond module boundaries.
 
Mapping results generated for HW version 0x0303. The full (default) hardware configuration includes all optional
processor modules (excluding the CFU and DADD instruction), an IMEM size of 4kB and a DMEM size of 2kB. Results were generated
using Intel Quartus Prime Lite 17.1.
Mapping results generated for HW version 0x0320. The full (default) hardware configuration includes all optional
processor modules (excluding the CFU and DADD instruction but including the TRNG), an IMEM size of 4kB and a DMEM size of
2kB. Results were generated using Intel Quartus Prime Lite 17.1.
 
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
|:------------------------------------|:----:|:---:|:------------|:----:|
| Bootloader Memory (Boot ROM, 2kB) | 2 | 1 | 16384 | 0 |
| Central Processing Unit (CPU) | 547 | 196 | 256 | 0 |
| Checksum Unit (CRC) | 111 | 94 | 0 | 0 |
| Custom Functions Unit (CFU) | - | - | - | - |
| Data Memory (DMEM, 2kB) | 5 | 1 | 16384 | 0 |
| IO Port Unit (GPIO) | 53 | 45 | 0 | 0 |
| Instruction Memory (IMEM, 4kB) | 6 | 1 | 32768 | 0 |
| Multiplier & Divider (MULDIV) | 186 | 131 | 0 | 0 |
| Pulse-Width Modulation Unit (PWM) | 80 | 67 | 0 | 0 |
| Serial Peripheral Interface (SPI) | 57 | 43 | 0 | 0 |
| System Info Memory (SYSCONFIG) | 16 | 14 | 0 | 0 |
| High-Precision Timer (TIMER) | 66 | 55 | 0 | 0 |
| Two Wire Interface (TWI) | 82 | 41 | 0 | 0 |
| Universal Asynchronous Rx/Tx (UART) | 129 | 89 | 0 | 0 |
| Wishbone Interface (WB32) | 130 | 117 | 0 | 0 |
| Watchdog TImer (WDT) | 51 | 34 | 0 | 0 |
| __Intel Cyclone IV (EP4CE22F17C6)__ | LUTs | FFs | Memory Bits | DSPs |
|:---------------------------------------|:----:|:---:|:------------|:----:|
| Bootloader Memory (Boot ROM, 2kB) | 2 | 1 | 16384 | 0 |
| Central Processing Unit (CPU) | 506 | 171 | 256 | 0 |
| Checksum Unit (CRC) | 110 | 94 | 0 | 0 |
| Custom Functions Unit (CFU) | - | - | - | - |
| Data Memory (DMEM, 2kB) | 6 | 1 | 16384 | 0 |
| IO Port Unit (GPIO) | 49 | 45 | 0 | 0 |
| Instruction Memory (IMEM, 4kB) | 4 | 1 | 32768 | 0 |
| Multiplier & Divider (MULDIV) | 184 | 131 | 0 | 0 |
| Pulse-Width Modulation Unit (PWM) | 80 | 66 | 0 | 0 |
| Serial Peripheral Interface (SPI) | 57 | 43 | 0 | 0 |
| System Info Memory (SYSCONFIG) | 15 | 13 | 0 | 0 |
| High-Precision Timer (TIMER) | 70 | 55 | 0 | 0 |
| True Random Number Generator (TRNG) | 44 | 36 | 0 | 0 |
| Two Wire Interface (TWI) | 80 | 41 | 0 | 0 |
| Universal Asynchronous Rx/Tx (UART) | 129 | 89 | 0 | 0 |
| Wishbone Interface (WB32) | 128 | 117 | 0 | 0 |
| External Interrupts Controller (EXIRQ) | 73 | 60 | 0 | 0 |
| Watchdog TImer (WDT) | 49 | 36 | 0 | 0 |
 
 
 
## Quick Start
 
* At first, make sure to get the most recent version of this project from GitHub:
* At first, get the most recent version the NEO430 Processor project from GitHub:
~~~
git clone https://github.com/stnolting/neo430.git
~~~
* Clone the NEO430 repository using `git` from the command line (suggested, as this allows easy project updates via `git pull`):
~~~
git clone https://github.com/stnolting/neo430.git
~~~
 
* Next, install the `MSP430-GCC` compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):
* Or download the current version of this project as ZIP file: [neo430-master.zip](https://github.com/stnolting/neo430/archive/master.zip)
 
* Next, install the free `MSP430-GCC` compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):
 
https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/index_FDS.html
 
* Make sure `GNU Make` and a native C compiler (`GCC`) are installed (double check for the newest versions)
* Make sure `GNU Make` and a native `GCC` compiler are installed (double check for the newest versions)
 
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary:
* Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary: [![NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/PDF_32.png) NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
 
![NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/PDF_32.png)[NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub")
* This documentary will guide you to create a simple test setup, which serves as ["hello word" FPGA demo](https://github.com/stnolting/neo430/blob/master/rtl/top_templates/neo430_test.vhd):
 
* The NEO430 documentary will guide you to create a simple test setup, which serves as "hello world" FPGA demo:
 
![NEO430 Test Example Setup](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/test_setup.jpg)
 
* The NEO430 project also includes some example programs from which you can start your own application:
* The NEO430 project also includes some example programs from which you can start your own application: [SW example projects](https://github.com/stnolting/neo430/tree/master/sw/example)
 
https://github.com/stnolting/neo430/tree/master/sw/example
 
* Have fun! =)
 
 
 
## Change Log
 
The official change log of this project can be found at the end of the [![NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/figures/PDF_32.png) NEO430 Datasheet](https://raw.githubusercontent.com/stnolting/neo430/master/doc/NEO430.pdf "NEO430 Datasheet from GitHub").
 
 
 
## Contact
 
If you have any questions, bug reports, ideas or if you are facing problems with the NEO430, feel free to drop me a line.
186,6 → 207,7
stnolting@gmail.com
 
 
 
## Citation
 
If you are using the NEO430 for some kind of publication, please cite it as follows:
193,6 → 215,7
> S. Nolting, "The NEO430 Processor", github.com/stnolting/neo430
 
 
 
## Disclaimer, Proprietary and Legal Notice
 
This is a hobby project released under the LGPL-3.0 license. No copyright infringement intended.
215,7 → 238,7
source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html
 
 
"MSP430" is a trademark of Texas Instruments Corporation.
"MSP430" and "Code Composer Studio" are trademarks of Texas Instruments Corporation.
 
"Windows" is a trademark of Microsoft Corporation.
 
/neo430/trunk/neo430/doc/NEO430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/doc/figures/neo430_arch.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/doc/figures/test_setup.jpg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neo430/trunk/neo430/rtl/core/neo430_alu.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 15.11.2019 #
-- # Stephan Nolting, Hannover, Germany 21.11.2019 #
-- #################################################################################################
 
library ieee;
44,7 → 44,7
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- results --
data_o : out std_ulogic_vector(15 downto 0); -- result
flag_o : out std_ulogic_vector(03 downto 0) -- new ALU flags
flag_o : out std_ulogic_vector(04 downto 0) -- new ALU flags
);
end neo430_alu;
 
55,11 → 55,11
signal add_res : std_ulogic_vector(17 downto 0); -- adder/subtractor kernel result
signal dadd_res : std_ulogic_vector(16 downto 0); -- decimal adder kernel result
signal dadd_res_ff : std_ulogic_vector(16 downto 0); -- decimal adder kernel result buffered
signal dadd_res_in : std_ulogic_vector(16 downto 0); -- decimal adder kernel result buffered
signal alu_res : std_ulogic_vector(15 downto 0); -- alu result
signal data_res : std_ulogic_vector(15 downto 0); -- final alu result
signal zero : std_ulogic; -- zero detector
signal negative : std_ulogic; -- sign detectors
signal negative : std_ulogic; -- sign detector
signal parity : std_ulogic; -- parity detector
 
begin
 
73,6 → 73,7
operand_register: process(clk_i)
begin
if rising_edge(clk_i) then
-- operand registers --
if (ctrl_i(ctrl_alu_opa_wr_c) = '1') then
op_a_ff <= op_data;
end if;
79,6 → 80,8
if (ctrl_i(ctrl_alu_opb_wr_c) = '1') then
op_b_ff <= op_data;
end if;
-- DADD pipeline register --
dadd_res_ff <= dadd_res;
end if;
end process operand_register;
 
159,22 → 162,9
end process bcd_arithmetic_core;
 
 
-- DADD Pipeline Register ---------------------------------------------------
-- -----------------------------------------------------------------------------
dadd_pipe_reg: process(clk_i)
begin
if rising_edge(clk_i) then
dadd_res_ff <= dadd_res;
end if;
end process dadd_pipe_reg;
 
-- implement DADD instruction? --
dadd_res_in <= dadd_res_ff when (use_dadd_cmd_c = true) else (others => '-');
 
 
-- ALU Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
alu_core: process(ctrl_i, op_a_ff, op_b_ff, sreg_i, negative, zero, add_res, dadd_res_in)
alu_core: process(ctrl_i, op_a_ff, op_b_ff, sreg_i, negative, zero, parity, add_res, dadd_res_ff)
begin
-- defaults --
alu_res <= op_a_ff;
182,6 → 172,7
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= negative; -- update
flag_o(flag_z_c) <= zero; -- update
flag_o(flag_p_c) <= parity; -- update
 
-- function selection --
case ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) is
196,9 → 187,15
flag_o(flag_v_c) <= add_res(17);
 
when alu_dadd_c => -- r <= a + b + c (decimal)
alu_res <= dadd_res_in(15 downto 0);
flag_o(flag_c_c) <= dadd_res_in(16);
flag_o(flag_v_c) <= '0';
if (use_dadd_cmd_c = true) then -- implement DADD instruction at all?
alu_res <= dadd_res_ff(15 downto 0);
flag_o(flag_c_c) <= dadd_res_ff(16);
flag_o(flag_v_c) <= '0';
else -- output is undefined when DADD instruction is disabled
alu_res <= (others => '-');
flag_o(flag_c_c) <= '-';
flag_o(flag_v_c) <= '-';
end if;
 
when alu_and_c => -- r <= a & b
alu_res <= op_a_ff and op_b_ff;
284,6 → 281,9
-- zero flag --
zero <= not or_all_f(data_res);
 
-- parity flag --
parity <= (not xor_all_f(data_res)) when (use_xalu_c = true) else '-'; -- if implemented
 
-- negative flag --
negative <= data_res(7) when (ctrl_i(ctrl_alu_bw_c) = '1') else data_res(15);
 
/neo430/trunk/neo430/rtl/core/neo430_application_image.vhd
8,8 → 8,8
 
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(15 downto 0);
constant application_init_image : application_init_image_t := (
000000 => x"4218",
000001 => x"fff8",
000000 => x"4038",
000001 => x"c000",
000002 => x"4211",
000003 => x"fffa",
000004 => x"4302",
33,9 → 33,9
000022 => x"5328",
000023 => x"3ffa",
000024 => x"4035",
000025 => x"025e",
000025 => x"0228",
000026 => x"4036",
000027 => x"025e",
000027 => x"0228",
000028 => x"4037",
000029 => x"c008",
000030 => x"9506",
70,247 → 70,220
000059 => x"4b00",
000060 => x"434d",
000061 => x"12b0",
000062 => x"00bc",
000063 => x"403a",
000064 => x"0150",
000065 => x"403c",
000066 => x"0220",
000067 => x"128a",
000068 => x"b2b2",
000069 => x"fff2",
000070 => x"2411",
000071 => x"434c",
000072 => x"4037",
000073 => x"0180",
000074 => x"4039",
000075 => x"0186",
000076 => x"4078",
000077 => x"00c8",
000078 => x"4c0a",
000079 => x"531a",
000080 => x"f03c",
000081 => x"00ff",
000082 => x"1287",
000083 => x"480c",
000084 => x"1289",
000085 => x"4a0c",
000086 => x"4030",
000087 => x"009c",
000088 => x"403c",
000089 => x"023c",
000090 => x"128a",
000091 => x"435c",
000092 => x"4030",
000093 => x"01b8",
000094 => x"120a",
000095 => x"1209",
000096 => x"421a",
000097 => x"fffc",
000098 => x"421b",
000099 => x"fffe",
000100 => x"4c0e",
000101 => x"5c0e",
000102 => x"4d0f",
000103 => x"6d0f",
000104 => x"434c",
000105 => x"4f09",
000106 => x"9f0b",
000107 => x"2804",
000108 => x"9b09",
000109 => x"201b",
000110 => x"9e0a",
000111 => x"2c19",
000112 => x"434a",
000113 => x"4079",
000114 => x"0003",
000115 => x"407d",
000116 => x"00ff",
000117 => x"9c0d",
000118 => x"2817",
000119 => x"4382",
000120 => x"ffa0",
000121 => x"4a0d",
000122 => x"5a0d",
000123 => x"5d0d",
000124 => x"5d0d",
000125 => x"5d0d",
000126 => x"5d0d",
000127 => x"5d0d",
000128 => x"5d0d",
000129 => x"5d0d",
000130 => x"dc0d",
000131 => x"d03d",
000132 => x"1000",
000133 => x"4d82",
000134 => x"ffa0",
000135 => x"4030",
000136 => x"01bc",
000137 => x"8e0a",
000138 => x"7f0b",
000139 => x"531c",
000140 => x"4030",
000141 => x"00d4",
000142 => x"936a",
000143 => x"2402",
000144 => x"926a",
000145 => x"2008",
000146 => x"490d",
000147 => x"12b0",
000148 => x"01c8",
000149 => x"535a",
000150 => x"f03a",
000151 => x"00ff",
000152 => x"4030",
000153 => x"00e6",
000154 => x"c312",
000155 => x"100c",
000156 => x"4030",
000157 => x"012a",
000158 => x"f03c",
000159 => x"00ff",
000160 => x"403e",
000161 => x"ffa0",
000162 => x"4e2d",
000163 => x"930d",
000164 => x"3bfd",
000165 => x"4c82",
000166 => x"ffa2",
000167 => x"4130",
000168 => x"120a",
000169 => x"1209",
000170 => x"1208",
000171 => x"1207",
000172 => x"4c09",
000173 => x"4038",
000174 => x"013c",
000175 => x"4077",
000176 => x"000d",
000177 => x"496a",
000178 => x"930a",
000179 => x"2002",
000062 => x"00a8",
000063 => x"403c",
000064 => x"020c",
000065 => x"12b0",
000066 => x"013c",
000067 => x"434c",
000068 => x"4037",
000069 => x"016c",
000070 => x"4039",
000071 => x"0172",
000072 => x"4078",
000073 => x"00c8",
000074 => x"4c0a",
000075 => x"531a",
000076 => x"f03c",
000077 => x"00ff",
000078 => x"1287",
000079 => x"480c",
000080 => x"1289",
000081 => x"4a0c",
000082 => x"4030",
000083 => x"0094",
000084 => x"120a",
000085 => x"1209",
000086 => x"421a",
000087 => x"fffc",
000088 => x"421b",
000089 => x"fffe",
000090 => x"4c0e",
000091 => x"5c0e",
000092 => x"4d0f",
000093 => x"6d0f",
000094 => x"434c",
000095 => x"4f09",
000096 => x"9f0b",
000097 => x"2804",
000098 => x"9b09",
000099 => x"201b",
000100 => x"9e0a",
000101 => x"2c19",
000102 => x"434a",
000103 => x"4079",
000104 => x"0003",
000105 => x"407d",
000106 => x"00ff",
000107 => x"9c0d",
000108 => x"2817",
000109 => x"4382",
000110 => x"ffa0",
000111 => x"4a0d",
000112 => x"5a0d",
000113 => x"5d0d",
000114 => x"5d0d",
000115 => x"5d0d",
000116 => x"5d0d",
000117 => x"5d0d",
000118 => x"5d0d",
000119 => x"5d0d",
000120 => x"dc0d",
000121 => x"d03d",
000122 => x"1000",
000123 => x"4d82",
000124 => x"ffa0",
000125 => x"4030",
000126 => x"01a8",
000127 => x"8e0a",
000128 => x"7f0b",
000129 => x"531c",
000130 => x"4030",
000131 => x"00c0",
000132 => x"936a",
000133 => x"2402",
000134 => x"926a",
000135 => x"2008",
000136 => x"490d",
000137 => x"12b0",
000138 => x"01b4",
000139 => x"535a",
000140 => x"f03a",
000141 => x"00ff",
000142 => x"4030",
000143 => x"00d2",
000144 => x"c312",
000145 => x"100c",
000146 => x"4030",
000147 => x"0116",
000148 => x"f03c",
000149 => x"00ff",
000150 => x"403e",
000151 => x"ffa0",
000152 => x"4e2d",
000153 => x"930d",
000154 => x"3bfd",
000155 => x"4c82",
000156 => x"ffa2",
000157 => x"4130",
000158 => x"120a",
000159 => x"1209",
000160 => x"1208",
000161 => x"1207",
000162 => x"4c09",
000163 => x"4038",
000164 => x"0128",
000165 => x"4077",
000166 => x"000d",
000167 => x"496a",
000168 => x"930a",
000169 => x"2002",
000170 => x"4030",
000171 => x"01a4",
000172 => x"903a",
000173 => x"000a",
000174 => x"2002",
000175 => x"474c",
000176 => x"1288",
000177 => x"4a4c",
000178 => x"1288",
000179 => x"5319",
000180 => x"4030",
000181 => x"01b8",
000182 => x"903a",
000183 => x"000a",
000184 => x"2002",
000185 => x"474c",
000186 => x"1288",
000187 => x"4a4c",
000188 => x"1288",
000189 => x"5319",
000190 => x"4030",
000191 => x"0162",
000192 => x"4c82",
000193 => x"ffae",
000194 => x"4130",
000195 => x"421e",
000196 => x"fffe",
000197 => x"430f",
000198 => x"4e0b",
000199 => x"5e0b",
000200 => x"4f0d",
000201 => x"6f0d",
000202 => x"4c0e",
000203 => x"430f",
000204 => x"4b0c",
000205 => x"12b0",
000206 => x"01ce",
000207 => x"533c",
000208 => x"633d",
000209 => x"933c",
000210 => x"2003",
000211 => x"933d",
000212 => x"2001",
000213 => x"4130",
000214 => x"4303",
000215 => x"4030",
000216 => x"019e",
000217 => x"4134",
000218 => x"4135",
000219 => x"4136",
000220 => x"4137",
000221 => x"4138",
000222 => x"4139",
000223 => x"413a",
000224 => x"4130",
000225 => x"533d",
000226 => x"c312",
000227 => x"100c",
000228 => x"930d",
000229 => x"23fb",
000230 => x"4130",
000231 => x"120a",
000232 => x"1209",
000233 => x"1208",
000234 => x"1207",
000235 => x"1206",
000236 => x"4c0a",
000237 => x"4d0b",
000238 => x"407d",
000239 => x"0021",
000240 => x"4348",
000241 => x"4349",
000242 => x"4e0c",
000243 => x"df0c",
000244 => x"930c",
000245 => x"2405",
000246 => x"537d",
000247 => x"f03d",
000248 => x"00ff",
000249 => x"930d",
000250 => x"2004",
000251 => x"480c",
000252 => x"490d",
000253 => x"4030",
000254 => x"01b6",
000255 => x"4e0c",
000256 => x"f35c",
000257 => x"930c",
000258 => x"2402",
000259 => x"5a08",
000260 => x"6b09",
000261 => x"4a06",
000262 => x"4b07",
000263 => x"5a06",
000264 => x"6b07",
000265 => x"460a",
000266 => x"470b",
000267 => x"c312",
000268 => x"100f",
000269 => x"100e",
000270 => x"4030",
000271 => x"01e4",
000272 => x"420a",
000273 => x"696c",
000274 => x"6b6e",
000275 => x"6e69",
000276 => x"2067",
000277 => x"454c",
000278 => x"2044",
000279 => x"6564",
000280 => x"6f6d",
000281 => x"7020",
000282 => x"6f72",
000283 => x"7267",
000284 => x"6d61",
000285 => x"000a",
000286 => x"7245",
000287 => x"6f72",
000288 => x"2172",
000289 => x"4e20",
000290 => x"206f",
000291 => x"5047",
000292 => x"4f49",
000293 => x"7520",
000294 => x"696e",
000295 => x"2074",
000296 => x"7973",
000297 => x"746e",
000298 => x"6568",
000299 => x"6973",
000300 => x"657a",
000301 => x"2164",
000302 => x"0000",
000181 => x"014e",
000182 => x"4c82",
000183 => x"ffae",
000184 => x"4130",
000185 => x"421e",
000186 => x"fffe",
000187 => x"430f",
000188 => x"4e0b",
000189 => x"5e0b",
000190 => x"4f0d",
000191 => x"6f0d",
000192 => x"4c0e",
000193 => x"430f",
000194 => x"4b0c",
000195 => x"12b0",
000196 => x"01ba",
000197 => x"533c",
000198 => x"633d",
000199 => x"933c",
000200 => x"2003",
000201 => x"933d",
000202 => x"2001",
000203 => x"4130",
000204 => x"4303",
000205 => x"4030",
000206 => x"018a",
000207 => x"4134",
000208 => x"4135",
000209 => x"4136",
000210 => x"4137",
000211 => x"4138",
000212 => x"4139",
000213 => x"413a",
000214 => x"4130",
000215 => x"533d",
000216 => x"c312",
000217 => x"100c",
000218 => x"930d",
000219 => x"23fb",
000220 => x"4130",
000221 => x"120a",
000222 => x"1209",
000223 => x"1208",
000224 => x"1207",
000225 => x"1206",
000226 => x"4c0a",
000227 => x"4d0b",
000228 => x"407d",
000229 => x"0021",
000230 => x"4348",
000231 => x"4349",
000232 => x"4e0c",
000233 => x"df0c",
000234 => x"930c",
000235 => x"2405",
000236 => x"537d",
000237 => x"f03d",
000238 => x"00ff",
000239 => x"930d",
000240 => x"2004",
000241 => x"480c",
000242 => x"490d",
000243 => x"4030",
000244 => x"01a2",
000245 => x"4e0c",
000246 => x"f35c",
000247 => x"930c",
000248 => x"2402",
000249 => x"5a08",
000250 => x"6b09",
000251 => x"4a06",
000252 => x"4b07",
000253 => x"5a06",
000254 => x"6b07",
000255 => x"460a",
000256 => x"470b",
000257 => x"c312",
000258 => x"100f",
000259 => x"100e",
000260 => x"4030",
000261 => x"01d0",
000262 => x"420a",
000263 => x"696c",
000264 => x"6b6e",
000265 => x"6e69",
000266 => x"2067",
000267 => x"454c",
000268 => x"2044",
000269 => x"6564",
000270 => x"6f6d",
000271 => x"7020",
000272 => x"6f72",
000273 => x"7267",
000274 => x"6d61",
000275 => x"000a",
others => x"0000"
);
 
/neo430/trunk/neo430/rtl/core/neo430_bootloader_image.vhd
8,963 → 8,963
 
type bootloader_init_image_t is array (0 to 65535) of std_ulogic_vector(15 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
000000 => x"4211",
000001 => x"fff8",
000000 => x"4031",
000001 => x"bffe",
000002 => x"5211",
000003 => x"fffa",
000004 => x"8321",
000005 => x"3d98",
000006 => x"120f",
000007 => x"120e",
000008 => x"120d",
000009 => x"120c",
000010 => x"120b",
000011 => x"5392",
000012 => x"c004",
000013 => x"435c",
000014 => x"12b0",
000015 => x"f64e",
000016 => x"413b",
000017 => x"413c",
000018 => x"413d",
000019 => x"413e",
000020 => x"413f",
000021 => x"1300",
000022 => x"403c",
000023 => x"f68e",
000024 => x"12b0",
000025 => x"f562",
000026 => x"403d",
000027 => x"ffa0",
000028 => x"4d2c",
000029 => x"930c",
000030 => x"3bfd",
000031 => x"4032",
000032 => x"4000",
000033 => x"4300",
000034 => x"4030",
000035 => x"f042",
000036 => x"403c",
000037 => x"f69b",
000038 => x"12b0",
000039 => x"f562",
000040 => x"4130",
000041 => x"120a",
000042 => x"1209",
000043 => x"1208",
000044 => x"1207",
000045 => x"1206",
000046 => x"1205",
000047 => x"407a",
000048 => x"0020",
000049 => x"4038",
000050 => x"f562",
000051 => x"4037",
000052 => x"f5cc",
000053 => x"4036",
000054 => x"f532",
000055 => x"403c",
000056 => x"f6fd",
000057 => x"1288",
000058 => x"4a09",
000059 => x"5039",
000060 => x"ffe0",
000061 => x"490c",
000062 => x"1287",
000063 => x"403c",
000064 => x"f6ff",
000065 => x"1288",
000066 => x"4075",
000067 => x"0020",
000068 => x"492c",
000069 => x"1287",
000070 => x"454c",
000071 => x"1286",
000072 => x"5329",
000073 => x"9a09",
000074 => x"23f9",
000075 => x"12b0",
000076 => x"f552",
000077 => x"930c",
000078 => x"2006",
000079 => x"930a",
000080 => x"2404",
000081 => x"503a",
000082 => x"0020",
000083 => x"4030",
000084 => x"f06e",
000085 => x"4030",
000086 => x"f674",
000087 => x"120a",
000088 => x"1209",
000089 => x"1208",
000090 => x"1207",
000091 => x"1206",
000092 => x"1205",
000093 => x"4c07",
000094 => x"4d46",
000095 => x"4038",
000096 => x"f600",
000097 => x"434c",
000098 => x"1288",
000099 => x"403a",
000100 => x"f62e",
000101 => x"407c",
000102 => x"0006",
000103 => x"128a",
000104 => x"4039",
000105 => x"f626",
000106 => x"1289",
000107 => x"434c",
000108 => x"1288",
000109 => x"436c",
000110 => x"128a",
000111 => x"470c",
000112 => x"427d",
000113 => x"12b0",
000114 => x"f688",
000115 => x"128a",
000116 => x"474c",
000117 => x"128a",
000118 => x"464c",
000119 => x"128a",
000120 => x"1289",
000121 => x"4347",
000122 => x"4075",
000123 => x"0005",
000124 => x"474c",
000125 => x"1288",
000126 => x"454c",
000127 => x"128a",
000128 => x"474c",
000129 => x"128a",
000130 => x"4c46",
000131 => x"1289",
000132 => x"b316",
000133 => x"23f6",
000134 => x"4030",
000135 => x"f674",
000136 => x"120a",
000137 => x"1209",
000138 => x"1208",
000139 => x"4c09",
000140 => x"4d08",
000141 => x"4d0c",
000142 => x"427d",
000143 => x"12b0",
000144 => x"f688",
000145 => x"403a",
000146 => x"f0ae",
000147 => x"4c4d",
000148 => x"490c",
000149 => x"128a",
000150 => x"484d",
000151 => x"490c",
000152 => x"531c",
000153 => x"128a",
000154 => x"4030",
000155 => x"f67a",
000156 => x"120a",
000157 => x"1209",
000158 => x"8321",
000159 => x"4c09",
000160 => x"434c",
000161 => x"12b0",
000162 => x"f600",
000163 => x"403a",
000164 => x"f62e",
000165 => x"407c",
000166 => x"0003",
000167 => x"128a",
000168 => x"490c",
000169 => x"427d",
000170 => x"12b0",
000171 => x"f688",
000172 => x"128a",
000173 => x"494c",
000174 => x"128a",
000175 => x"434c",
000176 => x"128a",
000177 => x"4c81",
000178 => x"0000",
000179 => x"12b0",
000180 => x"f626",
000181 => x"412c",
000182 => x"5321",
000183 => x"4030",
000184 => x"f67c",
000185 => x"120a",
000186 => x"1209",
000187 => x"1208",
000188 => x"4c08",
000189 => x"f03d",
000190 => x"00ff",
000191 => x"930d",
000192 => x"200b",
000193 => x"4039",
000194 => x"f546",
000195 => x"1289",
000196 => x"4c4a",
000197 => x"1289",
000198 => x"4c4d",
000199 => x"4a4c",
000200 => x"12b0",
000201 => x"f660",
000202 => x"4030",
000203 => x"f67a",
000204 => x"931d",
000205 => x"2009",
000206 => x"4039",
000207 => x"f138",
000208 => x"1289",
000209 => x"4c4a",
000210 => x"480c",
000211 => x"531c",
000212 => x"1289",
000213 => x"4030",
000214 => x"f18c",
000215 => x"434d",
000216 => x"4d0a",
000217 => x"4030",
000218 => x"f18e",
000219 => x"4c4a",
000220 => x"403c",
000221 => x"f703",
000222 => x"12b0",
000223 => x"f562",
000224 => x"4a4c",
000225 => x"12b0",
000226 => x"f5b0",
000227 => x"4302",
000228 => x"435c",
000229 => x"12b0",
000230 => x"f648",
000231 => x"4030",
000232 => x"f1ce",
000233 => x"120a",
000234 => x"1209",
000235 => x"1208",
000236 => x"1207",
000237 => x"1206",
000238 => x"403a",
000239 => x"f562",
000004 => x"3d90",
000005 => x"120f",
000006 => x"120e",
000007 => x"120d",
000008 => x"120c",
000009 => x"120b",
000010 => x"5392",
000011 => x"c004",
000012 => x"435c",
000013 => x"12b0",
000014 => x"f654",
000015 => x"413b",
000016 => x"413c",
000017 => x"413d",
000018 => x"413e",
000019 => x"413f",
000020 => x"1300",
000021 => x"403c",
000022 => x"f694",
000023 => x"12b0",
000024 => x"f568",
000025 => x"403d",
000026 => x"ffa0",
000027 => x"4d2c",
000028 => x"930c",
000029 => x"3bfd",
000030 => x"4032",
000031 => x"4000",
000032 => x"4300",
000033 => x"4030",
000034 => x"f040",
000035 => x"403c",
000036 => x"f6a1",
000037 => x"12b0",
000038 => x"f568",
000039 => x"4130",
000040 => x"120a",
000041 => x"1209",
000042 => x"1208",
000043 => x"1207",
000044 => x"1206",
000045 => x"1205",
000046 => x"407a",
000047 => x"0020",
000048 => x"4038",
000049 => x"f568",
000050 => x"4037",
000051 => x"f5d2",
000052 => x"4036",
000053 => x"f538",
000054 => x"403c",
000055 => x"f703",
000056 => x"1288",
000057 => x"4a09",
000058 => x"5039",
000059 => x"ffe0",
000060 => x"490c",
000061 => x"1287",
000062 => x"403c",
000063 => x"f705",
000064 => x"1288",
000065 => x"4075",
000066 => x"0020",
000067 => x"492c",
000068 => x"1287",
000069 => x"454c",
000070 => x"1286",
000071 => x"5329",
000072 => x"9a09",
000073 => x"23f9",
000074 => x"12b0",
000075 => x"f558",
000076 => x"930c",
000077 => x"2006",
000078 => x"930a",
000079 => x"2404",
000080 => x"503a",
000081 => x"0020",
000082 => x"4030",
000083 => x"f06c",
000084 => x"4030",
000085 => x"f67a",
000086 => x"120a",
000087 => x"1209",
000088 => x"1208",
000089 => x"1207",
000090 => x"1206",
000091 => x"1205",
000092 => x"4c07",
000093 => x"4d46",
000094 => x"4038",
000095 => x"f606",
000096 => x"434c",
000097 => x"1288",
000098 => x"403a",
000099 => x"f634",
000100 => x"407c",
000101 => x"0006",
000102 => x"128a",
000103 => x"4039",
000104 => x"f62c",
000105 => x"1289",
000106 => x"434c",
000107 => x"1288",
000108 => x"436c",
000109 => x"128a",
000110 => x"470c",
000111 => x"427d",
000112 => x"12b0",
000113 => x"f68e",
000114 => x"128a",
000115 => x"474c",
000116 => x"128a",
000117 => x"464c",
000118 => x"128a",
000119 => x"1289",
000120 => x"4347",
000121 => x"4075",
000122 => x"0005",
000123 => x"474c",
000124 => x"1288",
000125 => x"454c",
000126 => x"128a",
000127 => x"474c",
000128 => x"128a",
000129 => x"4c46",
000130 => x"1289",
000131 => x"b316",
000132 => x"23f6",
000133 => x"4030",
000134 => x"f67a",
000135 => x"120a",
000136 => x"1209",
000137 => x"1208",
000138 => x"4c09",
000139 => x"4d08",
000140 => x"4d0c",
000141 => x"427d",
000142 => x"12b0",
000143 => x"f68e",
000144 => x"403a",
000145 => x"f0ac",
000146 => x"4c4d",
000147 => x"490c",
000148 => x"128a",
000149 => x"484d",
000150 => x"490c",
000151 => x"531c",
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000562 => x"907a",
000563 => x"0064",
000564 => x"2004",
000565 => x"12b0",
000566 => x"f050",
000567 => x"4030",
000568 => x"f438",
000569 => x"907a",
000570 => x"0075",
000571 => x"2004",
000572 => x"434c",
000573 => x"1287",
000574 => x"4030",
000575 => x"f438",
000576 => x"907a",
000577 => x"0070",
000578 => x"2004",
000579 => x"12b0",
000580 => x"f1c0",
000581 => x"4030",
000582 => x"f438",
000583 => x"907a",
000584 => x"0065",
000585 => x"2003",
000586 => x"435c",
000587 => x"4030",
000588 => x"f47a",
000589 => x"907a",
000590 => x"0073",
000591 => x"27be",
000592 => x"907a",
000593 => x"0063",
000594 => x"2005",
000595 => x"403c",
000596 => x"f7df",
000597 => x"1289",
000598 => x"4030",
000599 => x"f438",
000600 => x"403c",
000601 => x"f7f2",
000602 => x"4030",
000603 => x"f4aa",
000604 => x"120a",
000605 => x"1209",
000606 => x"421a",
000607 => x"fffc",
000608 => x"421b",
000609 => x"fffe",
000610 => x"4c0e",
000611 => x"5c0e",
000612 => x"4d0f",
000613 => x"6d0f",
000614 => x"434c",
000615 => x"4f09",
000616 => x"9f0b",
000617 => x"2804",
000618 => x"9b09",
000619 => x"201b",
000620 => x"9e0a",
000621 => x"2c19",
000622 => x"434a",
000623 => x"4079",
000624 => x"0003",
000625 => x"407d",
000626 => x"00ff",
000627 => x"9c0d",
000628 => x"2817",
000629 => x"4382",
000630 => x"ffa0",
000631 => x"4a0d",
000632 => x"5a0d",
000633 => x"5d0d",
000634 => x"5d0d",
000635 => x"5d0d",
000636 => x"5d0d",
000637 => x"dc0d",
000638 => x"d03d",
000639 => x"1000",
000640 => x"4d82",
000641 => x"ffa0",
000642 => x"4030",
000643 => x"f67c",
000644 => x"8e0a",
000645 => x"7f0b",
000646 => x"531c",
000647 => x"4030",
000648 => x"f4ca",
000649 => x"936a",
000650 => x"2402",
000651 => x"926a",
000652 => x"2008",
000653 => x"490d",
000654 => x"12b0",
000655 => x"f688",
000656 => x"535a",
000657 => x"f03a",
000658 => x"00ff",
000659 => x"4030",
000660 => x"f4dc",
000661 => x"c312",
000662 => x"100c",
000663 => x"4030",
000664 => x"f520",
000665 => x"f03c",
000666 => x"00ff",
000667 => x"403e",
000668 => x"ffa0",
000669 => x"4e2d",
000670 => x"930d",
000671 => x"3bfd",
000672 => x"4c82",
000673 => x"ffa2",
000674 => x"4130",
000675 => x"403d",
000637 => x"5d0d",
000638 => x"5d0d",
000639 => x"5d0d",
000640 => x"dc0d",
000641 => x"d03d",
000642 => x"1000",
000643 => x"4d82",
000644 => x"ffa0",
000645 => x"4030",
000646 => x"f682",
000647 => x"8e0a",
000648 => x"7f0b",
000649 => x"531c",
000650 => x"4030",
000651 => x"f4d0",
000652 => x"936a",
000653 => x"2402",
000654 => x"926a",
000655 => x"2008",
000656 => x"490d",
000657 => x"12b0",
000658 => x"f68e",
000659 => x"535a",
000660 => x"f03a",
000661 => x"00ff",
000662 => x"4030",
000663 => x"f4e2",
000664 => x"c312",
000665 => x"100c",
000666 => x"4030",
000667 => x"f526",
000668 => x"f03c",
000669 => x"00ff",
000670 => x"403e",
000671 => x"ffa0",
000672 => x"4e2d",
000673 => x"930d",
000674 => x"3bfd",
000675 => x"4c82",
000676 => x"ffa2",
000677 => x"4d2c",
000678 => x"930c",
000679 => x"37fd",
000680 => x"4130",
000681 => x"421c",
000682 => x"ffa2",
000683 => x"f03c",
000684 => x"8000",
000685 => x"4130",
000686 => x"421c",
000687 => x"ffa2",
000677 => x"4130",
000678 => x"403d",
000679 => x"ffa2",
000680 => x"4d2c",
000681 => x"930c",
000682 => x"37fd",
000683 => x"4130",
000684 => x"421c",
000685 => x"ffa2",
000686 => x"f03c",
000687 => x"8000",
000688 => x"4130",
000689 => x"120a",
000690 => x"1209",
000691 => x"1208",
000692 => x"1207",
000693 => x"4c09",
000694 => x"4038",
000695 => x"f532",
000696 => x"4077",
000697 => x"000d",
000698 => x"496a",
000699 => x"930a",
000700 => x"2002",
000701 => x"4030",
000702 => x"f678",
000703 => x"903a",
000704 => x"000a",
000705 => x"2002",
000706 => x"474c",
000707 => x"1288",
000708 => x"4a4c",
000709 => x"1288",
000710 => x"5319",
000711 => x"4030",
000712 => x"f574",
000713 => x"f07c",
000714 => x"000f",
000715 => x"407d",
000716 => x"0009",
000717 => x"9c4d",
000718 => x"2805",
000719 => x"503c",
000720 => x"0030",
000721 => x"12b0",
000722 => x"f532",
000723 => x"4130",
000724 => x"503c",
000725 => x"0037",
000726 => x"4030",
000727 => x"f5a2",
000728 => x"120a",
000729 => x"1209",
000730 => x"4c49",
000731 => x"490c",
000732 => x"426d",
000733 => x"12b0",
000734 => x"f688",
000735 => x"403a",
000736 => x"f592",
000737 => x"128a",
000738 => x"494c",
000739 => x"128a",
000740 => x"4030",
000741 => x"f67c",
000742 => x"120a",
000743 => x"1209",
000744 => x"4c09",
000745 => x"427d",
000746 => x"12b0",
000747 => x"f688",
000748 => x"403a",
000749 => x"f5b0",
000750 => x"128a",
000751 => x"494c",
000752 => x"128a",
000753 => x"4030",
000754 => x"f67c",
000755 => x"f03c",
000756 => x"00ff",
000757 => x"403d",
000758 => x"ffa4",
000759 => x"438d",
000760 => x"0000",
000761 => x"5c0c",
000762 => x"5c0c",
000763 => x"5c0c",
000764 => x"d31c",
000765 => x"4c8d",
000766 => x"0000",
000767 => x"4130",
000768 => x"f03c",
000769 => x"00ff",
000770 => x"403d",
000771 => x"ffa4",
000772 => x"f0bd",
000773 => x"fc3f",
000774 => x"0000",
000775 => x"5c0c",
000776 => x"5c0c",
000777 => x"5c0c",
000689 => x"421c",
000690 => x"ffa2",
000691 => x"4130",
000692 => x"120a",
000693 => x"1209",
000694 => x"1208",
000695 => x"1207",
000696 => x"4c09",
000697 => x"4038",
000698 => x"f538",
000699 => x"4077",
000700 => x"000d",
000701 => x"496a",
000702 => x"930a",
000703 => x"2002",
000704 => x"4030",
000705 => x"f67e",
000706 => x"903a",
000707 => x"000a",
000708 => x"2002",
000709 => x"474c",
000710 => x"1288",
000711 => x"4a4c",
000712 => x"1288",
000713 => x"5319",
000714 => x"4030",
000715 => x"f57a",
000716 => x"f07c",
000717 => x"000f",
000718 => x"407d",
000719 => x"0009",
000720 => x"9c4d",
000721 => x"2805",
000722 => x"503c",
000723 => x"0030",
000724 => x"12b0",
000725 => x"f538",
000726 => x"4130",
000727 => x"503c",
000728 => x"0037",
000729 => x"4030",
000730 => x"f5a8",
000731 => x"120a",
000732 => x"1209",
000733 => x"4c49",
000734 => x"490c",
000735 => x"426d",
000736 => x"12b0",
000737 => x"f68e",
000738 => x"403a",
000739 => x"f598",
000740 => x"128a",
000741 => x"494c",
000742 => x"128a",
000743 => x"4030",
000744 => x"f682",
000745 => x"120a",
000746 => x"1209",
000747 => x"4c09",
000748 => x"427d",
000749 => x"12b0",
000750 => x"f68e",
000751 => x"403a",
000752 => x"f5b6",
000753 => x"128a",
000754 => x"494c",
000755 => x"128a",
000756 => x"4030",
000757 => x"f682",
000758 => x"f03c",
000759 => x"00ff",
000760 => x"403d",
000761 => x"ffa4",
000762 => x"438d",
000763 => x"0000",
000764 => x"5c0c",
000765 => x"5c0c",
000766 => x"5c0c",
000767 => x"d31c",
000768 => x"4c8d",
000769 => x"0000",
000770 => x"4130",
000771 => x"f03c",
000772 => x"00ff",
000773 => x"403d",
000774 => x"ffa4",
000775 => x"f0bd",
000776 => x"fc3f",
000777 => x"0000",
000778 => x"5c0c",
000779 => x"5c0c",
000780 => x"5c0c",
000781 => x"dd2c",
000782 => x"d03c",
000783 => x"0200",
000784 => x"4c8d",
000785 => x"0000",
000786 => x"4130",
000787 => x"f0b2",
000788 => x"fdff",
000789 => x"ffa4",
000790 => x"4130",
000791 => x"403d",
000792 => x"ffa6",
000793 => x"f03c",
000794 => x"00ff",
000795 => x"4c8d",
000796 => x"0000",
000797 => x"403e",
000798 => x"ffa4",
000799 => x"4e2c",
000800 => x"930c",
000801 => x"3bfd",
000802 => x"4d2c",
000803 => x"4130",
000804 => x"4c82",
000805 => x"ffae",
000781 => x"5c0c",
000782 => x"5c0c",
000783 => x"5c0c",
000784 => x"dd2c",
000785 => x"d03c",
000786 => x"0200",
000787 => x"4c8d",
000788 => x"0000",
000789 => x"4130",
000790 => x"f0b2",
000791 => x"fdff",
000792 => x"ffa4",
000793 => x"4130",
000794 => x"403d",
000795 => x"ffa6",
000796 => x"f03c",
000797 => x"00ff",
000798 => x"4c8d",
000799 => x"0000",
000800 => x"403e",
000801 => x"ffa4",
000802 => x"4e2c",
000803 => x"930c",
000804 => x"3bfd",
000805 => x"4d2c",
000806 => x"4130",
000807 => x"ec82",
000807 => x"4c82",
000808 => x"ffae",
000809 => x"4130",
000810 => x"d232",
000811 => x"4303",
000810 => x"ec82",
000811 => x"ffae",
000812 => x"4130",
000813 => x"d032",
000814 => x"4000",
000813 => x"d232",
000814 => x"4303",
000815 => x"4130",
000816 => x"4c4e",
000817 => x"4d4c",
000818 => x"108e",
000819 => x"de0c",
000820 => x"4130",
000821 => x"40b2",
000822 => x"4700",
000823 => x"ffb8",
000824 => x"4130",
000825 => x"4134",
000826 => x"4135",
000827 => x"4136",
000828 => x"4137",
000829 => x"4138",
000830 => x"4139",
000831 => x"413a",
000832 => x"4130",
000833 => x"533d",
000834 => x"c312",
000835 => x"100c",
000836 => x"930d",
000837 => x"23fb",
000838 => x"4130",
000839 => x"6f42",
000840 => x"746f",
000841 => x"6e69",
000842 => x"2e67",
000843 => x"2e2e",
000844 => x"0a0a",
000845 => x"4300",
000846 => x"444d",
000847 => x"3a73",
000848 => x"200a",
000849 => x"3a64",
000850 => x"4420",
000851 => x"6d75",
000852 => x"2070",
000853 => x"454d",
000854 => x"0a4d",
000855 => x"6520",
000856 => x"203a",
000857 => x"6f4c",
000858 => x"6461",
000859 => x"4520",
000860 => x"5045",
000861 => x"4f52",
000862 => x"0a4d",
000863 => x"6820",
000864 => x"203a",
000865 => x"6548",
000866 => x"706c",
000867 => x"200a",
000868 => x"3a70",
000869 => x"5320",
000870 => x"6f74",
000871 => x"6572",
000872 => x"4520",
000873 => x"5045",
000874 => x"4f52",
000875 => x"0a4d",
000876 => x"7220",
000877 => x"203a",
000878 => x"6552",
000879 => x"7473",
000880 => x"7261",
000881 => x"0a74",
000882 => x"7320",
000883 => x"203a",
000884 => x"7453",
000885 => x"7261",
000886 => x"2074",
000887 => x"7061",
000888 => x"0a70",
000889 => x"7520",
000890 => x"203a",
000891 => x"7055",
000892 => x"6f6c",
000893 => x"6461",
000894 => x"0a00",
000895 => x"3a00",
000896 => x"2020",
000897 => x"0700",
000898 => x"450a",
000899 => x"5252",
000900 => x"005f",
000901 => x"7250",
000902 => x"636f",
000903 => x"6565",
000904 => x"2064",
000905 => x"7928",
000906 => x"6e2f",
000907 => x"3f29",
000908 => x"0a00",
000909 => x"7257",
000910 => x"7469",
000911 => x"6e69",
000912 => x"2e67",
000913 => x"2e2e",
000914 => x"0020",
000915 => x"4b4f",
000916 => x"4100",
000917 => x"6177",
000918 => x"7469",
000919 => x"6e69",
000920 => x"2067",
000921 => x"4942",
000922 => x"454e",
000923 => x"4558",
000924 => x"2e2e",
000925 => x"202e",
000926 => x"4c00",
000927 => x"616f",
000928 => x"6964",
000929 => x"676e",
000930 => x"2e2e",
000931 => x"202e",
000932 => x"0a00",
000933 => x"4e0a",
000934 => x"4f45",
000935 => x"3334",
000936 => x"2030",
000937 => x"6f42",
000938 => x"746f",
000939 => x"6f6c",
000940 => x"6461",
000941 => x"7265",
000942 => x"5620",
000943 => x"3032",
000944 => x"3931",
000945 => x"3131",
000946 => x"3531",
000947 => x"420a",
000948 => x"2079",
000949 => x"7453",
000950 => x"7065",
000951 => x"6168",
000952 => x"206e",
000953 => x"6f4e",
000954 => x"746c",
000955 => x"6e69",
000956 => x"0a67",
000816 => x"d032",
000817 => x"4000",
000818 => x"4130",
000819 => x"4c4e",
000820 => x"4d4c",
000821 => x"108e",
000822 => x"de0c",
000823 => x"4130",
000824 => x"40b2",
000825 => x"4700",
000826 => x"ffb8",
000827 => x"4130",
000828 => x"4134",
000829 => x"4135",
000830 => x"4136",
000831 => x"4137",
000832 => x"4138",
000833 => x"4139",
000834 => x"413a",
000835 => x"4130",
000836 => x"533d",
000837 => x"c312",
000838 => x"100c",
000839 => x"930d",
000840 => x"23fb",
000841 => x"4130",
000842 => x"6f42",
000843 => x"746f",
000844 => x"6e69",
000845 => x"2e67",
000846 => x"2e2e",
000847 => x"0a0a",
000848 => x"4300",
000849 => x"444d",
000850 => x"3a73",
000851 => x"200a",
000852 => x"3a64",
000853 => x"4420",
000854 => x"6d75",
000855 => x"2070",
000856 => x"454d",
000857 => x"0a4d",
000858 => x"6520",
000859 => x"203a",
000860 => x"6f4c",
000861 => x"6461",
000862 => x"4520",
000863 => x"5045",
000864 => x"4f52",
000865 => x"0a4d",
000866 => x"6820",
000867 => x"203a",
000868 => x"6548",
000869 => x"706c",
000870 => x"200a",
000871 => x"3a70",
000872 => x"5320",
000873 => x"6f74",
000874 => x"6572",
000875 => x"4520",
000876 => x"5045",
000877 => x"4f52",
000878 => x"0a4d",
000879 => x"7220",
000880 => x"203a",
000881 => x"6552",
000882 => x"7473",
000883 => x"7261",
000884 => x"0a74",
000885 => x"7320",
000886 => x"203a",
000887 => x"7453",
000888 => x"7261",
000889 => x"2074",
000890 => x"7061",
000891 => x"0a70",
000892 => x"7520",
000893 => x"203a",
000894 => x"7055",
000895 => x"6f6c",
000896 => x"6461",
000897 => x"0a00",
000898 => x"3a00",
000899 => x"2020",
000900 => x"0700",
000901 => x"450a",
000902 => x"5252",
000903 => x"005f",
000904 => x"7250",
000905 => x"636f",
000906 => x"6565",
000907 => x"2064",
000908 => x"7928",
000909 => x"6e2f",
000910 => x"3f29",
000911 => x"0a00",
000912 => x"7257",
000913 => x"7469",
000914 => x"6e69",
000915 => x"2e67",
000916 => x"2e2e",
000917 => x"0020",
000918 => x"4b4f",
000919 => x"4100",
000920 => x"6177",
000921 => x"7469",
000922 => x"6e69",
000923 => x"2067",
000924 => x"4942",
000925 => x"454e",
000926 => x"4558",
000927 => x"2e2e",
000928 => x"202e",
000929 => x"4c00",
000930 => x"616f",
000931 => x"6964",
000932 => x"676e",
000933 => x"2e2e",
000934 => x"202e",
000935 => x"0a00",
000936 => x"3c0a",
000937 => x"203c",
000938 => x"454e",
000939 => x"344f",
000940 => x"3033",
000941 => x"4220",
000942 => x"6f6f",
000943 => x"6c74",
000944 => x"616f",
000945 => x"6564",
000946 => x"2072",
000947 => x"3e3e",
000948 => x"0a0a",
000949 => x"4c42",
000950 => x"3a56",
000951 => x"4e20",
000952 => x"766f",
000953 => x"3220",
000954 => x"2039",
000955 => x"3032",
000956 => x"3931",
000957 => x"480a",
000958 => x"5657",
000959 => x"203a",
1016,10 → 1016,20
001005 => x"3a44",
001006 => x"203e",
001007 => x"4200",
001008 => x"6461",
001009 => x"4320",
001010 => x"444d",
001011 => x"0021",
001008 => x"2079",
001009 => x"7453",
001010 => x"7065",
001011 => x"6168",
001012 => x"206e",
001013 => x"6f4e",
001014 => x"746c",
001015 => x"6e69",
001016 => x"0067",
001017 => x"6142",
001018 => x"2064",
001019 => x"4d43",
001020 => x"2144",
001021 => x"0000",
others => x"0000"
);
 
/neo430/trunk/neo430/rtl/core/neo430_cfu.vhd
26,7 → 26,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 28.04.2019 #
-- # Stephan Nolting, Hannover, Germany 22.11.2019 #
-- #################################################################################################
 
library ieee;
120,16 → 120,19
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0'); -- this is crucial for the final OR-ing of all device's outputs
data_o <= (others => '0'); -- this is crucial for the final OR-ing of all IO device's outputs
if (rden = '1') then -- valid read access
if (addr = cfu_reg0_addr_c) then data_o <= user_reg0;
elsif (addr = cfu_reg1_addr_c) then data_o <= user_reg1;
elsif (addr = cfu_reg2_addr_c) then data_o <= user_reg2;
elsif (addr = cfu_reg3_addr_c) then data_o <= user_reg3;
elsif (addr = cfu_reg4_addr_c) then data_o <= user_reg4;
elsif (addr = cfu_reg5_addr_c) then data_o <= user_reg5;
elsif (addr = cfu_reg6_addr_c) then data_o <= user_reg6;
else data_o <= user_reg7; end if;
case addr is
when cfu_reg0_addr_c => data_o <= user_reg0;
when cfu_reg1_addr_c => data_o <= user_reg1;
when cfu_reg2_addr_c => data_o <= user_reg2;
when cfu_reg3_addr_c => data_o <= user_reg3;
when cfu_reg4_addr_c => data_o <= user_reg4;
when cfu_reg5_addr_c => data_o <= user_reg5;
when cfu_reg6_addr_c => data_o <= user_reg6;
when cfu_reg7_addr_c => data_o <= user_reg7;
when others => data_o <= (others => '-');
end case;
end if;
end if;
end process rd_access;
/neo430/trunk/neo430/rtl/core/neo430_control.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 15.11.2019 #
-- # Stephan Nolting, Hannover, Germany 26.11.2019 #
-- #################################################################################################
 
library ieee;
72,9 → 72,10
signal sam_nxt, sam : std_ulogic_vector(01 downto 0); -- CMD according SRC addressing mode
 
-- irq system --
signal irq_start, irq_ack : std_ulogic;
signal irq_ack_mask, irq_buf : std_ulogic_vector(3 downto 0);
signal irq_vec_nxt, irq_vec : std_ulogic_vector(1 downto 0);
signal irq_start, irq_ack : std_ulogic;
signal irq_ack_mask, irq_buf : std_ulogic_vector(3 downto 0);
signal irq_vec_nxt, irq_vec : std_ulogic_vector(1 downto 0);
signal i_flag_ff0, i_flag_ff1 : std_ulogic;
 
begin
 
148,7 → 149,7
ctrl_nxt <= (others => '0');
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source reg A
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c); -- keep ALU function
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default: SRC addressing mode
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- SRC addressing mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2 as address offset
ctrl_nxt(ctrl_mem_rd_c) <= mem_rd_ff; -- memory read
ctrl_nxt(ctrl_alu_bw_c) <= ctrl(ctrl_alu_bw_c); -- keep byte/word mode
608,6 → 609,11
irq_buffer: process(clk_i)
begin
if rising_edge(clk_i) then
-- delay I flag 2 cycles to allow the interrupted program to execute at least one insruction even if we have
-- a permanent interrupt request
i_flag_ff0 <= sreg_i(sreg_i_c);
i_flag_ff1 <= i_flag_ff0;
-- interrupt vector and queue buffer --
irq_vec <= irq_vec_nxt;
for i in 0 to 3 loop
irq_buf(i) <= (irq_buf(i) or irq_i(i)) and (not sreg_i(sreg_q_c)) and (not irq_ack_mask(i));
616,7 → 622,7
end process irq_buffer;
 
-- valid start of IRQ handler --
irq_start <= '1' when (irq_buf /= "0000") and (sreg_i(sreg_i_c) = '1') else '0';
irq_start <= '1' when (irq_buf /= "0000") and (i_flag_ff1 = '1') and (sreg_i(sreg_i_c) = '1') else '0';
 
-- acknowledge mask --
irq_ack_mask_gen: process(irq_ack, irq_vec)
/neo430/trunk/neo430/rtl/core/neo430_cpu.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 21.11.2019 #
-- #################################################################################################
 
library ieee;
62,7 → 62,7
signal mdo_gate : std_ulogic_vector(15 downto 0); -- memory data_out power gate
signal ctrl_bus : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control spine
signal sreg : std_ulogic_vector(15 downto 0); -- current status register
signal alu_flags : std_ulogic_vector(03 downto 0); -- new ALU flags
signal alu_flags : std_ulogic_vector(04 downto 0); -- new ALU flags
signal imm : std_ulogic_vector(15 downto 0); -- branch offset
signal rf_read : std_ulogic_vector(15 downto 0); -- RF read data
signal alu_res : std_ulogic_vector(15 downto 0); -- ALU result
/neo430/trunk/neo430/rtl/core/neo430_exirq.vhd
0,0 → 1,226
-- #################################################################################################
-- # << NEO430 - External Interrupts Controller >> #
-- # ********************************************************************************************* #
-- # This unit provides 8 maskable external interrupt lines with according ACK lines. The IRQ #
-- # can be globally set to trigger either on a high-level or on a rising edge. Each line has a #
-- # unique enable bit. The acknowledge output is set high for one clock cycle to confirm the #
-- # interrupt has been sampled and has also been cpatured by the handler function. #
-- # All external interrupt requests are forwarded to a single CPU interrupt. The according #
-- # has to check the SRC bits in the unit's control register to determine the actual source and #
-- # start the according handler function. #
-- # If several IRQs occur at the same time, the one with highest priority is executed while the #
-- # others are kept in a buffer. The buffer is reset when the global enable flag of the unit is #
-- # cleared. #
-- # ext_irq_i(0) has highest priority while ext_irq_i(7) has the lowest priority. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
-- # #
-- # This source file may be used and distributed without restriction provided that this copyright #
-- # statement is not removed from the file and that any derivative work contains the original #
-- # copyright notice and the associated disclaimer. #
-- # #
-- # This source file is free software; you can redistribute it and/or modify it under the terms #
-- # of the GNU Lesser General Public License as published by the Free Software Foundation, #
-- # either version 3 of the License, or (at your option) any later version. #
-- # #
-- # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
-- # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
-- # See the GNU Lesser General Public License for more details. #
-- # #
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 29.11.2019 #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neo430;
use neo430.neo430_package.all;
 
entity neo430_exirq is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- cpu interrupt --
cpu_irq_o : out std_ulogic;
-- external interrupt lines --
ext_irq_i : in std_ulogic_vector(7 downto 0); -- IRQ
ext_ack_o : out std_ulogic_vector(7 downto 0) -- acknowledge
);
end neo430_exirq;
 
architecture neo430_exirq_rtl of neo430_exirq is
 
-- control register bits --
constant ctrl_src0_c : natural := 0; -- r/-: IRQ source bit 0
constant ctrl_src1_c : natural := 1; -- r/-: IRQ source bit 1
constant ctrl_src2_c : natural := 2; -- r/-: IRQ source bit 2
constant ctrl_trig_c : natural := 3; -- r/w: global trigger (0: high-level, 1: rising-edge)
constant ctrl_en_c : natural := 4; -- r/w: unit enable
-- ...
constant ctrl_en_irq0_c : natural := 8; -- r/w: IRQ 0 enable
constant ctrl_en_irq1_c : natural := 9; -- r/w: IRQ 1 enable
constant ctrl_en_irq2_c : natural := 10; -- r/w: IRQ 2 enable
constant ctrl_en_irq3_c : natural := 11; -- r/w: IRQ 3 enable
constant ctrl_en_irq4_c : natural := 12; -- r/w: IRQ 4 enable
constant ctrl_en_irq5_c : natural := 13; -- r/w: IRQ 5 enable
constant ctrl_en_irq6_c : natural := 14; -- r/w: IRQ 6 enable
constant ctrl_en_irq7_c : natural := 15; -- r/w: IRQ 7 enable
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(exirq_size_c); -- low address boundary bit
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
 
-- r/w accessible registers --
signal irq_enable : std_ulogic_vector(7 downto 0);
signal irq_trigger : std_ulogic;
signal enable : std_ulogic;
 
-- irq input / ack output system --
signal irq_sync0, irq_sync1, irq_sync2, irq_raw, irq_valid, ack_mask : std_ulogic_vector(7 downto 0);
 
-- controller core --
signal irq_buf : std_ulogic_vector(7 downto 0);
signal irq_src, irq_src_reg : std_ulogic_vector(2 downto 0);
signal irq_fire, state : std_ulogic;
 
begin
 
-- Access control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = exirq_base_c(hi_abb_c downto lo_abb_c)) else '0';
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
 
 
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
irq_trigger <= data_i(ctrl_trig_c);
enable <= data_i(ctrl_en_c);
irq_enable <= data_i(ctrl_en_irq7_c downto ctrl_en_irq0_c);
end if;
end if;
end process wr_access;
 
 
-- Get external interrupt request --------------------------------------------
-- -----------------------------------------------------------------------------
exirq_sync: process(clk_i)
begin
if rising_edge(clk_i) then
-- no metastability! --
irq_sync0 <= ext_irq_i;
irq_sync1 <= irq_sync0;
-- sample again for edge detection --
irq_sync2 <= irq_sync1;
end if;
end process exirq_sync;
 
-- rising-edge or high-level detector --
irq_raw <= (irq_sync1 and (not irq_sync2)) when (irq_trigger = '1') else irq_sync1;
 
-- only pass enabled interrupt sources --
irq_valid <= irq_raw and irq_enable;
 
 
-- IRQ controller core ------------------------------------------------------
-- -----------------------------------------------------------------------------
irq_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- irq buffer --
for i in 0 to 7 loop
-- keep requests until they are acknowledged
-- clear buffer when unit is disabled
irq_buf(i) <= (irq_buf(i) or irq_valid(i)) and enable and (not ack_mask(i));
end loop; -- i
 
-- mini state FSM - defaults --
cpu_irq_o <= '0';
ext_ack_o <= (others => '0');
 
-- mini state FSM --
if (state = '0') or (enable = '0') then -- idle or deactivated
state <= '0';
irq_src_reg <= irq_src; -- capture source
if (irq_fire = '1') then
cpu_irq_o <= '1'; -- trigger CPU
state <= '1'; -- goto active IRQ state
end if;
 
else -- active IRQ
if (rden = '1') then -- ACK on when reading IRQ source
ext_ack_o <= ack_mask;
state <= '0';
end if;
end if;
end if;
end process irq_core;
 
-- anybody firing? --
irq_fire <= or_all_f(irq_buf);
 
-- get interrupt priority --
irq_src <= "000" when (irq_buf(0) = '1') else
"001" when (irq_buf(1) = '1') else
"010" when (irq_buf(2) = '1') else
"011" when (irq_buf(3) = '1') else
"100" when (irq_buf(4) = '1') else
"101" when (irq_buf(5) = '1') else
"110" when (irq_buf(6) = '1') else
"111";-- when (irq_buf(7) = '1') else "---";
 
 
-- ACK priority decoder -----------------------------------------------------
-- -----------------------------------------------------------------------------
ack_priority_dec: process(irq_src_reg)
begin
case irq_src_reg is
when "000" => ack_mask <= "00000001";
when "001" => ack_mask <= "00000010";
when "010" => ack_mask <= "00000100";
when "011" => ack_mask <= "00001000";
when "100" => ack_mask <= "00010000";
when "101" => ack_mask <= "00100000";
when "110" => ack_mask <= "01000000";
when "111" => ack_mask <= "10000000";
when others => ack_mask <= "--------";
end case;
end process ack_priority_dec;
 
 
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden = '1') then
data_o(ctrl_src2_c downto ctrl_src0_c) <= irq_src_reg;
data_o(ctrl_en_irq7_c downto ctrl_en_irq0_c) <= irq_enable;
data_o(ctrl_trig_c) <= irq_trigger;
data_o(ctrl_en_c) <= enable;
end if;
end if;
end process rd_access;
 
 
end neo430_exirq_rtl;
/neo430/trunk/neo430/rtl/core/neo430_gpio.vhd
3,6 → 3,7
-- # ********************************************************************************************* #
-- # 16-bit parallel input & output unit. Any pin-change (HI->LO or LO->HI) triggers the IRQ. #
-- # Pins used for the pin change interrupt are selected using a 16-bit mask. #
-- # The PWM controller can be used to module the GPIO controller's output. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
22,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 28.04.2019 #
-- # Stephan Nolting, Hannover, Germany 21.11.2019 #
-- #################################################################################################
 
library ieee;
35,17 → 36,19
entity neo430_gpio is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
-- GPIO PWM --
gpio_pwm_i : in std_ulogic;
-- interrupt --
irq_o : out std_ulogic
irq_o : out std_ulogic
);
end neo430_gpio;
 
62,8 → 65,8
signal rden : std_ulogic; -- read enable
 
-- accessible regs --
signal dout, din : std_ulogic_vector(15 downto 0);
signal irq_mask : std_ulogic_vector(15 downto 0);
signal dout, din : std_ulogic_vector(15 downto 0); -- r/w
signal irq_mask : std_ulogic_vector(15 downto 0); -- -/w
 
-- misc --
signal irq_raw, sync_in, in_buf : std_ulogic_vector(15 downto 0);
94,8 → 97,8
end if;
end process wr_access;
 
-- output --
gpio_o <= dout;
-- (PWM modulated) output --
gpio_o <= dout when (gpio_pwm_i = '1') else (others => '0');
 
 
-- IRQ Generator ------------------------------------------------------------
/neo430/trunk/neo430/rtl/core/neo430_package.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 14.11.2019 #
-- # Stephan Nolting, Hannover, Germany 27.11.2019 #
-- #################################################################################################
 
library ieee;
30,13 → 30,14
 
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0305"; -- no touchy!
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0320"; -- no touchy!
 
-- Advanced Hardware Configuration --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant use_dsp_mul_c : boolean := false; -- use DSP blocks for MULDIV's multiplication (default=false)
constant use_dsp_mul_c : boolean := false; -- use DSP blocks for MULDIV's multiplication core (default=false)
constant use_dadd_cmd_c : boolean := false; -- implement CPU's DADD instruction (default=false)
constant low_power_mode_c : boolean := false; -- reduces switching activity, but will also decrease f_max and might increase area (default=false)
constant use_xalu_c : boolean := false; -- implement extended ALU function (default=false)
constant low_power_mode_c : boolean := false; -- can reduce switching activity, but will also decrease f_max and might increase area (default=false)
constant awesome_mode_c : boolean := true; -- of course! (default=true)
 
-- Internal Functions ---------------------------------------------------------------------
57,7 → 58,7
function and_all_f(a : std_ulogic_vector) return std_ulogic;
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
 
-- Address Space Layout -------------------------------------------------------------------
-- Address Space Layout (make sure this is always sync with neo430.h) ---------------------
-- -------------------------------------------------------------------------------------------
 
-- Main Memory: IMEM(ROM/RAM) --
182,13 → 183,18
constant twi_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"0000");
constant twi_rtx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"0002");
 
-- IO: RESERVED --
--constant ???_base_c : std_ulogic_vector(15 downto 0) := x"FFEC";
--constant ???_size_c : natural := 4; -- bytes
-- IO: True Random Number Generator (TRNG) --
constant trng_base_c : std_ulogic_vector(15 downto 0) := x"FFEC";
constant trng_size_c : natural := 2; -- bytes
 
--constant ???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(???_base_c) + x"0000");
--constant ???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(???_base_c) + x"0002");
constant trng_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"0000");
 
-- IO: External Interrupts Controller (EXIRQ) --
constant exirq_base_c : std_ulogic_vector(15 downto 0) := x"FFEE";
constant exirq_size_c : natural := 2; -- bytes
 
constant exirq_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(exirq_base_c) + x"0000");
 
-- IO: System Configuration (SYSCONFIG) --
constant sysconfig_base_c : std_ulogic_vector(15 downto 0) := x"FFF0";
constant sysconfig_size_c : natural := 16; -- bytes
218,6 → 224,7
constant sreg_n_c : natural := 2; -- r/w: negative flag
constant sreg_i_c : natural := 3; -- r/w: global interrupt enable
constant sreg_s_c : natural := 4; -- r/w: CPU sleep flag
constant sreg_p_c : natural := 5; -- r/w: parity flag
constant sreg_v_c : natural := 8; -- r/w: overflow flag
constant sreg_q_c : natural := 14; -- -/w: clear pending IRQ buffer when set
constant sreg_r_c : natural := 15; -- r/w: enable write access to IMEM (ROM) when set
228,6 → 235,7
constant flag_z_c : natural := 1; -- zero flag
constant flag_n_c : natural := 2; -- negative flag
constant flag_v_c : natural := 3; -- overflow flag
constant flag_p_c : natural := 4; -- parity flag
 
-- Main Control Bus -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
299,7 → 307,7
constant alu_and_c : std_ulogic_vector(3 downto 0) := "1111"; -- r <= a & b
 
 
-- The Core of the Problem: Processor Top Entity ------------------------------------------
-- The Core of the Problem: NEO430 Processor Top Entity -----------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_top
generic (
318,9 → 326,11
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller? (default = true)
PWM_USE : boolean := true; -- implement PWM controller? (default=true)
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
352,13 → 362,13
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic; -- transfer acknowledge
-- interrupts --
irq_i : in std_ulogic; -- external interrupt request line
irq_ack_o : out std_ulogic -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i : in std_ulogic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_ulogic_vector(07 downto 0) -- external interrupt request acknowledges
);
end component;
 
-- Component: Control ---------------------------------------------------------------------
-- Component: CPU Control -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_control
port (
392,7 → 402,7
-- data input --
alu_i : in std_ulogic_vector(15 downto 0); -- data from alu
addr_i : in std_ulogic_vector(15 downto 0); -- data from addr unit
flag_i : in std_ulogic_vector(03 downto 0); -- new ALU flags
flag_i : in std_ulogic_vector(04 downto 0); -- new ALU flags
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
415,7 → 425,7
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- results --
data_o : out std_ulogic_vector(15 downto 0); -- result
flag_o : out std_ulogic_vector(03 downto 0) -- new ALU flags
flag_o : out std_ulogic_vector(04 downto 0) -- new ALU flags
);
end component;
 
462,7 → 472,7
);
end component;
 
-- Component: Instruction Memory (ROM) ----------------------------------------------------
-- Component: Instruction Memory RAM (IMEM) -----------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_imem
generic (
481,7 → 491,7
);
end component;
 
-- Component: Data Memory (RAM) -----------------------------------------------------------
-- Component: Data Memory RAM (DMEM) ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_dmem
generic (
508,7 → 518,7
);
end component;
 
-- Component: Multiplier/Divider ----------------------------------------------------------
-- Component: Multiplier/Divider (MULDIV) -------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_muldiv
port (
522,7 → 532,7
);
end component;
 
-- Component: 32bit Wishbone Interface ----------------------------------------------------
-- Component: 32bit Wishbone Interface (WB32) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_wb_interface
port (
545,7 → 555,7
);
end component;
 
-- Component: UART ------------------------------------------------------------------------
-- Component: Universal Asynchornous Receiver/Transmitter (UART) --------------------------
-- -------------------------------------------------------------------------------------------
component neo430_uart
port (
567,7 → 577,7
);
end component;
 
-- Component: SPI -------------------------------------------------------------------------
-- Component: Serial Peripheral Interface (SPI) -------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_spi
port (
591,26 → 601,28
);
end component;
 
-- Component: GPIO ------------------------------------------------------------------------
-- Component: General Purpose Input/Ouput Controller (GPIO) -------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_gpio
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
-- GPIO PWM --
gpio_pwm_i : in std_ulogic;
-- interrupt --
irq_o : out std_ulogic
irq_o : out std_ulogic
);
end component;
 
-- Component: High-Precision Timer --------------------------------------------------------
-- Component: High-Precision Timer (TIMER) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_timer
port (
629,7 → 641,7
);
end component;
 
-- Component: Watchdog Timer --------------------------------------------------------------
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_wdt
port (
649,7 → 661,7
);
end component;
 
-- Component: CRC Module ------------------------------------------------------------------
-- Component: Cyclic Redundancy Check Unit (CRC)-------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_crc
port (
663,7 → 675,7
);
end component;
 
-- Component: Custom Functions Unit -------------------------------------------------------
-- Component: Custom Functions Unit (CFU) -------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_cfu
port (
679,7 → 691,7
);
end component;
 
-- Component: PWM Controller --------------------------------------------------------------
-- Component: PWM Controller (PWM) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_pwm
port (
693,12 → 705,14
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- GPIO output PWM --
gpio_pwm_o : out std_ulogic;
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
);
end component;
 
-- Component: Serial Two Wire Interfcae ---------------------------------------------------
-- Component: Serial Two Wire Interfcae (TWI) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_twi
port (
720,8 → 734,41
);
end component;
 
-- Component: System Configuration --------------------------------------------------------
-- Component: True Random Number Generator (TRNG) -----------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_trng
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
 
-- Component: External Interrupts Controller (EXIRQ) --------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_exirq
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- cpu interrupt --
cpu_irq_o : out std_ulogic;
-- external interrupt lines --
ext_irq_i : in std_ulogic_vector(7 downto 0); -- IRQ
ext_ack_o : out std_ulogic_vector(7 downto 0) -- acknowledge
);
end component;
 
-- Component: System Configuration (SYSCONFIG) --------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_sysconfig
generic (
-- general configuration --
742,6 → 789,8
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement TWI?
SPI_USE : boolean := true; -- implement SPI?
TRNG_USE : boolean := true; -- implement TRNG?
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
772,7 → 821,7
return 0;
end function index_size_f;
 
-- Function: Test is value (encoded with a certain bit width) is a power of 2 -------------
-- Function: Test if value (encoded with a certain bit width) is a power of 2 -------------
-- -------------------------------------------------------------------------------------------
function is_power_of_two_f(num : natural; bit_width : natural) return boolean is
begin
/neo430/trunk/neo430/rtl/core/neo430_pwm.vhd
1,8 → 1,9
-- #################################################################################################
-- # << NEO430 - PWM Controller >> #
-- # ********************************************************************************************* #
-- # Simple 4-channel PWM controller with 8 bit resolution for the duty cycle and selectable #
-- # counter width (frequency resolution) from 1 to 8 bits. #
-- # Simple 4-channel PWM controller with 4 or 8 bit resolution for the duty cycle and selectable #
-- # counter width (frequency resolution) 4 or 8 bits. #
-- # Channel 3 can be used to alternatively modulate the GPIO unit's output port. #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
22,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 12.05.2019 #
-- # Stephan Nolting, Hannover, Germany 22.11.2019 #
-- #################################################################################################
 
library ieee;
44,6 → 45,8
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- GPIO output PWM --
gpio_pwm_o : out std_ulogic;
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
);
53,7 → 56,6
 
-- internal configuration --
constant num_pwm_channels_c : natural := 4; -- number of PWM channels - FIXED!
constant pwm_resolution_c : natural := 8; -- bit-width - FIXED!
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
64,9 → 66,8
constant ctrl_prsc0_bit_c : natural := 1; -- -/w: prescaler select bit 0
constant ctrl_prsc1_bit_c : natural := 2; -- -/w: prescaler select bit 1
constant ctrl_prsc2_bit_c : natural := 3; -- -/w: prescaler select bit 2
constant ctrl_size0_bit_c : natural := 4; -- -/w: cnt size bit 0
constant ctrl_size1_bit_c : natural := 5; -- -/w: cnt size bit 1
constant ctrl_size2_bit_c : natural := 6; -- -/w: cnt size bit 2
constant ctrl_gpio_pwm_c : natural := 4; -- -/w: use channel 3 for GPIO controller output modulation
constant ctrl_size_sel_c : natural := 5; -- -/w: cnt size select (0 = 4-bit, 1 = 8-bit)
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
74,20 → 75,22
signal wren : std_ulogic; -- word write enable
 
-- accessible regs --
type pwm_ch_t is array (0 to num_pwm_channels_c-1) of std_ulogic_vector(pwm_resolution_c-1 downto 0);
signal pwm_ch : pwm_ch_t;
signal enable : std_ulogic;
signal prsc : std_ulogic_vector(2 downto 0);
signal size : std_ulogic_vector(2 downto 0);
type pwm_ch_t is array (0 to num_pwm_channels_c-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch : pwm_ch_t; -- duty cycle
signal enable : std_ulogic; -- enable unit
signal gpio_pwm : std_ulogic; -- use pwm channel 3 to module GPIO unit's output port
signal prsc : std_ulogic_vector(2 downto 0); -- clock prescaler
signal size_sel : std_ulogic; -- select pwm counter size
 
-- constrained pwm counter --
signal mask : std_ulogic_vector(7 downto 0);
signal mask : std_ulogic_vector(7 downto 0);
 
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
 
-- pwm counter --
signal pwm_cnt : std_ulogic_vector(pwm_resolution_c-1 downto 0);
signal pwm_cnt : std_ulogic_vector(7 downto 0);
signal pwm_out : std_ulogic_vector(3 downto 0);
 
begin
 
104,18 → 107,19
begin
if rising_edge(clk_i) then
if (wren = '1') then
if (addr = pwm_ctrl_addr_c) then
enable <= data_i(ctrl_enable_c);
prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
size <= data_i(ctrl_size2_bit_c downto ctrl_size0_bit_c);
if (addr = pwm_ctrl_addr_c) then -- control register
enable <= data_i(ctrl_enable_c);
prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
size_sel <= data_i(ctrl_size_sel_c);
gpio_pwm <= data_i(ctrl_gpio_pwm_c);
end if;
if (addr = pwm_ch10_addr_c) then
pwm_ch(0) <= data_i(0+(pwm_resolution_c-1) downto 0);
pwm_ch(1) <= data_i(8+(pwm_resolution_c-1) downto 8);
pwm_ch(0) <= data_i(07 downto 0);
pwm_ch(1) <= data_i(15 downto 8);
end if;
if (addr = pwm_ch32_addr_c) then
pwm_ch(2) <= data_i(0+(pwm_resolution_c-1) downto 0);
pwm_ch(3) <= data_i(8+(pwm_resolution_c-1) downto 8);
pwm_ch(2) <= data_i(07 downto 0);
pwm_ch(3) <= data_i(15 downto 8);
end if;
end if;
end if;
125,25 → 129,11
clkgen_en_o <= enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(prsc)));
 
-- effective counter width --
mask(3 downto 0) <= "1111";
mask(7 downto 4) <= (others => size_sel);
 
-- Virtual Counter Size -----------------------------------------------------
-- -----------------------------------------------------------------------------
mask_gen: process(size)
begin
case size is
when "000" => mask <= "00000001";
when "001" => mask <= "00000011";
when "010" => mask <= "00000111";
when "011" => mask <= "00001111";
when "100" => mask <= "00011111";
when "101" => mask <= "00111111";
when "110" => mask <= "01111111";
when "111" => mask <= "11111111";
when others => mask <= (others => '1');
end case;
end process mask_gen;
 
 
-- PWM Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
pwm_core: process(clk_i)
153,21 → 143,30
if (enable = '0') then
pwm_cnt <= (others => '0');
elsif (prsc_tick = '1') then
-- constrain counter to virtual size configured by SIZE register
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
-- channels --
for i in 0 to num_pwm_channels_c-1 loop
-- constrain counter to virtual size configured by SIZE register
if (unsigned(pwm_cnt and mask) >= unsigned(pwm_ch(i))) or (enable = '0') then
pwm_o(i) <= '0';
pwm_out(i) <= '0';
else
pwm_o(i) <= '1';
pwm_out(i) <= '1';
end if;
end loop; -- i, pwm channel
end if;
end process pwm_core;
 
-- output --
pwm_o(0) <= pwm_out(0);
pwm_o(1) <= pwm_out(1);
pwm_o(2) <= pwm_out(2);
pwm_o(3) <= pwm_out(3) when (gpio_pwm = '0') else '0'; -- output if channel is not used for GPIO
 
-- GPIO output modulation --
gpio_pwm_o <= pwm_out(3) when (gpio_pwm = '1') else '1';
 
 
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
175,12 → 174,12
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
if (addr = pwm_ch10_addr_c) then
data_o(0+(pwm_resolution_c-1) downto 0) <= pwm_ch(0);
data_o(8+(pwm_resolution_c-1) downto 8) <= pwm_ch(1);
else -- pwm_ch32_addr_c
data_o(0+(pwm_resolution_c-1) downto 0) <= pwm_ch(2);
data_o(8+(pwm_resolution_c-1) downto 8) <= pwm_ch(3);
if (addr = pwm_ch10_addr_c) then -- PWM channel 0 & 1
data_o(07 downto 0) <= pwm_ch(0);
data_o(15 downto 8) <= pwm_ch(1);
else -- PWM channel 2 & 3
data_o(07 downto 0) <= pwm_ch(2);
data_o(15 downto 8) <= pwm_ch(3);
end if;
end if;
end if;
/neo430/trunk/neo430/rtl/core/neo430_reg_file.vhd
21,7 → 21,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 26.05.2018 #
-- # Stephan Nolting, Hannover, Germany 29.11.2019 #
-- #################################################################################################
 
library ieee;
43,7 → 43,7
-- data input --
alu_i : in std_ulogic_vector(15 downto 0); -- data from alu
addr_i : in std_ulogic_vector(15 downto 0); -- data from addr unit
flag_i : in std_ulogic_vector(03 downto 0); -- new ALU flags
flag_i : in std_ulogic_vector(04 downto 0); -- new ALU flags
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
98,6 → 98,9
sreg(sreg_s_c) <= in_data(sreg_s_c);
sreg(sreg_v_c) <= in_data(sreg_v_c);
sreg(sreg_q_c) <= in_data(sreg_q_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg(sreg_p_c) <= in_data(sreg_p_c);
end if;
if (IMEM_AS_ROM = false) then -- r-flag is 0 when IMEM is ROM
sreg(sreg_r_c) <= in_data(sreg_r_c);
end if;
117,6 → 120,9
sreg(sreg_z_c) <= flag_i(flag_z_c);
sreg(sreg_n_c) <= flag_i(flag_n_c);
sreg(sreg_v_c) <= flag_i(flag_v_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg(sreg_p_c) <= flag_i(flag_p_c);
end if;
end if;
end if;
end if;
125,6 → 131,20
-- construct logical status register --
sreg_combine: process(sreg)
begin
-- SREG for system --
sreg_o <= (others => '0');
sreg_o(sreg_c_c) <= sreg(sreg_c_c);
sreg_o(sreg_z_c) <= sreg(sreg_z_c);
sreg_o(sreg_n_c) <= sreg(sreg_n_c);
sreg_o(sreg_i_c) <= sreg(sreg_i_c);
sreg_o(sreg_s_c) <= sreg(sreg_s_c);
sreg_o(sreg_v_c) <= sreg(sreg_v_c);
sreg_o(sreg_q_c) <= sreg(sreg_q_c);
sreg_o(sreg_r_c) <= sreg(sreg_r_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg_o(sreg_p_c) <= sreg(sreg_p_c);
end if;
-- SREG for user --
sreg_int <= (others => '0');
sreg_int(sreg_c_c) <= sreg(sreg_c_c);
sreg_int(sreg_z_c) <= sreg(sreg_z_c);
132,13 → 152,13
sreg_int(sreg_i_c) <= sreg(sreg_i_c);
sreg_int(sreg_s_c) <= sreg(sreg_s_c);
sreg_int(sreg_v_c) <= sreg(sreg_v_c);
sreg_int(sreg_q_c) <= sreg(sreg_q_c);
--sreg_int(sreg_q_c) <= sreg(sreg_q_c); -- is always zero for user
sreg_int(sreg_r_c) <= sreg(sreg_r_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg_int(sreg_p_c) <= sreg(sreg_p_c);
end if;
end process sreg_combine;
 
-- status register output --
sreg_o <= sreg_int;
 
-- general purpose register file (including PC, SP, dummy SR and dummy CG) --
rf_write: process(clk_i)
begin
/neo430/trunk/neo430/rtl/core/neo430_sysconfig.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
52,6 → 52,8
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement TWI?
SPI_USE : boolean := true; -- implement SPI?
TRNG_USE : boolean := true; -- implement TRNG?
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
116,8 → 118,8
sysinfo_mem(1)(11) <= bool_to_ulogic_f(PWM_USE); -- PWM present?
sysinfo_mem(1)(12) <= bool_to_ulogic_f(TWI_USE); -- TWI present?
sysinfo_mem(1)(13) <= bool_to_ulogic_f(SPI_USE); -- SPI present?
sysinfo_mem(1)(14) <= '0'; -- reserved
sysinfo_mem(1)(15) <= '0'; -- reserved
sysinfo_mem(1)(14) <= bool_to_ulogic_f(TRNG_USE); -- TRNG present?
sysinfo_mem(1)(15) <= bool_to_ulogic_f(EXIRQ_USE); -- EXIRQ present?
 
-- CPUID2: User code --
sysinfo_mem(2) <= USER_CODE;
125,8 → 127,8
-- CPUID3: IMEM (ROM/RAM) size --
sysinfo_mem(3) <= std_ulogic_vector(to_unsigned(IMEM_SIZE, 16)); -- size in bytes
 
-- CPUID4: DMEM (RAM) base address --
sysinfo_mem(4) <= dmem_base_c;
-- CPUID4: reserved --
sysinfo_mem(4) <= (others => '0');
 
-- CPUID5: DMEM (RAM) size --
sysinfo_mem(5) <= std_ulogic_vector(to_unsigned(DMEM_SIZE, 16)); -- size in bytes
/neo430/trunk/neo430/rtl/core/neo430_top.vhd
4,6 → 4,7
-- # This is the top entity of the NEO430 processor. Instantiate this unit in your own project and #
-- # define all the configuration generics according to your needs. Alternatively, you can use one #
-- # of the other top entities provided in rtl\top_templates #
-- # Check the processor's documentary for more information: doc\NEO430.pdf #
-- # ********************************************************************************************* #
-- # The NEO430 processor: #
-- # - Reset and clock generators #
24,6 → 25,8
-- # - Optional Custom Functions Unit to implement user-defined processor extension (CFU) #
-- # - Optional Pulse Width Modulation controller (PWM) #
-- # - Optional Two Wire Serial Interface (TWI) #
-- # - Optional True Random Number Generator (TRNG) #
-- # - OPtional External Interrupts Controller (EXIRQ) #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
43,7 → 46,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 29.11.2019 #
-- #################################################################################################
 
library ieee;
74,6 → 77,8
PWM_USE : boolean := true; -- implement PWM controller? (default=true)
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
105,9 → 110,9
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic; -- transfer acknowledge
-- external interrupt --
irq_i : in std_ulogic; -- external interrupt request line
irq_ack_o : out std_ulogic -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i : in std_ulogic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_ulogic_vector(07 downto 0) -- external interrupt request acknowledges
);
end neo430_top;
 
160,20 → 165,25
signal cfu_rdata : std_ulogic_vector(15 downto 0);
signal pwm_rdata : std_ulogic_vector(15 downto 0);
signal twi_rdata : std_ulogic_vector(15 downto 0);
signal trng_rdata : std_ulogic_vector(15 downto 0);
signal exirq_rdata : std_ulogic_vector(15 downto 0);
signal sysconfig_rdata : std_ulogic_vector(15 downto 0);
 
-- interrupt system --
signal irq : std_ulogic_vector(03 downto 0);
signal irq_ack : std_ulogic_vector(03 downto 0);
signal timer_irq : std_ulogic;
signal uart_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal gpio_irq : std_ulogic;
signal xirq_sync : std_ulogic;
signal irq : std_ulogic_vector(03 downto 0);
signal irq_ack : std_ulogic_vector(03 downto 0);
signal timer_irq : std_ulogic;
signal uart_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal gpio_irq : std_ulogic;
signal xirq_sync0 : std_ulogic;
signal xirq_sync1 : std_ulogic;
signal ext_irq : std_ulogic;
 
-- misc --
signal imem_up_en : std_ulogic;
signal gpio_pwm : std_ulogic;
 
begin
 
262,26 → 272,15
cpu_bus.rdata <= rom_rdata or ram_rdata or boot_rdata or muldiv_rdata or
wb_rdata or uart_rdata or spi_rdata or gpio_rdata or
timer_rdata or wdt_rdata or sysconfig_rdata or crc_rdata or
cfu_rdata or pwm_rdata or twi_rdata;
cfu_rdata or pwm_rdata or twi_rdata or trng_rdata or exirq_rdata;
 
-- sync for external IRQ --
external_irq_sync: process(clk_i)
begin
if rising_edge(clk_i) then
xirq_sync <= irq_i;
end if;
end process external_irq_sync;
 
-- interrupt priority assignment --
irq(0) <= timer_irq; -- timer match (highest priority)
irq(1) <= uart_irq or spi_irq or twi_irq; -- serial IRQ
irq(2) <= gpio_irq; -- GPIO input pin change
irq(3) <= xirq_sync; -- external interrupt request (lowest priority)
irq(3) <= ext_irq; -- external interrupt request (lowest priority)
 
-- external interrupt acknowledge --
irq_ack_o <= irq_ack(3); -- the internal irq sources do not require an acknowledge
 
 
-- Main Memory (ROM/IMEM & RAM/DMEM) ----------------------------------------
-- -----------------------------------------------------------------------------
neo430_imem_inst: neo430_imem
340,7 → 339,7
io_wr_en <= (cpu_bus.wr_en(0) or cpu_bus.wr_en(1)) and io_acc;
 
 
-- Multiplier/Divider Unit --------------------------------------------------
-- Multiplier/Divider Unit (MULDIV) -----------------------------------------
-- -----------------------------------------------------------------------------
neo430_muldiv_inst_true:
if (MULDIV_USE = true) generate
362,7 → 361,7
end generate;
 
 
-- Wishbone Adapter ---------------------------------------------------------
-- Wishbone Adapter (WB32) --------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_wb32_if_inst_true:
if (WB32_USE = true) generate
399,7 → 398,7
end generate;
 
 
-- Universal Asynchronous Receiver & Transmitter ----------------------------
-- Universal Asynchronous Receiver & Transmitter (UART) ---------------------
-- -----------------------------------------------------------------------------
neo430_uart_inst_true:
if (UART_USE = true) generate
432,7 → 431,7
end generate;
 
 
-- Serial Peripheral Interface ----------------------------------------------
-- Serial Peripheral Interface (SPI) ----------------------------------------
-- -----------------------------------------------------------------------------
neo430_spi_inst_true:
if (SPI_USE = true) generate
469,7 → 468,7
end generate;
 
 
-- Parallel IO --------------------------------------------------------------
-- General Purpose Parallel IO (GPIO) ---------------------------------------
-- -----------------------------------------------------------------------------
neo430_gpio_inst_true:
if (GPIO_USE = true) generate
476,17 → 475,19
neo430_gpio_inst: neo430_gpio
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => gpio_rdata, -- data out
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => gpio_rdata, -- data out
-- parallel io --
gpio_o => gpio_o,
gpio_i => gpio_i,
gpio_o => gpio_o,
gpio_i => gpio_i,
-- GPIO PWM --
gpio_pwm_i => gpio_pwm,
-- interrupt --
irq_o => gpio_irq -- pin-change interrupt
irq_o => gpio_irq -- pin-change interrupt
);
end generate;
 
498,7 → 499,7
end generate;
 
 
-- High Precision Timer -----------------------------------------------------
-- High Precision Timer (TIMER) ---------------------------------------------
-- -----------------------------------------------------------------------------
neo430_timer_inst_true:
if (TIMER_USE = true) generate
527,7 → 528,7
end generate;
 
 
-- Watchdog Timer -----------------------------------------------------------
-- Watchdog Timer (WDT) -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_wdt_inst_true:
if (WDT_USE = true) generate
557,7 → 558,7
end generate;
 
 
-- CRC Module ---------------------------------------------------------------
-- CRC Module (CRC) ---------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_crc_inst_true:
if (CRC_USE = true) generate
579,7 → 580,7
end generate;
 
 
-- Custom Functions Unit ----------------------------------------------------
-- Custom Functions Unit (CFU) ----------------------------------------------
-- -----------------------------------------------------------------------------
neo430_cfu_inst_true:
if (CFU_USE = true) generate
602,7 → 603,7
end generate;
 
 
-- PWM Controller -----------------------------------------------------------
-- PWM Controller (PWM) -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_pwm_inst_true:
if (PWM_USE = true) generate
618,6 → 619,8
-- clock generator --
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- GPIO output PWM --
gpio_pwm_o => gpio_pwm,
-- pwm output channels --
pwm_o => pwm_o
);
626,12 → 629,13
neo430_pwm_inst_false:
if (PWM_USE = false) generate
pwm_cg_en <= '0';
gpio_pwm <= '1';
pwm_rdata <= (others => '0');
pwm_o <= (others => '0');
end generate;
 
 
-- Two Wire Serial Interface ------------------------------------------------
-- Two Wire Serial Interface (SPI) ------------------------------------------
-- -----------------------------------------------------------------------------
neo430_twi_inst_true:
if (TWI_USE = true) generate
663,28 → 667,68
end generate;
 
 
-- Reserved -----------------------------------------------------------------
-- True Random Number Generator (TRNG) --------------------------------------
-- -----------------------------------------------------------------------------
--neo430_???_inst_true:
--if (???_USE = true) generate
-- neo430_???_inst: neo430_???
-- port map (
-- -- host access --
-- clk_i => clk_i, -- global clock line
-- rden_i => io_rd_en, -- read enable
-- wren_i => io_wr_en, -- write enable
-- addr_i => cpu_bus.addr, -- address
-- data_i => cpu_bus.wdata, -- data in
-- data_o => ???_rdata -- data out
-- );
--end generate;
--
--neo430_???_inst_false:
--if (???_USE = false) generate
-- ???_rdata <= (others => '0');
--end generate;
neo430_trng_inst_true:
if (TRNG_USE = true) generate
neo430_trng_inst: neo430_trng
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => trng_rdata -- data out
);
end generate;
 
neo430_trng_inst_false:
if (TRNG_USE = false) generate
trng_rdata <= (others => '0');
end generate;
 
 
-- External Interrupts Controller (EXIRQ) -----------------------------------
-- -----------------------------------------------------------------------------
neo430_exirq_inst_true:
if (EXIRQ_USE = true) generate
neo430_exirq_inst: neo430_exirq
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => exirq_rdata, -- data out
-- cpu interrupt --
cpu_irq_o => ext_irq,
-- external interrupt lines --
ext_irq_i => ext_irq_i, -- IRQ
ext_ack_o => ext_ack_o -- acknowledge
);
end generate;
 
neo430_exirq_inst_false:
if (EXIRQ_USE = false) generate
exirq_rdata <= (others => '0');
ext_ack_o <= "0000000" & irq_ack(3);
ext_irq <= xirq_sync1;
end generate;
 
-- sync for single external IRQ if EXIRQ is not implemented --
external_irq_sync: process(clk_i)
begin
if rising_edge(clk_i) then
if (EXIRQ_USE = false) then
xirq_sync0 <= ext_irq_i(0);
xirq_sync1 <= xirq_sync0;
end if;
end if;
end process external_irq_sync;
 
 
-- System Configuration -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_sysconfig_inst: neo430_sysconfig
707,6 → 751,8
PWM_USE => PWM_USE, -- implement PWM?
TWI_USE => TWI_USE, -- implement TWI?
SPI_USE => SPI_USE, -- implement SPI?
TRNG_USE => TRNG_USE, -- implement TRNG?
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader?
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
/neo430/trunk/neo430/rtl/core/neo430_trng.vhd
0,0 → 1,182
-- #################################################################################################
-- # << NEO430 - True Random Number Generator >> #
-- # ********************************************************************************************* #
-- # This unit implements a true random number generator which uses an inverter chain as entropy #
-- # source. The inverter chain is constructed as GARO (Galois Ring Oscillator) TRNG. The single #
-- # inverters are connected via simple latches that are used to enbale/disable the TRNG. Also, #
-- # these latches are used as additional delay element. By using unique enable signals for each #
-- # latch, the synthesis tool cannot "optimize" one of the inverters out of the design. Further- #
-- # more, the latches prevent the synthesis tool from detecting combinatorial loops. #
-- # #
-- # Sources: #
-- # - GARO: "Enhancing the Randomness of a Combined True Random Number Generator Based on the #
-- # Ring Oscillator Sampling Method" by Mieczyslaw Jessa and Lukasz Matuszewski #
-- # - Latches for platform independence: "Extended Abstract: The Butterfly PUF Protecting IP #
-- # on every FPGA" by Sandeep S. Kumar, Jorge Guajardo, Roel Maesyz, Geert-Jan Schrijen and #
-- # Pim Tuyls, Philips Research Europe, 2008 #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
-- # Copyright by Stephan Nolting: stnolting@gmail.com #
-- # #
-- # This source file may be used and distributed without restriction provided that this copyright #
-- # statement is not removed from the file and that any derivative work contains the original #
-- # copyright notice and the associated disclaimer. #
-- # #
-- # This source file is free software; you can redistribute it and/or modify it under the terms #
-- # of the GNU Lesser General Public License as published by the Free Software Foundation, #
-- # either version 3 of the License, or (at your option) any later version. #
-- # #
-- # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
-- # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
-- # See the GNU Lesser General Public License for more details. #
-- # #
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 27.11.2019 #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neo430;
use neo430.neo430_package.all;
 
entity neo430_trng is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_trng;
 
architecture neo430_trng_rtl of neo430_trng is
 
-- user configuration --------------------------------------------------------------------------------
constant num_oscs_c : natural := 5; -- number of oscillators (default=5)
constant garo_taps_c : std_ulogic_vector(num_oscs_c-2 downto 0) := "0101"; -- GARO xor feedback select
constant use_lfsr_c : boolean := true; -- use LFSR for post-processing (default=true)
constant lfsr_taps_c : std_ulogic_vector(7 downto 0) := "10111000"; -- LFSR feedback taps
-- ---------------------------------------------------------------------------------------------------
 
-- control register bits --
constant ctrl_rnd_en_c : natural := 15; -- -/w: TRNG enable
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(trng_size_c); -- low address boundary bit
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
 
-- random number generator --
signal rnd_inv : std_ulogic_vector(num_oscs_c-1 downto 0); -- inverter chain
signal rnd_enable_sreg : std_ulogic_vector(num_oscs_c-1 downto 0); -- enable shift register
signal rnd_enable : std_ulogic;
signal rnd_sync0 : std_ulogic;
signal rnd_sync1 : std_ulogic;
signal rnd_sreg : std_ulogic_vector(7 downto 0); -- sample shift reg
signal rnd_cnt : std_ulogic_vector(2 downto 0);
signal rnd_data : std_ulogic_vector(7 downto 0); -- random data register (read-only)
 
begin
 
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
 
 
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- write access --
if (wren = '1') then
rnd_enable <= data_i(ctrl_rnd_en_c);
end if;
-- using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool
-- from removing all but one inverter (since they implement "logical identical functions")
-- this also allows to make the trng platform independent
rnd_enable_sreg <= rnd_enable_sreg(num_oscs_c-2 downto 0) & rnd_enable; -- activate right most inverter first
end if;
end process wr_access;
 
 
-- True Random Generator ----------------------------------------------------
-- -----------------------------------------------------------------------------
entropy_source: process(rnd_enable_sreg, rnd_enable, rnd_inv)
begin
for i in 0 to num_oscs_c-1 loop
if (rnd_enable = '0') then -- start with a defined state (latch reset)
rnd_inv(i) <= '0';
-- use latches to decouple the inverters
-- by this, the synthesis tool does not complain about combinatorial loops
elsif (rnd_enable_sreg(i) = '1') then -- uniquely enable latches to prevent synthesis from removing chain elements
-- here we have the inverter chain --
if (i = num_oscs_c-1) then -- left most inverter?
rnd_inv(i) <= not rnd_inv(0); -- direct input of right most inverter (= output signal)
else
if (garo_taps_c(i) = '1') then
rnd_inv(i) <= (not rnd_inv(i+1)) xor rnd_inv(0); -- use final output as feedback
else
rnd_inv(i) <= not rnd_inv(i+1); -- normal chain: use previous inverter's output as input
end if;
end if;
end if;
end loop; -- i
end process entropy_source;
 
 
-- Random Data Shift Register -----------------------------------------------
-- -----------------------------------------------------------------------------
data_sreg: process(clk_i)
begin
if rising_edge(clk_i) then
-- synchronize output of oscillator chain --
rnd_sync0 <= rnd_inv(0);
rnd_sync1 <= rnd_sync0; -- no more metastability
-- sample random data --
if (rnd_enable = '0') then
rnd_cnt <= (others => '0');
rnd_sreg <= (others => '0');
else
rnd_cnt <= std_ulogic_vector(unsigned(rnd_cnt) + 1);
if (use_lfsr_c = true) then -- use LFSR for post-processing
rnd_sreg <= rnd_sreg(6 downto 0) & (xor_all_f(rnd_sreg and lfsr_taps_c) xor rnd_sync1);
else -- no post-processing
rnd_sreg <= rnd_sreg(6 downto 0) & rnd_sync1;
end if;
end if;
-- sample final output byte --
if (rnd_cnt = "000") and (rnd_enable = '1') then
rnd_data <= rnd_sreg;
end if;
end if;
end process data_sreg;
 
 
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden = '1') then
data_o(7 downto 0) <= rnd_data;
data_o(ctrl_rnd_en_c) <= rnd_enable;
end if;
end if;
end process rd_access;
 
 
end neo430_trng_rtl;
/neo430/trunk/neo430/rtl/core/neo430_wdt.vhd
25,7 → 25,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 29.09.2018 #
-- # Stephan Nolting, Hannover, Germany 27.11.2019 #
-- #################################################################################################
 
library ieee;
68,6 → 68,7
constant ctrl_clksel2_c : natural := 2; -- r/w: prescaler select bit 2
constant ctrl_enable_c : natural := 3; -- r/w: WDT enable
constant ctrl_rcause_c : natural := 4; -- r/-: reset cause (0: external, 1: watchdog timeout)
constant ctrl_rpwfail_c : natural := 5; -- r/-: watchdog reset caused by wrong password access when '1'
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
76,9 → 77,10
signal wren : std_ulogic;
 
-- accessible regs --
signal source : std_ulogic; -- source of the system reset: '0' = external, '1' = watchdog timeout
signal enable : std_ulogic;
signal clk_sel : std_ulogic_vector(02 downto 0);
signal rst_source : std_ulogic; -- source of the system reset: '0' = external, '1' = watchdog timeout
signal pw_fail : std_ulogic; -- watchdog reset caused by wrong password access
signal enable : std_ulogic;
signal clk_sel : std_ulogic_vector(02 downto 0);
 
-- reset counter --
signal cnt : std_ulogic_vector(16 downto 0);
94,8 → 96,8
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check
wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- access ok
fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- access fail!
wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok
fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail!
 
 
-- Write Access, Reset Generator --------------------------------------------
104,7 → 106,7
begin
if (rst_i = '0') or (rst_sync(1) = '0') then -- external or internal reset
enable <= '0'; -- disable WDT
clk_sel <= (others => '1'); -- slowest clock source
clk_sel <= (others => '1'); -- slowest clock rst_source
rst_gen <= (others => '1'); -- do NOT fire on reset!
elsif rising_edge(clk_i) then
-- control register write access --
153,9 → 155,12
rst_cause: process(rst_i, clk_i)
begin
if (rst_i = '0') then
source <= '0';
rst_source <= '0';
pw_fail <= '0';
elsif rising_edge(clk_i) then
source <= source or (not rst_sync(1));
rst_source <= rst_source or (cnt(cnt'left) and enable) or (fail_ff and enable); -- set on WDT timeout or access error
pw_fail <= (pw_fail or (fail_ff and enable)) and (not (cnt(cnt'left) and enable)); -- set on failed access, clear on WDT timeout
--pw_fail <= (pw_fail and (not (cnt(cnt'left) and enable))) or (fail_ff and enable); -- clear on WDT timeout, set on failed access
end if;
end process rst_cause;
 
168,8 → 173,9
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= clk_sel;
data_o(ctrl_enable_c) <= enable;
data_o(ctrl_rcause_c) <= source;
data_o(ctrl_enable_c) <= enable;
data_o(ctrl_rcause_c) <= rst_source;
data_o(ctrl_rpwfail_c) <= pw_fail;
end if;
end if;
end process read_access;
/neo430/trunk/neo430/rtl/top_templates/neo430_test.vhd
23,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
78,6 → 78,8
PWM_USE => true, -- implement PWM controller? (default=true)
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
TRNG_USE => false, -- implement TRNG? (default=false)
EXIRQ_USE => true, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
109,9 → 111,9
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- external interrupt --
irq_i => '0', -- external interrupt request line
irq_ack_o => open -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i => "00000000", -- external interrupt request lines
ext_ack_o => open -- external interrupt request acknowledges
);
 
-- constrain output signals --
/neo430/trunk/neo430/rtl/top_templates/neo430_top_avm.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
49,6 → 49,8
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
72,9 → 74,9
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic; -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0) -- external interrupt request acknowledges
-- Avalon master interface --
avm_address : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
126,8 → 128,8
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(07 downto 0);
signal irq_i_int : std_ulogic;
signal irq_ack_o_int : std_ulogic;
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
 
-- misc --
157,6 → 159,8
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
201,7 → 205,7
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic(irq_i);
irq_i_int <= std_ulogic_vector(irq_i);
 
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
209,7 → 213,7
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
irq_ack_o <= std_logic(irq_ack_o_int);
irq_ack_o <= std_logic_vector(irq_ack_o_int);
 
 
-- Wishbone-to-Avalon Bridge ------------------------------------------------
/neo430/trunk/neo430/rtl/top_templates/neo430_top_axi4lite.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
49,6 → 49,8
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
69,9 → 71,9
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic; -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0) -- external interrupt request acknowledges
-- AXI Lite-Compatible Master Interface --
-- Clock and Reset
m_axi_aclk : in std_logic;
128,8 → 130,8
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(07 downto 0);
signal irq_i_int : std_ulogic;
signal irq_ack_o_int : std_ulogic;
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
 
-- AXI arbiter --
164,6 → 166,8
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
206,7 → 210,7
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic(irq_i);
irq_i_int <= std_ulogic_vector(irq_i);
 
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
214,7 → 218,7
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
irq_ack_o <= std_logic(irq_ack_o_int);
irq_ack_o <= std_logic_vector(irq_ack_o_int);
 
 
-- Wishbone-to-AXI4-Lite-compatible Bridge ----------------------------------
/neo430/trunk/neo430/rtl/top_templates/neo430_top_std_logic.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 13.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
49,6 → 49,8
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
80,9 → 82,9
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0) -- external interrupt request acknowledges
);
end neo430_top_std_logic;
 
101,8 → 103,8
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(07 downto 0);
signal irq_i_int : std_ulogic;
signal irq_ack_o_int : std_ulogic;
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal wb_adr_o_int : std_ulogic_vector(31 downto 0);
signal wb_dat_i_int : std_ulogic_vector(31 downto 0);
signal wb_dat_o_int : std_ulogic_vector(31 downto 0);
136,6 → 138,8
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
182,7 → 186,7
spi_miso_i_int <= std_ulogic(spi_miso_i);
wb_dat_i_int <= std_ulogic_vector(wb_dat_i);
wb_ack_i_int <= std_ulogic(wb_ack_i);
irq_i_int <= std_logic(irq_i);
irq_i_int <= std_logic_vector(irq_i);
 
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
196,7 → 200,7
wb_sel_o <= std_logic_vector(wb_sel_o_int);
wb_stb_o <= std_logic(wb_stb_o_int);
wb_cyc_o <= std_logic(wb_cyc_o_int);
irq_ack_o <= std_logic(irq_ack_o_int);
irq_ack_o <= std_logic_vector(irq_ack_o_int);
 
 
end neo430_top_std_logic_rtl;
/neo430/trunk/neo430/sim/ISIM/neo430_tb.wcfg
12,15 → 12,15
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="335818933334fs"></ZoomStartTime>
<ZoomEndTime time="336035333335fs"></ZoomEndTime>
<Cursor1Time time="335860533000fs"></Cursor1Time>
<ZoomStartTime time="19996391666667fs"></ZoomStartTime>
<ZoomEndTime time="20018191666668fs"></ZoomEndTime>
<Cursor1Time time="20000025000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="167"></NameColumnWidth>
<ValueColumnWidth column_width="73"></ValueColumnWidth>
<ValueColumnWidth column_width="65"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="120" />
<WVObjectSize size="132" />
<wvobject type="divider" fp_name="divider6">
<obj_property name="label">Global</obj_property>
<obj_property name="DisplayName">label</obj_property>
267,6 → 267,7
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_gpio_inst_true/neo430_gpio_inst/gpio_o" type="array">
<obj_property name="ElementShortName">gpio_o[15:0]</obj_property>
<obj_property name="ObjectShortName">gpio_o[15:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_gpio_inst_true/neo430_gpio_inst/gpio_i" type="array">
<obj_property name="ElementShortName">gpio_i[15:0]</obj_property>
365,10 → 366,6
<obj_property name="ElementShortName">wr_en</obj_property>
<obj_property name="ObjectShortName">wr_en</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_muldiv_inst_true/neo430_muldiv_inst/acc_en" type="logic">
<obj_property name="ElementShortName">acc_en</obj_property>
<obj_property name="ObjectShortName">acc_en</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_muldiv_inst_true/neo430_muldiv_inst/opa" type="array">
<obj_property name="ElementShortName">opa[15:0]</obj_property>
<obj_property name="ObjectShortName">opa[15:0]</obj_property>
470,14 → 467,6
<obj_property name="label">IO: TWI</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_twi_inst_true/neo430_twi_inst/data_i" type="array">
<obj_property name="ElementShortName">data_i[15:0]</obj_property>
<obj_property name="ObjectShortName">data_i[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_twi_inst_true/neo430_twi_inst/data_o" type="array">
<obj_property name="ElementShortName">data_o[15:0]</obj_property>
<obj_property name="ObjectShortName">data_o[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_twi_inst_true/neo430_twi_inst/wr_en" type="logic">
<obj_property name="ElementShortName">wr_en</obj_property>
<obj_property name="ObjectShortName">wr_en</obj_property>
515,4 → 504,64
<obj_property name="ElementShortName">twi_scl_io</obj_property>
<obj_property name="ObjectShortName">twi_scl_io</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider22">
<obj_property name="label">IO: EXIRQ</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/ext_irq_i" type="array">
<obj_property name="ElementShortName">ext_irq_i[7:0]</obj_property>
<obj_property name="ObjectShortName">ext_irq_i[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/ext_ack_o" type="array">
<obj_property name="ElementShortName">ext_ack_o[7:0]</obj_property>
<obj_property name="ObjectShortName">ext_ack_o[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/acc_en" type="logic">
<obj_property name="ElementShortName">acc_en</obj_property>
<obj_property name="ObjectShortName">acc_en</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/wren" type="logic">
<obj_property name="ElementShortName">wren</obj_property>
<obj_property name="ObjectShortName">wren</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/rden" type="logic">
<obj_property name="ElementShortName">rden</obj_property>
<obj_property name="ObjectShortName">rden</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/enable" type="logic">
<obj_property name="ElementShortName">enable</obj_property>
<obj_property name="ObjectShortName">enable</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_trigger" type="logic">
<obj_property name="ElementShortName">irq_trigger</obj_property>
<obj_property name="ObjectShortName">irq_trigger</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/state" type="logic">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_raw" type="array">
<obj_property name="ElementShortName">irq_raw[7:0]</obj_property>
<obj_property name="ObjectShortName">irq_raw[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_enable" type="array">
<obj_property name="ElementShortName">irq_enable[7:0]</obj_property>
<obj_property name="ObjectShortName">irq_enable[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_valid" type="array">
<obj_property name="ElementShortName">irq_valid[7:0]</obj_property>
<obj_property name="ObjectShortName">irq_valid[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_buf" type="array">
<obj_property name="ElementShortName">irq_buf[7:0]</obj_property>
<obj_property name="ObjectShortName">irq_buf[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/irq_src_reg" type="array">
<obj_property name="ElementShortName">irq_src_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">irq_src_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/neo430_tb/neo430_top_inst/neo430_exirq_inst_true/neo430_exirq_inst/cpu_irq_o" type="logic">
<obj_property name="ElementShortName">cpu_irq_o</obj_property>
<obj_property name="ObjectShortName">cpu_irq_o</obj_property>
</wvobject>
</wave_config>
/neo430/trunk/neo430/sim/neo430_tb.vhd
22,7 → 22,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 14.11.2019 #
-- # Stephan Nolting, Hannover, Germany 28.11.2019 #
-- #################################################################################################
 
library ieee;
60,7 → 60,7
 
-- generators --
signal clk_gen, rst_gen : std_ulogic := '0';
signal irq, irq_ack : std_ulogic;
signal irq, irq_ack : std_ulogic_vector(7 downto 0);
 
-- local signals --
signal uart_txd : std_ulogic;
107,6 → 107,8
PWM_USE => true, -- implement PWM controller? (default=true)
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
TRNG_USE => false, -- implement TRNG? (default=false) - CANNOT BE SIMULATED!
EXIRQ_USE => true, -- implement EXIRQ? (default=true)
-- boot configuration --
BOOTLD_USE => false, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
138,9 → 140,9
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- external interrupt --
irq_i => irq, -- external interrupt request line
irq_ack_o => irq_ack -- external interrupt request acknowledge
-- external interrupts --
ext_irq_i => irq, -- external interrupt request lines
ext_ack_o => irq_ack -- external interrupt request acknowledges
);
 
-- twi pull-ups --
152,14 → 154,12
-- -----------------------------------------------------------------------------
interrupt_gen: process
begin
--irq <= '0';
--wait for 20 ms;
--wait until rising_edge(clk_gen);
--irq <= '1';
--wait for t_clock_c;
--wait until rising_edge(irq_ack);
--irq <= '0';
--wait;
irq <= (others => '0');
wait for 20 ms;
wait until rising_edge(clk_gen);
irq <= "00000111";
wait for t_clock_c;
wait;
end process interrupt_gen;
 
 
/neo430/trunk/neo430/sw/bootloader/boot_crt0.asm
19,7 → 19,7
; # You should have received a copy of the GNU Lesser General Public License along with this #
; # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
; # ********************************************************************************************* #
; # Stephan Nolting, Hannover, Germany 06.04.2019 #
; # Stephan Nolting, Hannover, Germany 27.11.2019 #
; #################################################################################################
 
.file "boot_crt0.asm"
30,15 → 30,15
; -----------------------------------------------------------
; Minimal required hardware setup
; -----------------------------------------------------------
mov &0xFFF8, r1 ; DMEM (RAM) base address
mov #(0xC000-2), r1 ; = DMEM (RAM) base address
add &0xFFFA, r1 ; add DMEM (RAM) size in bytes to SP
sub #2, r1 ; address of last entry of stack
;sub #2, r1 ; address of last entry of stack (done in first instruction)
 
; -----------------------------------------------------------
; This is where the actual application is started
; -----------------------------------------------------------
jmp main ; do a simple jump, as we will not return here
jmp main ; do a simple jump - we are not coming back
 
.Lfe0:
.size __boot_crt0,.Lfe0-__boot_crt0
/neo430/trunk/neo430/sw/bootloader/bootloader.c
29,7 → 29,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 15.11.2019 #
// # Stephan Nolting, Hannover, Germany 29.11.2019 #
// #################################################################################################
 
// Libraries
67,7 → 67,6
#define ERROR_EXECUTABLE 0x02 // invalid executable format
#define ERROR_SIZE 0x04 // executable is too big
#define ERROR_CHECKSUM 0x08 // checksum error
#define ERROR_EEPWR 0xFF // EEPROM write error
 
// Scratch registers - abuse unused IRQ vectors for this ;)
#define TIMEOUT_CNT IRQVEC_GPIO
105,6 → 104,9
// clear status register and disable interrupts, clear interrupt buffer, enable write access to IMEM
asm volatile ("mov %0, r2" : : "i" ((1<<R_FLAG) | (1<<Q_FLAG)));
 
// disable TRNG
TRNG_CT = 0;
 
// disable Wishbone interface
WB32_CT = 0;
 
114,6 → 116,9
// disable TWI
TWI_CT = 0;
 
// disable EXIRQ
EXIRQ_CT = 0;
 
// init timer interrupt vector
IRQVEC_TIMER = (uint16_t)(&timer_irq_handler); // timer match
 
147,7 → 152,9
// ****************************************************************
// Show bootloader intro and system information
// ****************************************************************
neo430_uart_br_print("\n\nNEO430 Bootloader V20191115\nBy Stephan Nolting\n\n"
neo430_uart_br_print("\n\n<< NEO430 Bootloader >>\n"
"\n"
"BLV: "__DATE__"\n"
"HWV: 0x");
neo430_uart_print_hex_word(HW_VERSION);
neo430_uart_br_print("\nUSR: 0x");
207,6 → 214,8
get_image(EEPROM_IMAGE_SPI);
else if (c == 's') // start program in RAM
start_app();
else if (c == 'c')
neo430_uart_br_print("By Stephan Nolting");
else // unknown command
neo430_uart_br_print("Bad CMD!");
}
496,14 → 505,14
c0 = (uint8_t)neo430_uart_getc();
c1 = (uint8_t)neo430_uart_getc();
}
else if (src == EEPROM_IMAGE_SPI) { // get image data from SPI EEPROM
else {// if (src == EEPROM_IMAGE_SPI) { // get image data from SPI EEPROM
c0 = spi_eeprom_read_byte(a+0);
c1 = spi_eeprom_read_byte(a+1);
}
else { // if (src == EEPROM_IMAGE_TWI) // get image data from TWI EEPROM
//c0 = twi_eeprom_read_byte(a+0);
//c1 = twi_eeprom_read_byte(a+1);
}
//else { // if (src == EEPROM_IMAGE_TWI) // get image data from TWI EEPROM
// //c0 = twi_eeprom_read_byte(a+0);
// //c1 = twi_eeprom_read_byte(a+1);
//}
 
//uint16_t r = (((uint16_t)c0) << 8) | (((uint16_t)c1) << 0);
uint16_t r = neo430_combine_bytes(c0, c1);
/neo430/trunk/neo430/sw/common/crt0.asm
19,7 → 19,7
; # You should have received a copy of the GNU Lesser General Public License along with this #
; # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
; # ********************************************************************************************* #
; # Stephan Nolting, Hannover, Germany 06.04.2019 #
; # Stephan Nolting, Hannover, Germany 27.11.2019 #
; #################################################################################################
 
.file "crt0.asm"
26,11 → 26,12
.section .text
.p2align 1,0
 
 
__crt0_begin:
; -----------------------------------------------------------
; Get required system info
; -----------------------------------------------------------
mov &0xFFF8, r8 ; = DMEM (RAM) base address
mov #0xC000, r8 ; = DMEM (RAM) base address
mov &0xFFFA, r1 ; = DMEM (RAM) size in byte
 
 
/neo430/trunk/neo430/sw/example/blink_led/main.c
44,13 → 44,7
// intro text
neo430_uart_br_print("\nBlinking LED demo program\n");
 
// check if GPIO unit was synthesized, exit if no GPIO is available
if (!(SYS_FEATURES & (1<<SYS_GPIO_EN))) {
neo430_uart_br_print("Error! No GPIO unit synthesized!");
return 1;
}
 
uint16_t i = 0; // init counter
uint16_t i = 0;
while (1) {
neo430_gpio_port_set(0x00FF & (i++)); // set output port and increment counter
neo430_cpu_delay_ms(200); // wait 200ms
/neo430/trunk/neo430/sw/example/crc_test/main.c
46,7 → 46,7
 
neo430_uart_br_print("\n<<< CRC16/CRC32 module test >>>\n");
 
// check if CRC unit was synthesized, exit if no WB is available
// check if CRC unit was synthesized, exit if not available
if (!(SYS_FEATURES & (1<<SYS_CRC_EN))) {
neo430_uart_br_print("Error! No CRC unit synthesized!");
return 1;
/neo430/trunk/neo430/sw/example/exirq_test/main.c
0,0 → 1,119
// #################################################################################################
// # < External Interrupts Controller test program > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 29.11.2019 #
// #################################################################################################
 
 
// Libraries
#include <neo430.h>
 
// Configuration
#define BAUD_RATE 19200
 
// Prototypes
void ext_irq_ch0_handler(void);
void ext_irq_ch1_handler(void);
void ext_irq_ch2_handler(void);
void ext_irq_ch3_handler(void);
 
 
/* ------------------------------------------------------------
* INFO Main function
* ------------------------------------------------------------ */
int main(void) {
 
// setup UART
neo430_uart_setup(BAUD_RATE);
 
// intro text
neo430_uart_br_print("\n<<< EXIRQ Test >>>\n");
 
// check if EXIRQ was synthesized, exit if not available
if (!(SYS_FEATURES & (1<<SYS_EXIRQ_EN))) {
neo430_uart_br_print("Error! No EXIRQ synthesized!");
return 1;
}
 
// clear output port
neo430_gpio_port_set(0);
 
 
// use this struct for configuring the EXIRQ controller
struct neo430_exirq_config_t exirq_config;
 
// initialise handler addresses
exirq_config.address[0] = (uint16_t)(&ext_irq_ch0_handler);
exirq_config.address[1] = (uint16_t)(&ext_irq_ch1_handler);
exirq_config.address[2] = (uint16_t)(&ext_irq_ch2_handler);
exirq_config.address[3] = (uint16_t)(&ext_irq_ch3_handler);
exirq_config.address[4] = 0; // set unused vectors to zero
exirq_config.address[5] = 0;
exirq_config.address[6] = 0;
exirq_config.address[7] = 0;
 
// enable used IRQ channels
exirq_config.enable = 0b00001111;
 
// use rising edge as trigger for all channels
exirq_config.trigger = 1;
 
// send configuration and activate EXIRQ controller
neo430_exirq_config(exirq_config);
neo430_exirq_enable();
 
// enable global interrupts and go to sleep
neo430_eint();
while(1) {
neo430_sleep();
}
 
return 0;
}
 
 
// handler functions for the external interrupt channels:
// - must not have parameters nor a return value
// - must not use the interrupt attribute, as they are normal functions, called by an actual interrupt handler
 
void ext_irq_ch0_handler(void) {
 
neo430_gpio_pin_toggle(0);
}
 
 
void ext_irq_ch1_handler(void) {
 
neo430_gpio_pin_toggle(1);
}
 
 
void ext_irq_ch2_handler(void) {
 
neo430_gpio_pin_toggle(2);
}
 
 
void ext_irq_ch3_handler(void) {
 
neo430_gpio_pin_toggle(3);
}
 
/neo430/trunk/neo430/sw/example/exirq_test/makefile
0,0 → 1,188
#################################################################################################
# < NEO430 Application Compile Script - Linux / Windows Powershell / Windows Linux Subsystem > #
# ********************************************************************************************* #
# This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
# Copyright by Stephan Nolting: stnolting@gmail.com #
# #
# This source file may be used and distributed without restriction provided that this copyright #
# statement is not removed from the file and that any derivative work contains the original #
# copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it and/or modify it under the terms #
# of the GNU Lesser General Public License as published by the Free Software Foundation, #
# either version 3 of the License, or (at your option) any later version. #
# #
# This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
# without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
# See the GNU Lesser General Public License for more details. #
# #
# You should have received a copy of the GNU Lesser General Public License along with this #
# source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
# ********************************************************************************************* #
# Stephan Nolting, Hannover, Germany 04.10.2019 #
#################################################################################################
 
 
#-------------------------------------------------------------------------------
# USER CONFIGURATION
#-------------------------------------------------------------------------------
# Compiler effort (-Os = optimize for size)
EFFORT = -Os
 
# User's application sources (add additional files here)
APP_SRC = main.c
 
# User's application include folders (don't forget the '-I' before each entry)
APP_INC = -I .
#-------------------------------------------------------------------------------
 
 
 
#-------------------------------------------------------------------------------
# NEO430 framework
#-------------------------------------------------------------------------------
# Path to NEO430 linker script and startup file
NEO430_COM_PATH=../../common
# Path to main NEO430 library include files
NEO430_INC_PATH=../../lib/neo430/include
# Path to main NEO430 library source files
NEO430_SRC_PATH=../../lib/neo430/source
# Path to NEO430 executable generator
NEO430_EXE_PATH=../../tools/image_gen
# Path to NEO430 core rtl folder
NEO430_RTL_PATH=../../../rtl/core
 
 
#-------------------------------------------------------------------------------
# Add NEO430 sources to input SRCs
#-------------------------------------------------------------------------------
APP_SRC += $(wildcard $(NEO430_SRC_PATH)/*.c)
 
 
#-------------------------------------------------------------------------------
# Make defaults
#-------------------------------------------------------------------------------
.SUFFIXES:
.PHONY: all
.DEFAULT_GOAL := help
 
 
#-------------------------------------------------------------------------------
# Application output definitions
#-------------------------------------------------------------------------------
APP_BIN = main.bin
APP_ASM = main.s
 
compile: $(APP_ASM) $(APP_BIN)
install: $(APP_ASM) neo430_application_image.vhd
all: $(APP_ASM) $(APP_BIN) neo430_application_image.vhd
 
# define all object files
OBJ = $(APP_SRC:.c=.o)
 
 
#-------------------------------------------------------------------------------
# Tools
#-------------------------------------------------------------------------------
#C ompiler tools
AS = msp430-elf-as
CC = msp430-elf-gcc
LD = msp430-elf-ld
STRIP = msp430-elf-strip
OBJDUMP = msp430-elf-objdump
OBJCOPY = msp430-elf-objcopy
SIZE = msp430-elf-size
IMAGE_GEN = $(NEO430_EXE_PATH)/image_gen
 
# Compiler flags
CC_OPTS = -mcpu=msp430 -pipe -Wall -Xassembler --mY -mhwmult=none -fno-delete-null-pointer-checks
CC_OPTS += -Wl,-static -mrelax -minrt -nostartfiles -fdata-sections -ffunction-sections -Xlinker --gc-sections
 
# Linker flags
LD_OPTS = -mcpu=msp430 -Wl,--gc-sections -mrelax -minrt -nostartfiles
 
 
#-------------------------------------------------------------------------------
# PC Host Compiler
#-------------------------------------------------------------------------------
CC_X86 = g++ -Wall -O -g
 
 
#-------------------------------------------------------------------------------
# Tool Targets
#-------------------------------------------------------------------------------
# install/compile tools
$(IMAGE_GEN): $(NEO430_EXE_PATH)/main.cpp
@echo Compiling $(IMAGE_GEN)
@$(CC_X86) $< -o $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# Application Targets
#-------------------------------------------------------------------------------
# Assemble startup code
crt0.elf: $(NEO430_COM_PATH)/crt0.asm
@$(AS) -mY -mcpu=msp430 $< -o $@
 
# Compile app sources
$(OBJ): %.o : %.c crt0.elf
@$(CC) -c $(CC_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) $< -o $@
 
# Link object files
main.elf: $(OBJ)
@$(CC) $(LD_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) -T $(NEO430_COM_PATH)/neo430_linker_script.x $(OBJ) -o $@ -lm
@echo Memory utilization:
@$(SIZE) main.elf
 
# Generate final executable (from .image section only)
image.dat: main.elf
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.dat
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
@$(OBJDUMP) -D -S -z $< > $@
@if grep -qR "dadd" $@; then echo "NEO430: WARNING! 'DADD' instruction might be used! Make sure it is synthesized!"; fi
 
# Generate NEO430 executable image for bootloader update
$(APP_BIN): image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_bin $< $@
 
# Generate NEO430 executable VHDL boot image
neo430_application_image.vhd: image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_img $< $@
@echo Installing application image to $(NEO430_RTL_PATH)/neo430_application_image.vhd
@cp neo430_application_image.vhd $(NEO430_RTL_PATH)/.
@rm -f neo430_application_image.vhd
 
 
#-------------------------------------------------------------------------------
# Help
#-------------------------------------------------------------------------------
help:
@echo "NEO430 Application Compilation Script"
@echo "Make sure to add the absolute path of the msp430-gcc bin folder to your PATH variable."
@echo "Targets:"
@echo " help - show this text"
@echo " compile - compile and generate *.bin executable for upload via bootloader"
@echo " install - compile, generate and install VHDL boot image"
@echo " all - compile and generate *.bin executable for upload via bootloader and generate and install VHDL boot image"
@echo " clean - clean up project"
@echo " clean_all - clean up project, core libraries and helper tools"
 
 
#-------------------------------------------------------------------------------
# Clean up
#-------------------------------------------------------------------------------
clean:
@rm -f *.elf *.o *.dat *.vhd *.s *.bin
 
clean_all:
@rm -f $(OBJ) *.elf *.dat *.bin *.vhd *.s $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# eof
/neo430/trunk/neo430/sw/example/gpio_pwm_demo/main.c
0,0 → 1,98
// #################################################################################################
// # < Use the PWM controller to modulate the GPIO output port > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: http://opencores.org/project,neo430 #
// # Copyright 2015-2016, Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from http://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 22.11.2019 #
// #################################################################################################
 
 
// Libraries
#include <stdint.h>
#include <neo430.h>
 
// Configuration
#define BAUD_RATE 19200
#define PWM_MAX 63
 
 
/* ------------------------------------------------------------
* INFO Main function
* ------------------------------------------------------------ */
int main(void) {
 
// setup UART
neo430_uart_setup(BAUD_RATE);
 
neo430_uart_br_print("\n<<< PWM GPIO modulation demo >>>\n");
 
// check if PWM unit was synthesized, exit if not
if (!(SYS_FEATURES & (1<<SYS_PWM_EN))) {
neo430_uart_br_print("Error! No PWM controller synthesized!");
return 1;
}
 
// check if GPIO unit was synthesized, exit if not
if (!(SYS_FEATURES & (1<<SYS_GPIO_EN))) {
neo430_uart_br_print("Error! No GPIO controller synthesized!");
return 1;
}
 
// enable pwm controller
neo430_pwm_enable(PWM_PRSC_4, 1, 1); // 2nd highest frequency, 8-bit resolution, use GPIO modulation
 
// clear GPIO output port
neo430_gpio_port_set(0);
 
// clear pwm channel 3 (GPIO PWM channel)
neo430_pwm_set(0, 0);
 
uint8_t pwm = 0;
uint8_t up = 1;
uint16_t cnt = 0;
 
// animate!
while(1) {
// update duty cycle
if (up) {
if (pwm == (256/2)) // half max
up = 0;
else
pwm++;
}
else {
if (pwm == 0)
up = 1;
else
pwm--;
}
 
// output new duty cycle
neo430_pwm_set(3, pwm);
 
// output simple counter on GPIO output port
neo430_gpio_port_set((cnt>>4) & 0x00FF);
cnt++;
 
neo430_cpu_delay_ms(8);
}
 
return 0;
}
/neo430/trunk/neo430/sw/example/gpio_pwm_demo/makefile
0,0 → 1,188
#################################################################################################
# < NEO430 Application Compile Script - Linux / Windows Powershell / Windows Linux Subsystem > #
# ********************************************************************************************* #
# This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
# Copyright by Stephan Nolting: stnolting@gmail.com #
# #
# This source file may be used and distributed without restriction provided that this copyright #
# statement is not removed from the file and that any derivative work contains the original #
# copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it and/or modify it under the terms #
# of the GNU Lesser General Public License as published by the Free Software Foundation, #
# either version 3 of the License, or (at your option) any later version. #
# #
# This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
# without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
# See the GNU Lesser General Public License for more details. #
# #
# You should have received a copy of the GNU Lesser General Public License along with this #
# source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
# ********************************************************************************************* #
# Stephan Nolting, Hannover, Germany 04.10.2019 #
#################################################################################################
 
 
#-------------------------------------------------------------------------------
# USER CONFIGURATION
#-------------------------------------------------------------------------------
# Compiler effort (-Os = optimize for size)
EFFORT = -Os
 
# User's application sources (add additional files here)
APP_SRC = main.c
 
# User's application include folders (don't forget the '-I' before each entry)
APP_INC = -I .
#-------------------------------------------------------------------------------
 
 
 
#-------------------------------------------------------------------------------
# NEO430 framework
#-------------------------------------------------------------------------------
# Path to NEO430 linker script and startup file
NEO430_COM_PATH=../../common
# Path to main NEO430 library include files
NEO430_INC_PATH=../../lib/neo430/include
# Path to main NEO430 library source files
NEO430_SRC_PATH=../../lib/neo430/source
# Path to NEO430 executable generator
NEO430_EXE_PATH=../../tools/image_gen
# Path to NEO430 core rtl folder
NEO430_RTL_PATH=../../../rtl/core
 
 
#-------------------------------------------------------------------------------
# Add NEO430 sources to input SRCs
#-------------------------------------------------------------------------------
APP_SRC += $(wildcard $(NEO430_SRC_PATH)/*.c)
 
 
#-------------------------------------------------------------------------------
# Make defaults
#-------------------------------------------------------------------------------
.SUFFIXES:
.PHONY: all
.DEFAULT_GOAL := help
 
 
#-------------------------------------------------------------------------------
# Application output definitions
#-------------------------------------------------------------------------------
APP_BIN = main.bin
APP_ASM = main.s
 
compile: $(APP_ASM) $(APP_BIN)
install: $(APP_ASM) neo430_application_image.vhd
all: $(APP_ASM) $(APP_BIN) neo430_application_image.vhd
 
# define all object files
OBJ = $(APP_SRC:.c=.o)
 
 
#-------------------------------------------------------------------------------
# Tools
#-------------------------------------------------------------------------------
#C ompiler tools
AS = msp430-elf-as
CC = msp430-elf-gcc
LD = msp430-elf-ld
STRIP = msp430-elf-strip
OBJDUMP = msp430-elf-objdump
OBJCOPY = msp430-elf-objcopy
SIZE = msp430-elf-size
IMAGE_GEN = $(NEO430_EXE_PATH)/image_gen
 
# Compiler flags
CC_OPTS = -mcpu=msp430 -pipe -Wall -Xassembler --mY -mhwmult=none -fno-delete-null-pointer-checks
CC_OPTS += -Wl,-static -mrelax -minrt -nostartfiles -fdata-sections -ffunction-sections -Xlinker --gc-sections
 
# Linker flags
LD_OPTS = -mcpu=msp430 -Wl,--gc-sections -mrelax -minrt -nostartfiles
 
 
#-------------------------------------------------------------------------------
# PC Host Compiler
#-------------------------------------------------------------------------------
CC_X86 = g++ -Wall -O -g
 
 
#-------------------------------------------------------------------------------
# Tool Targets
#-------------------------------------------------------------------------------
# install/compile tools
$(IMAGE_GEN): $(NEO430_EXE_PATH)/main.cpp
@echo Compiling $(IMAGE_GEN)
@$(CC_X86) $< -o $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# Application Targets
#-------------------------------------------------------------------------------
# Assemble startup code
crt0.elf: $(NEO430_COM_PATH)/crt0.asm
@$(AS) -mY -mcpu=msp430 $< -o $@
 
# Compile app sources
$(OBJ): %.o : %.c crt0.elf
@$(CC) -c $(CC_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) $< -o $@
 
# Link object files
main.elf: $(OBJ)
@$(CC) $(LD_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) -T $(NEO430_COM_PATH)/neo430_linker_script.x $(OBJ) -o $@ -lm
@echo Memory utilization:
@$(SIZE) main.elf
 
# Generate final executable (from .image section only)
image.dat: main.elf
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.dat
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
@$(OBJDUMP) -D -S -z $< > $@
@if grep -qR "dadd" $@; then echo "NEO430: WARNING! 'DADD' instruction might be used! Make sure it is synthesized!"; fi
 
# Generate NEO430 executable image for bootloader update
$(APP_BIN): image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_bin $< $@
 
# Generate NEO430 executable VHDL boot image
neo430_application_image.vhd: image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_img $< $@
@echo Installing application image to $(NEO430_RTL_PATH)/neo430_application_image.vhd
@cp neo430_application_image.vhd $(NEO430_RTL_PATH)/.
@rm -f neo430_application_image.vhd
 
 
#-------------------------------------------------------------------------------
# Help
#-------------------------------------------------------------------------------
help:
@echo "NEO430 Application Compilation Script"
@echo "Make sure to add the absolute path of the msp430-gcc bin folder to your PATH variable."
@echo "Targets:"
@echo " help - show this text"
@echo " compile - compile and generate *.bin executable for upload via bootloader"
@echo " install - compile, generate and install VHDL boot image"
@echo " all - compile and generate *.bin executable for upload via bootloader and generate and install VHDL boot image"
@echo " clean - clean up project"
@echo " clean_all - clean up project, core libraries and helper tools"
 
 
#-------------------------------------------------------------------------------
# Clean up
#-------------------------------------------------------------------------------
clean:
@rm -f *.elf *.o *.dat *.vhd *.s *.bin
 
clean_all:
@rm -f $(OBJ) *.elf *.dat *.bin *.vhd *.s $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# eof
/neo430/trunk/neo430/sw/example/hw_analysis/main.c
21,7 → 21,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 14.11.2019 #
// # Stephan Nolting, Hannover, Germany 28.11.2019 #
// #################################################################################################
 
 
61,10 → 61,10
neo430_printf("Clock speed: %n Hz\n", clock);
 
// ROM/IMEM
neo430_printf("IMEM/ROM: %u bytes @ 0x0000\n", IMEM_SIZE);
neo430_printf("IMEM/ROM: %u bytes @ 0x%x\n", IMEM_SIZE, IMEM_ADDR_BASE);
 
// RAM/DMEM
neo430_printf("DMEM/RAM: %u bytes @ 0x%x\n", DMEM_SIZE, DMEM_BASE);
neo430_printf("DMEM/RAM: %u bytes @ 0x%x\n", DMEM_SIZE, DMEM_ADDR_BASE);
 
// UART baud rate
uint16_t baud = UART_CT & 0x00FF;
145,7 → 145,15
neo430_printf("- Two Wire Interface: ");
print_state(ft & (1<<SYS_TWI_EN));
 
// TRNG
neo430_printf("- True Random Generator: ");
print_state(ft & (1<<SYS_TRNG_EN));
 
// EXIRQ
neo430_printf("- External IRQs Ctrl.: ");
print_state(ft & (1<<SYS_EXIRQ_EN));
 
 
// Exit
// --------------------------------------------
neo430_printf("\n\nPress any key to return to bootloader.\n");
166,7 → 174,7
void print_state(uint16_t d) {
 
if (d)
neo430_printf("enabled\n");
neo430_printf("synthesized\n");
else
neo430_printf("DISABLED\n");
neo430_printf("-\n");
}
/neo430/trunk/neo430/sw/example/pwm_demo/main.c
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from http://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 20.04.2019 #
// # Stephan Nolting, Hannover, Germany 22.11.2019 #
// #################################################################################################
 
 
49,7 → 49,7
}
 
// enable pwm controller
neo430_pwm_enable(PWM_PRSC_2, 8); // max frequency, 8-bit resolution
neo430_pwm_enable(PWM_PRSC_2, 1, 0); // max frequency, 8-bit resolution, no GPIO modulation
 
// clear all channels
neo430_pwm_set(0, 0);
/neo430/trunk/neo430/sw/example/trng_test/main.c
0,0 → 1,122
// #################################################################################################
// # < TRNG test program > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 27.11.2019 #
// #################################################################################################
 
 
// Libraries
#include <stdint.h>
#include <neo430.h>
 
// Configuration
#define BAUD_RATE 19200
#define NUM_SAMPLES 2000000000
 
// Global variables
uint32_t rnd_hist[256];
 
 
/* ------------------------------------------------------------
* INFO Main function
* ------------------------------------------------------------ */
int main(void) {
 
// setup UART
neo430_uart_setup(BAUD_RATE);
 
// intro text
neo430_printf("\n<<< TRNG Test >>>\n");
 
// check if TRNG was synthesized, exit if not available
if (!(SYS_FEATURES & (1<<SYS_TRNG_EN))) {
neo430_printf("Error! No TRNG synthesized!");
return 1;
}
 
// start TRNG
neo430_trng_enable();
 
while(1) {
 
// main menu
neo430_printf("\nCommands:\n"
" a: Print random numbers (abort by pressing any key)\n"
" b: Generate random data histogram (%n samples)\n"
" x: Return to bootloader\n", (uint32_t)NUM_SAMPLES);
 
neo430_printf("CMD:> ");
char cmd = neo430_uart_getc();
neo430_uart_putc(cmd); // echo
neo430_printf("\n");
 
// output RND data
if (cmd == 'a') {
uint32_t num_samples = 0;
while(1) {
neo430_printf("%u ", (uint16_t)neo430_trng_get());
num_samples++;
if (neo430_uart_char_received()) { // abort when key pressed
neo430_printf("\nNumber of samples: %n\n", num_samples);
break;
}
}
}
 
// compute histogram
else if (cmd == 'b') {
// clear histogram memory
uint16_t i;
for (i=0; i<256; i++) {
rnd_hist[i] = 0;
}
 
// generate histogram
neo430_printf("Sampling data (%n samples). This may take some time...\n", (uint32_t)NUM_SAMPLES);
uint32_t j;
for (j=0; j<NUM_SAMPLES; j++) {
uint8_t rnd_data = neo430_trng_get();
rnd_hist[rnd_data]++;
}
 
// output results
neo430_printf("rnd_hist:\n");
for(i=0; i<256; i++) {
neo430_printf("%u =%n\n", i, rnd_hist[i]);
}
}
 
// exit
else if (cmd == 'x') {
if (!(SYS_FEATURES & (1<<SYS_BTLD_EN)))
neo430_printf("No bootloader installed!\n");
else
asm volatile ("mov #0xF000, r0");
}
 
else {
neo430_printf("Invalid option.\n");
}
}
 
return 0;
}
 
/neo430/trunk/neo430/sw/example/trng_test/makefile
0,0 → 1,188
#################################################################################################
# < NEO430 Application Compile Script - Linux / Windows Powershell / Windows Linux Subsystem > #
# ********************************************************************************************* #
# This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
# Copyright by Stephan Nolting: stnolting@gmail.com #
# #
# This source file may be used and distributed without restriction provided that this copyright #
# statement is not removed from the file and that any derivative work contains the original #
# copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it and/or modify it under the terms #
# of the GNU Lesser General Public License as published by the Free Software Foundation, #
# either version 3 of the License, or (at your option) any later version. #
# #
# This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
# without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
# See the GNU Lesser General Public License for more details. #
# #
# You should have received a copy of the GNU Lesser General Public License along with this #
# source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
# ********************************************************************************************* #
# Stephan Nolting, Hannover, Germany 04.10.2019 #
#################################################################################################
 
 
#-------------------------------------------------------------------------------
# USER CONFIGURATION
#-------------------------------------------------------------------------------
# Compiler effort (-Os = optimize for size)
EFFORT = -Os
 
# User's application sources (add additional files here)
APP_SRC = main.c
 
# User's application include folders (don't forget the '-I' before each entry)
APP_INC = -I .
#-------------------------------------------------------------------------------
 
 
 
#-------------------------------------------------------------------------------
# NEO430 framework
#-------------------------------------------------------------------------------
# Path to NEO430 linker script and startup file
NEO430_COM_PATH=../../common
# Path to main NEO430 library include files
NEO430_INC_PATH=../../lib/neo430/include
# Path to main NEO430 library source files
NEO430_SRC_PATH=../../lib/neo430/source
# Path to NEO430 executable generator
NEO430_EXE_PATH=../../tools/image_gen
# Path to NEO430 core rtl folder
NEO430_RTL_PATH=../../../rtl/core
 
 
#-------------------------------------------------------------------------------
# Add NEO430 sources to input SRCs
#-------------------------------------------------------------------------------
APP_SRC += $(wildcard $(NEO430_SRC_PATH)/*.c)
 
 
#-------------------------------------------------------------------------------
# Make defaults
#-------------------------------------------------------------------------------
.SUFFIXES:
.PHONY: all
.DEFAULT_GOAL := help
 
 
#-------------------------------------------------------------------------------
# Application output definitions
#-------------------------------------------------------------------------------
APP_BIN = main.bin
APP_ASM = main.s
 
compile: $(APP_ASM) $(APP_BIN)
install: $(APP_ASM) neo430_application_image.vhd
all: $(APP_ASM) $(APP_BIN) neo430_application_image.vhd
 
# define all object files
OBJ = $(APP_SRC:.c=.o)
 
 
#-------------------------------------------------------------------------------
# Tools
#-------------------------------------------------------------------------------
#C ompiler tools
AS = msp430-elf-as
CC = msp430-elf-gcc
LD = msp430-elf-ld
STRIP = msp430-elf-strip
OBJDUMP = msp430-elf-objdump
OBJCOPY = msp430-elf-objcopy
SIZE = msp430-elf-size
IMAGE_GEN = $(NEO430_EXE_PATH)/image_gen
 
# Compiler flags
CC_OPTS = -mcpu=msp430 -pipe -Wall -Xassembler --mY -mhwmult=none -fno-delete-null-pointer-checks
CC_OPTS += -Wl,-static -mrelax -minrt -nostartfiles -fdata-sections -ffunction-sections -Xlinker --gc-sections
 
# Linker flags
LD_OPTS = -mcpu=msp430 -Wl,--gc-sections -mrelax -minrt -nostartfiles
 
 
#-------------------------------------------------------------------------------
# PC Host Compiler
#-------------------------------------------------------------------------------
CC_X86 = g++ -Wall -O -g
 
 
#-------------------------------------------------------------------------------
# Tool Targets
#-------------------------------------------------------------------------------
# install/compile tools
$(IMAGE_GEN): $(NEO430_EXE_PATH)/main.cpp
@echo Compiling $(IMAGE_GEN)
@$(CC_X86) $< -o $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# Application Targets
#-------------------------------------------------------------------------------
# Assemble startup code
crt0.elf: $(NEO430_COM_PATH)/crt0.asm
@$(AS) -mY -mcpu=msp430 $< -o $@
 
# Compile app sources
$(OBJ): %.o : %.c crt0.elf
@$(CC) -c $(CC_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) $< -o $@
 
# Link object files
main.elf: $(OBJ)
@$(CC) $(LD_OPTS) $(EFFORT) -I $(NEO430_INC_PATH) $(APP_INC) -T $(NEO430_COM_PATH)/neo430_linker_script.x $(OBJ) -o $@ -lm
@echo Memory utilization:
@$(SIZE) main.elf
 
# Generate final executable (from .image section only)
image.dat: main.elf
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.dat
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.dat
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.dat
@cat text.dat rodata.dat data.dat > $@
@rm -f text.dat rodata.dat data.dat
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
@$(OBJDUMP) -D -S -z $< > $@
@if grep -qR "dadd" $@; then echo "NEO430: WARNING! 'DADD' instruction might be used! Make sure it is synthesized!"; fi
 
# Generate NEO430 executable image for bootloader update
$(APP_BIN): image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_bin $< $@
 
# Generate NEO430 executable VHDL boot image
neo430_application_image.vhd: image.dat $(IMAGE_GEN)
@$(IMAGE_GEN) -app_img $< $@
@echo Installing application image to $(NEO430_RTL_PATH)/neo430_application_image.vhd
@cp neo430_application_image.vhd $(NEO430_RTL_PATH)/.
@rm -f neo430_application_image.vhd
 
 
#-------------------------------------------------------------------------------
# Help
#-------------------------------------------------------------------------------
help:
@echo "NEO430 Application Compilation Script"
@echo "Make sure to add the absolute path of the msp430-gcc bin folder to your PATH variable."
@echo "Targets:"
@echo " help - show this text"
@echo " compile - compile and generate *.bin executable for upload via bootloader"
@echo " install - compile, generate and install VHDL boot image"
@echo " all - compile and generate *.bin executable for upload via bootloader and generate and install VHDL boot image"
@echo " clean - clean up project"
@echo " clean_all - clean up project, core libraries and helper tools"
 
 
#-------------------------------------------------------------------------------
# Clean up
#-------------------------------------------------------------------------------
clean:
@rm -f *.elf *.o *.dat *.vhd *.s *.bin
 
clean_all:
@rm -f $(OBJ) *.elf *.dat *.bin *.vhd *.s $(IMAGE_GEN)
 
#-------------------------------------------------------------------------------
# eof
/neo430/trunk/neo430/sw/example/wdt_test/main.c
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 17.11.2018 #
// # Stephan Nolting, Hannover, Germany 27.11.2019 #
// #################################################################################################
 
 
49,28 → 49,40
}
 
neo430_uart_br_print("Cause of last processor reset: ");
if ((WDT_CT & (1<<WDT_CT_RCAUSE)) == 0)
uint16_t wdt_cause = WDT_CT;
if ((wdt_cause & (1<<WDT_CT_RCAUSE)) == 0) { // reset caused by WDT at all?
neo430_uart_br_print("EXTERNAL RESET");
else
neo430_uart_br_print("WATCHDOG");
}
else {
if ((wdt_cause & (1<<WDT_CT_RPWFAIL)) == 0) { // WDT reset caused by wrong password access?
neo430_uart_br_print("WATCHDOG Timeout");
}
else {
neo430_uart_br_print("WATCHDOG Access Error");
}
}
 
 
neo430_uart_br_print("\n\nWill reset WDT 64 times.\n"
"A system reset will be executed in the following time out.\n"
"Press any key to trigger manual WDT hardware reset.\n"
"[----------------------------------------------------------------]\n ");
"Press any key to trigger manual WDT hardware reset by WDT access with wrong password.\n"
"Restart this program after reset to check for the reset cause.\n\n"
"WDT resets: [................................................................]");
neo430_uart_bs(65); // back-space terminal cursor by 65 positions
 
// init watchdog: third largest period
neo430_wdt_enable(WDT_PRSC_1024);
// activate watchdog: second largest period
neo430_wdt_enable(WDT_PRSC_2048);
 
 
uint8_t i;
for (i=0; i<64; i++) {
neo430_uart_putc('.');
neo430_uart_putc('#');
neo430_wdt_reset(); // reset watchdog
neo430_cpu_delay(4); // wait some time
neo430_cpu_delay_ms(80); // wait some time
 
// trigger manual reset if key pressed
if (neo430_uart_char_received()) {
neo430_wdt_force_hw_reset();
neo430_wdt_force_hw_reset(); // access wdt with wrong password
}
}
 
/neo430/trunk/neo430/sw/lib/neo430/include/neo430.h
23,7 → 23,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 19.11.2019 #
// # Stephan Nolting, Hannover, Germany 28.11.2019 #
// #################################################################################################
 
#ifndef neo430_h
41,6 → 41,7
#define N_FLAG 2 // r/w: negative
#define I_FLAG 3 // r/w: global interrupt enable
#define S_FLAG 4 // r/w: sleep
#define P_FLAG 5 // r/w: parity (if enabled for synthesis)
#define V_FLAG 8 // r/w: overflow
#define Q_FLAG 14 // -/w: clear pending IRQ buffer when set
#define R_FLAG 15 // r/w: allow write-access to IMEM
60,9 → 61,11
 
 
// ----------------------------------------------------------------------------
// Start of data memory (DMEN)
// Start of memory sections
// ----------------------------------------------------------------------------
#define DMEM_ADDR_BASE 0xC000
#define IMEM_ADDR_BASE 0x0000 // r/(w)/x: instruction memory
#define DMEM_ADDR_BASE 0xC000 // r/w/x: data memory
#define BTLD_ADDR_BASE 0xF000 // r/-/x: bootloader memory
 
 
// ----------------------------------------------------------------------------
231,6 → 234,7
#define WDT_CT_PRSC2 2 // r/w: clock prescaler select bit 2
#define WDT_CT_EN 3 // r/w: WDT enable
#define WDT_CT_RCAUSE 4 // r/-: reset cause (0: external, 1: watchdog timeout)
#define WDT_CT_RPWFAIL 5 // r/-: watchdog resed caused by wrong WDT access password
 
// Watchdog clock prescaler select:
#define WDT_PRSC_2 0 // CLK/2
275,18 → 279,17
// ----------------------------------------------------------------------------
// Pulse Width Modulation Controller (PWM)
// ----------------------------------------------------------------------------
#define PWM_CT (*(REG16 0xFFE0)) // -/w: control register
#define PWM_CT (*(REG16 0xFFE0)) // r/w: control register
#define PWM_CH10 (*(REG16 0xFFE2)) // r/w: duty cycle channel 1 and 0
#define PWM_CH32 (*(REG16 0xFFE4)) // r/w: duty cycle channel 3 and 2
#define PWM_CH32 (*(REG16 0xFFE4)) // -/w: duty cycle channel 3 and 2
 
// PWM controller control register
#define PWM_CT_EN 0 // -/w: PWM enable
#define PWM_CT_PRSC0 1 // -/w: clock prescaler select bit 0
#define PWM_CT_PRSC1 2 // -/w: clock prescaler select bit 1
#define PWM_CT_PRSC2 3 // -/w: clock prescaler select bit 2
#define PWM_CT_SIZE0 4 // -/w: PWM counter size bit 0
#define PWM_CT_SIZE1 5 // -/w: PWM counter size bit 1
#define PWM_CT_SIZE2 6 // -/w: PWM counter size bit 2
#define PWM_CT_EN 0 // -/w: PWM enable
#define PWM_CT_PRSC0 1 // -/w: clock prescaler select bit 0
#define PWM_CT_PRSC1 2 // -/w: clock prescaler select bit 1
#define PWM_CT_PRSC2 3 // -/w: clock prescaler select bit 2
#define PWM_CT_GPIO_PWM 4 // -/w: use channel 3 for PWM modulation of GPIO unit's output port
#define PWM_CT_SIZE_SEL 5 // -/w: cnt size select (0 = 4-bit, 1 = 8-bit)
 
// PWM clock prescaler select:
#define PWM_PRSC_2 0 // CLK/2
326,20 → 329,49
#define TWI_PRSC_4096 7 // CLK/4096
 
// TWI data register flags
#define TWI_DT_ACK 15 // r/-: ACK received
#define TWI_DT_ACK 15 // r/-: ACK received
 
/*
 
// ----------------------------------------------------------------------------
// Reserved
// True Random Number Generator (TRNG)
// ----------------------------------------------------------------------------
#define ???_CT (*(REG16 0xFFEC)) // -/w: control register
#define ???_DATA (*(ROM16 0xFFEE)) // r/-: data register
#define TRNG_CT (*(REG16 0xFFEC)) // r/w: control register
 
// ??? control register
#define ???_CT_EN 0 // -/w: ??? enable
*/
// TRNG control register
#define TRNG_CT_RND0 0 // r/-: TRNG random data byte bit 0
#define TRNG_CT_RND1 1 // r/-: TRNG random data byte bit 1
#define TRNG_CT_RND2 2 // r/-: TRNG random data byte bit 2
#define TRNG_CT_RND3 3 // r/-: TRNG random data byte bit 3
#define TRNG_CT_RND4 4 // r/-: TRNG random data byte bit 4
#define TRNG_CT_RND5 5 // r/-: TRNG random data byte bit 5
#define TRNG_CT_RND6 6 // r/-: TRNG random data byte bit 6
#define TRNG_CT_RND7 7 // r/-: TRNG random data byte bit 7
#define TRNG_CT_EN 15 // r/w: TRNG enable
 
 
// ----------------------------------------------------------------------------
// External Interrupts Controller (EXIRQ)
// ----------------------------------------------------------------------------
#define EXIRQ_CT (*(REG16 0xFFEE)) // r/w: control register
 
// EXIRQ control register
#define EXIRQ_CT_SRC0 0 // r/-: IRQ source bit 0
#define EXIRQ_CT_SRC1 1 // r/-: IRQ source bit 1
#define EXIRQ_CT_SRC2 2 // r/-: IRQ source bit 2
#define EXIRQ_CT_TRIG 3 // r/w: global trigger (0: high-level, 1: rising-edge)
#define EXIRQ_CT_EN 4 // r/w: unit enable
 
#define EXIRQ_CT_IRQ0_EN 8 // r/w: Enable IRQ channel 0
#define EXIRQ_CT_IRQ1_EN 9 // r/w: Enable IRQ channel 1
#define EXIRQ_CT_IRQ2_EN 10 // r/w: Enable IRQ channel 2
#define EXIRQ_CT_IRQ3_EN 11 // r/w: Enable IRQ channel 3
#define EXIRQ_CT_IRQ4_EN 12 // r/w: Enable IRQ channel 4
#define EXIRQ_CT_IRQ5_EN 13 // r/w: Enable IRQ channel 5
#define EXIRQ_CT_IRQ6_EN 14 // r/w: Enable IRQ channel 6
#define EXIRQ_CT_IRQ7_EN 15 // r/w: Enable IRQ channel 7
 
 
// ----------------------------------------------------------------------------
// System Configuration (SYSCONFIG)
// ----------------------------------------------------------------------------
#define CPUID0 (*(ROM16 0xFFF0)) // r/-: HW version number
346,7 → 378,7
#define CPUID1 (*(ROM16 0xFFF2)) // r/-: synthesized system features
#define CPUID2 (*(ROM16 0xFFF4)) // r/-: custom user code
#define CPUID3 (*(ROM16 0xFFF6)) // r/-: IMEM/ROM size in bytes
#define CPUID4 (*(ROM16 0xFFF8)) // r/-: DMEM/RAM base address
#define CPUID4 (*(ROM16 0xFFF8)) // r/-: reserved
#define CPUID5 (*(ROM16 0xFFFA)) // r/-: DMEM/RAM size in bytes
#define CPUID6 (*(ROM16 0xFFFC)) // r/-: clock speed (in Hz) low part
#define CPUID7 (*(ROM16 0xFFFE)) // r/-: clock speed (in Hz) high part
356,7 → 388,7
#define SYS_FEATURES CPUID1 // r/-: synthesized system features
#define USER_CODE CPUID2 // r/-: custom user code
#define IMEM_SIZE CPUID3 // r/-: IMEM/ROM size in bytes
#define DMEM_BASE CPUID4 // r/-: DMEM/RAM base address
//#define CPUID4 // r/-: reserved
#define DMEM_SIZE CPUID5 // r/-: DMEM/RAM size in bytes
#define CLOCKSPEED_LO CPUID6 // r/-: clock speed (in Hz) low part
#define CLOCKSPEED_HI CPUID7 // r/-: clock speed (in Hz) high part
379,8 → 411,8
#define SYS_PWM_EN 11 // r/-: PWM controller synthesized
#define SYS_TWI_EN 12 // r/-: TWI synthesized
#define SYS_SPI_EN 13 // r/-: SPI synthesized
//define reserved_EN 14 // r/-: reserved
//define reserved_EN 15 // r/-: reserved
#define SYS_TRNG_EN 14 // r/-: TRNG synthesized
#define SYS_EXIRQ_EN 15 // r/-: EXIRQ synthesized
 
 
// ----------------------------------------------------------------------------
388,11 → 420,13
// ----------------------------------------------------------------------------
#include "neo430_cpu.h"
#include "neo430_crc.h"
#include "neo430_exirq.h"
#include "neo430_gpio.h"
#include "neo430_muldiv.h"
#include "neo430_pwm.h"
#include "neo430_spi.h"
#include "neo430_timer.h"
#include "neo430_trng.h"
#include "neo430_twi.h"
#include "neo430_uart.h"
#include "neo430_wdt.h"
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_cpu.h
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 01.03.2019 #
// # Stephan Nolting, Hannover, Germany 21.11.2019 #
// #################################################################################################
 
#ifndef neo430_cpu_h
31,6 → 31,7
uint16_t neo430_get_sp(void);
uint16_t neo430_get_sreg(void);
void neo430_set_sreg(uint16_t d);
uint16_t neo430_get_parity(uint16_t d);
void neo430_sleep(void);
void neo430_clear_irq_buffer(void);
void neo430_cpu_delay(uint16_t t);
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_exirq.h
0,0 → 1,44
// #################################################################################################
// # < neo430_exirqt.h - External interrupts controler driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 29.11.2019 #
// #################################################################################################
 
#ifndef neo430_exirq_h
#define neo430_exirq_h
 
// data types
struct neo430_exirq_config_t {
uint16_t address[8];
uint8_t trigger;
uint8_t enable;
};
 
// private variables
static uint16_t neo430_exirq_vectors[8] __attribute__((unused)); // do not ouput a warning when this variable is unused
 
// prototypes
void neo430_exirq_enable(void); // activate EXIRQ controller
void neo430_exirq_disable(void); // deactivate EXIRQ controller
void neo430_exirq_config(struct neo430_exirq_config_t config); // configure EXIRQ controller
void __attribute__((__interrupt__)) exirq_irq_handler(void); // EXIRQ IRQ handler
 
#endif // neo430_exirq_h
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_gpio.h
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 04.07.2018 #
// # Stephan Nolting, Hannover, Germany 04.07.2018 #
// #################################################################################################
 
#ifndef neo430_gpio_h
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_pwm.h
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 12.05.2019 #
// # Stephan Nolting, Hannover, Germany 22.11.2019 #
// #################################################################################################
 
#ifndef neo430_pwm_h
26,7 → 26,7
#define neo430_pwm_h
 
// prototypes
void neo430_pwm_enable(uint8_t prsc, uint8_t size);
void neo430_pwm_enable(const uint16_t prsc, const uint16_t size, const uint16_t gpio_pwm);
void neo430_pwm_disable(void);
void neo430_pwm_set(uint8_t channel, uint8_t dc);
 
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_spi.h
1,5 → 1,5
// #################################################################################################
// # < neo430_usart.h - Internal SPI module driver functions > #
// # < neo430_spi.h - Internal SPI module driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_trng.h
0,0 → 1,33
// #################################################################################################
// # < neo430_trng.h - True random number generator helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 21.11.2019 #
// #################################################################################################
 
#ifndef neo430_trng_h
#define neo430_trng_h
 
// prototypes
void neo430_trng_enable(void);
void neo430_trng_disable(void);
uint8_t neo430_trng_get(void);
 
#endif // neo430_trng_h
/neo430/trunk/neo430/sw/lib/neo430/include/neo430_uart.h
1,5 → 1,5
// #################################################################################################
// # < neo430_usart.h - Internal UARt driver functions > #
// # < neo430_uart.h - Internal UART driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 18.01.2019 #
// # Stephan Nolting, Hannover, Germany 27.11.2019 #
// #################################################################################################
 
#ifndef neo430_uart_h
48,5 → 48,6
void neo430_printf(char *format, ...); // print format string
void neo430_fp_print(int32_t num, const uint16_t fp); // print fixed point number
uint32_t neo430_hexstr_to_uint(char *buffer, uint8_t length); // convert hex string to number
void neo430_uart_bs(uint16_t n); // return terminal cursor n positions
 
#endif // neo430_uart_h
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_cpu.c
1,5 → 1,5
// #################################################################################################
// # < neo430_cpu.h - CPU helper functions > #
// # < neo430_cpu.c - CPU helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 13.03.2019 #
// # Stephan Nolting, Hannover, Germany 26.11.2019 #
// #################################################################################################
 
#include "neo430.h"
84,6 → 84,24
 
 
/* ------------------------------------------------------------
* INFO Get parity of value
* WARNING MAKE SURE THIS OPTION IS SYNTHESIZED (package switch "use_ext_alu_c")!!!
* PARAM d input value
* RETURN Resulting parity (1=even number of 1s, 0=odd number of 1s)
* ------------------------------------------------------------ */
uint16_t neo430_get_parity(uint16_t d){
 
register uint16_t r = d;
asm volatile ("mov %0, %0" : "=r" (r) : "r" (r)); // just get value through alu
 
if (neo430_get_sreg() & (1<<P_FLAG)) // get parity flag from SR
return 1;
else
return 0;
}
 
 
/* ------------------------------------------------------------
* INFO Set CPU to sleep mode
* ------------------------------------------------------------ */
void neo430_sleep(void){
191,7 → 209,7
 
/* ------------------------------------------------------------
* INFO Binary-coded decimal addition
* WARNING MAKE SURE THE DADD UNIT IS SYNTHESIZED!!!
* WARNING MAKE SURE THE DADD UNIT IS SYNTHESIZED (package switch "use_dadd_cmd_c")!!!
* PARAM 2x 16-bit BCD operands (4 digits)
* RETURN 16-bit BCD result (4 digits)
* ------------------------------------------------------------ */
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_crc.c
1,5 → 1,5
// #################################################################################################
// # < neo430_crc.h - CRC module helper functions > #
// # < neo430_crc.c - CRC module helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_exirq.c
0,0 → 1,85
// #################################################################################################
// # < neo430_exirqt.c - External interrupts controler driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 28.11.2019 #
// #################################################################################################
 
#include "neo430.h"
#include "neo430_exirq.h"
 
 
/* ------------------------------------------------------------
* INFO Enable external interrupts controller
* ------------------------------------------------------------ */
void neo430_exirq_enable(void) {
 
EXIRQ_CT |= (1<<EXIRQ_CT_EN);
}
 
 
/* ------------------------------------------------------------
* INFO Disable external interrupts controller
* ------------------------------------------------------------ */
void neo430_exirq_disable(void) {
 
EXIRQ_CT &= ~(1<<EXIRQ_CT_EN);
}
 
 
/* ------------------------------------------------------------
* INFO Configure external interrupts controller
* PARAM Struct containing the handler functions addresses and the channel enable bits
* ------------------------------------------------------------ */
void neo430_exirq_config(struct neo430_exirq_config_t config) {
 
// reset controller
EXIRQ_CT = 0;
 
// get handler function address
neo430_exirq_vectors[0] = config.address[0];
neo430_exirq_vectors[1] = config.address[1];
neo430_exirq_vectors[2] = config.address[2];
neo430_exirq_vectors[3] = config.address[3];
neo430_exirq_vectors[4] = config.address[4];
neo430_exirq_vectors[5] = config.address[5];
neo430_exirq_vectors[6] = config.address[6];
neo430_exirq_vectors[7] = config.address[7];
 
// set correct CPU external IRQ interrupt handler address
IRQVEC_EXT = (uint16_t)(&exirq_irq_handler);
 
// configure channel enables and global trigger
uint16_t trig = (uint16_t)config.trigger;
uint16_t ena = (uint16_t)config.enable;
 
EXIRQ_CT = (ena<<EXIRQ_CT_IRQ0_EN) | (trig<<EXIRQ_CT_TRIG) ;
}
 
 
/* ------------------------------------------------------------
* INFO Actual external interrupts controller IRQ handler
* ------------------------------------------------------------ */
void __attribute__((__interrupt__)) exirq_irq_handler(void) {
 
uint16_t src = EXIRQ_CT & ((8-1)<<EXIRQ_CT_SRC0);
neo430_call_address(neo430_exirq_vectors[src]);
}
 
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_gpio.c
1,5 → 1,5
// #################################################################################################
// # < neo430_gpio.h - PIO controller helper functions > #
// # < neo430_gpio.c - PIO controller helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 13.03.2019 #
// # Stephan Nolting, Hannover, Germany 13.03.2019 #
// #################################################################################################
 
#include "neo430.h"
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_muldiv.c
1,5 → 1,5
// #################################################################################################
// # < neo430_muldiv.h - Multiplier/Divider function > #
// # < neo430_muldiv.c - Multiplier/Divider function > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_pwm.c
1,5 → 1,5
// #################################################################################################
// # < neo430_pwm.h - PWM controller helper functions > #
// # < neo430_pwm.c - PWM controller helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 12.05.2019 #
// # Stephan Nolting, Hannover, Germany 22.11.2019 #
// #################################################################################################
 
#include "neo430.h"
29,12 → 29,13
/* ------------------------------------------------------------
* INFO Reset and activate PWM controller
* PARAM prsc: Clock prescaler for PWM clock
* PARAM size: Actual bit width of PWM counter (1..8)
* PARAM size: 1=use 8-bit counter, 0=use 4-bit counter
* PARAM gpio_pwm: Use channel 3 for GPIO.output modulation when '1'
* ------------------------------------------------------------ */
void neo430_pwm_enable(uint8_t prsc, uint8_t size) {
void neo430_pwm_enable(const uint16_t prsc, const uint16_t size, const uint16_t gpio_pwm) {
 
PWM_CT = 0; // reset
PWM_CT = (1<<PWM_CT_EN) | (((uint16_t)prsc)<<PWM_CT_PRSC0) | (((uint16_t)size-1)<<PWM_CT_SIZE0);
PWM_CT = (1<<PWM_CT_EN) | (prsc<<PWM_CT_PRSC0) | (size<<PWM_CT_SIZE_SEL) | (gpio_pwm<<PWM_CT_GPIO_PWM);
}
 
 
54,27 → 55,27
* ------------------------------------------------------------ */
void neo430_pwm_set(uint8_t channel, uint8_t dc) {
 
uint16_t data = 0;
uint16_t duty_cycle = 0;
 
// get current state
if (channel & 2) // channel 2 or 3
data = PWM_CH32;
duty_cycle = PWM_CH32;
else // channel 1 or 0
data = PWM_CH10;
duty_cycle = PWM_CH10;
 
// modify high or low part (even or odd channel)
if (channel & 1) { // channel 1 or 3
data &= 0x00ff;
data |= ((uint16_t)dc) << 8;
duty_cycle &= 0x00ff;
duty_cycle |= ((uint16_t)dc) << 8;
}
else { // channel 0 or 2
data &= 0xff00;
data |= ((uint16_t)dc) << 0;
duty_cycle &= 0xff00;
duty_cycle |= ((uint16_t)dc) << 0;
}
 
// write back
if (channel & 2) // channel 2 or 3
PWM_CH32 = data;
PWM_CH32 = duty_cycle;
else // channel 1 or 0
PWM_CH10 = data;
PWM_CH10 = duty_cycle;
}
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_spi.c
1,5 → 1,5
// #################################################################################################
// # < neo430_usart.h - Internal SPI module driver functions > #
// # < neo430_spi.c - Internal SPI module driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_timer.c
1,5 → 1,5
// #################################################################################################
// # < neo430_timer.h - Timer helper functions > #
// # < neo430_timer.c - Timer helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_trng.c
0,0 → 1,60
// #################################################################################################
// # < neo430_trng.c - True random number generator helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
// # #
// # This source file may be used and distributed without restriction provided that this copyright #
// # statement is not removed from the file and that any derivative work contains the original #
// # copyright notice and the associated disclaimer. #
// # #
// # This source file is free software; you can redistribute it and/or modify it under the terms #
// # of the GNU Lesser General Public License as published by the Free Software Foundation, #
// # either version 3 of the License, or (at your option) any later version. #
// # #
// # This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; #
// # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. #
// # See the GNU Lesser General Public License for more details. #
// # #
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 27.11.2019 #
// #################################################################################################
 
#include "neo430.h"
#include "neo430_trng.h"
 
 
/* ------------------------------------------------------------
* INFO Enable TRNG
* ------------------------------------------------------------ */
void neo430_trng_enable(void) {
 
TRNG_CT = 0; // reset
TRNG_CT = (1<<TRNG_CT_EN);
 
// wait for unit to get oscillating
asm volatile ("nop");
asm volatile ("nop");
}
 
 
/* ------------------------------------------------------------
* INFO Disable TRNG
* ------------------------------------------------------------ */
void neo430_trng_disable(void) {
 
TRNG_CT = 0;
}
 
 
/* ------------------------------------------------------------
* INFO Get TRNG data
* RETURN TRNG random data byte
* ------------------------------------------------------------ */
uint8_t neo430_trng_get(void) {
 
asm volatile ("nop"); // make sure TRNG has enough time to sample a new number
return (uint8_t)(TRNG_CT & 0xFF);
}
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_uart.c
1,5 → 1,5
// #################################################################################################
// # < neo430_usart.h - Internal UARt driver functions > #
// # < neo430_usart.c - Internal UARt driver functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 20.04.2019 #
// # Stephan Nolting, Hannover, Germany 21.11.2019 #
// #################################################################################################
 
#include "neo430.h"
336,6 → 336,9
case 'c': // char
neo430_uart_putc((char)va_arg(a, int));
break;
case 'b': // unsigned 16-bit binary
neo430_uart_print_bin_word(va_arg(a, unsigned int));
break;
case 'i': // 16-bit integer
n = (int32_t)va_arg(a, int);
if (n < 0) {
432,3 → 435,16
 
return res;
}
 
 
/* ------------------------------------------------------------
* INFO Return terminal cursor n positions
* PARAM n positions
* ------------------------------------------------------------ */
void neo430_uart_bs(uint16_t n) {
 
while (n--) {
neo430_uart_putc(0x08);
}
}
 
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_wdt.c
1,5 → 1,5
// #################################################################################################
// # < neo430_wdt.h - Watchdog helper functions > #
// # < neo430_wdt.c - Watchdog helper functions > #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
/neo430/trunk/neo430/sw/lib/neo430/source/neo430_wishbone.c
1,5 → 1,5
// #################################################################################################
// # < neo430_wishbone.h - Internal Wishbone interface control functions > #
// # < neo430_wishbone.c - Internal Wishbone interface control functions > #
// # ********************************************************************************************* #
// # Use the normal Wishbone functions for BLOCKING access (until ACK is asserted). #
// # Use non-blocking functions (*_start, wishbone_busy, wishbone_get_data*) to prevent dead locks #

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