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URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

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  • This comparison shows the changes necessary to convert path
    /neo430
    from Rev 178 to Rev 179
    Reverse comparison

Rev 178 → Rev 179

/trunk/neo430/doc/NEO430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/neo430/rtl/core/neo430_package.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 29.01.2020 #
-- # Stephan Nolting, Hannover, Germany 30.01.2020 #
-- #################################################################################################
 
library ieee;
30,7 → 30,7
 
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0330"; -- no touchy!
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0331"; -- no touchy!
 
-- Advanced Hardware Configuration --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
/trunk/neo430/rtl/core/neo430_twi.vhd
2,7 → 2,7
-- # << NEO430 - Two Wire Serial Interface Master (I2C) >> #
-- # ********************************************************************************************* #
-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
-- # No multi-master support and no slave mode support yet! #
-- # Supports ACKs by the master. No multi-master support and no slave mode support yet! #
-- # Interrupt: TWI_transfer_done #
-- # ********************************************************************************************* #
-- # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
23,7 → 23,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 09.11.2019 #
-- # Stephan Nolting, Hannover, Germany 30.01.2020 #
-- #################################################################################################
 
library ieee;
60,17 → 60,18
constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit
 
-- control reg bits --
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI unit is busy
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI unit is busy
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
constant ctrl_twi_mack_c : natural := 8; -- r/w: generate ACK by master for transmission
 
-- data register flags --
constant data_twi_ack_c : natural := 15; -- r/-: Set if ACK received
constant data_twi_ack_c : natural := 15; -- r/-: Set if ACK received
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
87,7 → 88,7
signal twi_clk_halt : std_ulogic;
 
-- twi transceiver core --
signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register
signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register
signal arbiter : std_ulogic_vector(2 downto 0);
signal twi_bitcnt : std_ulogic_vector(3 downto 0);
signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
115,7 → 116,7
if rising_edge(clk_i) then
if (wr_en = '1') then
if (addr = twi_ctrl_addr_c) then
ctrl <= data_i(7 downto 0);
ctrl <= data_i(ctrl'left downto 0);
end if;
end if;
end if;
177,7 → 178,9
arbiter(1 downto 0) <= "10";
end if;
elsif (addr = twi_rtx_addr_c) then -- start a data transmission
twi_rtx_sreg <= data_i(7 downto 0) & '1'; -- one bit extra for stop condition
-- one bit extra for ack, issued by master if ctrl_twi_mack_c is set,
-- sampled from slave if ctrl_twi_mack_c is cleared
twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
arbiter(1 downto 0) <= "11";
end if;
end if;
266,6 → 269,7
data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
else -- twi_rtx_addr_c =>
data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
data_o(data_twi_ack_c) <= not twi_rtx_sreg(0);
/trunk/neo430/sw/lib/neo430/include/neo430.h
23,7 → 23,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 10.01.2020 #
// # Stephan Nolting, Hannover, Germany 30.01.2020 #
// #################################################################################################
 
#ifndef neo430_h
321,6 → 321,7
#define TWI_CT_PRSC1 5 // r/w: clock prescaler select bit 1
#define TWI_CT_PRSC2 6 // r/w: clock prescaler select bit 2
#define TWI_CT_IRQ_EN 7 // r/w: transmission done interrupt enable
#define TWI_CT_MACK 8 // r/w: send ack by master after transmission
 
// TWI clock prescaler select:
#define TWI_PRSC_2 0 // CLK/2
/trunk/neo430/sw/lib/neo430/include/neo430_twi.h
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 10.10.2019 #
// # Stephan Nolting, Hannover, Germany 30.01.2020 #
// #################################################################################################
 
#ifndef neo430_twi_h
28,6 → 28,8
// prototypes
void neo430_twi_enable(uint8_t prsc); // configure and activate TWI module
void neo430_twi_disable(void); // deactivate TWI module
void neo430_twi_mack_enable(void); // activate ACK sending by master after transmission
void neo430_twi_mack_disable(void); // deactivate ACK sending by master after transmission (normal mode)
uint8_t neo430_twi_start_trans(uint8_t a); // start transmission (START) and send address and r/w bit
uint8_t neo430_twi_trans(uint8_t d); // send byte to active slave
uint8_t neo430_twi_get_data(void); // get last received data byte
/trunk/neo430/sw/lib/neo430/source/neo430_twi.c
19,7 → 19,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 10.10.2019 #
// # Stephan Nolting, Hannover, Germany 30.01.2020 #
// #################################################################################################
 
#include "neo430.h"
47,9 → 47,28
 
 
/* ------------------------------------------------------------
* INFO Activate sending ACK by master after transmission
* ------------------------------------------------------------ */
void neo430_twi_mack_enable(void) {
 
TWI_CT |= (1 << TWI_CT_MACK);
}
 
 
/* ------------------------------------------------------------
* INFO Deactivate sending ACK by master after transmission (normal mode)
* ACK is sampled from slave
* ------------------------------------------------------------ */
void neo430_twi_mack_disable(void) {
 
TWI_CT &= ~(1 << TWI_CT_MACK);
}
 
 
/* ------------------------------------------------------------
* INFO Generate START condition and send first byte (address & R/W)
* PARAM 8-bit including 7-bit address and read/write bit
* RETURN 0 if ACK received, 0xff if no valid ACK was received
* RETURN 0 if ACK received, 1 if no valid ACK was received
* ------------------------------------------------------------ */
uint8_t neo430_twi_start_trans(uint8_t a) {
 
60,9 → 79,9
 
// check for ACK/NACK
if (TWI_DATA & (1 << TWI_DT_ACK))
return 0x00; // ACK received
return 0; // ACK received
else
return 0xff; // NACK received
return 1; // NACK received
}
 
 
69,7 → 88,7
/* ------------------------------------------------------------
* INFO Send data and also sample input data
* PARAM Data byte to be sent
* RETURN 0 if ACK received, 0xff if no valid ACK was received
* RETURN 0 if ACK received, 1 if no valid ACK was received
* ------------------------------------------------------------ */
uint8_t neo430_twi_trans(uint8_t d) {
 
78,9 → 97,9
 
// check for ACK/NACK
if (TWI_DATA & (1 << TWI_DT_ACK))
return 0x00; // ACK received
return 0; // ACK received
else
return 0xff; // NACK received
return 1; // NACK received
}
 
 

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