OpenCores
URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neo430
    from Rev 181 to Rev 182
    ↔ Reverse comparison
  •

Rev 181 → Rev 182

/trunk/neo430/README.md
76,7 → 76,7
- Optional 4 channel PWM controller with 4 or 8 bit resolution ([PWM](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_pwm.vhd))
- Optional Galois Ring Oscillator (GARO) based true random number generator ([TRNG](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_trng.vhd)) with de-biasing and internal post-processing
- Optional external interrupts controller with 8 independent channels ([EXIRQ](https://github.com/stnolting/neo430/blob/master/rtl/core/neo430_exirq.vhd)), can also be used for software-triggered interrupts (traps, breakpoints, etc.)
- Optional internal [bootloader](https://github.com/stnolting/neo430/blob/master/sw/bootloader/bootloader.c) (2kB ROM) with serial user console and automatic boot from external SPI EEPROM
- Optional internal [bootloader](https://github.com/stnolting/neo430/blob/master/sw/bootloader/bootloader.c) (2kB ROM) with serial user console and automatic boot from external SPI flash (like the FPGA configuration storage)
 
 
 
/trunk/neo430/doc/NEO430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/neo430/rtl/core/neo430_bootloader_image.vhd
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000822 => x"413a",
000823 => x"4130",
000824 => x"533d",
000825 => x"c312",
000826 => x"100c",
000827 => x"930d",
000828 => x"23fb",
000829 => x"4130",
000830 => x"6f42",
000831 => x"746f",
000832 => x"6e69",
000833 => x"2e67",
000834 => x"2e2e",
000835 => x"0a0a",
000836 => x"4300",
000837 => x"444d",
000838 => x"3a73",
000839 => x"200a",
000840 => x"3a64",
000841 => x"4420",
000842 => x"6d75",
000843 => x"2070",
000844 => x"454d",
000845 => x"0a4d",
000846 => x"6520",
000847 => x"203a",
000848 => x"6f4c",
000849 => x"6461",
000850 => x"4520",
000851 => x"5045",
000852 => x"4f52",
000853 => x"0a4d",
000854 => x"6820",
000855 => x"203a",
000856 => x"6548",
000857 => x"706c",
000858 => x"200a",
000859 => x"3a70",
000860 => x"5320",
000861 => x"6f74",
000862 => x"6572",
000863 => x"4520",
000864 => x"5045",
000865 => x"4f52",
000866 => x"0a4d",
000867 => x"7220",
000868 => x"203a",
000869 => x"6552",
000870 => x"7473",
000871 => x"7261",
000872 => x"0a74",
000873 => x"7320",
000874 => x"203a",
000875 => x"7453",
000876 => x"7261",
000877 => x"2074",
000878 => x"7061",
000879 => x"0a70",
000880 => x"7520",
000881 => x"203a",
000882 => x"7055",
000883 => x"6f6c",
000884 => x"6461",
000885 => x"0a00",
000886 => x"3a00",
000887 => x"2020",
000888 => x"0700",
000889 => x"450a",
000890 => x"5252",
000891 => x"005f",
000892 => x"7250",
000893 => x"636f",
000894 => x"6565",
000895 => x"2064",
000896 => x"7928",
000897 => x"6e2f",
000898 => x"3f29",
000899 => x"0a00",
000900 => x"7257",
000901 => x"7469",
000902 => x"6e69",
000903 => x"2e67",
000904 => x"2e2e",
000905 => x"0020",
000906 => x"4b4f",
000907 => x"4100",
000908 => x"6177",
000909 => x"7469",
000910 => x"6e69",
000911 => x"2067",
000912 => x"4942",
000913 => x"454e",
000914 => x"4558",
000915 => x"2e2e",
000916 => x"202e",
000917 => x"4c00",
000918 => x"616f",
000919 => x"6964",
000920 => x"676e",
000921 => x"2e2e",
000922 => x"202e",
000923 => x"0a00",
000924 => x"3c0a",
000925 => x"203c",
000926 => x"454e",
000927 => x"344f",
000928 => x"3033",
000929 => x"4220",
000930 => x"6f6f",
000931 => x"6c74",
000932 => x"616f",
000933 => x"6564",
000934 => x"2072",
000935 => x"3e3e",
000936 => x"0a0a",
000937 => x"4c42",
000938 => x"3a56",
000939 => x"4620",
000940 => x"6265",
000941 => x"2020",
000942 => x"2034",
000943 => x"3032",
000944 => x"3032",
000945 => x"480a",
000946 => x"5657",
000947 => x"203a",
000948 => x"7830",
000949 => x"0a00",
000950 => x"5355",
000951 => x"3a52",
000952 => x"3020",
000953 => x"0078",
000954 => x"430a",
000955 => x"4b4c",
000956 => x"203a",
000957 => x"7830",
000958 => x"0a00",
000959 => x"4f52",
000960 => x"3a4d",
000961 => x"3020",
000962 => x"0078",
000963 => x"520a",
000964 => x"4d41",
000965 => x"203a",
000966 => x"7830",
000967 => x"0a00",
000968 => x"5953",
000969 => x"3a53",
000970 => x"3020",
000971 => x"0078",
000972 => x"0a0a",
000973 => x"7541",
000974 => x"6f74",
000975 => x"6f62",
000976 => x"746f",
000977 => x"6920",
000978 => x"206e",
000979 => x"7338",
000980 => x"202e",
000981 => x"7250",
000982 => x"7365",
000983 => x"2073",
000984 => x"656b",
000985 => x"2079",
000986 => x"6f74",
000987 => x"6120",
000988 => x"6f62",
000989 => x"7472",
000990 => x"0a2e",
000991 => x"0a00",
000992 => x"4d43",
000993 => x"3a44",
000994 => x"203e",
000995 => x"4200",
000996 => x"2079",
000997 => x"7453",
000998 => x"7065",
000999 => x"6168",
001000 => x"206e",
001001 => x"6f4e",
001002 => x"746c",
001003 => x"6e69",
001004 => x"0a67",
001005 => x"614d",
001006 => x"6564",
001007 => x"6920",
001008 => x"206e",
001009 => x"6148",
001010 => x"6e6e",
001011 => x"766f",
001012 => x"7265",
001013 => x"202c",
001014 => x"6547",
001015 => x"6d72",
001016 => x"6e61",
001017 => x"0079",
001018 => x"6142",
001019 => x"2064",
001020 => x"4d43",
001021 => x"2144",
001022 => x"0000",
000729 => x"403e",
000730 => x"ffa0",
000731 => x"4e2d",
000732 => x"930d",
000733 => x"3bfd",
000734 => x"4c82",
000735 => x"ffa2",
000736 => x"4130",
000737 => x"403d",
000738 => x"ffa2",
000739 => x"4d2c",
000740 => x"930c",
000741 => x"37fd",
000742 => x"4130",
000743 => x"421c",
000744 => x"ffa2",
000745 => x"4130",
000746 => x"120a",
000747 => x"1209",
000748 => x"1208",
000749 => x"1207",
000750 => x"4c09",
000751 => x"4038",
000752 => x"f5ae",
000753 => x"4077",
000754 => x"000d",
000755 => x"496a",
000756 => x"930a",
000757 => x"2002",
000758 => x"4030",
000759 => x"f6d0",
000760 => x"903a",
000761 => x"000a",
000762 => x"2002",
000763 => x"474c",
000764 => x"1288",
000765 => x"4a4c",
000766 => x"1288",
000767 => x"5319",
000768 => x"4030",
000769 => x"f5e6",
000770 => x"f07c",
000771 => x"000f",
000772 => x"407d",
000773 => x"0009",
000774 => x"9c4d",
000775 => x"2805",
000776 => x"503c",
000777 => x"0030",
000778 => x"12b0",
000779 => x"f5ae",
000780 => x"4130",
000781 => x"507c",
000782 => x"0057",
000783 => x"f03c",
000784 => x"00ff",
000785 => x"4030",
000786 => x"f614",
000787 => x"120a",
000788 => x"1209",
000789 => x"4c49",
000790 => x"490c",
000791 => x"426d",
000792 => x"12b0",
000793 => x"f6e0",
000794 => x"403a",
000795 => x"f604",
000796 => x"128a",
000797 => x"494c",
000798 => x"128a",
000799 => x"4030",
000800 => x"f6d4",
000801 => x"120a",
000802 => x"1209",
000803 => x"4c09",
000804 => x"427d",
000805 => x"12b0",
000806 => x"f6e0",
000807 => x"403a",
000808 => x"f626",
000809 => x"128a",
000810 => x"494c",
000811 => x"128a",
000812 => x"4030",
000813 => x"f6d4",
000814 => x"f03c",
000815 => x"00ff",
000816 => x"403d",
000817 => x"ffa4",
000818 => x"438d",
000819 => x"0000",
000820 => x"5c0c",
000821 => x"5c0c",
000822 => x"5c0c",
000823 => x"5c0c",
000824 => x"5c0c",
000825 => x"5c0c",
000826 => x"5c0c",
000827 => x"5c0c",
000828 => x"5c0c",
000829 => x"d03c",
000830 => x"0040",
000831 => x"4c8d",
000832 => x"0000",
000833 => x"4130",
000834 => x"f0b2",
000835 => x"ffc0",
000836 => x"ffa4",
000837 => x"4130",
000838 => x"403d",
000839 => x"ffa6",
000840 => x"4c8d",
000841 => x"0000",
000842 => x"403e",
000843 => x"ffa4",
000844 => x"4e2c",
000845 => x"930c",
000846 => x"3bfd",
000847 => x"4d2c",
000848 => x"4130",
000849 => x"4c82",
000850 => x"ffae",
000851 => x"4130",
000852 => x"ec82",
000853 => x"ffae",
000854 => x"4130",
000855 => x"d232",
000856 => x"4303",
000857 => x"4130",
000858 => x"108c",
000859 => x"4130",
000860 => x"4c4e",
000861 => x"4d4c",
000862 => x"108e",
000863 => x"de0c",
000864 => x"4130",
000865 => x"40b2",
000866 => x"4700",
000867 => x"ffb8",
000868 => x"4130",
000869 => x"4134",
000870 => x"4135",
000871 => x"4136",
000872 => x"4137",
000873 => x"4138",
000874 => x"4139",
000875 => x"413a",
000876 => x"4130",
000877 => x"533d",
000878 => x"c312",
000879 => x"100c",
000880 => x"930d",
000881 => x"23fb",
000882 => x"4130",
000883 => x"533e",
000884 => x"c312",
000885 => x"100d",
000886 => x"100c",
000887 => x"930e",
000888 => x"23fa",
000889 => x"4130",
000890 => x"4d43",
000891 => x"7344",
000892 => x"0a3a",
000893 => x"3a68",
000894 => x"4820",
000895 => x"6c65",
000896 => x"0a70",
000897 => x"3a72",
000898 => x"5220",
000899 => x"7365",
000900 => x"6174",
000901 => x"7472",
000902 => x"750a",
000903 => x"203a",
000904 => x"7055",
000905 => x"6f6c",
000906 => x"6461",
000907 => x"700a",
000908 => x"203a",
000909 => x"7250",
000910 => x"676f",
000911 => x"6172",
000912 => x"0a6d",
000913 => x"3a65",
000914 => x"4520",
000915 => x"6578",
000916 => x"7563",
000917 => x"6574",
000918 => x"0700",
000919 => x"450a",
000920 => x"5252",
000921 => x"005f",
000922 => x"6f42",
000923 => x"746f",
000924 => x"6e69",
000925 => x"2e67",
000926 => x"2e2e",
000927 => x"0a0a",
000928 => x"4100",
000929 => x"6177",
000930 => x"7469",
000931 => x"6e69",
000932 => x"2067",
000933 => x"4942",
000934 => x"454e",
000935 => x"4558",
000936 => x"2e2e",
000937 => x"002e",
000938 => x"6f4c",
000939 => x"6461",
000940 => x"6e69",
000941 => x"2e67",
000942 => x"2e2e",
000943 => x"4f00",
000944 => x"004b",
000945 => x"2e2e",
000946 => x"002e",
000947 => x"0a0a",
000948 => x"454e",
000949 => x"344f",
000950 => x"3033",
000951 => x"4220",
000952 => x"6f6f",
000953 => x"6c74",
000954 => x"616f",
000955 => x"6564",
000956 => x"0a72",
000957 => x"420a",
000958 => x"564c",
000959 => x"203a",
000960 => x"6546",
000961 => x"2062",
000962 => x"3131",
000963 => x"3220",
000964 => x"3230",
000965 => x"0a30",
000966 => x"5748",
000967 => x"3a56",
000968 => x"3020",
000969 => x"0078",
000970 => x"550a",
000971 => x"5253",
000972 => x"203a",
000973 => x"7830",
000974 => x"0a00",
000975 => x"4c43",
000976 => x"3a4b",
000977 => x"3020",
000978 => x"0078",
000979 => x"520a",
000980 => x"4d4f",
000981 => x"203a",
000982 => x"7830",
000983 => x"0a00",
000984 => x"4152",
000985 => x"3a4d",
000986 => x"3020",
000987 => x"0078",
000988 => x"530a",
000989 => x"5359",
000990 => x"203a",
000991 => x"7830",
000992 => x"0a00",
000993 => x"410a",
000994 => x"7475",
000995 => x"626f",
000996 => x"6f6f",
000997 => x"2074",
000998 => x"6e69",
000999 => x"3420",
001000 => x"2e73",
001001 => x"5020",
001002 => x"6572",
001003 => x"7373",
001004 => x"6b20",
001005 => x"7965",
001006 => x"7420",
001007 => x"206f",
001008 => x"6261",
001009 => x"726f",
001010 => x"2e74",
001011 => x"0a0a",
001012 => x"0a00",
001013 => x"0a00",
001014 => x"4d43",
001015 => x"3a44",
001016 => x"203e",
001017 => x"4200",
001018 => x"6461",
001019 => x"4320",
001020 => x"444d",
001021 => x"0000",
others => x"0000"
);
 
/trunk/neo430/rtl/core/neo430_cfu.vhd
26,7 → 26,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 22.11.2019 #
-- # Stephan Nolting, Hannover, Germany 06.02.2020 #
-- #################################################################################################
 
library ieee;
39,12 → 39,15
entity neo430_cfu is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0)
-- custom IOs --
-- ...
);
63,14 → 66,14
signal rden : std_ulogic; -- read enable
 
-- accessible regs (8x16-bit) --
signal user_reg0 : std_ulogic_vector(15 downto 0);
signal user_reg1 : std_ulogic_vector(15 downto 0);
signal user_reg2 : std_ulogic_vector(15 downto 0);
signal user_reg3 : std_ulogic_vector(15 downto 0);
signal user_reg4 : std_ulogic_vector(15 downto 0);
signal user_reg5 : std_ulogic_vector(15 downto 0);
signal user_reg6 : std_ulogic_vector(15 downto 0);
signal user_reg7 : std_ulogic_vector(15 downto 0);
signal cfu_ctrl_reg : std_ulogic_vector(15 downto 0);
signal user_reg1 : std_ulogic_vector(15 downto 0);
signal user_reg2 : std_ulogic_vector(15 downto 0);
signal user_reg3 : std_ulogic_vector(15 downto 0);
signal user_reg4 : std_ulogic_vector(15 downto 0);
signal user_reg5 : std_ulogic_vector(15 downto 0);
signal user_reg6 : std_ulogic_vector(15 downto 0);
signal user_reg7 : std_ulogic_vector(15 downto 0);
 
begin
 
84,23 → 87,57
rden <= acc_en and rden_i;
 
 
-- Clock System -------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- The top unit implements a clock generator providing 8 "derived clocks"
-- Actually, these signals must not be used as direct clock signals, but as clock enable signals.
-- If wou want to drive a system at MAIN_CLK/8 use the following construct:
 
-- if rising_edge(clk_i) then -- Always use the main clock for all clock processes!
-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
-- ...
-- end if;
-- end if;
 
-- The following clock divider rates are available:
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
 
-- this signal enabled the generator driving the clkgen_i
-- set this signal to '0' when you do not need the clkgen_i signal or when your CFU is disabled
-- to reduce dynamic power consumption
clkgen_en_o <= '0';
 
 
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- Here we are writing to the interface registers of the module. This unit can only be accessed
-- in full 16-bit word mode!
-- Please note, that all register of every unit are cleared during the processor boot sequence.
-- Make cfu_reg0_addr_c the CFU's control register. This register is cleared first during booting.
-- If the control register is cleared no actions should be taken when writing to other CFU registers.
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- write access to user registers --
if (wren = '1') then -- valid write access
if (addr = cfu_reg0_addr_c) then user_reg0 <= data_i; end if;
if (addr = cfu_reg1_addr_c) then user_reg1 <= data_i; end if;
if (addr = cfu_reg2_addr_c) then user_reg2 <= data_i; end if;
if (addr = cfu_reg3_addr_c) then user_reg3 <= data_i; end if;
if (addr = cfu_reg4_addr_c) then user_reg4 <= data_i; end if;
if (addr = cfu_reg5_addr_c) then user_reg5 <= data_i; end if;
if (addr = cfu_reg6_addr_c) then user_reg6 <= data_i; end if;
if (addr = cfu_reg7_addr_c) then user_reg7 <= data_i; end if;
case addr is
when cfu_reg0_addr_c => cfu_ctrl_reg <= data_i;
when cfu_reg1_addr_c => user_reg1 <= data_i;
when cfu_reg2_addr_c => user_reg2 <= data_i;
when cfu_reg3_addr_c => user_reg3 <= data_i;
when cfu_reg4_addr_c => user_reg4 <= data_i;
when cfu_reg5_addr_c => user_reg5 <= data_i;
when cfu_reg6_addr_c => user_reg6 <= data_i;
when cfu_reg7_addr_c => user_reg7 <= data_i;
when others => NULL;
end case;
end if;
end if;
end process wr_access;
123,7 → 160,7
data_o <= (others => '0'); -- this is crucial for the final OR-ing of all IO device's outputs
if (rden = '1') then -- valid read access
case addr is
when cfu_reg0_addr_c => data_o <= user_reg0;
when cfu_reg0_addr_c => data_o <= cfu_ctrl_reg;
when cfu_reg1_addr_c => data_o <= user_reg1;
when cfu_reg2_addr_c => data_o <= user_reg2;
when cfu_reg3_addr_c => data_o <= user_reg3;
/trunk/neo430/rtl/core/neo430_package.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 30.01.2020 #
-- # Stephan Nolting, Hannover, Germany 08.02.2020 #
-- #################################################################################################
 
library ieee;
30,7 → 30,7
 
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0331"; -- no touchy!
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0340"; -- no touchy!
 
-- Advanced Hardware Configuration --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
680,12 → 680,15
component neo430_cfu
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0)
-- custom IOs --
-- ...
);
/trunk/neo430/rtl/core/neo430_top.vhd
46,7 → 46,7
-- # You should have received a copy of the GNU Lesser General Public License along with this #
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
-- # ********************************************************************************************* #
-- # Stephan Nolting, Hannover, Germany 10.01.2020 #
-- # Stephan Nolting, Hannover, Germany 06.02.2020 #
-- #################################################################################################
 
library ieee;
135,6 → 135,7
signal wdt_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
signal twi_cg_en : std_ulogic;
signal cfu_cg_en : std_ulogic;
 
type cpu_bus_t is record
rd_en : std_ulogic;
221,7 → 222,7
if (sys_rst = '0') then
clk_div <= (others => '0');
elsif rising_edge(clk_i) then
if ((timer_cg_en or uart_cg_en or spi_cg_en or wdt_cg_en or pwm_cg_en or twi_cg_en) = '1') then -- anybody needing clocks?
if ((timer_cg_en or uart_cg_en or spi_cg_en or wdt_cg_en or pwm_cg_en or twi_cg_en or cfu_cg_en) = '1') then -- anybody needing clocks?
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
end if;
end if;
587,12 → 588,15
neo430_cfu_inst: neo430_cfu
port map(
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => cfu_rdata -- data out
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => cfu_rdata, -- data out
-- clock generator --
clkgen_en_o => cfu_cg_en, -- enable clock generator
clkgen_i => clk_gen
-- add custom IOs below --
);
end generate;
599,6 → 603,7
 
neo430_cfu_inst_false:
if (CFU_USE = false) generate
cfu_cg_en <= '0';
cfu_rdata <= (others => '0');
end generate;
 
/trunk/neo430/sw/bootloader/bootloader.c
1,15 → 1,15
// #################################################################################################
// # < NEO430 Bootloader > #
// # ********************************************************************************************* #
// # Boot from IMEM, UART or SPI EEPROM at SPI.CS[0] #
// # Boot from IMEM, UART or SPI Flash at SPI.CS[0] #
// # #
// # UART configuration: 8N1 at 19200 baud #
// # Boot EEPROM: SPI, 16-bit addresses (e.g., 25LC512) @ SPI.CS[0] #
// # Boot Flash: 8-bit SPI, 24-bit addresses (e.g., Micron N25Q032A) @ SPI.CS[0] #
// # GPIO.out[0] is used as high-active status LED #
// # #
// # Auto boot sequence after timeout: #
// # -> Try booting from SPI EEPROM at SPI.CS[0] #
// # -> permanently light up status led and freeze if SPI EEPROM booting attempt fails #
// # -> Try booting from SPI flash at SPI.CS[0] #
// # -> permanently light up status led and freeze if SPI flash booting attempt fails #
// # ********************************************************************************************* #
// # This file is part of the NEO430 Processor project: https://github.com/stnolting/neo430 #
// # Copyright by Stephan Nolting: stnolting@gmail.com #
29,7 → 29,7
// # You should have received a copy of the GNU Lesser General Public License along with this #
// # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html #
// # ********************************************************************************************* #
// # Stephan Nolting, Hannover, Germany 04.02.2020 #
// # Stephan Nolting, Hannover, Germany 10.02.2020 #
// #################################################################################################
 
// Libraries
38,24 → 38,28
 
// Configuration
#define BAUD_RATE 19200 // default UART baud rate
#define AUTOBOOT_TIMEOUT 8 // countdown (seconds) to auto boot
#define AUTOBOOT_TIMEOUT 4 // countdown (seconds) to auto boot
#define STATUS_LED 0 // GPIO.out(0) is status LED
 
// 25LC512 SPI EEPROM
#define BOOT_EEP_CS 0 // boot EEPROM CS (SPI.CS0)
#define EEP_IMAGE_BASE 0x00 // base address of NEO430 boot image
#define EEP_WRITE 0x02 // initialize start of write sequence
#define EEP_READ 0x03 // initialize start of read sequence
#define EEP_RDSR 0x05 // read status register
#define EEP_WREN 0x06 // write enable
// SPI flash boot base address
#define SPI_FLASH_BOOT_ADR 0x00040000L
 
// 24LC512 TWI EEPROM
#define TWI_BOOT_EEP_ADDR_READ 0b10100001 // READ address of TWI boot eeprom
// SPI flash hardware configuration
#define SPI_FLASH_CS 0
 
// SPI flash commands
#define SPI_FLASH_CMD_READ 0x03
#define SPI_FLASH_CMD_READ_STATUS 0x05
#define SPI_FLASH_CMD_WRITE_ENABLE 0x06
#define SPI_FLASH_CMD_PAGE_PROGRAM 0x02
#define SPI_FLASH_CMD_SECTOR_ERASE 0xD8
#define SPI_FLASH_CMD_READ_ID 0x9E
#define SPI_FLASH_CMD_POWER_DOWN 0xB9
#define SPI_FLASH_CMD_RELEASE 0xAB
 
// Image sources
#define UART_IMAGE 0x00
#define EEPROM_IMAGE_SPI 0x01
#define EEPROM_IMAGE_TWI 0x02
 
// Error codes
#define ERROR_EEPROM 0x00 // EEPROM access error
70,24 → 74,28
// Macros
#define xstr(a) str(a)
#define str(a) #a
#define BOOT_EEP_EN {SPI_CT |= 1 << (BOOT_EEP_CS+SPI_CT_CS_SEL0);}
#define SPI_FLASH_SEL {SPI_CT |= 1 << (SPI_FLASH_CS+SPI_CT_CS_SEL0);}
 
// Function prototypes
void __attribute__((__interrupt__)) timer_irq_handler(void);
void __attribute__((__interrupt__)) dummy_irq_handler(void);
void __attribute__((__naked__)) start_app(void);
void print_help(void);
void core_dump(void);
void store_eeprom(void);
void eeprom_write_word(uint16_t a, uint16_t d);
void spi_eeprom_write_byte(uint16_t a, uint8_t b);
uint8_t spi_eeprom_read_byte(uint16_t a);
uint8_t twi_eeprom_read_byte(uint16_t a);
void eeprom_write_word(uint32_t a, uint16_t d);
void get_image(uint8_t src);
uint16_t get_image_word(uint16_t a, uint8_t src);
uint16_t get_image_word(uint32_t a, uint8_t src);
void __attribute__((__naked__)) system_error(uint8_t err_code);
 
// Function prototypes - SPI flash
uint8_t spi_flash_read_byte();
void spi_flash_write_byte(uint32_t adr, uint8_t data);
void spi_flash_erase_sector(uint32_t base_adr);
uint8_t spi_flash_read_status(void);
void spi_flash_write_cmd(uint16_t cmd);
uint8_t spi_flash_read_1st_id(void);
void spi_flash_adr_conv(uint32_t adr, uint16_t *hi, uint16_t *mi, uint16_t *lo);
 
 
/* ------------------------------------------------------------
* INFO Bootloader main
* ------------------------------------------------------------ */
122,8 → 130,9
EXIRQ_CT = 0;
 
// init interrupt vectors
IRQVEC_TIMER = (uint16_t)(&timer_irq_handler); // timer match
IRQVEC_EXT = (uint16_t)(&dummy_irq_handler); // dummy handler in case an external IRQ occurs
IRQVEC_TIMER = (uint16_t)(&timer_irq_handler); // timer match
//IRQVEC_EXT = 0; // unused
//IRQVEC_SERIAL = 0; // unused
 
// init GPIO
GPIO_IRQMASK = 0; // no pin change interrupt please, thanks
136,8 → 145,7
 
// set SPI config:
// enable SPI, no IRQ, MSB first, 8-bit mode, SPI clock mode 0, set SPI speed, disable all SPI CS lines (set high)
neo430_spi_enable(SPI_PRSC_64); // this also resets the SPI module
neo430_spi_trans(0); // clear SPI RTX buffer
neo430_spi_enable(SPI_PRSC_8); // this also resets the SPI module
 
// Timeout counter: init timer, irq tick @ ~1Hz (prescaler = 4096)
// THR = f_main / (1Hz + 4096) -1
148,7 → 156,6
TMR_CT = (1<<TMR_CT_EN) | (1<<TMR_CT_ARST) | (1<<TMR_CT_IRQ) | ((16-1)<<TMR_CT_PRSC0) | (1<<TMR_CT_RUN);
TIMEOUT_CNT = 0; // console timeout ticker
 
neo430_clear_irq_buffer(); // clear all pending interrupts
neo430_eint(); // enable global interrupts
 
 
155,7 → 162,7
// ****************************************************************
// Show bootloader intro and system information
// ****************************************************************
neo430_uart_br_print("\n\n<< NEO430 Bootloader >>\n"
neo430_uart_br_print("\n\nNEO430 Bootloader\n"
"\n"
"BLV: "__DATE__"\n"
"HWV: 0x");
173,10 → 180,14
neo430_uart_print_hex_word(SYS_FEATURES);
 
 
// get SPI flash out of power down mode
spi_flash_write_cmd((uint16_t)SPI_FLASH_CMD_RELEASE);
 
 
// ****************************************************************
// Auto boot sequence
// ****************************************************************
neo430_uart_br_print("\n\nAutoboot in "xstr(AUTOBOOT_TIMEOUT)"s. Press key to abort.\n");
neo430_uart_br_print("\n\nAutoboot in "xstr(AUTOBOOT_TIMEOUT)"s. Press key to abort.\n\n");
while (1) { // wait for any key to be pressed or timeout
 
// timeout? start auto boot sequence
183,12 → 194,13
if (TIMEOUT_CNT == 4*AUTOBOOT_TIMEOUT) { // in 0.25 seconds
get_image(EEPROM_IMAGE_SPI); // try loading from EEPROM
neo430_uart_br_print("\n");
start_app(); // start app if loading was successful
start_app(); // start app
}
 
// key pressed? -> enter user console
if ((UART_RTX & (1<<UART_RTX_AVAIL)) != 0)
if ((UART_RTX & (1<<UART_RTX_AVAIL)) != 0) {
break;
}
}
print_help();
 
203,24 → 215,24
neo430_uart_putc(c); // echo
neo430_uart_br_print("\n");
 
if (c == 'r') // restart bootloader
if (c == 'r') { // restart bootloader
asm volatile ("mov #0xF000, r0"); // jump to beginning of bootloader ROM
else if (c == 'h') // help menu
}
else if (c == 'h') { // help menu
print_help();
else if (c == 'd') // core dump
core_dump();
else if (c == 'u') // upload program to RAM via UART
}
else if (c == 'u') { // upload program to RAM via UART
get_image(UART_IMAGE);
else if (c == 'p') // program EEPROM from RAM
}
else if (c == 'p') { // program EEPROM from RAM
store_eeprom();
else if (c == 'e') // copy program from EEPROM to RAM
get_image(EEPROM_IMAGE_SPI);
else if (c == 's') // start program in RAM
}
else if (c == 'e') { // start program in RAM
start_app();
else if (c == 'c')
neo430_uart_br_print("By Stephan Nolting\nMade in Hannover, Germany");
else // unknown command
neo430_uart_br_print("Bad CMD!");
}
else { // unknown command
neo430_uart_br_print("Bad CMD");
}
}
}
 
236,20 → 248,14
 
 
/* ------------------------------------------------------------
* INFO Dummy IRQ handler
* ------------------------------------------------------------ */
void __attribute__((__interrupt__)) dummy_irq_handler(void) {
 
asm volatile ("nop");
}
 
 
/* ------------------------------------------------------------
* INFO Start application in IMEM
* INFO "naked" since this is final...
* ------------------------------------------------------------ */
void __attribute__((__naked__)) start_app(void) {
 
// put SPI flah into power-down mode
spi_flash_write_cmd((uint16_t)SPI_FLASH_CMD_POWER_DOWN);
 
neo430_uart_br_print("Booting...\n\n");
 
// wait for UART to finish transmitting
271,89 → 277,50
void print_help(void) {
 
neo430_uart_br_print("CMDs:\n"
" d: Dump MEM\n"
" e: Load EEPROM\n"
" h: Help\n"
" p: Store EEPROM\n"
" r: Restart\n"
" s: Start app\n"
" u: Upload");
"h: Help\n"
"r: Restart\n"
"u: Upload\n"
"p: Program\n"
"e: Execute");
}
 
 
/* ------------------------------------------------------------
* INFO Print whole address space content
* ------------------------------------------------------------ */
void core_dump(void) {
 
uint16_t *pnt = (uint16_t*)0x0000;
uint16_t i = 0, j = 0;
while (1) {
neo430_uart_br_print("\n");
neo430_uart_print_hex_word((uint16_t)pnt); // print address
neo430_uart_br_print(": ");
// print hexadecimal data
for (i=0; i<16; i++) {
neo430_uart_print_hex_word(*pnt++);
neo430_uart_putc(' ');
}
// user abort or all done?
if ((neo430_uart_char_received() != 0) || (j == 0xFFE0))
return;
j += 32;
}
}
 
 
/* ------------------------------------------------------------
* INFO Store full IMEM content to SPI EEPROM at SPI.CS0
* ------------------------------------------------------------ */
void store_eeprom(void) {
 
neo430_uart_br_print("Proceed (y/n)?");
if (neo430_uart_getc() != 'y')
return;
neo430_uart_br_print("...");
 
neo430_uart_br_print("\nWriting... ");
// clear memory before writing
spi_flash_erase_sector(SPI_FLASH_BOOT_ADR);
 
BOOT_EEP_EN;
neo430_spi_trans(EEP_WREN); // write enable
neo430_spi_cs_dis();
 
// check if eeprom ready (or available at all)
BOOT_EEP_EN;
neo430_spi_trans(EEP_RDSR); // read status register CMD
uint16_t b = neo430_spi_trans(0); // read status register data
neo430_spi_cs_dis();
 
if ((b & 0x008F) != 0x0002)
if (spi_flash_read_1st_id() == 0x00) { // manufacturer ID
system_error(ERROR_EEPROM);
}
 
// write EXE signature
eeprom_write_word(EEP_IMAGE_BASE + 0, 0xCAFE);
eeprom_write_word(SPI_FLASH_BOOT_ADR + 0, 0xCAFE);
 
// write size
uint16_t end = IMEM_SIZE;
eeprom_write_word(EEP_IMAGE_BASE + 2, end);
eeprom_write_word(SPI_FLASH_BOOT_ADR + 2, end);
 
// store data from IMEM and update checksum
uint16_t checksum = 0;
uint16_t i = 0;
uint16_t *pnt = (uint16_t*)0x0000;;
uint16_t *pnt = (uint16_t*)0x0000;
 
while (i < end) {
uint16_t d = (uint16_t)*pnt++;
checksum ^= d;
eeprom_write_word(EEP_IMAGE_BASE + 6 + i, d);
eeprom_write_word(SPI_FLASH_BOOT_ADR + 6 + i, d);
i+= 2;
}
 
// write checksum
eeprom_write_word(EEP_IMAGE_BASE + 4, checksum);
eeprom_write_word(SPI_FLASH_BOOT_ADR + 4, checksum);
 
neo430_uart_br_print("OK");
}
361,81 → 328,20
 
/* ------------------------------------------------------------
* INFO EEPROM write data word
* PARAM a destination address (16 bit)
* PARAM a destination address (24 bit effective)
* PARAM d word to be written
* ------------------------------------------------------------ */
void eeprom_write_word(uint16_t a, uint16_t d) {
void eeprom_write_word(uint32_t a, uint16_t d) {
 
uint8_t lo = (uint8_t)(d);
uint8_t hi = (uint8_t)(d >> 8);
uint8_t hi = (uint8_t)neo430_bswap(d);
spi_eeprom_write_byte(a+0, hi);
spi_eeprom_write_byte(a+1, lo);
spi_flash_write_byte(a+0, hi);
spi_flash_write_byte(a+1, lo);
}
 
 
/* ------------------------------------------------------------
* INFO SPI EEPROM write single byte
* PARAM a destination address (16 bit)
* PARAM b byte to be written
* ------------------------------------------------------------ */
void spi_eeprom_write_byte(uint16_t a, uint8_t b) {
 
BOOT_EEP_EN;
neo430_spi_trans(EEP_WREN); // write enable
neo430_spi_cs_dis();
 
BOOT_EEP_EN;
neo430_spi_trans(EEP_WRITE); // byte write instruction
neo430_spi_trans(neo430_bswap(a)); // was ">> 8"
neo430_spi_trans(a >> 0);
neo430_spi_trans((uint16_t)b);
neo430_spi_cs_dis();
 
// wait for write to finish
while(1) {
BOOT_EEP_EN;
neo430_spi_trans(EEP_RDSR); // read status register CMD
uint16_t s = neo430_spi_trans(0);
neo430_spi_cs_dis();
 
if ((s & 0x0001) == 0) { // check WIP flag
break; // done!
}
}
}
 
 
/* ------------------------------------------------------------
* INFO SPI EEPROM read data
* PARAM a destination address (16 bit)
* RETURN byte read data
* ------------------------------------------------------------ */
uint8_t spi_eeprom_read_byte(uint16_t a) {
 
BOOT_EEP_EN;
neo430_spi_trans(EEP_READ); // byte read instruction
neo430_spi_trans(neo430_bswap(a)); // was ">> 8"
neo430_spi_trans(a >> 0);
uint8_t d = (uint8_t)neo430_spi_trans(0);
neo430_spi_cs_dis();
 
return d;
}
 
 
/* ------------------------------------------------------------
* INFO TWI EEPROM read data
* PARAM a destination address (16 bit)
* RETURN byte read data
* ------------------------------------------------------------ */
uint8_t twi_eeprom_read_byte(uint16_t a) {
 
return 0;
}
 
 
/* ------------------------------------------------------------
* INFO Get IMEM image from SPI EEPROM at SPI.CS0 or from UART
* PARAM src Image source 0: UART, 1: SPI_EEPROM
* RETURN error code (0 if successful)
448,22 → 354,25
}
 
// print intro
if (src == UART_IMAGE) // boot via UART
neo430_uart_br_print("Awaiting BINEXE... ");
else //if (src == EEPROM_IMAGE_SPI)// boot from EEPROM
neo430_uart_br_print("Loading... ");
if (src == UART_IMAGE) { // boot via UART
neo430_uart_br_print("Awaiting BINEXE...");
}
else { //if (src == EEPROM_IMAGE_SPI)// boot from EEPROM
neo430_uart_br_print("Loading...");
}
 
// check if valid image
if (get_image_word(0x0000, src) != 0xCAFE) { // signature
if (get_image_word(SPI_FLASH_BOOT_ADR + 0, src) != 0xCAFE) { // signature
system_error(ERROR_EXECUTABLE);
}
 
// image size and checksum
uint16_t size = get_image_word(0x0002, src);
uint16_t check = get_image_word(0x0004, src);
uint16_t size = get_image_word(SPI_FLASH_BOOT_ADR + 2, src); // size in bytes
uint16_t check = get_image_word(SPI_FLASH_BOOT_ADR + 4, src); // XOR checksum
uint16_t end = IMEM_SIZE;
if (size > end)
if (size > end) {
system_error(ERROR_SIZE);
}
 
// transfer program data
uint16_t *pnt = (uint16_t*)0x0000;
470,7 → 379,7
uint16_t checksum = 0x0000;
uint16_t d = 0, i = 0;
while (i < size/2) { // in words
d = get_image_word(2*i+0x0006, src);
d = get_image_word(SPI_FLASH_BOOT_ADR + 2*i + 6, src);
checksum ^= d;
pnt[i++] = d;
}
492,11 → 401,11
 
/* ------------------------------------------------------------
* INFO Get image word from SPI_EEPROM or UART
* PARAM a source address (16 bit)
* PARAM a source address (24 bit effective)
* PARAM src: 0: UART, 1: SPI_EEPROM
* RETURN accessed data word
* ------------------------------------------------------------ */
uint16_t get_image_word(uint16_t a, uint8_t src) {
uint16_t get_image_word(uint32_t a, uint8_t src) {
 
uint8_t c0 = 0, c1 = 0;
 
506,13 → 415,9
c1 = (uint8_t)neo430_uart_getc();
}
else {// if (src == EEPROM_IMAGE_SPI) { // get image data from SPI EEPROM
c0 = spi_eeprom_read_byte(a+0);
c1 = spi_eeprom_read_byte(a+1);
c0 = spi_flash_read_byte(a+0);
c1 = spi_flash_read_byte(a+1);
}
//else { // if (src == EEPROM_IMAGE_TWI) // get image data from TWI EEPROM
// //c0 = twi_eeprom_read_byte(a+0);
// //c1 = twi_eeprom_read_byte(a+1);
//}
 
//uint16_t r = (((uint16_t)c0) << 8) | (((uint16_t)c1) << 0);
uint16_t r = neo430_combine_bytes(c0, c1);
536,3 → 441,146
 
while(1); // freeze
}
 
 
 
// *************************************************************************************
// SPI flash functions
// *************************************************************************************
 
/* ------------------------------------------------------------
* Read single byte from flash (24-bit adress)
* ------------------------------------------------------------ */
uint8_t spi_flash_read_byte(uint32_t adr) {
 
uint16_t adr_lo;
uint16_t adr_mi;
uint16_t adr_hi;
spi_flash_adr_conv(adr, &adr_hi, &adr_mi, &adr_lo);
 
SPI_FLASH_SEL;
 
neo430_spi_trans((uint16_t)SPI_FLASH_CMD_READ);
// no masking required, SPI unit in 8 bit mode ignores upper 8 bits
neo430_spi_trans(adr_hi);
neo430_spi_trans(adr_mi);
neo430_spi_trans(adr_lo);
uint16_t data = neo430_spi_trans(0);
 
neo430_spi_cs_dis();
 
return (uint8_t)data;
}
 
 
/* ------------------------------------------------------------
* Write single data byte to flash at base adress
* ------------------------------------------------------------ */
void spi_flash_write_byte(uint32_t adr, uint8_t data) {
 
uint16_t adr_lo;
uint16_t adr_mi;
uint16_t adr_hi;
spi_flash_adr_conv(adr, &adr_hi, &adr_mi, &adr_lo);
 
spi_flash_write_cmd((uint16_t)SPI_FLASH_CMD_WRITE_ENABLE); // allow write-access
 
SPI_FLASH_SEL;
 
neo430_spi_trans((uint16_t)SPI_FLASH_CMD_PAGE_PROGRAM);
// no masking required, SPI unit in 8 bit mode ignores upper 8 bits
neo430_spi_trans(adr_hi);
neo430_spi_trans(adr_mi);
neo430_spi_trans(adr_lo);
neo430_spi_trans((uint16_t)data);
 
neo430_spi_cs_dis();
 
while(spi_flash_read_status());
}
 
 
/* ------------------------------------------------------------
* Erase sector (64kB) at base adress
* ------------------------------------------------------------ */
void spi_flash_erase_sector(uint32_t base_adr) {
 
uint16_t adr_lo;
uint16_t adr_mi;
uint16_t adr_hi;
spi_flash_adr_conv(base_adr, &adr_hi, &adr_mi, &adr_lo);
 
spi_flash_write_cmd((uint16_t)SPI_FLASH_CMD_WRITE_ENABLE); // allow write-access
 
SPI_FLASH_SEL;
 
neo430_spi_trans((uint16_t)SPI_FLASH_CMD_SECTOR_ERASE);
// no masking required, SPI unit in 8 bit mode ignores upper 8 bits
neo430_spi_trans(adr_hi);
neo430_spi_trans(adr_mi);
neo430_spi_trans(adr_lo);
 
neo430_spi_cs_dis();
 
while(spi_flash_read_status());
}
 
 
/* ------------------------------------------------------------
* Read status register
* ------------------------------------------------------------ */
uint8_t spi_flash_read_status(void) {
 
SPI_FLASH_SEL;
 
neo430_spi_trans((uint16_t)SPI_FLASH_CMD_READ_STATUS);
uint16_t status = neo430_spi_trans(0);
 
neo430_spi_cs_dis();
 
return (uint8_t)status;
}
 
 
/* ------------------------------------------------------------
* Read first byte of ID (manufacturer ID), should be != 0x00
* ------------------------------------------------------------ */
uint8_t spi_flash_read_1st_id(void) {
 
SPI_FLASH_SEL;
 
neo430_spi_trans((uint16_t)SPI_FLASH_CMD_READ_ID);
uint16_t id = neo430_spi_trans(0);
 
neo430_spi_cs_dis();
 
return (uint8_t)id;
}
 
 
/* ------------------------------------------------------------
* Write command to flash
* ------------------------------------------------------------ */
void spi_flash_write_cmd(uint16_t cmd) {
 
SPI_FLASH_SEL;
 
neo430_spi_trans(cmd);
 
neo430_spi_cs_dis();
}
 
 
/* ------------------------------------------------------------
* Adress conversion helper
* ------------------------------------------------------------ */
void spi_flash_adr_conv(uint32_t adr, uint16_t *hi, uint16_t *mi, uint16_t *lo) {
 
uint16_t adr_hi16 = (uint16_t)(adr >> 16);
uint16_t adr_lo16 = (uint16_t)(adr >> 0);
 
*lo = adr_lo16;
*mi = neo430_bswap(adr_lo16);
*hi = adr_hi16;
}
 
/trunk/neo430/sw/lib/neo430/source/neo430_spi.c
56,7 → 56,7
 
 
/* ------------------------------------------------------------
* INFO Enable SPI CSx (set low), can be used to set several CS lines
* INFO Enable SPI CSx (set low)
* PARAM CS line (0..5)
* ------------------------------------------------------------ */
void neo430_spi_cs_en(uint8_t cs) {

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