URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/
- from Rev 47 to Rev 48
- ↔ Reverse comparison
Rev 47 → Rev 48
/neorv32/trunk/docs/figures/neorv32_processor.png
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/neorv32/trunk/docs/NEORV32.pdf
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svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 1032) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 1043) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
54,13 → 54,13
00000043 => x"feb01ce3", |
00000044 => x"80000597", |
00000045 => x"f5058593", |
00000046 => x"85418613", |
00000046 => x"87418613", |
00000047 => x"00c5d863", |
00000048 => x"00058023", |
00000049 => x"00158593", |
00000050 => x"ff5ff06f", |
00000051 => x"00001597", |
00000052 => x"f5458593", |
00000052 => x"f8058593", |
00000053 => x"80000617", |
00000054 => x"f2c60613", |
00000055 => x"80000697", |
107,939 → 107,950
00000096 => x"30200073", |
00000097 => x"00005537", |
00000098 => x"ff010113", |
00000099 => x"00000693", |
00000100 => x"00000613", |
00000101 => x"00000593", |
00000102 => x"b0050513", |
00000103 => x"00112623", |
00000104 => x"63c000ef", |
00000105 => x"0f1000ef", |
00000106 => x"02050063", |
00000107 => x"480000ef", |
00000108 => x"00000513", |
00000109 => x"4d4000ef", |
00000110 => x"00001537", |
00000111 => x"cd450513", |
00000112 => x"6c8000ef", |
00000113 => x"020000ef", |
00000114 => x"00001537", |
00000115 => x"cb050513", |
00000116 => x"6b8000ef", |
00000117 => x"00c12083", |
00000118 => x"00000513", |
00000119 => x"01010113", |
00000120 => x"00008067", |
00000121 => x"ff010113", |
00000122 => x"00000513", |
00000123 => x"00812423", |
00000124 => x"00112623", |
00000125 => x"00000413", |
00000126 => x"0ad000ef", |
00000127 => x"0ff47513", |
00000128 => x"0a5000ef", |
00000129 => x"0c800513", |
00000130 => x"0d1000ef", |
00000131 => x"00140413", |
00000132 => x"fedff06f", |
00000133 => x"00000000", |
00000134 => x"00000000", |
00000135 => x"00000000", |
00000136 => x"fc010113", |
00000137 => x"02112e23", |
00000138 => x"02512c23", |
00000139 => x"02612a23", |
00000140 => x"02712823", |
00000141 => x"02a12623", |
00000142 => x"02b12423", |
00000143 => x"02c12223", |
00000144 => x"02d12023", |
00000145 => x"00e12e23", |
00000146 => x"00f12c23", |
00000147 => x"01012a23", |
00000148 => x"01112823", |
00000149 => x"01c12623", |
00000150 => x"01d12423", |
00000151 => x"01e12223", |
00000152 => x"01f12023", |
00000153 => x"34102773", |
00000154 => x"34071073", |
00000155 => x"342027f3", |
00000156 => x"0807c863", |
00000157 => x"00071683", |
00000158 => x"00300593", |
00000159 => x"0036f693", |
00000160 => x"00270613", |
00000161 => x"00b69463", |
00000162 => x"00470613", |
00000163 => x"34161073", |
00000164 => x"00b00713", |
00000165 => x"04f77a63", |
00000166 => x"46800793", |
00000167 => x"000780e7", |
00000168 => x"03c12083", |
00000169 => x"03812283", |
00000170 => x"03412303", |
00000171 => x"03012383", |
00000172 => x"02c12503", |
00000173 => x"02812583", |
00000174 => x"02412603", |
00000175 => x"02012683", |
00000176 => x"01c12703", |
00000177 => x"01812783", |
00000178 => x"01412803", |
00000179 => x"01012883", |
00000180 => x"00c12e03", |
00000181 => x"00812e83", |
00000182 => x"00412f03", |
00000183 => x"00012f83", |
00000184 => x"04010113", |
00000185 => x"30200073", |
00000186 => x"00001737", |
00000187 => x"00279793", |
00000188 => x"cf070713", |
00000189 => x"00e787b3", |
00000190 => x"0007a783", |
00000191 => x"00078067", |
00000192 => x"80000737", |
00000193 => x"ffd74713", |
00000194 => x"00e787b3", |
00000195 => x"01400713", |
00000196 => x"f8f764e3", |
00000197 => x"00001737", |
00000198 => x"00279793", |
00000199 => x"d2070713", |
00000200 => x"00e787b3", |
00000201 => x"0007a783", |
00000202 => x"00078067", |
00000203 => x"800007b7", |
00000204 => x"0007a783", |
00000205 => x"f69ff06f", |
00000206 => x"800007b7", |
00000207 => x"0047a783", |
00000208 => x"f5dff06f", |
00000209 => x"800007b7", |
00000210 => x"0087a783", |
00000211 => x"f51ff06f", |
00000212 => x"800007b7", |
00000213 => x"00c7a783", |
00000214 => x"f45ff06f", |
00000215 => x"8101a783", |
00000216 => x"f3dff06f", |
00000217 => x"8141a783", |
00000218 => x"f35ff06f", |
00000219 => x"8181a783", |
00000220 => x"f2dff06f", |
00000221 => x"81c1a783", |
00000222 => x"f25ff06f", |
00000223 => x"8201a783", |
00000224 => x"f1dff06f", |
00000225 => x"8241a783", |
00000226 => x"f15ff06f", |
00000227 => x"8281a783", |
00000228 => x"f0dff06f", |
00000229 => x"82c1a783", |
00000230 => x"f05ff06f", |
00000231 => x"8301a783", |
00000232 => x"efdff06f", |
00000233 => x"8341a783", |
00000234 => x"ef5ff06f", |
00000235 => x"8381a783", |
00000236 => x"eedff06f", |
00000237 => x"83c1a783", |
00000238 => x"ee5ff06f", |
00000239 => x"8401a783", |
00000240 => x"eddff06f", |
00000241 => x"8441a783", |
00000242 => x"ed5ff06f", |
00000243 => x"8481a783", |
00000244 => x"ecdff06f", |
00000245 => x"84c1a783", |
00000246 => x"ec5ff06f", |
00000247 => x"8501a783", |
00000248 => x"ebdff06f", |
00000249 => x"00000000", |
00000250 => x"00000000", |
00000251 => x"01553513", |
00000252 => x"00154513", |
00000253 => x"00008067", |
00000254 => x"fe010113", |
00000255 => x"01212823", |
00000256 => x"00050913", |
00000257 => x"00001537", |
00000258 => x"00912a23", |
00000259 => x"d7450513", |
00000260 => x"000014b7", |
00000261 => x"00812c23", |
00000262 => x"01312623", |
00000263 => x"00112e23", |
00000264 => x"01c00413", |
00000265 => x"464000ef", |
00000266 => x"ff048493", |
00000267 => x"ffc00993", |
00000268 => x"008957b3", |
00000269 => x"00f7f793", |
00000270 => x"00f487b3", |
00000271 => x"0007c503", |
00000272 => x"ffc40413", |
00000273 => x"434000ef", |
00000274 => x"ff3414e3", |
00000275 => x"01c12083", |
00000276 => x"01812403", |
00000277 => x"01412483", |
00000278 => x"01012903", |
00000279 => x"00c12983", |
00000280 => x"02010113", |
00000281 => x"00008067", |
00000282 => x"00001537", |
00000283 => x"ff010113", |
00000284 => x"d7850513", |
00000285 => x"00112623", |
00000286 => x"00812423", |
00000287 => x"40c000ef", |
00000288 => x"34202473", |
00000289 => x"00b00793", |
00000290 => x"0087ee63", |
00000291 => x"00001737", |
00000292 => x"00241793", |
00000293 => x"f0470713", |
00000294 => x"00e787b3", |
00000295 => x"0007a783", |
00000296 => x"00078067", |
00000297 => x"800007b7", |
00000298 => x"00b78713", |
00000299 => x"12e40663", |
00000300 => x"02876663", |
00000301 => x"00378713", |
00000302 => x"10e40463", |
00000303 => x"00778793", |
00000304 => x"10f40663", |
00000305 => x"00001537", |
00000306 => x"ed850513", |
00000307 => x"3bc000ef", |
00000308 => x"00040513", |
00000309 => x"f25ff0ef", |
00000310 => x"03c0006f", |
00000311 => x"ff07c793", |
00000312 => x"00f407b3", |
00000313 => x"00700713", |
00000314 => x"fcf76ee3", |
00000315 => x"00001537", |
00000316 => x"ec850513", |
00000317 => x"394000ef", |
00000318 => x"00747513", |
00000319 => x"03050513", |
00000320 => x"378000ef", |
00000321 => x"0100006f", |
00000322 => x"00001537", |
00000323 => x"d8050513", |
00000324 => x"378000ef", |
00000325 => x"00001537", |
00000326 => x"ef050513", |
00000327 => x"36c000ef", |
00000328 => x"34002573", |
00000329 => x"ed5ff0ef", |
00000099 => x"00000593", |
00000100 => x"b0050513", |
00000101 => x"00112623", |
00000102 => x"668000ef", |
00000103 => x"105000ef", |
00000104 => x"02050063", |
00000105 => x"4ac000ef", |
00000106 => x"00000513", |
00000107 => x"500000ef", |
00000108 => x"00001537", |
00000109 => x"ce050513", |
00000110 => x"6dc000ef", |
00000111 => x"020000ef", |
00000112 => x"00001537", |
00000113 => x"cbc50513", |
00000114 => x"6cc000ef", |
00000115 => x"00c12083", |
00000116 => x"00000513", |
00000117 => x"01010113", |
00000118 => x"00008067", |
00000119 => x"ff010113", |
00000120 => x"00000513", |
00000121 => x"00812423", |
00000122 => x"00112623", |
00000123 => x"00000413", |
00000124 => x"0c1000ef", |
00000125 => x"0ff47513", |
00000126 => x"0b9000ef", |
00000127 => x"0c800513", |
00000128 => x"0e5000ef", |
00000129 => x"00140413", |
00000130 => x"fedff06f", |
00000131 => x"00000000", |
00000132 => x"fc010113", |
00000133 => x"02112e23", |
00000134 => x"02512c23", |
00000135 => x"02612a23", |
00000136 => x"02712823", |
00000137 => x"02a12623", |
00000138 => x"02b12423", |
00000139 => x"02c12223", |
00000140 => x"02d12023", |
00000141 => x"00e12e23", |
00000142 => x"00f12c23", |
00000143 => x"01012a23", |
00000144 => x"01112823", |
00000145 => x"01c12623", |
00000146 => x"01d12423", |
00000147 => x"01e12223", |
00000148 => x"01f12023", |
00000149 => x"34102773", |
00000150 => x"34071073", |
00000151 => x"342027f3", |
00000152 => x"0807c863", |
00000153 => x"00071683", |
00000154 => x"00300593", |
00000155 => x"0036f693", |
00000156 => x"00270613", |
00000157 => x"00b69463", |
00000158 => x"00470613", |
00000159 => x"34161073", |
00000160 => x"00b00713", |
00000161 => x"04f77a63", |
00000162 => x"48c00793", |
00000163 => x"000780e7", |
00000164 => x"03c12083", |
00000165 => x"03812283", |
00000166 => x"03412303", |
00000167 => x"03012383", |
00000168 => x"02c12503", |
00000169 => x"02812583", |
00000170 => x"02412603", |
00000171 => x"02012683", |
00000172 => x"01c12703", |
00000173 => x"01812783", |
00000174 => x"01412803", |
00000175 => x"01012883", |
00000176 => x"00c12e03", |
00000177 => x"00812e83", |
00000178 => x"00412f03", |
00000179 => x"00012f83", |
00000180 => x"04010113", |
00000181 => x"30200073", |
00000182 => x"00001737", |
00000183 => x"00279793", |
00000184 => x"cfc70713", |
00000185 => x"00e787b3", |
00000186 => x"0007a783", |
00000187 => x"00078067", |
00000188 => x"80000737", |
00000189 => x"ffd74713", |
00000190 => x"00e787b3", |
00000191 => x"01c00713", |
00000192 => x"f8f764e3", |
00000193 => x"00001737", |
00000194 => x"00279793", |
00000195 => x"d2c70713", |
00000196 => x"00e787b3", |
00000197 => x"0007a783", |
00000198 => x"00078067", |
00000199 => x"800007b7", |
00000200 => x"0007a783", |
00000201 => x"f69ff06f", |
00000202 => x"800007b7", |
00000203 => x"0047a783", |
00000204 => x"f5dff06f", |
00000205 => x"800007b7", |
00000206 => x"0087a783", |
00000207 => x"f51ff06f", |
00000208 => x"800007b7", |
00000209 => x"00c7a783", |
00000210 => x"f45ff06f", |
00000211 => x"8101a783", |
00000212 => x"f3dff06f", |
00000213 => x"8141a783", |
00000214 => x"f35ff06f", |
00000215 => x"8181a783", |
00000216 => x"f2dff06f", |
00000217 => x"81c1a783", |
00000218 => x"f25ff06f", |
00000219 => x"8201a783", |
00000220 => x"f1dff06f", |
00000221 => x"8241a783", |
00000222 => x"f15ff06f", |
00000223 => x"8281a783", |
00000224 => x"f0dff06f", |
00000225 => x"82c1a783", |
00000226 => x"f05ff06f", |
00000227 => x"8301a783", |
00000228 => x"efdff06f", |
00000229 => x"8341a783", |
00000230 => x"ef5ff06f", |
00000231 => x"8381a783", |
00000232 => x"eedff06f", |
00000233 => x"83c1a783", |
00000234 => x"ee5ff06f", |
00000235 => x"8401a783", |
00000236 => x"eddff06f", |
00000237 => x"8441a783", |
00000238 => x"ed5ff06f", |
00000239 => x"8481a783", |
00000240 => x"ecdff06f", |
00000241 => x"84c1a783", |
00000242 => x"ec5ff06f", |
00000243 => x"8501a783", |
00000244 => x"ebdff06f", |
00000245 => x"8541a783", |
00000246 => x"eb5ff06f", |
00000247 => x"8581a783", |
00000248 => x"eadff06f", |
00000249 => x"85c1a783", |
00000250 => x"ea5ff06f", |
00000251 => x"8601a783", |
00000252 => x"e9dff06f", |
00000253 => x"8641a783", |
00000254 => x"e95ff06f", |
00000255 => x"8681a783", |
00000256 => x"e8dff06f", |
00000257 => x"86c1a783", |
00000258 => x"e85ff06f", |
00000259 => x"8701a783", |
00000260 => x"e7dff06f", |
00000261 => x"00000000", |
00000262 => x"00000000", |
00000263 => x"fe010113", |
00000264 => x"01212823", |
00000265 => x"00050913", |
00000266 => x"00001537", |
00000267 => x"00912a23", |
00000268 => x"da050513", |
00000269 => x"000014b7", |
00000270 => x"00812c23", |
00000271 => x"01312623", |
00000272 => x"00112e23", |
00000273 => x"01c00413", |
00000274 => x"44c000ef", |
00000275 => x"01c48493", |
00000276 => x"ffc00993", |
00000277 => x"008957b3", |
00000278 => x"00f7f793", |
00000279 => x"00f487b3", |
00000280 => x"0007c503", |
00000281 => x"ffc40413", |
00000282 => x"41c000ef", |
00000283 => x"ff3414e3", |
00000284 => x"01c12083", |
00000285 => x"01812403", |
00000286 => x"01412483", |
00000287 => x"01012903", |
00000288 => x"00c12983", |
00000289 => x"02010113", |
00000290 => x"00008067", |
00000291 => x"00001537", |
00000292 => x"ff010113", |
00000293 => x"da450513", |
00000294 => x"00112623", |
00000295 => x"00812423", |
00000296 => x"00912223", |
00000297 => x"3f0000ef", |
00000298 => x"34202473", |
00000299 => x"00900713", |
00000300 => x"00f47793", |
00000301 => x"05778493", |
00000302 => x"00f76463", |
00000303 => x"03078493", |
00000304 => x"00b00793", |
00000305 => x"0087ee63", |
00000306 => x"00001737", |
00000307 => x"00241793", |
00000308 => x"f3070713", |
00000309 => x"00e787b3", |
00000310 => x"0007a783", |
00000311 => x"00078067", |
00000312 => x"800007b7", |
00000313 => x"00b78713", |
00000314 => x"12e40663", |
00000315 => x"02876663", |
00000316 => x"00378713", |
00000317 => x"10e40463", |
00000318 => x"00778793", |
00000319 => x"10f40663", |
00000320 => x"00001537", |
00000321 => x"f0450513", |
00000322 => x"38c000ef", |
00000323 => x"00040513", |
00000324 => x"f0dff0ef", |
00000325 => x"0380006f", |
00000326 => x"ff07c793", |
00000327 => x"00f407b3", |
00000328 => x"00f00713", |
00000329 => x"fcf76ee3", |
00000330 => x"00001537", |
00000331 => x"ef850513", |
00000332 => x"358000ef", |
00000333 => x"34302573", |
00000334 => x"ec1ff0ef", |
00000335 => x"00812403", |
00000336 => x"00c12083", |
00000337 => x"00001537", |
00000338 => x"f6050513", |
00000339 => x"01010113", |
00000340 => x"3380006f", |
00000341 => x"00001537", |
00000342 => x"da050513", |
00000343 => x"fb5ff06f", |
00000331 => x"ef450513", |
00000332 => x"364000ef", |
00000333 => x"00048513", |
00000334 => x"34c000ef", |
00000335 => x"0100006f", |
00000336 => x"00001537", |
00000337 => x"dac50513", |
00000338 => x"34c000ef", |
00000339 => x"00001537", |
00000340 => x"f1c50513", |
00000341 => x"340000ef", |
00000342 => x"34002573", |
00000343 => x"ec1ff0ef", |
00000344 => x"00001537", |
00000345 => x"dbc50513", |
00000346 => x"fa9ff06f", |
00000347 => x"00001537", |
00000348 => x"dd050513", |
00000349 => x"f9dff06f", |
00000350 => x"00001537", |
00000351 => x"ddc50513", |
00000352 => x"f91ff06f", |
00000353 => x"00001537", |
00000354 => x"df450513", |
00000355 => x"f85ff06f", |
00000345 => x"f2450513", |
00000346 => x"32c000ef", |
00000347 => x"34302573", |
00000348 => x"eadff0ef", |
00000349 => x"00812403", |
00000350 => x"00c12083", |
00000351 => x"00412483", |
00000352 => x"00001537", |
00000353 => x"f8c50513", |
00000354 => x"01010113", |
00000355 => x"3080006f", |
00000356 => x"00001537", |
00000357 => x"e0850513", |
00000358 => x"f79ff06f", |
00000357 => x"dcc50513", |
00000358 => x"fb1ff06f", |
00000359 => x"00001537", |
00000360 => x"e2450513", |
00000361 => x"f6dff06f", |
00000360 => x"de850513", |
00000361 => x"fa5ff06f", |
00000362 => x"00001537", |
00000363 => x"e3850513", |
00000364 => x"f61ff06f", |
00000363 => x"dfc50513", |
00000364 => x"f99ff06f", |
00000365 => x"00001537", |
00000366 => x"e5850513", |
00000367 => x"f55ff06f", |
00000366 => x"e0850513", |
00000367 => x"f8dff06f", |
00000368 => x"00001537", |
00000369 => x"e7850513", |
00000370 => x"f49ff06f", |
00000369 => x"e2050513", |
00000370 => x"f81ff06f", |
00000371 => x"00001537", |
00000372 => x"e9450513", |
00000373 => x"f3dff06f", |
00000372 => x"e3450513", |
00000373 => x"f75ff06f", |
00000374 => x"00001537", |
00000375 => x"eac50513", |
00000376 => x"f31ff06f", |
00000377 => x"ff010113", |
00000378 => x"00812423", |
00000379 => x"00112623", |
00000380 => x"00050413", |
00000381 => x"df9ff0ef", |
00000382 => x"02051663", |
00000383 => x"800007b7", |
00000384 => x"00241413", |
00000385 => x"00078793", |
00000386 => x"008787b3", |
00000387 => x"46800713", |
00000388 => x"00e7a023", |
00000389 => x"00c12083", |
00000390 => x"00812403", |
00000391 => x"01010113", |
00000392 => x"00008067", |
00000393 => x"00100513", |
00000394 => x"fedff06f", |
00000395 => x"ff010113", |
00000396 => x"00112623", |
00000397 => x"00812423", |
00000398 => x"00912223", |
00000399 => x"301027f3", |
00000400 => x"00079863", |
00000401 => x"00001537", |
00000402 => x"f3450513", |
00000403 => x"23c000ef", |
00000404 => x"22000793", |
00000405 => x"30579073", |
00000406 => x"00000413", |
00000407 => x"01500493", |
00000408 => x"00040513", |
00000409 => x"00140413", |
00000410 => x"0ff47413", |
00000411 => x"f79ff0ef", |
00000412 => x"fe9418e3", |
00000413 => x"00c12083", |
00000414 => x"00812403", |
00000415 => x"00412483", |
00000416 => x"01010113", |
00000417 => x"00008067", |
00000418 => x"ff010113", |
00000419 => x"00112623", |
00000420 => x"00812423", |
00000421 => x"30102673", |
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00001030 => x"000a0a29", |
00001031 => x"33323130", |
00001032 => x"37363534", |
00001033 => x"42413938", |
00001034 => x"46454443", |
00001035 => x"33323130", |
00001036 => x"37363534", |
00001037 => x"00003938", |
00001038 => x"33323130", |
00001039 => x"37363534", |
00001040 => x"62613938", |
00001041 => x"66656463", |
00001042 => x"00000000", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 999) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 987) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
44,7 → 44,7
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"f1058593", |
00000036 => x"ee058593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
106,907 → 106,895
00000095 => x"01712623", |
00000096 => x"01812423", |
00000097 => x"9ff78793", |
00000098 => x"00000693", |
00000099 => x"00000613", |
00000100 => x"00000593", |
00000101 => x"00200513", |
00000102 => x"0087f463", |
00000103 => x"00400513", |
00000104 => x"339000ef", |
00000105 => x"00100513", |
00000106 => x"3e5000ef", |
00000107 => x"00005537", |
00000108 => x"00000693", |
00000109 => x"00000613", |
00000110 => x"00000593", |
00000111 => x"b0050513", |
00000112 => x"1f9000ef", |
00000113 => x"1b1000ef", |
00000114 => x"00245793", |
00000115 => x"00a78533", |
00000116 => x"00f537b3", |
00000117 => x"00b785b3", |
00000118 => x"1c9000ef", |
00000119 => x"ffff07b7", |
00000120 => x"4c878793", |
00000121 => x"30579073", |
00000122 => x"08000793", |
00000123 => x"30479073", |
00000124 => x"30046073", |
00000125 => x"00000013", |
00000126 => x"00000013", |
00000127 => x"ffff1537", |
00000128 => x"eb850513", |
00000129 => x"27d000ef", |
00000130 => x"f1302573", |
00000131 => x"24c000ef", |
00000132 => x"ffff1537", |
00000133 => x"ef050513", |
00000134 => x"269000ef", |
00000135 => x"fe002503", |
00000136 => x"238000ef", |
00000137 => x"ffff1537", |
00000138 => x"ef850513", |
00000139 => x"255000ef", |
00000140 => x"fe402503", |
00000141 => x"224000ef", |
00000142 => x"ffff1537", |
00000143 => x"f0450513", |
00000144 => x"241000ef", |
00000145 => x"30102573", |
00000146 => x"210000ef", |
00000147 => x"ffff1537", |
00000148 => x"f0c50513", |
00000149 => x"22d000ef", |
00000150 => x"fe802503", |
00000151 => x"ffff14b7", |
00000152 => x"00341413", |
00000153 => x"1f4000ef", |
00000154 => x"ffff1537", |
00000155 => x"f1450513", |
00000156 => x"211000ef", |
00000157 => x"ff802503", |
00000158 => x"1e0000ef", |
00000159 => x"f1c48513", |
00000160 => x"201000ef", |
00000161 => x"ff002503", |
00000162 => x"1d0000ef", |
00000163 => x"ffff1537", |
00000164 => x"f2850513", |
00000165 => x"1ed000ef", |
00000166 => x"ffc02503", |
00000167 => x"1bc000ef", |
00000168 => x"f1c48513", |
00000169 => x"1dd000ef", |
00000170 => x"ff402503", |
00000171 => x"1ac000ef", |
00000172 => x"ffff1537", |
00000173 => x"f3050513", |
00000174 => x"1c9000ef", |
00000175 => x"0b9000ef", |
00000176 => x"00a404b3", |
00000177 => x"0084b433", |
00000178 => x"00b40433", |
00000179 => x"fa402783", |
00000180 => x"0207d263", |
00000181 => x"ffff1537", |
00000182 => x"f5850513", |
00000183 => x"1a5000ef", |
00000184 => x"195000ef", |
00000185 => x"02300793", |
00000186 => x"02f51263", |
00000187 => x"00000513", |
00000188 => x"0180006f", |
00000189 => x"081000ef", |
00000190 => x"fc85eae3", |
00000191 => x"00b41463", |
00000192 => x"fc9566e3", |
00000193 => x"00100513", |
00000194 => x"5dc000ef", |
00000195 => x"0b4000ef", |
00000196 => x"ffff1937", |
00000197 => x"ffff19b7", |
00000198 => x"02300a13", |
00000199 => x"07200a93", |
00000200 => x"06800b13", |
00000201 => x"07500b93", |
00000202 => x"ffff14b7", |
00000203 => x"ffff1c37", |
00000204 => x"f6490513", |
00000205 => x"14d000ef", |
00000206 => x"12d000ef", |
00000207 => x"00050413", |
00000208 => x"115000ef", |
00000209 => x"e7098513", |
00000210 => x"139000ef", |
00000211 => x"fb4400e3", |
00000212 => x"01541863", |
00000213 => x"ffff02b7", |
00000214 => x"00028067", |
00000215 => x"fd5ff06f", |
00000216 => x"01641663", |
00000217 => x"05c000ef", |
00000218 => x"fc9ff06f", |
00000219 => x"00000513", |
00000220 => x"03740063", |
00000221 => x"07300793", |
00000222 => x"00f41663", |
00000223 => x"67c000ef", |
00000224 => x"fb1ff06f", |
00000225 => x"06c00793", |
00000226 => x"00f41863", |
00000227 => x"00100513", |
00000228 => x"3fc000ef", |
00000229 => x"f9dff06f", |
00000230 => x"06500793", |
00000231 => x"00f41663", |
00000232 => x"02c000ef", |
00000233 => x"f8dff06f", |
00000234 => x"03f00793", |
00000235 => x"f6cc0513", |
00000236 => x"00f40463", |
00000237 => x"f8048513", |
00000238 => x"0c9000ef", |
00000239 => x"f75ff06f", |
00000240 => x"ffff1537", |
00000241 => x"d9450513", |
00000242 => x"0b90006f", |
00000243 => x"800007b7", |
00000244 => x"0007a783", |
00000245 => x"00079863", |
00000246 => x"ffff1537", |
00000247 => x"df850513", |
00000248 => x"0a10006f", |
00000249 => x"ff010113", |
00000250 => x"00112623", |
00000251 => x"30047073", |
00000252 => x"00000013", |
00000253 => x"00000013", |
00000254 => x"ffff1537", |
00000255 => x"e1450513", |
00000256 => x"081000ef", |
00000257 => x"fa002783", |
00000258 => x"fe07cee3", |
00000259 => x"ff002783", |
00000260 => x"00078067", |
00000261 => x"0000006f", |
00000262 => x"ff010113", |
00000263 => x"00812423", |
00000264 => x"00050413", |
00000265 => x"ffff1537", |
00000266 => x"e2450513", |
00000267 => x"00112623", |
00000268 => x"051000ef", |
00000269 => x"03040513", |
00000270 => x"0ff57513", |
00000271 => x"019000ef", |
00000272 => x"30047073", |
00000273 => x"00000013", |
00000274 => x"00000013", |
00000275 => x"00100513", |
00000276 => x"13d000ef", |
00000277 => x"0000006f", |
00000278 => x"fe010113", |
00000279 => x"01212823", |
00000280 => x"00050913", |
00000281 => x"ffff1537", |
00000282 => x"00912a23", |
00000283 => x"e3c50513", |
00000284 => x"ffff14b7", |
00000285 => x"00812c23", |
00000286 => x"01312623", |
00000287 => x"00112e23", |
00000288 => x"01c00413", |
00000289 => x"7fc000ef", |
00000290 => x"f8c48493", |
00000291 => x"ffc00993", |
00000292 => x"008957b3", |
00000293 => x"00f7f793", |
00000294 => x"00f487b3", |
00000295 => x"0007c503", |
00000296 => x"ffc40413", |
00000297 => x"7b0000ef", |
00000298 => x"ff3414e3", |
00000299 => x"01c12083", |
00000300 => x"01812403", |
00000301 => x"01412483", |
00000302 => x"01012903", |
00000303 => x"00c12983", |
00000304 => x"02010113", |
00000305 => x"00008067", |
00000306 => x"fb010113", |
00000307 => x"04112623", |
00000308 => x"04512423", |
00000309 => x"04612223", |
00000310 => x"04712023", |
00000311 => x"02812e23", |
00000312 => x"02a12c23", |
00000313 => x"02b12a23", |
00000314 => x"02c12823", |
00000315 => x"02d12623", |
00000316 => x"02e12423", |
00000317 => x"02f12223", |
00000318 => x"03012023", |
00000319 => x"01112e23", |
00000320 => x"01c12c23", |
00000321 => x"01d12a23", |
00000322 => x"01e12823", |
00000323 => x"01f12623", |
00000324 => x"34202473", |
00000325 => x"800007b7", |
00000326 => x"00778793", |
00000327 => x"06f41a63", |
00000328 => x"00000513", |
00000329 => x"04d000ef", |
00000330 => x"64c000ef", |
00000331 => x"fe002783", |
00000332 => x"0027d793", |
00000333 => x"00a78533", |
00000334 => x"00f537b3", |
00000335 => x"00b785b3", |
00000336 => x"660000ef", |
00000337 => x"03c12403", |
00000338 => x"04c12083", |
00000339 => x"04812283", |
00000340 => x"04412303", |
00000341 => x"04012383", |
00000342 => x"03812503", |
00000343 => x"03412583", |
00000344 => x"03012603", |
00000345 => x"02c12683", |
00000346 => x"02812703", |
00000347 => x"02412783", |
00000348 => x"02012803", |
00000349 => x"01c12883", |
00000350 => x"01812e03", |
00000351 => x"01412e83", |
00000352 => x"01012f03", |
00000353 => x"00c12f83", |
00000354 => x"05010113", |
00000355 => x"30200073", |
00000356 => x"00700793", |
00000357 => x"00f41863", |
00000358 => x"8041a783", |
00000359 => x"00100513", |
00000360 => x"02079863", |
00000361 => x"ffff1537", |
00000362 => x"e3050513", |
00000363 => x"6d4000ef", |
00000364 => x"00040513", |
00000365 => x"ea5ff0ef", |
00000366 => x"ffff1537", |
00000367 => x"e3850513", |
00000368 => x"6c0000ef", |
00000369 => x"34102573", |
00000370 => x"e91ff0ef", |
00000371 => x"00500513", |
00000372 => x"e49ff0ef", |
00000373 => x"ff010113", |
00000374 => x"00000513", |
00000375 => x"00112623", |
00000376 => x"00812423", |
00000377 => x"734000ef", |
00000378 => x"09e00513", |
00000379 => x"770000ef", |
00000098 => x"00000613", |
00000099 => x"00000593", |
00000100 => x"00200513", |
00000101 => x"0087f463", |
00000102 => x"00400513", |
00000103 => x"319000ef", |
00000104 => x"00100513", |
00000105 => x"3b9000ef", |
00000106 => x"00005537", |
00000107 => x"00000593", |
00000108 => x"b0050513", |
00000109 => x"1f9000ef", |
00000110 => x"1b1000ef", |
00000111 => x"00245793", |
00000112 => x"00a78533", |
00000113 => x"00f537b3", |
00000114 => x"00b785b3", |
00000115 => x"1c9000ef", |
00000116 => x"ffff07b7", |
00000117 => x"4bc78793", |
00000118 => x"30579073", |
00000119 => x"08000793", |
00000120 => x"30479073", |
00000121 => x"30046073", |
00000122 => x"00000013", |
00000123 => x"00000013", |
00000124 => x"ffff1537", |
00000125 => x"e8850513", |
00000126 => x"265000ef", |
00000127 => x"f1302573", |
00000128 => x"24c000ef", |
00000129 => x"ffff1537", |
00000130 => x"ec050513", |
00000131 => x"251000ef", |
00000132 => x"fe002503", |
00000133 => x"238000ef", |
00000134 => x"ffff1537", |
00000135 => x"ec850513", |
00000136 => x"23d000ef", |
00000137 => x"fe402503", |
00000138 => x"224000ef", |
00000139 => x"ffff1537", |
00000140 => x"ed450513", |
00000141 => x"229000ef", |
00000142 => x"30102573", |
00000143 => x"210000ef", |
00000144 => x"ffff1537", |
00000145 => x"edc50513", |
00000146 => x"215000ef", |
00000147 => x"fe802503", |
00000148 => x"ffff14b7", |
00000149 => x"00341413", |
00000150 => x"1f4000ef", |
00000151 => x"ffff1537", |
00000152 => x"ee450513", |
00000153 => x"1f9000ef", |
00000154 => x"ff802503", |
00000155 => x"1e0000ef", |
00000156 => x"eec48513", |
00000157 => x"1e9000ef", |
00000158 => x"ff002503", |
00000159 => x"1d0000ef", |
00000160 => x"ffff1537", |
00000161 => x"ef850513", |
00000162 => x"1d5000ef", |
00000163 => x"ffc02503", |
00000164 => x"1bc000ef", |
00000165 => x"eec48513", |
00000166 => x"1c5000ef", |
00000167 => x"ff402503", |
00000168 => x"1ac000ef", |
00000169 => x"ffff1537", |
00000170 => x"f0050513", |
00000171 => x"1b1000ef", |
00000172 => x"0b9000ef", |
00000173 => x"00a404b3", |
00000174 => x"0084b433", |
00000175 => x"00b40433", |
00000176 => x"fa402783", |
00000177 => x"0207d263", |
00000178 => x"ffff1537", |
00000179 => x"f2850513", |
00000180 => x"18d000ef", |
00000181 => x"17d000ef", |
00000182 => x"02300793", |
00000183 => x"02f51263", |
00000184 => x"00000513", |
00000185 => x"0180006f", |
00000186 => x"081000ef", |
00000187 => x"fc85eae3", |
00000188 => x"00b41463", |
00000189 => x"fc9566e3", |
00000190 => x"00100513", |
00000191 => x"5dc000ef", |
00000192 => x"0b4000ef", |
00000193 => x"ffff1937", |
00000194 => x"ffff19b7", |
00000195 => x"02300a13", |
00000196 => x"07200a93", |
00000197 => x"06800b13", |
00000198 => x"07500b93", |
00000199 => x"ffff14b7", |
00000200 => x"ffff1c37", |
00000201 => x"f3490513", |
00000202 => x"135000ef", |
00000203 => x"115000ef", |
00000204 => x"00050413", |
00000205 => x"0fd000ef", |
00000206 => x"e4098513", |
00000207 => x"121000ef", |
00000208 => x"fb4400e3", |
00000209 => x"01541863", |
00000210 => x"ffff02b7", |
00000211 => x"00028067", |
00000212 => x"fd5ff06f", |
00000213 => x"01641663", |
00000214 => x"05c000ef", |
00000215 => x"fc9ff06f", |
00000216 => x"00000513", |
00000217 => x"03740063", |
00000218 => x"07300793", |
00000219 => x"00f41663", |
00000220 => x"67c000ef", |
00000221 => x"fb1ff06f", |
00000222 => x"06c00793", |
00000223 => x"00f41863", |
00000224 => x"00100513", |
00000225 => x"3fc000ef", |
00000226 => x"f9dff06f", |
00000227 => x"06500793", |
00000228 => x"00f41663", |
00000229 => x"02c000ef", |
00000230 => x"f8dff06f", |
00000231 => x"03f00793", |
00000232 => x"f3cc0513", |
00000233 => x"00f40463", |
00000234 => x"f5048513", |
00000235 => x"0b1000ef", |
00000236 => x"f75ff06f", |
00000237 => x"ffff1537", |
00000238 => x"d6450513", |
00000239 => x"0a10006f", |
00000240 => x"800007b7", |
00000241 => x"0007a783", |
00000242 => x"00079863", |
00000243 => x"ffff1537", |
00000244 => x"dc850513", |
00000245 => x"0890006f", |
00000246 => x"ff010113", |
00000247 => x"00112623", |
00000248 => x"30047073", |
00000249 => x"00000013", |
00000250 => x"00000013", |
00000251 => x"ffff1537", |
00000252 => x"de450513", |
00000253 => x"069000ef", |
00000254 => x"fa002783", |
00000255 => x"fe07cee3", |
00000256 => x"ff002783", |
00000257 => x"00078067", |
00000258 => x"0000006f", |
00000259 => x"ff010113", |
00000260 => x"00812423", |
00000261 => x"00050413", |
00000262 => x"ffff1537", |
00000263 => x"df450513", |
00000264 => x"00112623", |
00000265 => x"039000ef", |
00000266 => x"03040513", |
00000267 => x"0ff57513", |
00000268 => x"001000ef", |
00000269 => x"30047073", |
00000270 => x"00000013", |
00000271 => x"00000013", |
00000272 => x"00100513", |
00000273 => x"119000ef", |
00000274 => x"0000006f", |
00000275 => x"fe010113", |
00000276 => x"01212823", |
00000277 => x"00050913", |
00000278 => x"ffff1537", |
00000279 => x"00912a23", |
00000280 => x"e0c50513", |
00000281 => x"ffff14b7", |
00000282 => x"00812c23", |
00000283 => x"01312623", |
00000284 => x"00112e23", |
00000285 => x"01c00413", |
00000286 => x"7e4000ef", |
00000287 => x"f5c48493", |
00000288 => x"ffc00993", |
00000289 => x"008957b3", |
00000290 => x"00f7f793", |
00000291 => x"00f487b3", |
00000292 => x"0007c503", |
00000293 => x"ffc40413", |
00000294 => x"798000ef", |
00000295 => x"ff3414e3", |
00000296 => x"01c12083", |
00000297 => x"01812403", |
00000298 => x"01412483", |
00000299 => x"01012903", |
00000300 => x"00c12983", |
00000301 => x"02010113", |
00000302 => x"00008067", |
00000303 => x"fb010113", |
00000304 => x"04112623", |
00000305 => x"04512423", |
00000306 => x"04612223", |
00000307 => x"04712023", |
00000308 => x"02812e23", |
00000309 => x"02a12c23", |
00000310 => x"02b12a23", |
00000311 => x"02c12823", |
00000312 => x"02d12623", |
00000313 => x"02e12423", |
00000314 => x"02f12223", |
00000315 => x"03012023", |
00000316 => x"01112e23", |
00000317 => x"01c12c23", |
00000318 => x"01d12a23", |
00000319 => x"01e12823", |
00000320 => x"01f12623", |
00000321 => x"34202473", |
00000322 => x"800007b7", |
00000323 => x"00778793", |
00000324 => x"06f41a63", |
00000325 => x"00000513", |
00000326 => x"029000ef", |
00000327 => x"64c000ef", |
00000328 => x"fe002783", |
00000329 => x"0027d793", |
00000330 => x"00a78533", |
00000331 => x"00f537b3", |
00000332 => x"00b785b3", |
00000333 => x"660000ef", |
00000334 => x"03c12403", |
00000335 => x"04c12083", |
00000336 => x"04812283", |
00000337 => x"04412303", |
00000338 => x"04012383", |
00000339 => x"03812503", |
00000340 => x"03412583", |
00000341 => x"03012603", |
00000342 => x"02c12683", |
00000343 => x"02812703", |
00000344 => x"02412783", |
00000345 => x"02012803", |
00000346 => x"01c12883", |
00000347 => x"01812e03", |
00000348 => x"01412e83", |
00000349 => x"01012f03", |
00000350 => x"00c12f83", |
00000351 => x"05010113", |
00000352 => x"30200073", |
00000353 => x"00700793", |
00000354 => x"00f41863", |
00000355 => x"8041a783", |
00000356 => x"00100513", |
00000357 => x"02079863", |
00000358 => x"ffff1537", |
00000359 => x"e0050513", |
00000360 => x"6bc000ef", |
00000361 => x"00040513", |
00000362 => x"ea5ff0ef", |
00000363 => x"ffff1537", |
00000364 => x"e0850513", |
00000365 => x"6a8000ef", |
00000366 => x"34102573", |
00000367 => x"e91ff0ef", |
00000368 => x"00500513", |
00000369 => x"e49ff0ef", |
00000370 => x"ff010113", |
00000371 => x"00000513", |
00000372 => x"00112623", |
00000373 => x"00812423", |
00000374 => x"710000ef", |
00000375 => x"09e00513", |
00000376 => x"74c000ef", |
00000377 => x"00000513", |
00000378 => x"744000ef", |
00000379 => x"00050413", |
00000380 => x"00000513", |
00000381 => x"768000ef", |
00000382 => x"00050413", |
00000383 => x"00000513", |
00000384 => x"738000ef", |
00000385 => x"00c12083", |
00000386 => x"0ff47513", |
00000387 => x"00812403", |
00000388 => x"01010113", |
00000389 => x"00008067", |
00000390 => x"ff010113", |
00000391 => x"00112623", |
00000392 => x"00812423", |
00000393 => x"00000513", |
00000394 => x"6f0000ef", |
00000395 => x"00500513", |
00000396 => x"72c000ef", |
00000397 => x"00000513", |
00000398 => x"724000ef", |
00000399 => x"00050413", |
00000400 => x"00147413", |
00000401 => x"00000513", |
00000402 => x"6f0000ef", |
00000403 => x"fc041ce3", |
00000404 => x"00c12083", |
00000405 => x"00812403", |
00000406 => x"01010113", |
00000407 => x"00008067", |
00000408 => x"ff010113", |
00000409 => x"00000513", |
00000410 => x"00112623", |
00000411 => x"6ac000ef", |
00000412 => x"00600513", |
00000413 => x"6e8000ef", |
00000414 => x"00c12083", |
00000415 => x"00000513", |
00000416 => x"01010113", |
00000417 => x"6b40006f", |
00000418 => x"ff010113", |
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00000986 => x"46454443", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
113,8 → 113,8
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(7 downto 0) |
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(15 downto 0) |
); |
end neorv32_cpu; |
|
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
89,8 → 89,8
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(7 downto 0); |
firq_ack_o : out std_ulogic_vector(7 downto 0); |
firq_i : in std_ulogic_vector(15 downto 0); |
firq_ack_o : out std_ulogic_vector(15 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- physical memory protection -- |
214,7 → 214,7
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); |
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer |
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0); |
firq_sync : std_ulogic_vector(7 downto 0); |
firq_sync : std_ulogic_vector(15 downto 0); |
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer |
exc_ack : std_ulogic; -- acknowledge all exceptions |
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt |
277,7 → 277,7
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mie_firqe : std_ulogic_vector(7 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
-- |
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode |
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode |
1189,7 → 1189,7
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') or (decode_aux.is_atomic_sc = '1') then -- load / load-reservate / store conditional |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
end if; |
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment |
atomic_ctrl.env_end <= not decode_aux.is_atomic_lr; -- normal end of LOCKED (atomic) memory access environment - if we are not starting it via LR instruction |
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
1603,17 → 1603,11
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c))); |
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c))); |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c))); |
-- interrupt buffer: custom fast interrupts |
-- interrupt buffer: NEORV32-specific fast interrupts |
trap_ctrl.firq_sync <= firq_i; |
-- |
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or trap_ctrl.firq_sync(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c))); |
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or trap_ctrl.firq_sync(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c))); |
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or trap_ctrl.firq_sync(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c))); |
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or trap_ctrl.firq_sync(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c))); |
trap_ctrl.irq_buf(interrupt_firq_4_c) <= csr.mie_firqe(4) and (trap_ctrl.irq_buf(interrupt_firq_4_c) or trap_ctrl.firq_sync(4)) and (not (trap_ctrl.irq_ack(interrupt_firq_4_c) or csr.mip_clear(interrupt_firq_4_c))); |
trap_ctrl.irq_buf(interrupt_firq_5_c) <= csr.mie_firqe(5) and (trap_ctrl.irq_buf(interrupt_firq_5_c) or trap_ctrl.firq_sync(5)) and (not (trap_ctrl.irq_ack(interrupt_firq_5_c) or csr.mip_clear(interrupt_firq_5_c))); |
trap_ctrl.irq_buf(interrupt_firq_6_c) <= csr.mie_firqe(6) and (trap_ctrl.irq_buf(interrupt_firq_6_c) or trap_ctrl.firq_sync(6)) and (not (trap_ctrl.irq_ack(interrupt_firq_6_c) or csr.mip_clear(interrupt_firq_6_c))); |
trap_ctrl.irq_buf(interrupt_firq_7_c) <= csr.mie_firqe(7) and (trap_ctrl.irq_buf(interrupt_firq_7_c) or trap_ctrl.firq_sync(7)) and (not (trap_ctrl.irq_ack(interrupt_firq_7_c) or csr.mip_clear(interrupt_firq_7_c))); |
for i in 0 to 15 loop |
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or trap_ctrl.firq_sync(i)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c+i) or csr.mip_clear(interrupt_firq_0_c+i))); |
end loop; |
-- trap control -- |
if (trap_ctrl.env_start = '0') then -- no started trap handler |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected! |
1642,7 → 1636,7
csr.mip_status <= trap_ctrl.irq_buf; |
|
-- acknowledge mask output -- |
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_7_c downto interrupt_firq_0_c); |
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_15_c downto interrupt_firq_0_c); |
|
|
-- Trap Priority Encoder ------------------------------------------------------------------ |
1712,7 → 1706,47
trap_ctrl.cause_nxt <= trap_firq7_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_7_c) <= '1'; |
|
-- interrupt: 1.24 fast interrupt channel 8 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_8_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq8_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_8_c) <= '1'; |
|
-- interrupt: 1.25 fast interrupt channel 9 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_9_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq9_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_9_c) <= '1'; |
|
-- interrupt: 1.26 fast interrupt channel 10 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_10_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq10_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_10_c) <= '1'; |
|
-- interrupt: 1.27 fast interrupt channel 11 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_11_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq11_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_11_c) <= '1'; |
|
-- interrupt: 1.28 fast interrupt channel 12 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_12_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq12_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_12_c) <= '1'; |
|
-- interrupt: 1.29 fast interrupt channel 13 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_13_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq13_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_13_c) <= '1'; |
|
-- interrupt: 1.30 fast interrupt channel 14 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_14_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq14_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_14_c) <= '1'; |
|
-- interrupt: 1.31 fast interrupt channel 15 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq15_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_15_c) <= '1'; |
|
|
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions) |
-- here we do not need a specific acknowledge mask since only one exception (the one |
-- with highest priority) is evaluated at once |
1886,15 → 1920,9
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable |
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable |
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable |
-- |
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0 |
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1 |
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2 |
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3 |
csr.mie_firqe(4) <= csr.wdata(20); -- fast interrupt channel 4 |
csr.mie_firqe(5) <= csr.wdata(21); -- fast interrupt channel 5 |
csr.mie_firqe(6) <= csr.wdata(22); -- fast interrupt channel 6 |
csr.mie_firqe(7) <= csr.wdata(22); -- fast interrupt channel 7 |
for i in 0 to 15 loop -- fast interrupt channels 0..15 |
csr.mie_firqe(i) <= csr.wdata(16+i); |
end loop; -- i |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
1919,15 → 1947,9
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03); |
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07); |
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11); |
-- |
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16); |
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17); |
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18); |
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19); |
csr.mip_clear(interrupt_firq_4_c) <= not csr.wdata(20); |
csr.mip_clear(interrupt_firq_5_c) <= not csr.wdata(21); |
csr.mip_clear(interrupt_firq_6_c) <= not csr.wdata(22); |
csr.mip_clear(interrupt_firq_7_c) <= not csr.wdata(23); |
for i in 0 to 15 loop -- fast interrupt channels 0..15 |
csr.mip_clear(interrupt_firq_0_c+i) <= not csr.wdata(16+i); |
end loop; -- i |
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers -- |
-- -------------------------------------------------------------------- |
2235,15 → 2257,9
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable |
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable |
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable |
-- |
csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0 |
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1 |
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2 |
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3 |
csr.rdata(20) <= csr.mie_firqe(4); -- fast interrupt channel 4 |
csr.rdata(21) <= csr.mie_firqe(5); -- fast interrupt channel 5 |
csr.rdata(22) <= csr.mie_firqe(6); -- fast interrupt channel 6 |
csr.rdata(23) <= csr.mie_firqe(7); -- fast interrupt channel 7 |
for i in 0 to 15 loop -- fast interrupt channels 0..15 enable |
csr.rdata(16+i) <= csr.mie_firqe(i); |
end loop; -- i |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
2265,15 → 2281,9
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c); |
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c); |
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c); |
-- |
csr.rdata(16) <= csr.mip_status(interrupt_firq_0_c); |
csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c); |
csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c); |
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c); |
csr.rdata(20) <= csr.mip_status(interrupt_firq_4_c); |
csr.rdata(21) <= csr.mip_status(interrupt_firq_5_c); |
csr.rdata(22) <= csr.mip_status(interrupt_firq_6_c); |
csr.rdata(23) <= csr.mip_status(interrupt_firq_7_c); |
for i in 0 to 15 loop -- fast interrupt channels 0..15 pending |
csr.rdata(16+i) <= csr.mip_status(interrupt_firq_0_c+i); |
end loop; -- i |
|
-- physical memory protection - configuration -- |
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0 |
/neorv32/trunk/rtl/core/neorv32_package.vhd
57,10 → 57,10
-- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle! |
constant pmp_num_regions_critical_c : natural := 8; |
|
-- Architecture Constants (do not modify!)= ----------------------------------------------- |
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050009"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050100"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW |
678,31 → 678,39
|
-- Trap ID Codes -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- RISC-V compliant exceptions -- |
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault |
constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode |
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode |
-- RISC-V compliant interrupts -- |
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt |
-- NEORV32-specific (custom) interrupts -- |
constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: hardware reset |
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3 |
constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4 |
constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5 |
constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6 |
constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7 |
-- RISC-V compliant sync. exceptions -- |
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault |
constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode |
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode |
-- RISC-V compliant interrupts (async. exceptions) -- |
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt |
-- NEORV32-specific (custom) interrupts (async. exceptions) -- |
constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: hardware reset |
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3 |
constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4 |
constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5 |
constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6 |
constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7 |
constant trap_firq8_c : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8 |
constant trap_firq9_c : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9 |
constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10 |
constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11 |
constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12 |
constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13 |
constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14 |
constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15 |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
731,8 → 739,16
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5 |
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6 |
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7 |
constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8 |
constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9 |
constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10 |
constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11 |
constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12 |
constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13 |
constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14 |
constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15 |
-- |
constant interrupt_width_c : natural := 11; -- length of this list in bits |
constant interrupt_width_c : natural := 19; -- length of this list in bits |
|
-- CPU Privilege Modes -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
863,7 → 879,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
934,8 → 950,8
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(7 downto 0) |
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(15 downto 0) |
); |
end component; |
|
985,8 → 1001,8
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(7 downto 0); |
firq_ack_o : out std_ulogic_vector(7 downto 0); |
firq_i : in std_ulogic_vector(15 downto 0); |
firq_ack_o : out std_ulogic_vector(15 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- physical memory protection -- |
1401,7 → 1417,8
uart_txd_o : out std_ulogic; |
uart_rxd_i : in std_ulogic; |
-- interrupts -- |
uart_irq_o : out std_ulogic -- uart rx/tx interrupt |
irq_rxd_o : out std_ulogic; -- uart data received interrupt |
irq_txd_o : out std_ulogic -- uart transmission done interrupt |
); |
end component; |
|
1426,7 → 1443,7
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- interrupt -- |
spi_irq_o : out std_ulogic -- transmission done interrupt |
irq_o : out std_ulogic -- transmission done interrupt |
); |
end component; |
|
1449,7 → 1466,7
twi_sda_io : inout std_logic; -- serial data line |
twi_scl_io : inout std_logic; -- serial clock line |
-- interrupt -- |
twi_irq_o : out std_ulogic -- transfer done IRQ |
irq_o : out std_ulogic -- transfer done IRQ |
); |
end component; |
|
/neorv32/trunk/rtl/core/neorv32_spi.vhd
7,7 → 7,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
62,7 → 62,7
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- interrupt -- |
spi_irq_o : out std_ulogic -- transmission done interrupt |
irq_o : out std_ulogic -- transmission done interrupt |
); |
end neorv32_spi; |
|
89,7 → 89,6
constant ctrl_spi_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2 |
constant ctrl_spi_size0_c : natural := 13; -- r/w: data size (00: 8-bit, 01: 16-bit) |
constant ctrl_spi_size1_c : natural := 14; -- r/w: data size (10: 24-bit, 11: 32-bit) |
constant ctrl_spi_irq_en_c : natural := 15; -- r/w: spi transmission done interrupt enable |
-- |
constant ctrl_spi_busy_c : natural := 31; -- r/-: spi transceiver is busy |
|
100,7 → 99,7
signal rden : std_ulogic; -- read enable |
|
-- accessible regs -- |
signal ctrl : std_ulogic_vector(15 downto 0); |
signal ctrl : std_ulogic_vector(14 downto 0); |
signal tx_data_reg : std_ulogic_vector(31 downto 0); |
signal rx_data : std_ulogic_vector(31 downto 0); |
|
166,7 → 165,6
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c); |
data_o(ctrl_spi_size0_c) <= ctrl(ctrl_spi_size0_c); |
data_o(ctrl_spi_size1_c) <= ctrl(ctrl_spi_size1_c); |
data_o(ctrl_spi_irq_en_c) <= ctrl(ctrl_spi_irq_en_c); |
-- |
data_o(ctrl_spi_busy_c) <= spi_busy; |
else -- spi_rtx_addr_c |
199,7 → 197,7
spi_sdi_ff1 <= spi_sdi_ff0; |
|
-- serial engine -- |
spi_irq_o <= '0'; |
irq_o <= '0'; |
if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled |
-- -------------------------------------------------------------- |
spi_bitcnt <= (others => '0'); |
247,7 → 245,7
if (spi_bitcnt = spi_bitcnt_max) then |
spi_state0 <= '0'; |
spi_busy <= '0'; |
spi_irq_o <= ctrl(ctrl_spi_irq_en_c); |
irq_o <= '1'; |
end if; |
end if; |
end if; |
/neorv32/trunk/rtl/core/neorv32_top.vhd
136,7 → 136,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
233,16 → 233,19
signal sysinfo_ack : std_ulogic; |
|
-- IRQs -- |
signal mtime_irq : std_ulogic; |
signal mtime_irq : std_ulogic; |
-- |
signal fast_irq : std_ulogic_vector(7 downto 0); |
signal fast_irq_ack : std_ulogic_vector(7 downto 0); |
signal fast_irq : std_ulogic_vector(15 downto 0); |
signal fast_irq_ack : std_ulogic_vector(15 downto 0); |
-- |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart_irq : std_ulogic; |
signal uart_rxd_irq : std_ulogic; |
signal uart_txd_irq : std_ulogic; |
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
signal cfs_irq : std_ulogic; |
signal cfs_irq_ack : std_ulogic; |
|
-- misc -- |
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME |
412,17 → 415,29
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- fast interrupts - processor-internal -- |
fast_irq(0) <= wdt_irq; -- highest priority, watchdog timeout interrupt |
fast_irq(1) <= gpio_irq or cfs_irq; -- GPIO input pin-change interrupt or custom CFS interrupt |
fast_irq(2) <= uart_irq; -- UART TX done or RX complete interrupt |
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI |
-- fast interrupts - platform level (for cutsom use) -- |
fast_irq(4) <= soc_firq_i(0); |
fast_irq(5) <= soc_firq_i(1); |
fast_irq(6) <= soc_firq_i(2); |
fast_irq(7) <= soc_firq_i(3); |
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout |
fast_irq(01) <= '0'; -- reserved |
fast_irq(02) <= cfs_irq; -- custom functions subsystem |
fast_irq(03) <= uart_rxd_irq; -- UART data received |
fast_irq(04) <= uart_txd_irq; -- UART transmission done |
fast_irq(05) <= spi_irq; -- SPI transmission done |
fast_irq(06) <= twi_irq; -- TWI transmission done |
fast_irq(07) <= gpio_irq; -- GPIO pin-change |
|
-- fast interrupts - platform level (for custom use) -- |
fast_irq(08) <= soc_firq_i(0); |
fast_irq(09) <= soc_firq_i(1); |
fast_irq(10) <= soc_firq_i(2); |
fast_irq(11) <= soc_firq_i(3); |
fast_irq(12) <= soc_firq_i(4); |
fast_irq(13) <= soc_firq_i(5); |
fast_irq(14) <= soc_firq_i(6); |
fast_irq(15) <= soc_firq_i(7); |
|
-- IRQ acknowledge -- |
cfs_irq_ack <= fast_irq_ack(2); |
|
|
-- CPU Instruction Cache ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_icache_inst_true: |
720,7 → 735,7
sleep_i => cpu_sleep, -- set if cpu is in sleep mode |
-- interrupt -- |
irq_o => cfs_irq, -- interrupt request |
irq_ack_i => fast_irq_ack(1), -- interrupt acknowledge |
irq_ack_i => cfs_irq_ack, -- interrupt acknowledge |
-- custom io (conduit) -- |
cfs_in_i => cfs_in_i, -- custom inputs |
cfs_out_o => cfs_out_o -- custom outputs |
841,31 → 856,33
neorv32_uart_inst: neorv32_uart |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => uart_cg_en, -- enable clock generator |
clkgen_en_o => uart_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
uart_txd_o => uart_txd_o, |
uart_rxd_i => uart_rxd_i, |
-- interrupts -- |
uart_irq_o => uart_irq -- uart rx/tx interrupt |
irq_rxd_o => uart_rxd_irq, -- uart data received interrupt |
irq_txd_o => uart_txd_irq -- uart transmission done interrupt |
); |
end generate; |
|
neorv32_uart_inst_false: |
if (IO_UART_EN = false) generate |
uart_rdata <= (others => '0'); |
uart_ack <= '0'; |
uart_txd_o <= '0'; |
uart_cg_en <= '0'; |
uart_irq <= '0'; |
uart_rdata <= (others => '0'); |
uart_ack <= '0'; |
uart_txd_o <= '0'; |
uart_cg_en <= '0'; |
uart_rxd_irq <= '0'; |
uart_txd_irq <= '0'; |
end generate; |
|
|
892,7 → 909,7
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out |
spi_csn_o => spi_csn_o, -- SPI CS |
-- interrupt -- |
spi_irq_o => spi_irq -- transmission done interrupt |
irq_o => spi_irq -- transmission done interrupt |
); |
end generate; |
|
929,7 → 946,7
twi_sda_io => twi_sda_io, -- serial data line |
twi_scl_io => twi_scl_io, -- serial clock line |
-- interrupt -- |
twi_irq_o => twi_irq -- transfer done IRQ |
irq_o => twi_irq -- transfer done IRQ |
); |
end generate; |
|
/neorv32/trunk/rtl/core/neorv32_twi.vhd
7,7 → 7,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
60,7 → 60,7
twi_sda_io : inout std_logic; -- serial data line |
twi_scl_io : inout std_logic; -- serial clock line |
-- interrupt -- |
twi_irq_o : out std_ulogic -- transfer done IRQ |
irq_o : out std_ulogic -- transfer done IRQ |
); |
end neorv32_twi; |
|
74,12 → 74,11
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable |
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition |
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition |
constant ctrl_twi_irq_en_c : natural := 3; -- r/w: Enable transmission done interrupt |
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0 |
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1 |
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2 |
constant ctrl_twi_mack_c : natural := 7; -- r/w: generate ACK by controller for transmission |
constant ctrl_twi_cksten_c : natural := 8; -- r/w: enable clock stretching by peripheral |
constant ctrl_twi_prsc0_c : natural := 3; -- r/w: CLK prsc bit 0 |
constant ctrl_twi_prsc1_c : natural := 4; -- r/w: CLK prsc bit 1 |
constant ctrl_twi_prsc2_c : natural := 5; -- r/w: CLK prsc bit 2 |
constant ctrl_twi_mack_c : natural := 6; -- r/w: generate ACK by controller for transmission |
constant ctrl_twi_cksten_c : natural := 7; -- r/w: enable clock stretching by peripheral |
-- |
constant ctrl_twi_ack_c : natural := 30; -- r/-: Set if ACK received |
constant ctrl_twi_busy_c : natural := 31; -- r/-: Set if TWI unit is busy |
99,7 → 98,7
signal twi_clk_halt : std_ulogic; |
|
-- twi transceiver core -- |
signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register |
signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register |
signal arbiter : std_ulogic_vector(2 downto 0); |
signal twi_bitcnt : std_ulogic_vector(3 downto 0); |
signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg |
137,7 → 136,6
if (rd_en = '1') then |
if (addr = twi_ctrl_addr_c) then |
data_o(ctrl_twi_en_c) <= ctrl(ctrl_twi_en_c); |
data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c); |
data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c); |
data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c); |
data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c); |
193,7 → 191,7
twi_scl_i_ff1 <= twi_scl_i_ff0; |
|
-- defaults -- |
twi_irq_o <= '0'; |
irq_o <= '0'; |
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated? |
|
-- serial engine -- |
259,7 → 257,7
|
if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay |
arbiter(1 downto 0) <= "00"; -- go back to IDLE |
twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled |
irq_o <= '1'; -- fire IRQ |
end if; |
|
when others => -- "0--" OFFLINE: TWI deactivated |
/neorv32/trunk/rtl/core/neorv32_uart.vhd
15,7 → 15,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
69,7 → 69,8
uart_txd_o : out std_ulogic; |
uart_rxd_i : in std_ulogic; |
-- interrupts -- |
uart_irq_o : out std_ulogic -- uart rx/tx interrupt |
irq_rxd_o : out std_ulogic; -- uart data received interrupt |
irq_txd_o : out std_ulogic -- uart transmission done interrupt |
); |
end neorv32_uart; |
|
111,8 → 112,6
constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2 |
-- |
constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable |
constant ctrl_uart_rx_irq_c : natural := 29; -- r/w: UART rx done interrupt enable |
constant ctrl_uart_tx_irq_c : natural := 30; -- r/w: UART tx done interrupt enable |
constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy |
|
-- data register flags -- |
183,8 → 182,6
ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c); |
ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c); |
ctrl(ctrl_uart_en_c) <= data_i(ctrl_uart_en_c); |
ctrl(ctrl_uart_rx_irq_c) <= data_i(ctrl_uart_rx_irq_c); |
ctrl(ctrl_uart_tx_irq_c) <= data_i(ctrl_uart_tx_irq_c); |
end if; |
end if; |
-- read access -- |
196,8 → 193,6
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c); |
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c); |
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c); |
data_o(ctrl_uart_rx_irq_c) <= ctrl(ctrl_uart_rx_irq_c); |
data_o(ctrl_uart_tx_irq_c) <= ctrl(ctrl_uart_tx_irq_c); |
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy; |
else -- uart_rtx_addr_c |
data_o(data_rx_avail_c) <= uart_rx.avail(0); |
317,8 → 312,10
|
-- Interrupt ------------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
-- UART Rx data available [OR] UART Tx complete |
uart_irq_o <= (uart_rx.busy_ff and (not uart_rx.busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx.done and ctrl(ctrl_uart_tx_irq_c)); |
-- UART Rx data available |
irq_rxd_o <= uart_rx.busy_ff and (not uart_rx.busy); |
-- UART Tx complete |
irq_txd_o <= uart_tx.done; |
|
|
-- SIMULATION Output ---------------------------------------------------------------------- |
/neorv32/trunk/rtl/top_templates/neorv32_top_axi4lite.vhd
139,7 → 139,7
cfs_in_i : in std_logic_vector(31 downto 0); -- custom inputs |
cfs_out_o : out std_logic_vector(31 downto 0); -- custom outputs |
-- Interrupts -- |
soc_firq_i : in std_logic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_logic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
mext_irq_i : in std_logic := '0' -- machine external interrupt |
172,7 → 172,7
signal cfs_in_i_int : std_ulogic_vector(31 downto 0); |
signal cfs_out_o_int : std_ulogic_vector(31 downto 0); |
-- |
signal soc_firq_i_int : std_ulogic_vector(3 downto 0); |
signal soc_firq_i_int : std_ulogic_vector(7 downto 0); |
signal mtime_irq_i_int : std_ulogic; |
signal msw_irq_i_int : std_ulogic; |
signal mext_irq_i_int : std_ulogic; |
/neorv32/trunk/rtl/top_templates/neorv32_top_stdlogic.vhd
130,7 → 130,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_logic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_logic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
mext_irq_i : in std_logic := '0' -- machine external interrupt |
180,7 → 180,7
-- |
signal mtime_i_int : std_ulogic_vector(63 downto 0); |
-- |
signal soc_firq_i_int : std_ulogic_vector(3 downto 0); |
signal soc_firq_i_int : std_ulogic_vector(7 downto 0); |
signal mtime_irq_i_int : std_ulogic; |
signal msw_irq_i_int : std_ulogic; |
signal mext_irq_i_int : std_ulogic; |
/neorv32/trunk/sim/neorv32_tb.vhd
108,7 → 108,7
|
-- irq -- |
signal msi_ring, mei_ring : std_ulogic; |
signal soc_firq_ring : std_ulogic_vector(3 downto 0); |
signal soc_firq_ring : std_ulogic_vector(7 downto 0); |
|
-- Wishbone bus -- |
type wishbone_t is record |
168,7 → 168,7
rst_gen <= '0', '1' after 60*(t_clock_c/2); |
|
|
-- CPU Core ------------------------------------------------------------------------------- |
-- The Core of the Problem ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_top_inst: neorv32_top |
generic map ( |
500,19 → 500,23
if rising_edge(clk_gen) then |
-- bus interface -- |
wb_irq.rdata <= (others => '0'); |
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we; |
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel); |
wb_irq.err <= '0'; |
-- trigger IRQ using CSR.MIE bit layout -- |
msi_ring <= '0'; |
mei_ring <= '0'; |
soc_firq_ring <= (others => '0'); |
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we) = '1') then |
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then |
msi_ring <= wb_irq.wdata(03); -- machine software interrupt |
mei_ring <= wb_irq.wdata(11); -- machine software interrupt |
soc_firq_ring(0) <= wb_irq.wdata(20); -- fast interrupt channel 4 |
soc_firq_ring(1) <= wb_irq.wdata(21); -- fast interrupt channel 5 |
soc_firq_ring(2) <= wb_irq.wdata(22); -- fast interrupt channel 6 |
soc_firq_ring(3) <= wb_irq.wdata(22); -- fast interrupt channel 7 |
soc_firq_ring(0) <= wb_irq.wdata(24); -- fast interrupt SoC channel 0 |
soc_firq_ring(1) <= wb_irq.wdata(25); -- fast interrupt SoC channel 1 |
soc_firq_ring(2) <= wb_irq.wdata(26); -- fast interrupt SoC channel 2 |
soc_firq_ring(3) <= wb_irq.wdata(27); -- fast interrupt SoC channel 3 |
soc_firq_ring(4) <= wb_irq.wdata(28); -- fast interrupt SoC channel 4 |
soc_firq_ring(5) <= wb_irq.wdata(29); -- fast interrupt SoC channel 5 |
soc_firq_ring(6) <= wb_irq.wdata(30); -- fast interrupt SoC channel 6 |
soc_firq_ring(7) <= wb_irq.wdata(31); -- fast interrupt SoC channel 7 |
end if; |
end if; |
end process irq_trigger; |
/neorv32/trunk/sw/bootloader/bootloader.c
204,12 → 204,12
// get clock speed (in Hz) |
uint32_t clock_speed = SYSINFO_CLK; |
|
// init SPI for 8-bit, clock-mode 0, no interrupt |
// init SPI for 8-bit, clock-mode 0 |
if (clock_speed < 40000000) { |
neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0, 0); |
neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0); |
} |
else { |
neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0); |
neorv32_spi_setup(CLK_PRSC_128, 0, 0); |
} |
|
if (STATUS_LED_EN == 1) { |
217,8 → 217,8
neorv32_gpio_port_set(1 << STATUS_LED); |
} |
|
// init UART (no parity bit, no interrupts) |
neorv32_uart_setup(BAUD_RATE, 0, 0, 0); |
// init UART (no parity bit) |
neorv32_uart_setup(BAUD_RATE, 0); |
|
// Configure machine system timer interrupt for ~2Hz |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4)); |
/neorv32/trunk/sw/example/bit_manipulation/main.c
75,8 → 75,8
// capture all exceptions and give debug info via UART |
neorv32_rte_setup(); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// intro |
neorv32_uart_printf("NEORV32 Bit Manipulation (B.Zbb) Extension Test\n\n"); |
/neorv32/trunk/sw/example/blink_led/main.c
73,8 → 73,8
**************************************************************************/ |
int main() { |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check if GPIO unit is implemented at all |
if (neorv32_gpio_available() == 0) { |
/neorv32/trunk/sw/example/coremark/core_portme.c
151,7 → 151,7
/* NEORV32-specific */ |
neorv32_cpu_dint(); // no interrupt, thanks |
neorv32_rte_setup(); // capture all exceptions and give debug information |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); // init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00); // init UART at default baud rate, no parity bits |
|
|
// Disable coremark compilation by default |
/neorv32/trunk/sw/example/cpu_test/main.c
104,12 → 104,14
**************************************************************************/ |
int main() { |
|
volatile uint64_t temp64; |
register uint32_t tmp_a, tmp_b; |
volatile uint32_t dummy_dst __attribute__((unused)); |
uint8_t id; |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// Disable cpu_test compilation by default |
#ifndef RUN_CPUTEST |
141,13 → 143,12
neorv32_cpu_set_minstret(0); |
neorv32_cpu_set_mcycle(0); |
|
// enable performance counter auto increment |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable performance counter auto increment (ALL counters) |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code to standard counters only |
|
neorv32_mtime_set_time(0); |
// set CMP of machine system timer MTIME to max to prevent an IRQ |
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFUL; |
uint64_t mtime_cmp_max = 0xffffffffffffffffULL; |
neorv32_mtime_set_timecmp(mtime_cmp_max); |
|
|
171,28 → 172,10
neorv32_rte_setup(); // this will install a full-detailed debug handler for all traps |
|
int install_err = 0; |
// here we are overriding the default debug handlers |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_BREAKPOINT, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_L_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_L_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_S_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_S_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_UENV_CALL, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MENV_CALL, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MTI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MSI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MEI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_0, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_2, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_3, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_4, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_5, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_6, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_7, global_trap_handler); |
// initialize ALL provided trap handler (overriding the default debug handlers) |
for (id=0; id<NEORV32_RTE_NUM_TRAPS; id++) { |
install_err += neorv32_rte_exception_install(id, global_trap_handler); |
} |
|
if (install_err) { |
neorv32_uart_printf("RTE install error (%i)!\n", install_err); |
200,23 → 183,11
} |
|
// enable interrupt sources |
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // machine external interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // fast interrupt channel 0 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // fast interrupt channel 1 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // fast interrupt channel 2 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // fast interrupt channel 3 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E); // fast interrupt channel 4 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E); // fast interrupt channel 5 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E); // fast interrupt channel 6 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E); // fast interrupt channel 7 |
neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt |
neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt |
neorv32_cpu_irq_enable(CSR_MIE_MEIE); // machine external interrupt |
// enable FAST IRQ sources only where actually needed |
|
if (install_err) { |
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err); |
return 0; |
} |
|
// test intro |
neorv32_uart_printf("\nStarting tests...\n\n"); |
|
233,7 → 204,7
cnt_test++; |
|
// get current cycle counter |
tmp_a = neorv32_cpu_get_cycle(); |
temp64 = neorv32_cpu_get_cycle(); |
|
// wait some time to have a nice increment |
asm volatile ("nop"); |
240,8 → 211,7
asm volatile ("nop"); |
|
// make sure cycle counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_cycle() > tmp_a) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
if ((neorv32_cpu_get_cycle() > temp64) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
258,7 → 228,7
cnt_test++; |
|
// get current instruction counter |
tmp_a = neorv32_cpu_get_instret(); |
temp64 = neorv32_cpu_get_instret(); |
|
// wait some time to have a nice increment |
asm volatile ("nop"); |
265,7 → 235,7
asm volatile ("nop"); |
|
// make sure instruction counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_instret() > tmp_a) && |
if ((neorv32_cpu_get_instret() > temp64) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
958,11 → 928,14
// Fast interrupt channel 0 (WDT) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ0 (fast interrupt 0) test (via WDT): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ0 test (via WDT): ", cnt_test); |
|
if (neorv32_wdt_available()) { |
cnt_test++; |
|
// enable fast interrupt |
neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); |
|
// configure WDT |
neorv32_wdt_setup(CLK_PRSC_4096, 0, 1); // highest clock prescaler, trigger IRQ on timeout, lock access |
WDT_CT = 0; // try to deactivate WDT (should fail as access is loced) |
981,6 → 954,9
|
// no more WDT interrupts |
neorv32_wdt_disable(); |
|
// disable fast interrupt |
neorv32_cpu_irq_disable(CSR_MIE_FIRQ0E); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
988,60 → 964,31
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 1 (GPIO) |
// Fast interrupt channel 1 (reserved) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ1 (fast interrupt 1) test (via GPIO): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ1 test (reserved): ", cnt_test); |
neorv32_uart_printf("skipped (not implemented)\n"); |
|
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation |
if (neorv32_gpio_available()) { |
cnt_test++; |
|
// clear output port |
neorv32_gpio_port_set(0); |
// ---------------------------------------------------------- |
// Fast interrupt channel 2 (CFS) |
// ---------------------------------------------------------- |
neorv32_uart_printf("[%i] FIRQ2 test (via CFS): ", cnt_test); |
neorv32_uart_printf("skipped (not implemented)\n"); |
|
// configure GPIO.in(31) for pin-change IRQ |
neorv32_gpio_pin_change_config(0x80000000); |
|
// trigger pin-change IRQ by setting GPIO.out(31) |
// the testbench connects GPIO.out => GPIO.in |
neorv32_gpio_pin_set(31); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_1) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
// disable GPIO pin-change IRQ |
neorv32_gpio_pin_change_config(0); |
|
// clear output port |
neorv32_gpio_port_set(0); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
} |
} |
else { |
neorv32_uart_printf("skipped (on real HW)\n"); |
} |
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 2 (UART) |
// Fast interrupt channel 3 (UART.RX) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ2 (fast interrupt 2) test (via UART): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ3 test (via UART.RX): ", cnt_test); |
|
if (neorv32_uart_available()) { |
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation |
cnt_test++; |
|
// enable fast interrupt |
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); |
|
// wait for UART to finish transmitting |
while(neorv32_uart_tx_busy()); |
|
1051,10 → 998,8
// disable UART sim_mode if it is enabled |
UART_CT &= ~(1 << UART_CT_SIM_MODE); |
|
// enable UART TX done IRQ |
UART_CT |= (1 << UART_CT_TX_IRQ); |
|
// trigger UART TX IRQ |
// trigger UART RX IRQ |
// the default test bench connects UART.TXD_O to UART_RXD_I |
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active |
|
// wait for UART to finish transmitting |
1064,37 → 1009,82
asm volatile("nop"); |
asm volatile("nop"); |
|
// wait for UART to finish transmitting |
while(neorv32_uart_tx_busy()); |
|
// re-enable UART sim_mode if it was enabled and disable UART TX done IRQ |
// re-enable UART sim_mode if it was enabled |
UART_CT = uart_ct_backup; |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_2) { |
// disable fast interrupt |
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (on real HW)\n"); |
} |
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 4 (UART.TX) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ4 test (via UART.TX): ", cnt_test); |
|
cnt_test++; |
|
// UART TX interrupt enable |
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E); |
|
// wait for UART to finish transmitting |
while(neorv32_uart_tx_busy()); |
|
// backup current UART configuration |
volatile uint32_t uart_ct_backup = UART_CT; |
|
// disable UART sim_mode if it is enabled |
UART_CT &= ~(1 << UART_CT_SIM_MODE); |
|
// trigger UART TX IRQ |
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active |
|
// wait for UART to finish transmitting |
while(neorv32_uart_tx_busy()); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
|
// re-enable UART sim_mode if it was enabled |
UART_CT = uart_ct_backup; |
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) { |
test_ok(); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 3 (SPI) |
// Fast interrupt channel 5 (SPI) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via SPI): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ5 test (via SPI): ", cnt_test); |
|
if (neorv32_spi_available()) { |
cnt_test++; |
|
// configure SPI, enable transfer-done IRQ |
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 1); |
// enable fast interrupt |
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E); |
|
// configure SPI |
neorv32_spi_setup(CLK_PRSC_2, 0, 0); |
|
// trigger SPI IRQ |
neorv32_spi_trans(0); |
while(neorv32_spi_busy()); // wait for current transfer to finish |
1103,7 → 1093,7
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) { |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) { |
test_ok(); |
} |
else { |
1112,6 → 1102,9
|
// disable SPI |
neorv32_spi_disable(); |
|
// disable fast interrupt |
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
1119,17 → 1112,19
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 3 (TWI) |
// Fast interrupt channel 6 (TWI) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via TWI): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ6 test (via TWI): ", cnt_test); |
|
if (neorv32_twi_available()) { |
cnt_test++; |
|
// configure TWI, fastest clock, transfer-done IRQ enable, disable peripheral clock stretching |
neorv32_twi_setup(CLK_PRSC_2, 1, 0); |
// configure TWI, fastest clock, no peripheral clock stretching |
neorv32_twi_setup(CLK_PRSC_2, 0); |
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E); |
|
// trigger TWI IRQ |
neorv32_twi_generate_start(); |
neorv32_twi_trans(0); |
1139,7 → 1134,7
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) { |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) { |
test_ok(); |
} |
else { |
1148,6 → 1143,7
|
// disable TWI |
neorv32_twi_disable(); |
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
1155,38 → 1151,105
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 4..7 (SoC fast IRQ) |
// Fast interrupt channel 7 (GPIO) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ4..7 (SoC fast interrupt 0..3, via testbench) test: ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ7 test (via GPIO): ", cnt_test); |
|
cnt_test++; |
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation |
if (neorv32_gpio_available()) { |
cnt_test++; |
|
// trigger all SoC Fast interrupts at once |
neorv32_cpu_dint(); // do not fire yet! |
sim_irq_trigger((1 << CSR_MIE_FIRQ4E) | (1 << CSR_MIE_FIRQ5E) | (1 << CSR_MIE_FIRQ6E) | (1 << CSR_MIE_FIRQ7E)); |
// clear output port |
neorv32_gpio_port_set(0); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E); |
|
// make sure all SoC FIRQs have been triggered |
tmp_a = (1 << CSR_MIP_FIRQ4P) | (1 << CSR_MIP_FIRQ5P) | (1 << CSR_MIP_FIRQ6P) | (1 << CSR_MIP_FIRQ7P); |
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) { |
neorv32_cpu_eint(); // allow IRQs to fire again |
asm volatile ("nop"); |
asm volatile ("nop"); // irq should kick in HERE |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) { // make sure FIRQ7 was last IRQ to be handled |
test_ok(); |
// configure GPIO.in(31) for pin-change IRQ |
neorv32_gpio_pin_change_config(0x80000000); |
|
// trigger pin-change IRQ by setting GPIO.out(31) |
// the testbench connects GPIO.out => GPIO.in |
neorv32_gpio_pin_set(31); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
// disable GPIO pin-change IRQ |
neorv32_gpio_pin_change_config(0); |
|
// clear output port |
neorv32_gpio_port_set(0); |
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E); |
} |
else { |
test_fail(); |
neorv32_uart_printf("skipped (not implemented)\n"); |
} |
} |
else { |
test_fail(); |
neorv32_uart_printf("skipped (on real HW)\n"); |
} |
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 8..15 (SoC fast IRQ 0..7) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ8..15 (SoC fast IRQ 0..7; via testbench) test: ", cnt_test); |
|
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation |
|
cnt_test++; |
|
// enable SOC FIRQs |
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) { |
neorv32_cpu_irq_enable(id); |
} |
|
// trigger all SoC Fast interrupts at once |
neorv32_cpu_dint(); // do not fire yet! |
sim_irq_trigger((1 << CSR_MIE_FIRQ8E) | (1 << CSR_MIE_FIRQ9E) | (1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) | |
(1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E)); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
|
// make sure all SoC FIRQs have been triggered |
tmp_a = (1 << CSR_MIP_FIRQ8P) | (1 << CSR_MIP_FIRQ9P) | (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) | |
(1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P); |
|
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) { |
neorv32_cpu_eint(); // allow IRQs to fire again |
asm volatile ("nop"); |
asm volatile ("nop"); // irq should kick in HERE |
|
tmp_a = neorv32_cpu_csr_read(CSR_MCAUSE); |
if ((tmp_a >= TRAP_CODE_FIRQ_8) && (tmp_a <= TRAP_CODE_FIRQ_15)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
|
// disable SOC FIRQs |
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) { |
neorv32_cpu_irq_disable(id); |
} |
} |
else { |
neorv32_uart_printf("skipped (on real HW)\n"); |
} |
|
neorv32_cpu_eint(); // re-enable IRQs globally |
|
|
1291,7 → 1354,7
// check if PMP is implemented |
if (neorv32_cpu_pmp_get_num_regions() != 0) { |
|
// Test access to protected region |
// Create PMP protected region |
// --------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
cnt_test++; |
/neorv32/trunk/sw/example/demo_freeRTOS/main.c
127,8 → 127,8
// clear GPIO.out port |
neorv32_gpio_port_set(0); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
231,8 → 231,8
#include <neorv32.h> |
int main() { |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n"); |
return 0; |
} |
/neorv32/trunk/sw/example/demo_gpio_irq/main.c
72,8 → 72,8
// setup run-time environment for interrupts and exceptions |
neorv32_rte_setup(); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/demo_pwm/main.c
73,8 → 73,8
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/demo_trng/main.c
75,8 → 75,8
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/demo_twi/main.c
83,8 → 83,8
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
104,8 → 104,8
neorv32_uart_printf("This program allows to create TWI transfers by hand.\n" |
"Type 'help' to see the help menu.\n\n"); |
|
// configure TWI, second slowest clock, no IRQ, no clock-stretching |
neorv32_twi_setup(CLK_PRSC_2048, 0, 0); |
// configure TWI, second slowest clock, no clock-stretching |
neorv32_twi_setup(CLK_PRSC_2048, 0); |
|
// no active bus session yet |
bus_claimed = 0; |
/neorv32/trunk/sw/example/demo_wdt/main.c
75,8 → 75,8
// this is not required, but keeps us safe |
neorv32_rte_setup(); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/game_of_life/main.c
97,8 → 97,8
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/hello_world/main.c
65,8 → 65,8
// this is not required, but keeps us safe |
neorv32_rte_setup(); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
/neorv32/trunk/sw/example/hex_viewer/main.c
81,9 → 81,11
// capture all exceptions and give debug info via UART |
neorv32_rte_setup(); |
|
// disable global interrupts |
neorv32_cpu_dint(); |
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
// init UART at default baud rate, no parity bits |
neorv32_uart_setup(BAUD_RATE, 0b00); |
|
// check available hardware extensions and compare with compiler flags |
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch |
229,11 → 231,11
cas_desired = (uint32_t)hexstr_to_uint(terminal_buffer, strlen(terminal_buffer)); |
|
// try to execute atomic compare-and-swap |
if (neorv32_cpu_atomic_cas(mem_address, cas_expected, cas_desired)) { |
neorv32_uart_printf("\nAtomic-CAS: Failed!\n"); |
if (neorv32_cpu_atomic_cas(mem_address, cas_expected, cas_desired) == 0) { |
neorv32_uart_printf("\nAtomic-CAS: Successful!\n"); |
} |
else { |
neorv32_uart_printf("\nAtomic-CAS: Successful!\n"); |
neorv32_uart_printf("\nAtomic-CAS: Failed!\n"); |
} |
} |
else { |
/neorv32/trunk/sw/lib/include/neorv32.h
366,17 → 366,26
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CSR_MIE_enum { |
CSR_MIE_MSIE = 3, /**< CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) */ |
CSR_MIE_MTIE = 7, /**< CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) */ |
CSR_MIE_MEIE = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */ |
CSR_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */ |
CSR_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */ |
CSR_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */ |
CSR_MIE_FIRQ3E = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */ |
CSR_MIE_FIRQ4E = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */ |
CSR_MIE_FIRQ5E = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */ |
CSR_MIE_FIRQ6E = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */ |
CSR_MIE_FIRQ7E = 23 /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */ |
CSR_MIE_MSIE = 3, /**< CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) */ |
CSR_MIE_MTIE = 7, /**< CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) */ |
CSR_MIE_MEIE = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */ |
|
CSR_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */ |
CSR_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */ |
CSR_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */ |
CSR_MIE_FIRQ3E = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */ |
CSR_MIE_FIRQ4E = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */ |
CSR_MIE_FIRQ5E = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */ |
CSR_MIE_FIRQ6E = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */ |
CSR_MIE_FIRQ7E = 23, /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */ |
CSR_MIE_FIRQ8E = 24, /**< CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w) */ |
CSR_MIE_FIRQ9E = 25, /**< CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w) */ |
CSR_MIE_FIRQ10E = 26, /**< CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w) */ |
CSR_MIE_FIRQ11E = 27, /**< CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w) */ |
CSR_MIE_FIRQ12E = 28, /**< CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w) */ |
CSR_MIE_FIRQ13E = 29, /**< CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w) */ |
CSR_MIE_FIRQ14E = 30, /**< CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w) */ |
CSR_MIE_FIRQ15E = 31 /**< CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w) */ |
}; |
|
|
384,18 → 393,27
* CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CSR_MIP_enum { |
CSR_MIP_MSIP = 3, /**< CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) */ |
CSR_MIP_MTIP = 7, /**< CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) */ |
CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */ |
CSR_MIP_MSIP = 3, /**< CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) */ |
CSR_MIP_MTIP = 7, /**< CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) */ |
CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */ |
|
CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */ |
CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */ |
CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */ |
CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */ |
CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */ |
CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */ |
CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */ |
CSR_MIP_FIRQ7P = 23 /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */ |
CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */ |
CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */ |
CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */ |
CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */ |
CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */ |
CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */ |
CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */ |
CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */ |
|
CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */ |
CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */ |
CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */ |
CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */ |
CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */ |
CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/-) */ |
CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/-) */ |
CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/-) */ |
}; |
|
|
475,7 → 493,15
TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */ |
TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */ |
TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */ |
TRAP_CODE_FIRQ_7 = 0x80000017 /**< 1.23: Fast interrupt channel 7 */ |
TRAP_CODE_FIRQ_7 = 0x80000017, /**< 1.23: Fast interrupt channel 7 */ |
TRAP_CODE_FIRQ_8 = 0x80000018, /**< 1.24: Fast interrupt channel 8 */ |
TRAP_CODE_FIRQ_9 = 0x80000019, /**< 1.25: Fast interrupt channel 9 */ |
TRAP_CODE_FIRQ_10 = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */ |
TRAP_CODE_FIRQ_11 = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */ |
TRAP_CODE_FIRQ_12 = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */ |
TRAP_CODE_FIRQ_13 = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */ |
TRAP_CODE_FIRQ_14 = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */ |
TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */ |
}; |
|
|
714,8 → 740,6
UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */ |
|
UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */ |
UART_CT_RX_IRQ = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */ |
UART_CT_TX_IRQ = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */ |
UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */ |
}; |
|
759,7 → 783,6
SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */ |
SPI_CT_SIZE0 = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_SIZE1 = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_IRQ_EN = 15, /**< UART control register(15) (r/w): Transfer done interrupt enable */ |
|
SPI_CT_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */ |
}; |
780,12 → 803,11
TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */ |
TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */ |
TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */ |
TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */ |
TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */ |
TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */ |
TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */ |
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */ |
TWI_CT_CKSTEN = 8, /**< TWI control register(8) (r/w): Enable clock stretching (by peripheral) */ |
TWI_CT_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */ |
TWI_CT_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */ |
TWI_CT_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */ |
TWI_CT_MACK = 6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */ |
TWI_CT_CKSTEN = 7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */ |
|
TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ |
TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ |
/neorv32/trunk/sw/lib/include/neorv32_rte.h
66,9 → 66,24
RTE_TRAP_FIRQ_4 = 17, /**< Fast interrupt channel 4 */ |
RTE_TRAP_FIRQ_5 = 18, /**< Fast interrupt channel 5 */ |
RTE_TRAP_FIRQ_6 = 19, /**< Fast interrupt channel 6 */ |
RTE_TRAP_FIRQ_7 = 20 /**< Fast interrupt channel 7 */ |
RTE_TRAP_FIRQ_7 = 20, /**< Fast interrupt channel 7 */ |
RTE_TRAP_FIRQ_8 = 21, /**< Fast interrupt channel 8 */ |
RTE_TRAP_FIRQ_9 = 22, /**< Fast interrupt channel 9 */ |
RTE_TRAP_FIRQ_10 = 23, /**< Fast interrupt channel 10 */ |
RTE_TRAP_FIRQ_11 = 24, /**< Fast interrupt channel 11 */ |
RTE_TRAP_FIRQ_12 = 25, /**< Fast interrupt channel 12 */ |
RTE_TRAP_FIRQ_13 = 26, /**< Fast interrupt channel 13 */ |
RTE_TRAP_FIRQ_14 = 27, /**< Fast interrupt channel 14 */ |
RTE_TRAP_FIRQ_15 = 28 /**< Fast interrupt channel 15 */ |
}; |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Number of available traps. |
**************************************************************************/ |
#define NEORV32_RTE_NUM_TRAPS 29 |
|
|
// prototypes |
void neorv32_rte_setup(void); |
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)); |
/neorv32/trunk/sw/lib/include/neorv32_spi.h
46,7 → 46,7
|
// prototypes |
int neorv32_spi_available(void); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size); |
void neorv32_spi_disable(void); |
void neorv32_spi_cs_en(uint8_t cs); |
void neorv32_spi_cs_dis(uint8_t cs); |
/neorv32/trunk/sw/lib/include/neorv32_twi.h
46,7 → 46,7
|
// prototypes |
int neorv32_twi_available(void); |
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en, uint8_t ckst_en); |
void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en); |
void neorv32_twi_disable(void); |
void neorv32_twi_mack_enable(void); |
int neorv32_twi_busy(void); |
/neorv32/trunk/sw/lib/include/neorv32_uart.h
49,7 → 49,7
|
// prototypes |
int neorv32_uart_available(void); |
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity, uint8_t rx_irq, uint8_t tx_irq); |
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity); |
void neorv32_uart_disable(void); |
void neorv32_uart_putc(char c); |
int neorv32_uart_tx_busy(void); |
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
60,9 → 60,8
**************************************************************************/ |
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) { |
|
if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) || |
(irq_sel == CSR_MIE_FIRQ0E) || (irq_sel == CSR_MIE_FIRQ1E) || (irq_sel == CSR_MIE_FIRQ2E) || (irq_sel == CSR_MIE_FIRQ3E) || |
(irq_sel == CSR_MIE_FIRQ4E) || (irq_sel == CSR_MIE_FIRQ5E) || (irq_sel == CSR_MIE_FIRQ6E) || (irq_sel == CSR_MIE_FIRQ7E)) { |
if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) || |
((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) { |
return 0; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_rte.c
45,7 → 45,7
/**********************************************************************//** |
* The >private< trap vector look-up table of the NEORV32 RTE. |
**************************************************************************/ |
static uint32_t __neorv32_rte_vector_lut[21] __attribute__((unused)); // trap handler vector table |
static uint32_t __neorv32_rte_vector_lut[29] __attribute__((unused)); // trap handler vector table |
|
// private functions |
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused)); |
52,7 → 52,6
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused)); |
static void __neorv32_rte_print_hex_word(uint32_t num); |
static int __neorv32_rte_check_exc_id(uint32_t id); |
|
|
/**********************************************************************//** |
94,7 → 93,7
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) { |
|
// id valid? |
if (__neorv32_rte_check_exc_id(id) == 0) { |
if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) { |
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler |
return 0; |
} |
115,7 → 114,7
int neorv32_rte_exception_uninstall(uint8_t id) { |
|
// id valid? |
if (__neorv32_rte_check_exc_id(id) == 0) { |
if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) { |
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered |
return 0; |
} |
179,6 → 178,14
case TRAP_CODE_FIRQ_5: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break; |
case TRAP_CODE_FIRQ_6: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break; |
case TRAP_CODE_FIRQ_7: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break; |
case TRAP_CODE_FIRQ_8: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break; |
case TRAP_CODE_FIRQ_9: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break; |
case TRAP_CODE_FIRQ_10: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break; |
case TRAP_CODE_FIRQ_11: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break; |
case TRAP_CODE_FIRQ_12: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break; |
case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break; |
case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break; |
case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break; |
default: break; |
} |
|
195,11 → 202,20
**************************************************************************/ |
static void __neorv32_rte_debug_exc_handler(void) { |
|
char tmp; |
|
// intro |
neorv32_uart_print("<RTE> "); |
|
// cause |
register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
tmp = (char)(trap_cause & 0xf); |
if (tmp >= 10) { |
tmp = 'a' + (tmp - 10); |
} |
else { |
tmp = '0' + tmp; |
} |
switch (trap_cause) { |
case TRAP_CODE_I_MISALIGNED: neorv32_uart_print("Instruction address misaligned"); break; |
case TRAP_CODE_I_ACCESS: neorv32_uart_print("Instruction access fault"); break; |
221,7 → 237,15
case TRAP_CODE_FIRQ_4: |
case TRAP_CODE_FIRQ_5: |
case TRAP_CODE_FIRQ_6: |
case TRAP_CODE_FIRQ_7: neorv32_uart_print("Fast interrupt "); neorv32_uart_putc((char)('0' + (trap_cause & 0x7))); break; |
case TRAP_CODE_FIRQ_7: |
case TRAP_CODE_FIRQ_8: |
case TRAP_CODE_FIRQ_9: |
case TRAP_CODE_FIRQ_10: |
case TRAP_CODE_FIRQ_11: |
case TRAP_CODE_FIRQ_12: |
case TRAP_CODE_FIRQ_13: |
case TRAP_CODE_FIRQ_14: |
case TRAP_CODE_FIRQ_15: neorv32_uart_print("Fast interrupt "); neorv32_uart_putc(tmp); break; |
default: neorv32_uart_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break; |
} |
|
471,31 → 495,6
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Private function to check exception id |
* as 8-digit hexadecimal value (with "0x" suffix). |
* |
* @param[in] id Exception id (#NEORV32_RTE_TRAP_enum). |
* @return Return 0 if id is valid |
**************************************************************************/ |
static int __neorv32_rte_check_exc_id(uint32_t id) { |
|
// id valid? |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || (id == RTE_TRAP_UENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3) || |
(id == RTE_TRAP_FIRQ_4) || (id == RTE_TRAP_FIRQ_5) || (id == RTE_TRAP_FIRQ_6) || (id == RTE_TRAP_FIRQ_7)) { |
return 0; |
} |
else { |
return 1; |
} |
} |
|
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print the processor version in human-readable format. |
**************************************************************************/ |
void neorv32_rte_print_hw_version(void) { |
/neorv32/trunk/sw/lib/source/neorv32_spi.c
67,9 → 67,8
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] clk_polarity Idle clock polarity (0, 1). |
* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit). |
* @param[in] irq_en Enable transfer-done interrupt when 1. |
**************************************************************************/ |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en) { |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) { |
|
SPI_CT = 0; // reset |
|
85,10 → 84,7
uint32_t ct_size = (uint32_t)(data_size & 0x03); |
ct_size = ct_size << SPI_CT_SIZE0; |
|
uint32_t ct_irq = (uint32_t)(irq_en & 0x01); |
ct_irq = ct_irq << SPI_CT_IRQ_EN; |
|
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size | ct_irq; |
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size; |
} |
|
|
/neorv32/trunk/sw/lib/source/neorv32_twi.c
65,10 → 65,9
* Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CT_enum. |
* |
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] irq_en Enable transfer-done interrupt when 1. |
* @param[in] ckst_en Enable clock-stretching by peripherals when 1. |
**************************************************************************/ |
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en, uint8_t ckst_en) { |
void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en) { |
|
TWI_CT = 0; // reset |
|
78,13 → 77,10
uint32_t ct_prsc = (uint32_t)(prsc & 0x07); |
ct_prsc = ct_prsc << TWI_CT_PRSC0; |
|
uint32_t ct_irq = (uint32_t)(irq_en & 0x01); |
ct_irq = ct_irq << TWI_CT_IRQ_EN; |
|
uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01); |
ct_cksten = ct_cksten << TWI_CT_CKSTEN; |
|
TWI_CT = ct_enable | ct_prsc | ct_irq | ct_cksten; |
TWI_CT = ct_enable | ct_prsc | ct_cksten; |
} |
|
|
93,7 → 89,7
**************************************************************************/ |
void neorv32_twi_disable(void) { |
|
TWI_CT &= ~((uint32_t)(1 << TWI_CT_IRQ_EN)); |
TWI_CT &= ~((uint32_t)(1 << TWI_CT_EN)); |
} |
|
|
/neorv32/trunk/sw/lib/source/neorv32_uart.c
78,10 → 78,8
* |
* @param[in] baudrate Targeted BAUD rate (e.g. 9600). |
* @param[in] parity PArity configuration (00=off, 10=even, 11=odd). |
* @param[in] rx_irq Enable RX interrupt (data received) when 1. |
* @param[in] tx_irq Enable TX interrupt (transmission done) when 1. |
**************************************************************************/ |
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity, uint8_t rx_irq, uint8_t tx_irq) { |
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity) { |
|
UART_CT = 0; // reset |
|
123,12 → 121,6
uint32_t parity_config = (uint32_t)(parity & 3); |
parity_config = parity_config << UART_CT_PMODE0; |
|
uint32_t rx_irq_en = (uint32_t)(rx_irq & 1); |
rx_irq_en = rx_irq_en << UART_CT_RX_IRQ; |
|
uint32_t tx_irq_en = (uint32_t)(tx_irq & 1); |
tx_irq_en = tx_irq_en << UART_CT_TX_IRQ; |
|
/* Enable the UART for SIM mode. */ |
/* USE THIS ONLY FOR SIMULATION! */ |
#ifdef UART_SIM_MODE |
138,7 → 130,7
uint32_t sim_mode = 0; |
#endif |
|
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode; |
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode; |
} |
|
|
/neorv32/trunk/sw/lib/README.md
0,0 → 1,6
## NEORV32 Core Library |
|
This folder provides the hardware abstraction layer (HAL) libraries for the CPU itself and the individual processor modules (peripheral/IO devices). |
|
The `source` folder contains the actual C-code hardware driver functions (*.c*) while the `include` folder provides the according header files (*.h). |
Application programs should only include the *main NEORV32 define file* `source/neorv32.h`. This file automatically includes all other provided header files. |
/neorv32/trunk/CHANGELOG.md
6,15 → 6,17
A list of all releases can be found [here](https://github.com/stnolting/neorv32/releases). The most recent version of the *NEORV32 data sheet* |
can be found [here](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
|
:information_source: To see a list of all commits |
between release run `git log v1.4.7.0..v1.4.8.0` (example to to see commits between v1.4.7.0 and v1.4.8.0). |
:information_source: To see a list of all commits between release run `git log RELEASE_A..RELEASE_B` (example: `v1.4.7.0..v1.4.8.0`). |
|
:information_source: The processor can determine it's version from the `mimpid` CSR (at CSR address 0xf13). A 8x4-bit BCD representation is used. Leading |
zeros are optional. Example: `CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12`. The version number is globally defined by the |
`hw_version_c` constant in the main VHDL package file [`rtl/core/neorv32_package.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_package.vhd). |
:information_source: The processor can determine it's version from the `mimpid` CSR (at CSR address 0xf13). A 8x4-bit BCD representation is used. |
Leading zeros are optional. Example: `CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12`. The version number is globally |
defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/neorv32_package.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_package.vhd). |
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 07.02.2021 | [**:rocket:1.5.1.0**](https://github.com/stnolting/neorv32/releases/tag/v1.5.1.0) | **New release** | |
| 05.02.2021 | 1.5.0.11 | :bug: fixed error in atomic instruction `LR.W` | |
| 05.02.2021 | 1.5.0.10 | CPU now provides 16 fast interrupt request lines (`FIRQ0 .. FIRQ15`) with according `mie`/`mip` CSR bits and `mcause` trap codes; removed IRQ enable flags from SPI, UART & TWI; reworked processor-internal interrupt system - assignment/priority list; UART now features individual IRQs for "RX-done" and "TX-done" conditions; changed bit order in TWI control register | |
| 29.01.2021 | 1.5.0.9 | removed custom function units `CFU0` & `CFU1`; :sparkles: replaced them by new *Custom Functions Subsystem `CFS`*, which provides up to 32x32-bit memory-mapped registers; new configuration generics: `IO_CFS_EN`, `IO_CFS_CONFIG`; new top entity signals: `cfs_in_i`, `cfs_out_o`; increased processor's IO area from 128 bytes to 256 bytes, now starting at `0xFFFFFF00` | |
| 28.01.2021 | 1.5.0.8 | added *critical limit* for number of implemented PMP regions: When implementing more PMP regions that a certain critical limit an additional register stage is automatically inserted into the CPU’s memory interfaces increasing the latency of instruction fetches and data access by +1 cycle. The critical limit can be adapted for custom use by a constant from the main VHDL package file (rtl/core/neorv32_package.vhd). The default value is 8: `constant pmp_num_regions_critical_c : natural := 8;` | |
| 27.01.2021 | 1.5.0.7 | added four additional *fast interrupt* channels `FIRQ4..7`, available via processor's top `soc_firq_i(3:0)` signal for custom platform use; fixed minor error in UART setup function (baud rate prescaler calculation for very high baud rates) | |
/neorv32/trunk/README.md
58,6 → 58,7
* serial interfaces (SPI, TWI, UART) |
* general purpose IO and PWM channels |
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity)) |
* subsystem for custom co-processors |
* [more ...](#NEORV32-Processor-Features) |
* Software framework |
* core libraries for high-level usage of the provided functions and peripherals |
107,16 → 108,16
|
* Use LaTeX for data sheet |
* Further size and performance optimization |
* Further expand associativity configuration of instruction cache (4x/8x set-associativity) |
* Add data cache |
* Burst mode for the external memory/bus interface |
* Further expand associativity configuration of instruction cache (4x/8x set-associativity)? |
* Add data cache? |
* Burst mode for the external memory/bus interface? |
* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point) |
* Add template (HW module + intrinsics skeleton) for custom instructions? |
* Implement further RISC-V (or custom?) CPU extensions |
* More support for FreeRTOS (like *all* traps) |
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org)) |
* Maybe port [CircuitPython](https://circuitpython.org/) (just for fun) |
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec)) |
* Implement further RISC-V (or custom) CPU extensions? |
* More support for FreeRTOS (like *all* traps)? |
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))? |
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))? |
* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))? |
* ... |
* [Ideas?](#ContributeFeedbackQuestions) |
|
228,7 → 229,7
#### NEORV32-specific CPU extensions (`X` extension) |
|
* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR. |
* Eight *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause` |
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause` |
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`) |
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception |
|