OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 49 to Rev 50
    ↔ Reverse comparison
  •

Rev 49 → Rev 50

/neorv32/trunk/.ci/hw_check.sh
8,7 → 8,7
homedir=$homedir/..
 
# Run simulation
sh $homedir/sim/ghdl/ghdl_sim.sh --stop-time=6ms
sh $homedir/sim/ghdl/ghdl_sim.sh --stop-time=7ms
 
# Check if reference can be found in output
grep -qf $homedir/check_reference.out neorv32.uart.sim_mode.text.out && echo "Hardware test completed successfully!"
# Check if reference can be found in output (UART0 primary UART simulation output)
grep -qf $homedir/check_reference.out neorv32.uart0.sim_mode.text.out && echo "Hardware test completed successfully!"
/neorv32/trunk/.ci/sw_check.sh
26,9 → 26,9
make -C $srcdir_bootloader clean_all info bootloader
 
# Compile and install test application
# Redirect UART TX to text.io simulation output via <UART_SIM_MODE> user flag
# Redirect UART0 TX to text.io simulation output via <UART0_SIM_MODE> user flag
echo "Compiling and installing CPU (/Processor) test application"
make -C $test_app_dir clean_all USER_FLAGS+=-DRUN_CPUTEST USER_FLAGS+=-DUART_SIM_MODE MARCH=-march=rv32imac info all
make -C $test_app_dir clean_all USER_FLAGS+=-DRUN_CPUTEST USER_FLAGS+=-DUART0_SIM_MODE MARCH=-march=rv32imac info all
 
# Verification reference string
touch $homedir/check_reference.out
/neorv32/trunk/docs/figures/neorv32_logo_dark.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/docs/figures/neorv32_logo_dark.png
neorv32/trunk/docs/figures/neorv32_logo_dark.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neorv32/trunk/docs/figures/neorv32_logo_transparent.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/figures/neorv32_processor.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/figures/neorv32_test_setup.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/NEORV32.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include =================================================================== --- neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (revision 49) +++ neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (revision 50) @@ -33,7 +33,7 @@ make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \ - cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + cp $(work_dir_isa)/neorv32.uart0.sim_mode.data.out $(*).signature.output; RISCV_PREFIX ?= riscv32-unknown-elf-
/neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include
33,7 → 33,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output;
cp $(work_dir_isa)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
 
 
RISCV_PREFIX ?= riscv32-unknown-elf-
/neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include
33,7 → 33,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output;
cp $(work_dir_isa)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
 
 
RISCV_PREFIX ?= riscv32-unknown-elf-
/neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include
32,7 → 32,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output;
cp $(work_dir_isa)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
 
 
RISCV_PREFIX ?= riscv32-unknown-elf-
/neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include
33,7 → 33,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output;
cp $(work_dir_isa)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
 
 
RISCV_PREFIX ?= riscv32-unknown-elf-
/neorv32/trunk/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/model_test.h
16,7 → 16,7
.word 4;
 
//RV_COMPLIANCE_HALT
// neorv32: this will dump the results via the UART_SIM_MODE data file output
// neorv32: this will dump the results via the UART0_SIM_MODE data file output
// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here
// neorv32: -> for zero-padding of the rest of the SIGNATURE section
#define RVMODEL_HALT \
57,7 → 57,7
RVMODEL_DATA_SECTION
 
//RVMODEL_BOOT
// neorv32: enable UART (ctrl(28)) and enable UART_SIM_MODE (ctrl(12))
// neorv32: enable UART0 (ctrl(28)) and enable UART0_SIM_MODE (ctrl(12))
// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE
// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF
// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction
69,7 → 69,7
core_init: \
la x1, core_dummy_trap_handler; \
csrw mtvec, x1; \
j uart_sim_mode_init; \
j uart0_sim_mode_init; \
nop; \
nop; \
.balign 4; \
100,7 → 100,7
mret; \
nop; \
nop; \
uart_sim_mode_init: \
uart0_sim_mode_init: \
li a0, 0xFFFFFFA0; \
sw zero, 0(a0); \
li a1, 1 << 28; \
139,7 → 139,7
addi a0, a0, 4; \
j init_signature_loop; \
init_signature_loop_end: \
j uart_sim_mode_init; \
j uart0_sim_mode_init; \
nop; \
nop; \
.balign 4; \
170,7 → 170,7
mret; \
nop; \
nop; \
uart_sim_mode_init: \
uart0_sim_mode_init: \
li a0, 0xFFFFFFA0; \
sw zero, 0(a0); \
li a1, 1 << 28; \
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1043) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1063) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"f8058593",
00000052 => x"fd058593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
110,19 → 110,19
00000099 => x"00000593",
00000100 => x"b0050513",
00000101 => x"00112623",
00000102 => x"668000ef",
00000103 => x"1a1000ef",
00000102 => x"728000ef",
00000103 => x"1f1000ef",
00000104 => x"02050063",
00000105 => x"4ac000ef",
00000106 => x"00000513",
00000107 => x"500000ef",
00000108 => x"00001537",
00000109 => x"ce050513",
00000110 => x"6dc000ef",
00000109 => x"d3050513",
00000110 => x"778000ef",
00000111 => x"020000ef",
00000112 => x"00001537",
00000113 => x"cbc50513",
00000114 => x"6cc000ef",
00000113 => x"d0c50513",
00000114 => x"768000ef",
00000115 => x"00c12083",
00000116 => x"00000513",
00000117 => x"01010113",
132,11 → 132,11
00000121 => x"00812423",
00000122 => x"00112623",
00000123 => x"00000413",
00000124 => x"15d000ef",
00000124 => x"1ad000ef",
00000125 => x"0ff47513",
00000126 => x"155000ef",
00000126 => x"1a5000ef",
00000127 => x"0c800513",
00000128 => x"0cd000ef",
00000128 => x"11d000ef",
00000129 => x"00140413",
00000130 => x"fedff06f",
00000131 => x"00000000",
192,7 → 192,7
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"cfc70713",
00000184 => x"d4c70713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
203,7 → 203,7
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d2c70713",
00000195 => x"d7c70713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
276,14 → 276,14
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"da050513",
00000268 => x"df050513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"44c000ef",
00000275 => x"01c48493",
00000274 => x"4e8000ef",
00000275 => x"06c48493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
290,7 → 290,7
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"41c000ef",
00000282 => x"46c000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
301,11 → 301,11
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"da450513",
00000293 => x"df450513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"3f0000ef",
00000297 => x"48c000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
316,7 → 316,7
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"f3070713",
00000308 => x"f8070713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
329,8 → 329,8
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f0450513",
00000322 => x"38c000ef",
00000321 => x"f5450513",
00000322 => x"428000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
339,22 → 339,22
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"ef450513",
00000332 => x"364000ef",
00000331 => x"f4450513",
00000332 => x"400000ef",
00000333 => x"00048513",
00000334 => x"34c000ef",
00000334 => x"39c000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"dac50513",
00000338 => x"34c000ef",
00000337 => x"dfc50513",
00000338 => x"3e8000ef",
00000339 => x"00001537",
00000340 => x"f1c50513",
00000341 => x"340000ef",
00000340 => x"f6c50513",
00000341 => x"3dc000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f2450513",
00000346 => x"32c000ef",
00000345 => x"f7450513",
00000346 => x"3c8000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
361,44 → 361,44
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"f8c50513",
00000353 => x"fdc50513",
00000354 => x"01010113",
00000355 => x"3080006f",
00000355 => x"3a40006f",
00000356 => x"00001537",
00000357 => x"dcc50513",
00000357 => x"e1c50513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"de850513",
00000360 => x"e3850513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"dfc50513",
00000363 => x"e4c50513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e0850513",
00000366 => x"e5850513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e2050513",
00000369 => x"e7050513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"e3450513",
00000372 => x"e8450513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"e5050513",
00000375 => x"ea050513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"e6450513",
00000378 => x"eb450513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"e8450513",
00000381 => x"ed450513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"ea450513",
00000384 => x"ef450513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"ec050513",
00000387 => x"f1050513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"ed850513",
00000390 => x"f2850513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
419,8 → 419,8
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"f6050513",
00000412 => x"224000ef",
00000411 => x"fb050513",
00000412 => x"2c0000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
447,8 → 447,8
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"f9450513",
00000440 => x"20c000ef",
00000439 => x"fe450513",
00000440 => x"3dc000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
468,10 → 468,10
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"02ca0a13",
00000460 => x"07ca0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"51c000ef",
00000463 => x"56c000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
478,7 → 478,7
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"4b8000ef",
00000470 => x"508000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
520,537 → 520,557
00000509 => x"00008067",
00000510 => x"00070793",
00000511 => x"fadff06f",
00000512 => x"fa002023",
00000513 => x"fe002783",
00000514 => x"00151513",
00000515 => x"00000713",
00000516 => x"02a7fe63",
00000517 => x"000016b7",
00000518 => x"00000793",
00000519 => x"ffe68693",
00000520 => x"04e6e063",
00000521 => x"fff70713",
00000522 => x"0035f593",
00000523 => x"01879793",
00000524 => x"00e7e7b3",
00000525 => x"01659593",
00000526 => x"00b7e7b3",
00000527 => x"10000737",
00000528 => x"00e7e7b3",
00000529 => x"faf02023",
00000530 => x"00008067",
00000531 => x"00170713",
00000532 => x"01071713",
00000533 => x"40a787b3",
00000534 => x"01075713",
00000535 => x"fb5ff06f",
00000536 => x"ffe78613",
00000537 => x"0fd67613",
00000538 => x"00061a63",
00000539 => x"00375713",
00000540 => x"00178793",
00000541 => x"0ff7f793",
00000542 => x"fa9ff06f",
00000543 => x"00175713",
00000544 => x"ff1ff06f",
00000545 => x"fa002783",
00000546 => x"fe07cee3",
00000547 => x"faa02223",
00000548 => x"00008067",
00000549 => x"ff010113",
00000550 => x"00812423",
00000551 => x"01212023",
00000552 => x"00112623",
00000553 => x"00912223",
00000554 => x"00050413",
00000555 => x"00a00913",
00000556 => x"00044483",
00000557 => x"00140413",
00000558 => x"00049e63",
00000559 => x"00c12083",
00000560 => x"00812403",
00000561 => x"00412483",
00000562 => x"00012903",
00000563 => x"01010113",
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"08860613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
00000519 => x"00f607b3",
00000520 => x"0007c783",
00000521 => x"00470713",
00000522 => x"fff68693",
00000523 => x"00f680a3",
00000524 => x"ff0712e3",
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002783",
00000529 => x"00151513",
00000530 => x"00000713",
00000531 => x"02a7fe63",
00000532 => x"000016b7",
00000533 => x"00000793",
00000534 => x"ffe68693",
00000535 => x"04e6e063",
00000536 => x"fff70713",
00000537 => x"0035f593",
00000538 => x"01879793",
00000539 => x"00e7e7b3",
00000540 => x"01659593",
00000541 => x"00b7e7b3",
00000542 => x"10000737",
00000543 => x"00e7e7b3",
00000544 => x"faf02023",
00000545 => x"00008067",
00000546 => x"00170713",
00000547 => x"01071713",
00000548 => x"40a787b3",
00000549 => x"01075713",
00000550 => x"fb5ff06f",
00000551 => x"ffe78613",
00000552 => x"0fd67613",
00000553 => x"00061a63",
00000554 => x"00375713",
00000555 => x"00178793",
00000556 => x"0ff7f793",
00000557 => x"fa9ff06f",
00000558 => x"00175713",
00000559 => x"ff1ff06f",
00000560 => x"f7dff06f",
00000561 => x"fa002783",
00000562 => x"fe07cee3",
00000563 => x"faa02223",
00000564 => x"00008067",
00000565 => x"01249663",
00000566 => x"00d00513",
00000567 => x"fa9ff0ef",
00000568 => x"00048513",
00000569 => x"fa1ff0ef",
00000570 => x"fc9ff06f",
00000571 => x"fa010113",
00000572 => x"02912a23",
00000573 => x"04f12a23",
00000574 => x"000014b7",
00000575 => x"04410793",
00000576 => x"02812c23",
00000577 => x"03212823",
00000578 => x"03412423",
00000579 => x"03512223",
00000580 => x"03612023",
00000581 => x"01712e23",
00000582 => x"02112e23",
00000583 => x"03312623",
00000584 => x"01812c23",
00000585 => x"00050413",
00000586 => x"04b12223",
00000587 => x"04c12423",
00000588 => x"04d12623",
00000589 => x"04e12823",
00000590 => x"05012c23",
00000591 => x"05112e23",
00000592 => x"00f12023",
00000593 => x"02500a13",
00000594 => x"00a00a93",
00000595 => x"07300913",
00000596 => x"07500b13",
00000597 => x"07800b93",
00000598 => x"03848493",
00000599 => x"00044c03",
00000600 => x"020c0463",
00000601 => x"134c1263",
00000602 => x"00144783",
00000603 => x"00240993",
00000604 => x"09278c63",
00000605 => x"04f96263",
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00000816 => x"40b005b3",
00000817 => x"f9dff06f",
00000818 => x"40b005b3",
00000819 => x"00008293",
00000820 => x"f91ff0ef",
00000821 => x"40a00533",
00000822 => x"00028067",
00000823 => x"00008293",
00000824 => x"0005ca63",
00000825 => x"00054c63",
00000826 => x"f79ff0ef",
00000827 => x"00058513",
00000828 => x"00028067",
00000829 => x"40b005b3",
00000830 => x"fe0558e3",
00000831 => x"40a00533",
00000832 => x"f61ff0ef",
00000833 => x"40b00533",
00000834 => x"00028067",
00000835 => x"6f727245",
00000836 => x"4e202172",
00000837 => x"5047206f",
00000838 => x"75204f49",
00000839 => x"2074696e",
00000840 => x"746e7973",
00000841 => x"69736568",
00000842 => x"2164657a",
00000843 => x"0000000a",
00000844 => x"6e696c42",
00000845 => x"676e696b",
00000846 => x"44454c20",
00000847 => x"6d656420",
00000848 => x"7270206f",
00000849 => x"6172676f",
00000850 => x"00000a6d",
00000851 => x"0000031c",
00000852 => x"00000328",
00000853 => x"00000334",
00000854 => x"00000340",
00000855 => x"0000034c",
00000856 => x"00000354",
00000857 => x"0000035c",
00000858 => x"00000364",
00000859 => x"0000036c",
00000860 => x"00000288",
00000861 => x"00000288",
00000862 => x"00000374",
00000863 => x"0000037c",
00000864 => x"00000288",
00000865 => x"00000288",
00000866 => x"00000288",
00000867 => x"00000384",
00000868 => x"00000288",
00000869 => x"00000288",
00000870 => x"00000288",
00000871 => x"0000038c",
00000872 => x"00000288",
00000873 => x"00000288",
00000874 => x"00000288",
00000875 => x"00000288",
00000876 => x"00000394",
00000877 => x"0000039c",
00000878 => x"000003a4",
00000879 => x"000003ac",
00000880 => x"000003b4",
00000881 => x"000003bc",
00000882 => x"000003c4",
00000883 => x"000003cc",
00000884 => x"000003d4",
00000885 => x"000003dc",
00000886 => x"000003e4",
00000887 => x"000003ec",
00000888 => x"000003f4",
00000889 => x"000003fc",
00000890 => x"00000404",
00000891 => x"0000040c",
00000892 => x"00007830",
00000893 => x"4554523c",
00000894 => x"0000203e",
00000895 => x"74736e49",
00000896 => x"74637572",
00000897 => x"206e6f69",
00000898 => x"72646461",
00000899 => x"20737365",
00000900 => x"6173696d",
00000901 => x"6e67696c",
00000902 => x"00006465",
00000903 => x"74736e49",
00000904 => x"74637572",
00000905 => x"206e6f69",
00000906 => x"65636361",
00000907 => x"66207373",
00000908 => x"746c7561",
00000909 => x"00000000",
00000910 => x"656c6c49",
00000911 => x"206c6167",
00000912 => x"74736e69",
00000913 => x"74637572",
00000914 => x"006e6f69",
00000915 => x"61657242",
00000916 => x"696f706b",
00000917 => x"0000746e",
00000918 => x"64616f4c",
00000919 => x"64646120",
00000920 => x"73736572",
00000921 => x"73696d20",
00000922 => x"67696c61",
00000923 => x"0064656e",
00000924 => x"64616f4c",
00000925 => x"63636120",
00000926 => x"20737365",
00000927 => x"6c756166",
00000928 => x"00000074",
00000929 => x"726f7453",
00000930 => x"64612065",
00000931 => x"73657264",
00000932 => x"696d2073",
00000933 => x"696c6173",
00000934 => x"64656e67",
00000935 => x"00000000",
00000936 => x"726f7453",
00000937 => x"63612065",
00000938 => x"73736563",
00000939 => x"75616620",
00000940 => x"0000746c",
00000941 => x"69766e45",
00000942 => x"6d6e6f72",
00000943 => x"20746e65",
00000944 => x"6c6c6163",
00000945 => x"6f726620",
00000946 => x"2d55206d",
00000947 => x"65646f6d",
00000948 => x"00000000",
00000949 => x"69766e45",
00000950 => x"6d6e6f72",
00000951 => x"20746e65",
00000952 => x"6c6c6163",
00000953 => x"6f726620",
00000954 => x"2d4d206d",
00000955 => x"65646f6d",
00000956 => x"00000000",
00000957 => x"6863614d",
00000958 => x"20656e69",
00000959 => x"74666f73",
00000960 => x"65726177",
00000961 => x"746e6920",
00000962 => x"75727265",
00000963 => x"00007470",
00000964 => x"6863614d",
00000965 => x"20656e69",
00000966 => x"656d6974",
00000967 => x"6e692072",
00000968 => x"72726574",
00000969 => x"00747075",
00000970 => x"6863614d",
00000971 => x"20656e69",
00000972 => x"65747865",
00000973 => x"6c616e72",
00000974 => x"746e6920",
00000975 => x"75727265",
00000976 => x"00007470",
00000977 => x"74736146",
00000978 => x"746e6920",
00000979 => x"75727265",
00000980 => x"00207470",
00000981 => x"6e6b6e55",
00000982 => x"206e776f",
00000983 => x"70617274",
00000984 => x"75616320",
00000985 => x"203a6573",
00000986 => x"00000000",
00000987 => x"50204020",
00000988 => x"00003d43",
00000989 => x"544d202c",
00000990 => x"3d4c4156",
00000991 => x"00000000",
00000992 => x"00000540",
00000993 => x"00000590",
00000994 => x"0000059c",
00000995 => x"000005a8",
00000996 => x"000005b4",
00000997 => x"000005c0",
00000998 => x"000005cc",
00000999 => x"000005d8",
00001000 => x"000005e4",
00001001 => x"00000500",
00001002 => x"00000500",
00001003 => x"000005f0",
00001004 => x"4554523c",
00001005 => x"4157203e",
00001006 => x"4e494e52",
00001007 => x"43202147",
00001008 => x"43205550",
00001009 => x"73205253",
00001010 => x"65747379",
00001011 => x"6f6e206d",
00001012 => x"76612074",
00001013 => x"616c6961",
00001014 => x"21656c62",
00001015 => x"522f3c20",
00001016 => x"003e4554",
00001017 => x"5241570a",
00001018 => x"474e494e",
00001019 => x"57532021",
00001020 => x"4153495f",
00001021 => x"65662820",
00001022 => x"72757461",
00001023 => x"72207365",
00001024 => x"69757165",
00001025 => x"29646572",
00001026 => x"20737620",
00001027 => x"495f5748",
00001028 => x"28204153",
00001029 => x"74616566",
00001030 => x"73657275",
00001031 => x"61766120",
00001032 => x"62616c69",
00001033 => x"2029656c",
00001034 => x"6d73696d",
00001035 => x"68637461",
00001036 => x"57530a21",
00001037 => x"4153495f",
00001038 => x"30203d20",
00001039 => x"20782578",
00001040 => x"6d6f6328",
00001041 => x"656c6970",
00001042 => x"6c662072",
00001043 => x"29736761",
00001044 => x"5f57480a",
00001045 => x"20415349",
00001046 => x"7830203d",
00001047 => x"28207825",
00001048 => x"6173696d",
00001049 => x"72736320",
00001050 => x"000a0a29",
00001051 => x"33323130",
00001052 => x"37363534",
00001053 => x"42413938",
00001054 => x"46454443",
00001055 => x"33323130",
00001056 => x"37363534",
00001057 => x"00003938",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"62613938",
00001061 => x"66656463",
00001062 => x"00000000",
others => x"00000000"
);
 
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 987) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 999) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"ee058593",
00000036 => x"f1058593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
111,13 → 111,13
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"319000ef",
00000103 => x"349000ef",
00000104 => x"00100513",
00000105 => x"3b9000ef",
00000105 => x"3e9000ef",
00000106 => x"00005537",
00000107 => x"00000593",
00000108 => x"b0050513",
00000109 => x"1f9000ef",
00000109 => x"289000ef",
00000110 => x"1b1000ef",
00000111 => x"00245793",
00000112 => x"00a78533",
133,63 → 133,63
00000122 => x"00000013",
00000123 => x"00000013",
00000124 => x"ffff1537",
00000125 => x"e8850513",
00000126 => x"265000ef",
00000125 => x"eb850513",
00000126 => x"2e9000ef",
00000127 => x"f1302573",
00000128 => x"24c000ef",
00000129 => x"ffff1537",
00000130 => x"ec050513",
00000131 => x"251000ef",
00000130 => x"ef050513",
00000131 => x"2d5000ef",
00000132 => x"fe002503",
00000133 => x"238000ef",
00000134 => x"ffff1537",
00000135 => x"ec850513",
00000136 => x"23d000ef",
00000135 => x"ef850513",
00000136 => x"2c1000ef",
00000137 => x"fe402503",
00000138 => x"224000ef",
00000139 => x"ffff1537",
00000140 => x"ed450513",
00000141 => x"229000ef",
00000140 => x"f0450513",
00000141 => x"2ad000ef",
00000142 => x"30102573",
00000143 => x"210000ef",
00000144 => x"ffff1537",
00000145 => x"edc50513",
00000146 => x"215000ef",
00000145 => x"f0c50513",
00000146 => x"299000ef",
00000147 => x"fe802503",
00000148 => x"ffff14b7",
00000149 => x"00341413",
00000150 => x"1f4000ef",
00000151 => x"ffff1537",
00000152 => x"ee450513",
00000153 => x"1f9000ef",
00000152 => x"f1450513",
00000153 => x"27d000ef",
00000154 => x"ff802503",
00000155 => x"1e0000ef",
00000156 => x"eec48513",
00000157 => x"1e9000ef",
00000156 => x"f1c48513",
00000157 => x"26d000ef",
00000158 => x"ff002503",
00000159 => x"1d0000ef",
00000160 => x"ffff1537",
00000161 => x"ef850513",
00000162 => x"1d5000ef",
00000161 => x"f2850513",
00000162 => x"259000ef",
00000163 => x"ffc02503",
00000164 => x"1bc000ef",
00000165 => x"eec48513",
00000166 => x"1c5000ef",
00000165 => x"f1c48513",
00000166 => x"249000ef",
00000167 => x"ff402503",
00000168 => x"1ac000ef",
00000169 => x"ffff1537",
00000170 => x"f0050513",
00000171 => x"1b1000ef",
00000170 => x"f3050513",
00000171 => x"235000ef",
00000172 => x"0b9000ef",
00000173 => x"00a404b3",
00000174 => x"0084b433",
00000175 => x"00b40433",
00000176 => x"fa402783",
00000177 => x"0207d263",
00000176 => x"1c5000ef",
00000177 => x"02050263",
00000178 => x"ffff1537",
00000179 => x"f2850513",
00000180 => x"18d000ef",
00000181 => x"17d000ef",
00000179 => x"f5850513",
00000180 => x"211000ef",
00000181 => x"0d9000ef",
00000182 => x"02300793",
00000183 => x"02f51263",
00000184 => x"00000513",
209,13 → 209,13
00000198 => x"07500b93",
00000199 => x"ffff14b7",
00000200 => x"ffff1c37",
00000201 => x"f3490513",
00000202 => x"135000ef",
00000203 => x"115000ef",
00000201 => x"f6490513",
00000202 => x"1b9000ef",
00000203 => x"149000ef",
00000204 => x"00050413",
00000205 => x"0fd000ef",
00000206 => x"e4098513",
00000207 => x"121000ef",
00000205 => x"11d000ef",
00000206 => x"e7098513",
00000207 => x"1a5000ef",
00000208 => x"fb4400e3",
00000209 => x"01541863",
00000210 => x"ffff02b7",
240,20 → 240,20
00000229 => x"02c000ef",
00000230 => x"f8dff06f",
00000231 => x"03f00793",
00000232 => x"f3cc0513",
00000232 => x"f6cc0513",
00000233 => x"00f40463",
00000234 => x"f5048513",
00000235 => x"0b1000ef",
00000234 => x"f8048513",
00000235 => x"135000ef",
00000236 => x"f75ff06f",
00000237 => x"ffff1537",
00000238 => x"d6450513",
00000239 => x"0a10006f",
00000238 => x"d9450513",
00000239 => x"1250006f",
00000240 => x"800007b7",
00000241 => x"0007a783",
00000242 => x"00079863",
00000243 => x"ffff1537",
00000244 => x"dc850513",
00000245 => x"0890006f",
00000244 => x"df850513",
00000245 => x"10d0006f",
00000246 => x"ff010113",
00000247 => x"00112623",
00000248 => x"30047073",
260,10 → 260,10
00000249 => x"00000013",
00000250 => x"00000013",
00000251 => x"ffff1537",
00000252 => x"de450513",
00000253 => x"069000ef",
00000254 => x"fa002783",
00000255 => x"fe07cee3",
00000252 => x"e1450513",
00000253 => x"0ed000ef",
00000254 => x"069000ef",
00000255 => x"fe051ee3",
00000256 => x"ff002783",
00000257 => x"00078067",
00000258 => x"0000006f",
271,17 → 271,17
00000260 => x"00812423",
00000261 => x"00050413",
00000262 => x"ffff1537",
00000263 => x"df450513",
00000263 => x"e2450513",
00000264 => x"00112623",
00000265 => x"039000ef",
00000265 => x"0bd000ef",
00000266 => x"03040513",
00000267 => x"0ff57513",
00000268 => x"001000ef",
00000268 => x"021000ef",
00000269 => x"30047073",
00000270 => x"00000013",
00000271 => x"00000013",
00000272 => x"00100513",
00000273 => x"119000ef",
00000273 => x"149000ef",
00000274 => x"0000006f",
00000275 => x"fe010113",
00000276 => x"01212823",
288,14 → 288,14
00000277 => x"00050913",
00000278 => x"ffff1537",
00000279 => x"00912a23",
00000280 => x"e0c50513",
00000280 => x"e3c50513",
00000281 => x"ffff14b7",
00000282 => x"00812c23",
00000283 => x"01312623",
00000284 => x"00112e23",
00000285 => x"01c00413",
00000286 => x"7e4000ef",
00000287 => x"f5c48493",
00000286 => x"069000ef",
00000287 => x"f8c48493",
00000288 => x"ffc00993",
00000289 => x"008957b3",
00000290 => x"00f7f793",
302,7 → 302,7
00000291 => x"00f487b3",
00000292 => x"0007c503",
00000293 => x"ffc40413",
00000294 => x"798000ef",
00000294 => x"7b8000ef",
00000295 => x"ff3414e3",
00000296 => x"01c12083",
00000297 => x"01812403",
334,7 → 334,7
00000323 => x"00778793",
00000324 => x"06f41a63",
00000325 => x"00000513",
00000326 => x"029000ef",
00000326 => x"059000ef",
00000327 => x"64c000ef",
00000328 => x"fe002783",
00000329 => x"0027d793",
367,13 → 367,13
00000356 => x"00100513",
00000357 => x"02079863",
00000358 => x"ffff1537",
00000359 => x"e0050513",
00000360 => x"6bc000ef",
00000359 => x"e3050513",
00000360 => x"740000ef",
00000361 => x"00040513",
00000362 => x"ea5ff0ef",
00000363 => x"ffff1537",
00000364 => x"e0850513",
00000365 => x"6a8000ef",
00000364 => x"e3850513",
00000365 => x"72c000ef",
00000366 => x"34102573",
00000367 => x"e91ff0ef",
00000368 => x"00500513",
382,14 → 382,14
00000371 => x"00000513",
00000372 => x"00112623",
00000373 => x"00812423",
00000374 => x"710000ef",
00000374 => x"740000ef",
00000375 => x"09e00513",
00000376 => x"74c000ef",
00000376 => x"77c000ef",
00000377 => x"00000513",
00000378 => x"744000ef",
00000378 => x"774000ef",
00000379 => x"00050413",
00000380 => x"00000513",
00000381 => x"714000ef",
00000381 => x"744000ef",
00000382 => x"00c12083",
00000383 => x"0ff47513",
00000384 => x"00812403",
399,15 → 399,15
00000388 => x"00112623",
00000389 => x"00812423",
00000390 => x"00000513",
00000391 => x"6cc000ef",
00000391 => x"6fc000ef",
00000392 => x"00500513",
00000393 => x"708000ef",
00000393 => x"738000ef",
00000394 => x"00000513",
00000395 => x"700000ef",
00000395 => x"730000ef",
00000396 => x"00050413",
00000397 => x"00147413",
00000398 => x"00000513",
00000399 => x"6cc000ef",
00000399 => x"6fc000ef",
00000400 => x"fc041ce3",
00000401 => x"00c12083",
00000402 => x"00812403",
416,13 → 416,13
00000405 => x"ff010113",
00000406 => x"00000513",
00000407 => x"00112623",
00000408 => x"688000ef",
00000408 => x"6b8000ef",
00000409 => x"00600513",
00000410 => x"6c4000ef",
00000410 => x"6f4000ef",
00000411 => x"00c12083",
00000412 => x"00000513",
00000413 => x"01010113",
00000414 => x"6900006f",
00000414 => x"6c00006f",
00000415 => x"ff010113",
00000416 => x"00812423",
00000417 => x"00050413",
429,30 → 429,30
00000418 => x"01055513",
00000419 => x"0ff57513",
00000420 => x"00112623",
00000421 => x"698000ef",
00000421 => x"6c8000ef",
00000422 => x"00845513",
00000423 => x"0ff57513",
00000424 => x"68c000ef",
00000424 => x"6bc000ef",
00000425 => x"0ff47513",
00000426 => x"00812403",
00000427 => x"00c12083",
00000428 => x"01010113",
00000429 => x"6780006f",
00000429 => x"6a80006f",
00000430 => x"ff010113",
00000431 => x"00812423",
00000432 => x"00050413",
00000433 => x"00000513",
00000434 => x"00112623",
00000435 => x"61c000ef",
00000435 => x"64c000ef",
00000436 => x"00300513",
00000437 => x"658000ef",
00000437 => x"688000ef",
00000438 => x"00040513",
00000439 => x"fa1ff0ef",
00000440 => x"00000513",
00000441 => x"648000ef",
00000441 => x"678000ef",
00000442 => x"00050413",
00000443 => x"00000513",
00000444 => x"618000ef",
00000444 => x"648000ef",
00000445 => x"00c12083",
00000446 => x"0ff47513",
00000447 => x"00812403",
471,7 → 471,7
00000460 => x"00000413",
00000461 => x"00400a13",
00000462 => x"02091e63",
00000463 => x"504000ef",
00000463 => x"538000ef",
00000464 => x"00a481a3",
00000465 => x"00140413",
00000466 => x"fff48493",
513,8 → 513,8
00000502 => x"04079663",
00000503 => x"02041863",
00000504 => x"ffff1537",
00000505 => x"e1050513",
00000506 => x"474000ef",
00000505 => x"e4050513",
00000506 => x"4f8000ef",
00000507 => x"008005b7",
00000508 => x"00040513",
00000509 => x"f15ff0ef",
524,8 → 524,8
00000513 => x"00000513",
00000514 => x"01c0006f",
00000515 => x"ffff1537",
00000516 => x"e3050513",
00000517 => x"448000ef",
00000516 => x"e6050513",
00000517 => x"4cc000ef",
00000518 => x"db1ff0ef",
00000519 => x"fc0518e3",
00000520 => x"00300513",
550,8 → 550,8
00000539 => x"00200513",
00000540 => x"fa049ae3",
00000541 => x"ffff1537",
00000542 => x"e3c50513",
00000543 => x"3e0000ef",
00000542 => x"e6c50513",
00000543 => x"464000ef",
00000544 => x"02c12083",
00000545 => x"02812403",
00000546 => x"800007b7",
578,8 → 578,8
00000567 => x"00112623",
00000568 => x"ea1ff0ef",
00000569 => x"ffff1537",
00000570 => x"e4050513",
00000571 => x"370000ef",
00000570 => x"e7050513",
00000571 => x"3f4000ef",
00000572 => x"ad1ff0ef",
00000573 => x"0000006f",
00000574 => x"ff010113",
590,15 → 590,15
00000579 => x"00050493",
00000580 => x"d45ff0ef",
00000581 => x"00000513",
00000582 => x"3d0000ef",
00000582 => x"400000ef",
00000583 => x"00200513",
00000584 => x"40c000ef",
00000584 => x"43c000ef",
00000585 => x"00048513",
00000586 => x"d55ff0ef",
00000587 => x"00040513",
00000588 => x"3fc000ef",
00000588 => x"42c000ef",
00000589 => x"00000513",
00000590 => x"3d0000ef",
00000590 => x"400000ef",
00000591 => x"00812403",
00000592 => x"00c12083",
00000593 => x"00412483",
632,13 → 632,13
00000621 => x"00050413",
00000622 => x"c9dff0ef",
00000623 => x"00000513",
00000624 => x"328000ef",
00000624 => x"358000ef",
00000625 => x"0d800513",
00000626 => x"364000ef",
00000626 => x"394000ef",
00000627 => x"00040513",
00000628 => x"cadff0ef",
00000629 => x"00000513",
00000630 => x"330000ef",
00000630 => x"360000ef",
00000631 => x"00812403",
00000632 => x"00c12083",
00000633 => x"01010113",
655,7 → 655,7
00000644 => x"01512223",
00000645 => x"02041863",
00000646 => x"ffff1537",
00000647 => x"dc850513",
00000647 => x"df850513",
00000648 => x"01812403",
00000649 => x"01c12083",
00000650 => x"01412483",
664,23 → 664,23
00000653 => x"00812a03",
00000654 => x"00412a83",
00000655 => x"02010113",
00000656 => x"21c0006f",
00000656 => x"2a00006f",
00000657 => x"ffff1537",
00000658 => x"e4450513",
00000659 => x"210000ef",
00000658 => x"e7450513",
00000659 => x"294000ef",
00000660 => x"00040513",
00000661 => x"9f9ff0ef",
00000662 => x"ffff1537",
00000663 => x"e5050513",
00000664 => x"1fc000ef",
00000663 => x"e8050513",
00000664 => x"280000ef",
00000665 => x"00800537",
00000666 => x"9e5ff0ef",
00000667 => x"ffff1537",
00000668 => x"e6c50513",
00000669 => x"1e8000ef",
00000670 => x"1c8000ef",
00000668 => x"e9c50513",
00000669 => x"26c000ef",
00000670 => x"1fc000ef",
00000671 => x"00050493",
00000672 => x"1b0000ef",
00000672 => x"1d0000ef",
00000673 => x"07900793",
00000674 => x"0af49e63",
00000675 => x"b3dff0ef",
688,9 → 688,9
00000677 => x"00300513",
00000678 => x"975ff0ef",
00000679 => x"ffff1537",
00000680 => x"e7850513",
00000680 => x"ea850513",
00000681 => x"01045493",
00000682 => x"1b4000ef",
00000682 => x"238000ef",
00000683 => x"00148493",
00000684 => x"00800937",
00000685 => x"fff00993",
718,7 → 718,7
00000707 => x"412005b3",
00000708 => x"e41ff0ef",
00000709 => x"ffff1537",
00000710 => x"e3c50513",
00000710 => x"e6c50513",
00000711 => x"f05ff06f",
00000712 => x"00090513",
00000713 => x"e85ff0ef",
755,246 → 755,258
00000744 => x"00a6a023",
00000745 => x"00b6a223",
00000746 => x"00008067",
00000747 => x"fa002023",
00000748 => x"fe002783",
00000749 => x"00151513",
00000750 => x"00000713",
00000751 => x"02a7fe63",
00000752 => x"000016b7",
00000753 => x"00000793",
00000754 => x"ffe68693",
00000755 => x"04e6e063",
00000756 => x"fff70713",
00000757 => x"0035f593",
00000758 => x"01879793",
00000759 => x"00e7e7b3",
00000760 => x"01659593",
00000761 => x"00b7e7b3",
00000762 => x"10000737",
00000763 => x"00e7e7b3",
00000764 => x"faf02023",
00000765 => x"00008067",
00000766 => x"00170713",
00000767 => x"01071713",
00000768 => x"40a787b3",
00000769 => x"01075713",
00000770 => x"fb5ff06f",
00000771 => x"ffe78613",
00000772 => x"0fd67613",
00000773 => x"00061a63",
00000774 => x"00375713",
00000775 => x"00178793",
00000776 => x"0ff7f793",
00000777 => x"fa9ff06f",
00000778 => x"00175713",
00000779 => x"ff1ff06f",
00000780 => x"fa002783",
00000781 => x"fe07cee3",
00000782 => x"faa02223",
00000783 => x"00008067",
00000784 => x"fa402503",
00000785 => x"fe055ee3",
00000786 => x"0ff57513",
00000747 => x"fa402503",
00000748 => x"0ff57513",
00000749 => x"00008067",
00000750 => x"fa002023",
00000751 => x"fe002783",
00000752 => x"00151513",
00000753 => x"00000713",
00000754 => x"02a7fe63",
00000755 => x"000016b7",
00000756 => x"00000793",
00000757 => x"ffe68693",
00000758 => x"04e6e063",
00000759 => x"fff70713",
00000760 => x"0035f593",
00000761 => x"01879793",
00000762 => x"00e7e7b3",
00000763 => x"01659593",
00000764 => x"00b7e7b3",
00000765 => x"10000737",
00000766 => x"00e7e7b3",
00000767 => x"faf02023",
00000768 => x"00008067",
00000769 => x"00170713",
00000770 => x"01071713",
00000771 => x"40a787b3",
00000772 => x"01075713",
00000773 => x"fb5ff06f",
00000774 => x"ffe78613",
00000775 => x"0fd67613",
00000776 => x"00061a63",
00000777 => x"00375713",
00000778 => x"00178793",
00000779 => x"0ff7f793",
00000780 => x"fa9ff06f",
00000781 => x"00175713",
00000782 => x"ff1ff06f",
00000783 => x"f7dff06f",
00000784 => x"fa002783",
00000785 => x"fe07cee3",
00000786 => x"faa02223",
00000787 => x"00008067",
00000788 => x"fa402503",
00000789 => x"0ff57513",
00000790 => x"00008067",
00000791 => x"ff010113",
00000792 => x"00812423",
00000793 => x"01212023",
00000794 => x"00112623",
00000795 => x"00912223",
00000796 => x"00050413",
00000797 => x"00a00913",
00000798 => x"00044483",
00000799 => x"00140413",
00000800 => x"00049e63",
00000801 => x"00c12083",
00000802 => x"00812403",
00000803 => x"00412483",
00000804 => x"00012903",
00000805 => x"01010113",
00000806 => x"00008067",
00000807 => x"01249663",
00000808 => x"00d00513",
00000809 => x"f8dff0ef",
00000810 => x"00048513",
00000811 => x"f85ff0ef",
00000812 => x"fc9ff06f",
00000813 => x"00757513",
00000814 => x"00367613",
00000815 => x"0015f593",
00000816 => x"00a51513",
00000817 => x"00d61613",
00000818 => x"00c56533",
00000819 => x"00959593",
00000820 => x"fa800793",
00000821 => x"00b56533",
00000822 => x"0007a023",
00000823 => x"10056513",
00000824 => x"00a7a023",
00000825 => x"00008067",
00000826 => x"fa800713",
00000827 => x"00072683",
00000828 => x"00757793",
00000829 => x"00100513",
00000830 => x"00f51533",
00000831 => x"00d56533",
00000832 => x"00a72023",
00000833 => x"00008067",
00000834 => x"fa800713",
00000835 => x"00072683",
00000836 => x"00757513",
00000837 => x"00100793",
00000838 => x"00a797b3",
00000839 => x"fff7c793",
00000840 => x"00d7f7b3",
00000841 => x"00f72023",
00000842 => x"00008067",
00000843 => x"faa02623",
00000844 => x"fa802783",
00000845 => x"fe07cee3",
00000846 => x"fac02503",
00000847 => x"00008067",
00000848 => x"f8400713",
00000849 => x"00072683",
00000850 => x"00100793",
00000851 => x"00a797b3",
00000852 => x"00d7c7b3",
00000788 => x"ff1ff06f",
00000789 => x"fa002503",
00000790 => x"01f55513",
00000791 => x"00008067",
00000792 => x"ff5ff06f",
00000793 => x"fa402503",
00000794 => x"fe055ee3",
00000795 => x"0ff57513",
00000796 => x"00008067",
00000797 => x"ff1ff06f",
00000798 => x"fa402503",
00000799 => x"01f55513",
00000800 => x"00008067",
00000801 => x"ff5ff06f",
00000802 => x"ff010113",
00000803 => x"00812423",
00000804 => x"01212023",
00000805 => x"00112623",
00000806 => x"00912223",
00000807 => x"00050413",
00000808 => x"00a00913",
00000809 => x"00044483",
00000810 => x"00140413",
00000811 => x"00049e63",
00000812 => x"00c12083",
00000813 => x"00812403",
00000814 => x"00412483",
00000815 => x"00012903",
00000816 => x"01010113",
00000817 => x"00008067",
00000818 => x"01249663",
00000819 => x"00d00513",
00000820 => x"f71ff0ef",
00000821 => x"00048513",
00000822 => x"f69ff0ef",
00000823 => x"fc9ff06f",
00000824 => x"fa9ff06f",
00000825 => x"00757513",
00000826 => x"00367613",
00000827 => x"0015f593",
00000828 => x"00a51513",
00000829 => x"00d61613",
00000830 => x"00c56533",
00000831 => x"00959593",
00000832 => x"fa800793",
00000833 => x"00b56533",
00000834 => x"0007a023",
00000835 => x"10056513",
00000836 => x"00a7a023",
00000837 => x"00008067",
00000838 => x"fa800713",
00000839 => x"00072683",
00000840 => x"00757793",
00000841 => x"00100513",
00000842 => x"00f51533",
00000843 => x"00d56533",
00000844 => x"00a72023",
00000845 => x"00008067",
00000846 => x"fa800713",
00000847 => x"00072683",
00000848 => x"00757513",
00000849 => x"00100793",
00000850 => x"00a797b3",
00000851 => x"fff7c793",
00000852 => x"00d7f7b3",
00000853 => x"00f72023",
00000854 => x"00008067",
00000855 => x"f8a02223",
00000856 => x"00008067",
00000857 => x"69617641",
00000858 => x"6c62616c",
00000859 => x"4d432065",
00000860 => x"0a3a7344",
00000861 => x"203a6820",
00000862 => x"706c6548",
00000863 => x"3a72200a",
00000864 => x"73655220",
00000865 => x"74726174",
00000866 => x"3a75200a",
00000867 => x"6c705520",
00000868 => x"0a64616f",
00000869 => x"203a7320",
00000870 => x"726f7453",
00000871 => x"6f742065",
00000872 => x"616c6620",
00000873 => x"200a6873",
00000874 => x"4c203a6c",
00000875 => x"2064616f",
00000876 => x"6d6f7266",
00000877 => x"616c6620",
00000878 => x"200a6873",
00000879 => x"45203a65",
00000880 => x"75636578",
00000881 => x"00006574",
00000882 => x"65206f4e",
00000883 => x"75636578",
00000884 => x"6c626174",
00000885 => x"76612065",
00000886 => x"616c6961",
00000887 => x"2e656c62",
00000888 => x"00000000",
00000889 => x"746f6f42",
00000890 => x"2e676e69",
00000891 => x"0a0a2e2e",
00000892 => x"00000000",
00000893 => x"52450a07",
00000894 => x"5f524f52",
00000895 => x"00000000",
00000896 => x"58450a0a",
00000897 => x"00282043",
00000898 => x"20402029",
00000899 => x"00007830",
00000900 => x"69617741",
00000901 => x"676e6974",
00000902 => x"6f656e20",
00000903 => x"32337672",
00000904 => x"6578655f",
00000905 => x"6e69622e",
00000906 => x"202e2e2e",
00000855 => x"faa02623",
00000856 => x"fa802783",
00000857 => x"fe07cee3",
00000858 => x"fac02503",
00000859 => x"00008067",
00000860 => x"f8400713",
00000861 => x"00072683",
00000862 => x"00100793",
00000863 => x"00a797b3",
00000864 => x"00d7c7b3",
00000865 => x"00f72023",
00000866 => x"00008067",
00000867 => x"f8a02223",
00000868 => x"00008067",
00000869 => x"69617641",
00000870 => x"6c62616c",
00000871 => x"4d432065",
00000872 => x"0a3a7344",
00000873 => x"203a6820",
00000874 => x"706c6548",
00000875 => x"3a72200a",
00000876 => x"73655220",
00000877 => x"74726174",
00000878 => x"3a75200a",
00000879 => x"6c705520",
00000880 => x"0a64616f",
00000881 => x"203a7320",
00000882 => x"726f7453",
00000883 => x"6f742065",
00000884 => x"616c6620",
00000885 => x"200a6873",
00000886 => x"4c203a6c",
00000887 => x"2064616f",
00000888 => x"6d6f7266",
00000889 => x"616c6620",
00000890 => x"200a6873",
00000891 => x"45203a65",
00000892 => x"75636578",
00000893 => x"00006574",
00000894 => x"65206f4e",
00000895 => x"75636578",
00000896 => x"6c626174",
00000897 => x"76612065",
00000898 => x"616c6961",
00000899 => x"2e656c62",
00000900 => x"00000000",
00000901 => x"746f6f42",
00000902 => x"2e676e69",
00000903 => x"0a0a2e2e",
00000904 => x"00000000",
00000905 => x"52450a07",
00000906 => x"5f524f52",
00000907 => x"00000000",
00000908 => x"64616f4c",
00000909 => x"2e676e69",
00000910 => x"00202e2e",
00000911 => x"00004b4f",
00000912 => x"0000000a",
00000913 => x"74697257",
00000914 => x"78302065",
00000915 => x"00000000",
00000916 => x"74796220",
00000917 => x"74207365",
00000918 => x"5053206f",
00000919 => x"6c662049",
00000920 => x"20687361",
00000921 => x"78302040",
00000922 => x"00000000",
00000923 => x"7928203f",
00000924 => x"20296e2f",
00000925 => x"00000000",
00000926 => x"616c460a",
00000927 => x"6e696873",
00000928 => x"2e2e2e67",
00000929 => x"00000020",
00000930 => x"0a0a0a0a",
00000931 => x"4e203c3c",
00000932 => x"56524f45",
00000933 => x"42203233",
00000934 => x"6c746f6f",
00000935 => x"6564616f",
00000936 => x"3e3e2072",
00000937 => x"4c420a0a",
00000938 => x"203a5644",
00000939 => x"20626546",
00000940 => x"32203420",
00000941 => x"0a313230",
00000942 => x"3a565748",
00000943 => x"00002020",
00000944 => x"4b4c430a",
00000945 => x"0020203a",
00000946 => x"0a7a4820",
00000947 => x"52455355",
00000948 => x"0000203a",
00000949 => x"53494d0a",
00000950 => x"00203a41",
00000951 => x"4f52500a",
00000952 => x"00203a43",
00000953 => x"454d490a",
00000954 => x"00203a4d",
00000955 => x"74796220",
00000956 => x"40207365",
00000957 => x"00000020",
00000958 => x"454d440a",
00000959 => x"00203a4d",
00000960 => x"75410a0a",
00000961 => x"6f626f74",
00000962 => x"6920746f",
00000963 => x"7338206e",
00000964 => x"7250202e",
00000965 => x"20737365",
00000966 => x"2079656b",
00000967 => x"61206f74",
00000968 => x"74726f62",
00000969 => x"00000a2e",
00000970 => x"726f6241",
00000971 => x"2e646574",
00000972 => x"00000a0a",
00000973 => x"444d430a",
00000974 => x"00203e3a",
00000975 => x"53207962",
00000976 => x"68706574",
00000977 => x"4e206e61",
00000978 => x"69746c6f",
00000979 => x"0000676e",
00000980 => x"61766e49",
00000981 => x"2064696c",
00000982 => x"00444d43",
00000983 => x"33323130",
00000984 => x"37363534",
00000985 => x"42413938",
00000986 => x"46454443",
00000908 => x"58450a0a",
00000909 => x"00282043",
00000910 => x"20402029",
00000911 => x"00007830",
00000912 => x"69617741",
00000913 => x"676e6974",
00000914 => x"6f656e20",
00000915 => x"32337672",
00000916 => x"6578655f",
00000917 => x"6e69622e",
00000918 => x"202e2e2e",
00000919 => x"00000000",
00000920 => x"64616f4c",
00000921 => x"2e676e69",
00000922 => x"00202e2e",
00000923 => x"00004b4f",
00000924 => x"0000000a",
00000925 => x"74697257",
00000926 => x"78302065",
00000927 => x"00000000",
00000928 => x"74796220",
00000929 => x"74207365",
00000930 => x"5053206f",
00000931 => x"6c662049",
00000932 => x"20687361",
00000933 => x"78302040",
00000934 => x"00000000",
00000935 => x"7928203f",
00000936 => x"20296e2f",
00000937 => x"00000000",
00000938 => x"616c460a",
00000939 => x"6e696873",
00000940 => x"2e2e2e67",
00000941 => x"00000020",
00000942 => x"0a0a0a0a",
00000943 => x"4e203c3c",
00000944 => x"56524f45",
00000945 => x"42203233",
00000946 => x"6c746f6f",
00000947 => x"6564616f",
00000948 => x"3e3e2072",
00000949 => x"4c420a0a",
00000950 => x"203a5644",
00000951 => x"20626546",
00000952 => x"32203731",
00000953 => x"0a313230",
00000954 => x"3a565748",
00000955 => x"00002020",
00000956 => x"4b4c430a",
00000957 => x"0020203a",
00000958 => x"0a7a4820",
00000959 => x"52455355",
00000960 => x"0000203a",
00000961 => x"53494d0a",
00000962 => x"00203a41",
00000963 => x"4f52500a",
00000964 => x"00203a43",
00000965 => x"454d490a",
00000966 => x"00203a4d",
00000967 => x"74796220",
00000968 => x"40207365",
00000969 => x"00000020",
00000970 => x"454d440a",
00000971 => x"00203a4d",
00000972 => x"75410a0a",
00000973 => x"6f626f74",
00000974 => x"6920746f",
00000975 => x"7338206e",
00000976 => x"7250202e",
00000977 => x"20737365",
00000978 => x"2079656b",
00000979 => x"61206f74",
00000980 => x"74726f62",
00000981 => x"00000a2e",
00000982 => x"726f6241",
00000983 => x"2e646574",
00000984 => x"00000a0a",
00000985 => x"444d430a",
00000986 => x"00203e3a",
00000987 => x"53207962",
00000988 => x"68706574",
00000989 => x"4e206e61",
00000990 => x"69746c6f",
00000991 => x"0000676e",
00000992 => x"61766e49",
00000993 => x"2064696c",
00000994 => x"00444d43",
00000995 => x"33323130",
00000996 => x"37363534",
00000997 => x"42413938",
00000998 => x"46454443",
others => x"00000000"
);
 
/neorv32/trunk/rtl/core/neorv32_cfs.vhd
57,7 → 57,6
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic; -- transfer error
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
189,12 → 188,10
-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
-- for issueing commands and a <status register> for status information.
--
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal.
-- If no ACK is generated, the bus access will time out and cause a store bus access fault exception. This exception can also be immediatly
-- triggered by setting err_o high for one cycle (only during a valid bus access).
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
-- if the module needs additional time; the maximumx latency until an unacknwoledged access will trigger a bus exception is defined via the package's
-- gloabl "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception.
 
err_o <= '0'; -- not used for this minimal example
 
-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
/neorv32/trunk/rtl/core/neorv32_package.vhd
60,7 → 60,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050104"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
70,6 → 70,7
function index_size_f(input : natural) return natural;
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
function or_all_f(a : std_ulogic_vector) return std_ulogic;
function and_all_f(a : std_ulogic_vector) return std_ulogic;
164,11 → 165,11
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
 
-- Universal Asynchronous Receiver/Transmitter (UART) --
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
constant uart_size_c : natural := 2*4; -- module's address space in bytes
constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
constant uart0_size_c : natural := 2*4; -- module's address space in bytes
constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
 
-- Serial Peripheral Interface (SPI) --
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
196,9 → 197,15
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
 
-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
constant uart1_size_c : natural := 2*4; -- module's address space in bytes
constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
 
-- reserved --
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
--constant reserved_size_c : natural := 4*4; -- module's address space in bytes
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address
--constant reserved_size_c : natural := 2*4; -- module's address space in bytes
 
-- System Information Memory (SYSINFO) --
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
842,7 → 849,8
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
874,9 → 882,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
895,7 → 906,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
1407,6 → 1418,9
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
-- -------------------------------------------------------------------------------------------
component neorv32_uart
generic (
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
1571,7 → 1585,6
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic; -- transfer error
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
1631,7 → 1644,8
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
1688,8 → 1702,19
end if;
end function cond_sel_stdulogicvector_f;
 
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
-- Function: Conditional select string ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
begin
if (cond = true) then
return val_t;
else
return val_f;
end if;
end function cond_sel_string_f;
 
-- Function: Convert bool to std_ulogic ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
begin
if (cond = true) then
/neorv32/trunk/rtl/core/neorv32_spi.vhd
2,7 → 2,7
-- # << NEORV32 - Serial Peripheral Interface Controller (SPI) >> #
-- # ********************************************************************************************* #
-- # Frame format: 8/16/24/32-bit receive/transmit data, always MSB first, 2 clock modes, #
-- # 8 clock speeds (derived from system clock), 8 dedicated chip-select lines (low-active). #
-- # 8 pre-scaled clocks (derived from system clock), 8 dedicated chip-select lines (low-active). #
-- # Interrupt: SPI_transfer_done #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
/neorv32/trunk/rtl/core/neorv32_sysinfo.vhd
65,7 → 65,8
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
133,7 → 134,7
-- IO --
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented?
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_EN); -- universal asynchronous receiver/transmitter (UART) implemented?
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented?
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented?
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN); -- pulse-width modulation unit (PWM) implemented?
141,8 → 142,9
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_NCO_EN); -- numerically-controlled oscillator (NCO) implemented?
sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
--
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
sysinfo_mem(2)(31 downto 27) <= (others => '0'); -- reserved
 
-- SYSINFO(3): Cache configuration --
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
/neorv32/trunk/rtl/core/neorv32_top.vhd
52,6 → 52,7
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
 
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
61,32 → 62,41
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
 
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
 
-- Internal Instruction memory --
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
 
-- Internal Data memory --
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
 
-- Internal Cache memory --
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
 
-- External memory interface --
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
 
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
100,6 → 110,7
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
 
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
112,34 → 123,48
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
 
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
 
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
 
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
 
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
 
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
 
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
 
-- PWM (available if IO_PWM_EN = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
 
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CFS inputs conduit
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CFS outputs conduit
 
-- NCO output (available if IO_NCO_EN = true) --
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
 
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
 
-- Interrupts --
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
172,14 → 197,16
signal clk_div : std_ulogic_vector(11 downto 0);
signal clk_div_ff : std_ulogic_vector(11 downto 0);
signal clk_gen : std_ulogic_vector(07 downto 0);
signal clk_gen_en : std_ulogic_vector(07 downto 0);
--
signal wdt_cg_en : std_ulogic;
signal uart_cg_en : std_ulogic;
signal spi_cg_en : std_ulogic;
signal twi_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
signal cfs_cg_en : std_ulogic;
signal nco_cg_en : std_ulogic;
signal wdt_cg_en : std_ulogic;
signal uart0_cg_en : std_ulogic;
signal uart1_cg_en : std_ulogic;
signal spi_cg_en : std_ulogic;
signal twi_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
signal cfs_cg_en : std_ulogic;
signal nco_cg_en : std_ulogic;
 
-- bus interface --
type bus_interface_t is record
218,8 → 245,10
signal gpio_ack : std_ulogic;
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal mtime_ack : std_ulogic;
signal uart_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal uart_ack : std_ulogic;
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal uart0_ack : std_ulogic;
signal uart1_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal uart1_ack : std_ulogic;
signal spi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal spi_ack : std_ulogic;
signal twi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
231,7 → 260,6
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal trng_ack : std_ulogic;
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal cfs_err : std_ulogic;
signal cfs_ack : std_ulogic;
signal nco_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal nco_ack : std_ulogic;
244,14 → 272,16
signal fast_irq : std_ulogic_vector(15 downto 0);
signal fast_irq_ack : std_ulogic_vector(15 downto 0);
--
signal gpio_irq : std_ulogic;
signal wdt_irq : std_ulogic;
signal uart_rxd_irq : std_ulogic;
signal uart_txd_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal cfs_irq : std_ulogic;
signal cfs_irq_ack : std_ulogic;
signal gpio_irq : std_ulogic;
signal wdt_irq : std_ulogic;
signal uart0_rxd_irq : std_ulogic;
signal uart0_txd_irq : std_ulogic;
signal uart1_rxd_irq : std_ulogic;
signal uart1_txd_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal cfs_irq : std_ulogic;
signal cfs_irq_ack : std_ulogic;
 
-- misc --
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
319,9 → 349,18
if (sys_rstn = '0') then
clk_div <= (others => '0');
clk_div_ff <= (others => '0');
clk_gen_en <= (others => '0');
elsif rising_edge(clk_i) then
-- fresh clocks anyone? --
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfs_cg_en or nco_cg_en) = '1') then
clk_gen_en(0) <= wdt_cg_en;
clk_gen_en(1) <= uart0_cg_en;
clk_gen_en(2) <= uart1_cg_en;
clk_gen_en(3) <= spi_cg_en;
clk_gen_en(4) <= twi_cg_en;
clk_gen_en(5) <= pwm_cg_en;
clk_gen_en(6) <= cfs_cg_en;
clk_gen_en(7) <= nco_cg_en;
if (or_all_f(clk_gen_en) = '1') then
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
end if;
clk_div_ff <= clk_div;
421,24 → 460,24
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- fast interrupts - processor-internal --
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
fast_irq(01) <= '0'; -- reserved
fast_irq(02) <= cfs_irq; -- custom functions subsystem
fast_irq(03) <= uart_rxd_irq; -- UART data received
fast_irq(04) <= uart_txd_irq; -- UART transmission done
fast_irq(05) <= spi_irq; -- SPI transmission done
fast_irq(06) <= twi_irq; -- TWI transmission done
fast_irq(07) <= gpio_irq; -- GPIO pin-change
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
fast_irq(01) <= cfs_irq; -- custom functions subsystem
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done
fast_irq(06) <= spi_irq; -- SPI transmission done
fast_irq(07) <= twi_irq; -- TWI transmission done
fast_irq(08) <= gpio_irq; -- GPIO pin-change
fast_irq(09) <= '0'; -- reserved
 
-- fast interrupts - platform level (for custom use) --
fast_irq(08) <= soc_firq_i(0);
fast_irq(09) <= soc_firq_i(1);
fast_irq(10) <= soc_firq_i(2);
fast_irq(11) <= soc_firq_i(3);
fast_irq(12) <= soc_firq_i(4);
fast_irq(13) <= soc_firq_i(5);
fast_irq(14) <= soc_firq_i(6);
fast_irq(15) <= soc_firq_i(7);
fast_irq(10) <= soc_firq_i(0);
fast_irq(11) <= soc_firq_i(1);
fast_irq(12) <= soc_firq_i(2);
fast_irq(13) <= soc_firq_i(3);
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
 
-- IRQ acknowledge --
cfs_irq_ack <= fast_irq_ack(2);
547,15 → 586,15
);
 
-- processor bus: CPU transfer data input --
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or sysinfo_rdata);
 
-- processor bus: CPU transfer ACK input --
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or sysinfo_ack);
 
-- processor bus: CPU transfer data bus error input --
p_bus.err <= wishbone_err or cfs_err;
p_bus.err <= wishbone_err;
 
-- current CPU privilege level --
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv
733,7 → 772,6
data_i => p_bus.wdata, -- data in
data_o => cfs_rdata, -- data out
ack_o => cfs_ack, -- transfer acknowledge
err_o => cfs_err, -- transfer error
-- clock generator --
clkgen_en_o => cfs_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- "clock" inputs
752,7 → 790,6
if (IO_CFS_EN = false) generate
cfs_rdata <= (others => '0');
cfs_ack <= '0';
cfs_err <= '0';
cfs_cg_en <= '0';
cfs_irq <= '0';
cfs_out_o <= (others => '0');
855,11 → 892,14
end generate;
 
 
-- Universal Asynchronous Receiver/Transmitter (UART) -------------------------------------
-- Universal Asynchronous Receiver/Transmitter 0, Primary UART (UART0) --------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart_inst_true:
if (IO_UART_EN = true) generate
neorv32_uart_inst: neorv32_uart
neorv32_uart0_inst_true:
if (IO_UART0_EN = true) generate
neorv32_uart0_inst: neorv32_uart
generic map (
UART_PRIMARY => true -- true = primary UART (UART0), false = secondary UART (UART1)
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
867,31 → 907,71
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart_rdata, -- data out
ack_o => uart_ack, -- transfer acknowledge
data_o => uart0_rdata, -- data out
ack_o => uart0_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart_cg_en, -- enable clock generator
clkgen_en_o => uart0_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart0_txd_o,
uart_rxd_i => uart0_rxd_i,
-- interrupts --
irq_rxd_o => uart_rxd_irq, -- uart data received interrupt
irq_txd_o => uart_txd_irq -- uart transmission done interrupt
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
);
end generate;
 
neorv32_uart_inst_false:
if (IO_UART_EN = false) generate
uart_rdata <= (others => '0');
uart_ack <= '0';
uart_txd_o <= '0';
uart_cg_en <= '0';
uart_rxd_irq <= '0';
uart_txd_irq <= '0';
neorv32_uart0_inst_false:
if (IO_UART0_EN = false) generate
uart0_rdata <= (others => '0');
uart0_ack <= '0';
uart0_txd_o <= '0';
uart0_cg_en <= '0';
uart0_rxd_irq <= '0';
uart0_txd_irq <= '0';
end generate;
 
 
-- Universal Asynchronous Receiver/Transmitter 1, Secondary UART (UART1) ------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart1_inst_true:
if (IO_UART1_EN = true) generate
neorv32_uart1_inst: neorv32_uart
generic map (
UART_PRIMARY => false -- true = primary UART (UART0), false = secondary UART (UART1)
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart1_rdata, -- data out
ack_o => uart1_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart1_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart1_txd_o,
uart_rxd_i => uart1_rxd_i,
-- interrupts --
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
);
end generate;
 
neorv32_uart1_inst_false:
if (IO_UART1_EN = false) generate
uart1_rdata <= (others => '0');
uart1_ack <= '0';
uart1_txd_o <= '0';
uart1_cg_en <= '0';
uart1_rxd_irq <= '0';
uart1_txd_irq <= '0';
end generate;
 
 
-- Serial Peripheral Interface (SPI) ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_spi_inst_true:
1078,7 → 1158,8
-- Processor peripherals --
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
/neorv32/trunk/rtl/core/neorv32_uart.vhd
1,17 → 1,23
-- #################################################################################################
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> #
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> #
-- # ********************************************************************************************* #
-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, #
-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. #
-- # Interrupt: UART_RX_available or UART_TX_done #
-- # #
-- # UART0 / UART1: #
-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the #
-- # interface register addresses and simulation output setting for UART0 (UART_PRIMARY = true) #
-- # or UART1 (UART_PRIMARY = false). #
-- # #
-- # SIMULATION: #
-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write #
-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
-- # ASCII char to the simulator console. This char is also stored to a text file #
-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char #
-- # encoded value to text file "neorv32.uart.sim_mode.data.out". #
-- # ASCII char to the simulator console. #
-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 #
-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value #
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
53,6 → 59,9
use std.textio.all; -- obviously only for simulation
 
entity neorv32_uart is
generic (
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
76,14 → 85,24
 
architecture neorv32_uart_rtl of neorv32_uart is
 
-- interface configuration for UART0 / UART1 --
constant uart_id_base_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c);
constant uart_id_size_c : natural := cond_sel_natural_f( UART_PRIMARY, uart0_size_c, uart1_size_c);
constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c);
constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c);
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(uart_id_size_c); -- low address boundary bit
 
-- simulation output configuration --
constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled
constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
-- simulation output file configuration --
constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out");
constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out");
 
-- accessible regs --
signal ctrl : std_ulogic_vector(31 downto 0);
97,7 → 116,6
constant ctrl_uart_baud05_c : natural := 5; -- r/w: UART baud config bit 5
constant ctrl_uart_baud06_c : natural := 6; -- r/w: UART baud config bit 6
constant ctrl_uart_baud07_c : natural := 7; -- r/w: UART baud config bit 7
--
constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8
constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
161,8 → 179,8
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= uart_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_id_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= uart_id_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
 
175,7 → 193,7
ack_o <= acc_en and (rden_i or wren_i);
-- write access --
if (wr_en = '1') then
if (addr = uart_ctrl_addr_c) then
if (addr = uart_id_ctrl_addr_c) then
ctrl <= (others => '0');
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
187,7 → 205,7
-- read access --
data_o <= (others => '0');
if (rd_en = '1') then
if (addr = uart_ctrl_addr_c) then
if (addr = uart_id_ctrl_addr_c) then
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
194,7 → 212,7
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
else -- uart_rtx_addr_c
else -- uart_id_rtx_addr_c
data_o(data_rx_avail_c) <= uart_rx.avail(0);
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
data_o(data_rx_ferr_c) <= uart_rx.ferr;
232,7 → 250,7
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx.bitcnt <= num_bits;
uart_tx.sreg(0) <= '1';
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
else
301,7 → 319,7
 
-- RX available flag --
uart_rx.busy_ff <= uart_rx.busy;
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then -- off/RX read access
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_id_rtx_addr_c)) then -- off/RX read access
uart_rx.avail <= "00";
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done
uart_rx.avail <= uart_rx.avail(0) & '1';
321,16 → 339,16
-- SIMULATION Output ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
sim_output: process(clk_i) -- for SIMULATION ONLY!
file file_devnull_text_out : text open write_mode is "neorv32.uart.sim_mode.text.out";
file file_devnull_data_out : text open write_mode is "neorv32.uart.sim_mode.data.out";
variable char_v : integer;
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
variable line_text_v : line;
variable line_data_v : line;
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
variable char_v : integer;
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
variable line_text_v : line;
variable line_data_v : line;
begin
if rising_edge(clk_i) then
if (ctrl(ctrl_uart_en_c) = '1') and (ctrl(ctrl_uart_sim_en_c) = '1') then -- UART enabled and simulation output selected?
if (wr_en = '1') and (addr = uart_rtx_addr_c) then -- write access to tx register
if (wr_en = '1') and (addr = uart_id_rtx_addr_c) then -- write access to tx register
-- print lowest byte to ASCII char --
char_v := to_integer(unsigned(data_i(7 downto 0)));
352,7 → 370,7
writeline(output, line_screen_v);
end if;
if (sim_text_output_en_c = true) then
writeline(file_devnull_text_out, line_text_v);
writeline(file_uart_text_out, line_text_v);
end if;
end if;
 
361,7 → 379,7
for x in 7 downto 0 loop
write(line_data_v, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form
end loop; -- x
writeline(file_devnull_data_out, line_data_v);
writeline(file_uart_data_out, line_data_v);
end if;
 
end if;
/neorv32/trunk/rtl/top_templates/neorv32_test_setup.vhd
47,13 → 47,13
entity neorv32_test_setup is
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0' -- UART receive data
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART0 --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data
);
end neorv32_test_setup;
 
107,7 → 107,8
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART_EN => true, -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => false, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => false, -- implement two-wire interface (TWI)?
IO_PWM_EN => false, -- implement pulse-width modulation unit (PWM)?
139,9 → 140,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio_out, -- parallel output
gpio_i => (others => '0'), -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o => uart_txd_o, -- UART send data
uart_rxd_i => uart_rxd_i, -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o, -- UART0 send data
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => open, -- UART1 send data
uart1_rxd_i => '0', -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => open, -- SPI serial clock
spi_sdo_o => open, -- controller data out, peripheral data in
/neorv32/trunk/rtl/top_templates/neorv32_top_axi4lite.vhd
83,7 → 83,8
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
130,9 → 131,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_logic_vector(31 downto 0); -- parallel output
gpio_i : in std_logic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic := '0'; -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_logic; -- UART0 send data
uart0_rxd_i : in std_logic := '0'; -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_logic; -- UART1 send data
uart1_rxd_i : in std_logic := '0'; -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_logic; -- SPI serial clock
spi_sdo_o : out std_logic; -- controller data out, peripheral data in
149,7 → 153,7
-- NCO output (available if IO_NCO_EN = true) --
nco_o : out std_logic_vector(02 downto 0); -- numerically-controlled oscillator channels
-- Interrupts --
soc_firq_i : in std_logic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
soc_firq_i : in std_logic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_logic := '0'; -- machine software interrupt
mext_irq_i : in std_logic := '0' -- machine external interrupt
168,8 → 172,10
signal gpio_o_int : std_ulogic_vector(31 downto 0);
signal gpio_i_int : std_ulogic_vector(31 downto 0);
--
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal uart0_txd_o_int : std_ulogic;
signal uart0_rxd_i_int : std_ulogic;
signal uart1_txd_o_int : std_ulogic;
signal uart1_rxd_i_int : std_ulogic;
--
signal spi_sck_o_int : std_ulogic;
signal spi_sdo_o_int : std_ulogic;
183,7 → 189,7
--
signal nco_o_int : std_ulogic_vector(02 downto 0);
--
signal soc_firq_i_int : std_ulogic_vector(7 downto 0);
signal soc_firq_i_int : std_ulogic_vector(05 downto 0);
signal mtime_irq_i_int : std_ulogic;
signal msw_irq_i_int : std_ulogic;
signal mext_irq_i_int : std_ulogic;
265,7 → 271,8
-- Processor peripherals --
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
297,9 → 304,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o_int, -- UART0 send data
uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => uart1_txd_o_int, -- UART1 send data
uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => spi_sck_o_int, -- SPI serial clock
spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in
325,27 → 335,29
);
 
-- type conversion --
gpio_o <= std_logic_vector(gpio_o_int);
gpio_i_int <= std_ulogic_vector(gpio_i);
gpio_o <= std_logic_vector(gpio_o_int);
gpio_i_int <= std_ulogic_vector(gpio_i);
 
uart_txd_o <= std_logic(uart_txd_o_int);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
uart0_txd_o <= std_logic(uart0_txd_o_int);
uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
uart1_txd_o <= std_logic(uart0_txd_o_int);
uart1_rxd_i_int <= std_ulogic(uart0_rxd_i);
 
spi_sck_o <= std_logic(spi_sck_o_int);
spi_sdo_o <= std_logic(spi_sdo_o_int);
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
spi_csn_o <= std_logic_vector(spi_csn_o_int);
spi_sck_o <= std_logic(spi_sck_o_int);
spi_sdo_o <= std_logic(spi_sdo_o_int);
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
spi_csn_o <= std_logic_vector(spi_csn_o_int);
 
pwm_o <= std_logic_vector(pwm_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
 
cfs_in_i_int <= std_ulogic_vector(cfs_in_i);
cfs_out_o <= std_logic_vector(cfs_out_o_int);
cfs_in_i_int <= std_ulogic_vector(cfs_in_i);
cfs_out_o <= std_logic_vector(cfs_out_o_int);
 
nco_o <= std_logic_vector(nco_o_int);
nco_o <= std_logic_vector(nco_o_int);
 
soc_firq_i_int <= std_ulogic_vector(soc_firq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);
soc_firq_i_int <= std_ulogic_vector(soc_firq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);
 
-- Wishbone to AXI4-Lite Bridge -----------------------------------------------------------
/neorv32/trunk/rtl/top_templates/neorv32_top_stdlogic.vhd
80,7 → 80,8
-- Processor peripherals --
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
112,9 → 113,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_logic_vector(31 downto 0); -- parallel output
gpio_i : in std_logic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic := '0'; -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_logic; -- UART0 send data
uart0_rxd_i : in std_logic := '0'; -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_logic; -- UART1 send data
uart1_rxd_i : in std_logic := '0'; -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_logic; -- SPI serial clock
spi_sdo_o : out std_logic; -- controller data out, peripheral data in
133,7 → 137,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
soc_firq_i : in std_logic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
soc_firq_i : in std_logic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_logic := '0'; -- machine software interrupt
mext_irq_i : in std_logic := '0' -- machine external interrupt
167,8 → 171,10
signal gpio_o_int : std_ulogic_vector(31 downto 0);
signal gpio_i_int : std_ulogic_vector(31 downto 0);
--
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal uart0_txd_o_int : std_ulogic;
signal uart0_rxd_i_int : std_ulogic;
signal uart1_txd_o_int : std_ulogic;
signal uart1_rxd_i_int : std_ulogic;
--
signal spi_sck_o_int : std_ulogic;
signal spi_sdo_o_int : std_ulogic;
184,7 → 190,7
--
signal mtime_i_int : std_ulogic_vector(63 downto 0);
--
signal soc_firq_i_int : std_ulogic_vector(7 downto 0);
signal soc_firq_i_int : std_ulogic_vector(05 downto 0);
signal mtime_irq_i_int : std_ulogic;
signal msw_irq_i_int : std_ulogic;
signal mext_irq_i_int : std_ulogic;
234,7 → 240,8
-- Processor peripherals --
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
266,9 → 273,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o_int, -- UART0 send data
uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => uart1_txd_o_int, -- UART1 send data
uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => spi_sck_o_int, -- SPI serial clock
spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in
294,47 → 304,49
);
 
-- type conversion --
clk_i_int <= std_ulogic(clk_i);
rstn_i_int <= std_ulogic(rstn_i);
clk_i_int <= std_ulogic(clk_i);
rstn_i_int <= std_ulogic(rstn_i);
 
wb_tag_o <= std_logic_vector(wb_tag_o_int);
wb_adr_o <= std_logic_vector(wb_adr_o_int);
wb_dat_i_int <= std_ulogic_vector(wb_dat_i);
wb_dat_o <= std_logic_vector(wb_dat_o_int);
wb_we_o <= std_logic(wb_we_o_int);
wb_sel_o <= std_logic_vector(wb_sel_o_int);
wb_stb_o <= std_logic(wb_stb_o_int);
wb_cyc_o <= std_logic(wb_cyc_o_int);
wb_lock_o <= std_logic(wb_lock_o_int);
wb_ack_i_int <= std_ulogic(wb_ack_i);
wb_err_i_int <= std_ulogic(wb_err_i);
wb_tag_o <= std_logic_vector(wb_tag_o_int);
wb_adr_o <= std_logic_vector(wb_adr_o_int);
wb_dat_i_int <= std_ulogic_vector(wb_dat_i);
wb_dat_o <= std_logic_vector(wb_dat_o_int);
wb_we_o <= std_logic(wb_we_o_int);
wb_sel_o <= std_logic_vector(wb_sel_o_int);
wb_stb_o <= std_logic(wb_stb_o_int);
wb_cyc_o <= std_logic(wb_cyc_o_int);
wb_lock_o <= std_logic(wb_lock_o_int);
wb_ack_i_int <= std_ulogic(wb_ack_i);
wb_err_i_int <= std_ulogic(wb_err_i);
 
fence_o <= std_logic(fence_o_int);
fencei_o <= std_logic(fencei_o_int);
fence_o <= std_logic(fence_o_int);
fencei_o <= std_logic(fencei_o_int);
 
gpio_o <= std_logic_vector(gpio_o_int);
gpio_i_int <= std_ulogic_vector(gpio_i);
gpio_o <= std_logic_vector(gpio_o_int);
gpio_i_int <= std_ulogic_vector(gpio_i);
 
uart_txd_o <= std_logic(uart_txd_o_int);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
uart0_txd_o <= std_logic(uart0_txd_o_int);
uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
uart1_txd_o <= std_logic(uart1_txd_o_int);
uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
 
spi_sck_o <= std_logic(spi_sck_o_int);
spi_sdo_o <= std_logic(spi_sdo_o_int);
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
spi_csn_o <= std_logic_vector(spi_csn_o_int);
spi_sck_o <= std_logic(spi_sck_o_int);
spi_sdo_o <= std_logic(spi_sdo_o_int);
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
spi_csn_o <= std_logic_vector(spi_csn_o_int);
 
pwm_o <= std_logic_vector(pwm_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
 
cfs_in_i_int <= std_ulogic_vector(cfs_in_i);
cfs_out_o <= std_logic_vector(cfs_out_o_int);
cfs_in_i_int <= std_ulogic_vector(cfs_in_i);
cfs_out_o <= std_logic_vector(cfs_out_o_int);
 
nco_o <= std_logic_vector(nco_o_int);
nco_o <= std_logic_vector(nco_o_int);
 
mtime_i_int <= std_ulogic_vector(mtime_i);
mtime_i_int <= std_ulogic_vector(mtime_i);
 
soc_firq_i_int <= std_ulogic_vector(soc_firq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);
soc_firq_i_int <= std_ulogic_vector(soc_firq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);
 
 
end neorv32_top_stdlogic_rtl;
/neorv32/trunk/sim/ghdl/ghdl_sim.sh
4,7 → 4,7
set -e
 
# Default simulation configuration
SIM_CONFIG=--stop-time=6ms
SIM_CONFIG=--stop-time=7ms
 
# Project home folder
homedir="$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
72,14 → 72,26
#
ghdl -a --work=neorv32 $srcdir_sim/neorv32_tb.vhd
 
# Prepare simulation output files
touch neorv32.testbench_uart.out
chmod 777 neorv32.testbench_uart.out
touch neorv32.uart.sim_mode.text.out
chmod 777 neorv32.uart.sim_mode.text.out
touch neorv32.uart.sim_mode.data.out
chmod 777 neorv32.uart.sim_mode.data.out
# Prepare simulation output files for UART0
# Testbench receiver log file
touch neorv32.testbench_uart0.out
chmod 777 neorv32.testbench_uart0.out
# UART0 direct simulation output
touch neorv32.uart0.sim_mode.text.out
chmod 777 neorv32.uart0.sim_mode.text.out
touch neorv32.uart0.sim_mode.data.out
chmod 777 neorv32.uart0.sim_mode.data.out
 
# Prepare simulation output files for UART1
# Testbench receiver log file
touch neorv32.testbench_uart1.out
chmod 777 neorv32.testbench_uart1.out
# UART1 direct simulation output
touch neorv32.uart1.sim_mode.text.out
chmod 777 neorv32.uart1.sim_mode.text.out
touch neorv32.uart1.sim_mode.data.out
chmod 777 neorv32.uart1.sim_mode.data.out
 
# Run simulation
ghdl -e --work=neorv32 neorv32_tb
ghdl -r --work=neorv32 neorv32_tb --max-stack-alloc=0 --ieee-asserts=disable --assert-level=error $SIM_CONFIG
/neorv32/trunk/sim/vivado/neorv32_tb_behav.wcfg
12,13 → 12,13
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="78970416fs"></ZoomStartTime>
<ZoomEndTime time="79485917fs"></ZoomEndTime>
<Cursor1Time time="79325000fs"></Cursor1Time>
<ZoomStartTime time="52817125fs"></ZoomStartTime>
<ZoomEndTime time="52920626fs"></ZoomEndTime>
<Cursor1Time time="52850225fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="203"></NameColumnWidth>
<ValueColumnWidth column_width="88"></ValueColumnWidth>
<ValueColumnWidth column_width="84"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="133" />
<wave_markers>
117,8 → 117,8
<obj_property name="ObjectShortName">be_store_i</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ctrl_o" type="array">
<obj_property name="ElementShortName">ctrl_o[69:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_o[69:0]</obj_property>
<obj_property name="ElementShortName">ctrl_o[68:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_o[68:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ci_instr32" type="array">
<obj_property name="ElementShortName">ci_instr32[31:0]</obj_property>
148,6 → 148,90
<obj_property name="ElementShortName">execute_engine</obj_property>
<obj_property name="ObjectShortName">execute_engine</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other">
<obj_property name="ElementShortName">.state</obj_property>
<obj_property name="ObjectShortName">.state</obj_property>
<obj_property name="CustomSignalColor">#FFFFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other">
<obj_property name="ElementShortName">.state_nxt</obj_property>
<obj_property name="ObjectShortName">.state_nxt</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_prev" type="other">
<obj_property name="ElementShortName">.state_prev</obj_property>
<obj_property name="ObjectShortName">.state_prev</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array">
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property>
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array">
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property>
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_last" type="array">
<obj_property name="ElementShortName">.i_reg_last[31:0]</obj_property>
<obj_property name="ObjectShortName">.i_reg_last[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic">
<obj_property name="ElementShortName">.is_ci</obj_property>
<obj_property name="ObjectShortName">.is_ci</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic">
<obj_property name="ElementShortName">.is_ci_nxt</obj_property>
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_cp_op" type="logic">
<obj_property name="ElementShortName">.is_cp_op</obj_property>
<obj_property name="ObjectShortName">.is_cp_op</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_cp_op_nxt" type="logic">
<obj_property name="ElementShortName">.is_cp_op_nxt</obj_property>
<obj_property name="ObjectShortName">.is_cp_op_nxt</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic">
<obj_property name="ElementShortName">.branch_taken</obj_property>
<obj_property name="ObjectShortName">.branch_taken</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array">
<obj_property name="ElementShortName">.pc[31:0]</obj_property>
<obj_property name="ObjectShortName">.pc[31:0]</obj_property>
<obj_property name="CustomSignalColor">#FFFFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_mux_sel" type="array">
<obj_property name="ElementShortName">.pc_mux_sel[1:0]</obj_property>
<obj_property name="ObjectShortName">.pc_mux_sel[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_we" type="logic">
<obj_property name="ElementShortName">.pc_we</obj_property>
<obj_property name="ObjectShortName">.pc_we</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array">
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property>
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array">
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property>
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep" type="logic">
<obj_property name="ElementShortName">.sleep</obj_property>
<obj_property name="ObjectShortName">.sleep</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep_nxt" type="logic">
<obj_property name="ElementShortName">.sleep_nxt</obj_property>
<obj_property name="ObjectShortName">.sleep_nxt</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.if_rst" type="logic">
<obj_property name="ElementShortName">.if_rst</obj_property>
<obj_property name="ObjectShortName">.if_rst</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.if_rst_nxt" type="logic">
<obj_property name="ElementShortName">.if_rst_nxt</obj_property>
<obj_property name="ObjectShortName">.if_rst_nxt</obj_property>
</wvobject>
</wvobject>
<wvobject type="divider" fp_name="divider139">
<obj_property name="label">CPU: Control.ATOMICS</obj_property>
/neorv32/trunk/sim/neorv32_tb.vhd
60,7 → 60,8
constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
constant f_clock_c : natural := 100000000; -- main clock in Hz
constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
constant baud0_rate_c : natural := 19200; -- simulation UART0 (primary UART) baud rate
constant baud1_rate_c : natural := 19200; -- simulation UART1 (secondary UART) baud rate
-- simulated external Wishbone memory A (can be used as external IMEM) --
constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
78,25 → 79,35
-- -------------------------------------------------------------------------------------------
 
-- internals - hands off! --
constant int_imem_c : boolean := not ext_imem_c;
constant int_dmem_c : boolean := not ext_dmem_c;
constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
constant t_clock_c : time := (1 sec) / f_clock_c;
constant int_imem_c : boolean := not ext_imem_c;
constant int_dmem_c : boolean := not ext_dmem_c;
constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c);
constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c);
constant t_clock_c : time := (1 sec) / f_clock_c;
 
-- text.io --
file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
 
-- generators --
signal clk_gen, rst_gen : std_ulogic := '0';
 
-- simulation uart receiver --
signal uart_txd : std_ulogic;
signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
signal uart_rx_busy : std_ulogic := '0';
signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
signal uart_rx_baud_cnt : real;
signal uart_rx_bitcnt : natural;
-- text.io --
file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
file file_uart1_tx_out : text open write_mode is "neorv32.testbench_uart1.out";
 
-- simulation uart0 receiver --
signal uart0_txd : std_ulogic;
signal uart0_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
signal uart0_rx_busy : std_ulogic := '0';
signal uart0_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
signal uart0_rx_baud_cnt : real;
signal uart0_rx_bitcnt : natural;
 
-- simulation uart1 receiver --
signal uart1_txd : std_ulogic;
signal uart1_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
signal uart1_rx_busy : std_ulogic := '0';
signal uart1_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
signal uart1_rx_baud_cnt : real;
signal uart1_rx_bitcnt : natural;
 
-- gpio --
signal gpio : std_ulogic_vector(31 downto 0);
 
108,7 → 119,7
 
-- irq --
signal msi_ring, mei_ring : std_ulogic;
signal soc_firq_ring : std_ulogic_vector(7 downto 0);
signal soc_firq_ring : std_ulogic_vector(5 downto 0);
 
-- Wishbone bus --
type wishbone_t is record
211,7 → 222,8
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART_EN => true, -- implement universal asynchronous receiver/transmitter (UART)?
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => true, -- implement two-wire interface (TWI)?
IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
243,9 → 255,12
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio, -- parallel output
gpio_i => gpio, -- parallel input
-- UART (available if IO_UART_EN = true) --
uart_txd_o => uart_txd, -- UART send data
uart_rxd_i => uart_txd, -- UART receive data
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd, -- UART0 send data
uart0_rxd_i => uart0_txd, -- UART0 receive data
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => uart1_txd, -- UART1 send data
uart1_rxd_i => uart1_txd, -- UART1 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => open, -- SPI serial clock
spi_sdo_o => spi_data, -- controller data out, peripheral data in
275,9 → 290,9
twi_sda <= 'H';
 
 
-- Console UART Receiver ------------------------------------------------------------------
-- Console UART0 Receiver -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
uart_rx_console: process(clk_gen)
uart0_rx_console: process(clk_gen)
variable i : integer;
variable l : line;
begin
284,49 → 299,101
-- "UART" --
if rising_edge(clk_gen) then
-- synchronizer --
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
uart0_rx_sync <= uart0_rx_sync(3 downto 0) & uart0_txd;
-- arbiter --
if (uart_rx_busy = '0') then -- idle
uart_rx_busy <= '0';
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
uart_rx_bitcnt <= 9;
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
uart_rx_busy <= '1';
if (uart0_rx_busy = '0') then -- idle
uart0_rx_busy <= '0';
uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
uart0_rx_bitcnt <= 9;
if (uart0_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
uart0_rx_busy <= '1';
end if;
else
if (uart_rx_baud_cnt <= 0.0) then
if (uart_rx_bitcnt = 1) then
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
if (uart0_rx_baud_cnt <= 0.0) then
if (uart0_rx_bitcnt = 1) then
uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
else
uart_rx_baud_cnt <= round(baud_val_c);
uart0_rx_baud_cnt <= round(uart0_baud_val_c);
end if;
if (uart_rx_bitcnt = 0) then
uart_rx_busy <= '0'; -- done
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
if (uart0_rx_bitcnt = 0) then
uart0_rx_busy <= '0'; -- done
i := to_integer(unsigned(uart0_rx_sreg(8 downto 1)));
 
if (i < 32) or (i > 32+95) then -- printable char?
report "NEORV32_TB_UART.TX: (" & integer'image(i) & ")"; -- print code
report "NEORV32_TB_UART0.TX: (" & integer'image(i) & ")"; -- print code
else
report "NEORV32_TB_UART.TX: " & character'val(i); -- print ASCII
report "NEORV32_TB_UART0.TX: " & character'val(i); -- print ASCII
end if;
 
if (i = 10) then -- Linux line break
writeline(file_uart_tx_out, l);
writeline(file_uart0_tx_out, l);
elsif (i /= 13) then -- Remove additional carriage return
write(l, character'val(i));
end if;
else
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
uart0_rx_sreg <= uart0_rx_sync(4) & uart0_rx_sreg(8 downto 1);
uart0_rx_bitcnt <= uart0_rx_bitcnt - 1;
end if;
else
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
uart0_rx_baud_cnt <= uart0_rx_baud_cnt - 1.0;
end if;
end if;
end if;
end process uart_rx_console;
end process uart0_rx_console;
 
 
-- Console UART1 Receiver -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
uart1_rx_console: process(clk_gen)
variable i : integer;
variable l : line;
begin
-- "UART" --
if rising_edge(clk_gen) then
-- synchronizer --
uart1_rx_sync <= uart1_rx_sync(3 downto 0) & uart1_txd;
-- arbiter --
if (uart1_rx_busy = '0') then -- idle
uart1_rx_busy <= '0';
uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
uart1_rx_bitcnt <= 9;
if (uart1_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
uart1_rx_busy <= '1';
end if;
else
if (uart1_rx_baud_cnt <= 0.0) then
if (uart1_rx_bitcnt = 1) then
uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
else
uart1_rx_baud_cnt <= round(uart1_baud_val_c);
end if;
if (uart1_rx_bitcnt = 0) then
uart1_rx_busy <= '0'; -- done
i := to_integer(unsigned(uart1_rx_sreg(8 downto 1)));
 
if (i < 32) or (i > 32+95) then -- printable char?
report "NEORV32_TB_UART1.TX: (" & integer'image(i) & ")"; -- print code
else
report "NEORV32_TB_UART1.TX: " & character'val(i); -- print ASCII
end if;
 
if (i = 10) then -- Linux line break
writeline(file_uart1_tx_out, l);
elsif (i /= 13) then -- Remove additional carriage return
write(l, character'val(i));
end if;
else
uart1_rx_sreg <= uart1_rx_sync(4) & uart1_rx_sreg(8 downto 1);
uart1_rx_bitcnt <= uart1_rx_bitcnt - 1;
end if;
else
uart1_rx_baud_cnt <= uart1_rx_baud_cnt - 1.0;
end if;
end if;
end if;
end process uart1_rx_console;
 
 
-- Wishbone Fabric ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- CPU broadcast signals --
512,14 → 579,13
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
msi_ring <= wb_irq.wdata(03); -- machine software interrupt
mei_ring <= wb_irq.wdata(11); -- machine software interrupt
soc_firq_ring(0) <= wb_irq.wdata(24); -- fast interrupt SoC channel 0
soc_firq_ring(1) <= wb_irq.wdata(25); -- fast interrupt SoC channel 1
soc_firq_ring(2) <= wb_irq.wdata(26); -- fast interrupt SoC channel 2
soc_firq_ring(3) <= wb_irq.wdata(27); -- fast interrupt SoC channel 3
soc_firq_ring(4) <= wb_irq.wdata(28); -- fast interrupt SoC channel 4
soc_firq_ring(5) <= wb_irq.wdata(29); -- fast interrupt SoC channel 5
soc_firq_ring(6) <= wb_irq.wdata(30); -- fast interrupt SoC channel 6
soc_firq_ring(7) <= wb_irq.wdata(31); -- fast interrupt SoC channel 7
--
soc_firq_ring(0) <= wb_irq.wdata(26); -- fast interrupt SoC channel 0 (-> FIRQ channel 10)
soc_firq_ring(1) <= wb_irq.wdata(27); -- fast interrupt SoC channel 1 (-> FIRQ channel 11)
soc_firq_ring(2) <= wb_irq.wdata(28); -- fast interrupt SoC channel 2 (-> FIRQ channel 12)
soc_firq_ring(3) <= wb_irq.wdata(29); -- fast interrupt SoC channel 3 (-> FIRQ channel 13)
soc_firq_ring(4) <= wb_irq.wdata(30); -- fast interrupt SoC channel 4 (-> FIRQ channel 14)
soc_firq_ring(5) <= wb_irq.wdata(31); -- fast interrupt SoC channel 5 (-> FIRQ channel 15)
end if;
end if;
end process irq_trigger;
/neorv32/trunk/sw/bootloader/bootloader.c
6,6 → 6,8
// # ********************************************************************************************* #
// # Boot from (internal) instruction memory, UART or SPI Flash. #
// # #
// # The bootloader uses the primary UART (UART0) for user console interface. #
// # #
// # UART configuration: 8 data bits, NO parity bit, 1 stop bit, 19200 baud (19200-8N1) #
// # Boot Flash: 8-bit SPI, 24-bit addresses (like Micron N25Q032A) @ neorv32.spi_csn_o(0) #
// # neorv32.gpio_o(0) is used as high-active status LED (can be disabled via #STATUS_LED_EN). #
283,7 → 285,7
 
uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTOBOOT_TIMEOUT * clock_speed);
 
while ((UART_DATA & (1 << UART_DATA_AVAIL)) == 0) { // wait for any key to be pressed
while (neorv32_uart_char_received() == 0) { // wait for any key to be pressed
 
if (neorv32_mtime_get_time() >= timeout_time) { // timeout? start auto boot sequence
fast_upload(EXE_STREAM_FLASH); // try booting from flash
395,7 → 397,7
neorv32_uart_print("Booting...\n\n");
 
// wait for UART to finish transmitting
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
while (neorv32_uart_tx_busy());
 
// start app at instruction space base address
register uint32_t app_base = SYSINFO_ISPACE_BASE;
/neorv32/trunk/sw/example/blink_led/main.c
73,7 → 73,7
**************************************************************************/
int main() {
 
// init UART at default baud rate, no parity bits
// init UART (primary UART = UART0; if no id number is specified the primary UART is used) at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check if GPIO unit is implemented at all
/neorv32/trunk/sw/example/cpu_test/main.c
108,6 → 108,7
register uint32_t tmp_a, tmp_b;
volatile uint32_t dummy_dst __attribute__((unused));
uint8_t id;
uint32_t is_simulation = 0;
 
 
// init UART at default baud rate, no parity bits
123,6 → 124,14
return 0;
#endif
 
// check if this is a simulation (using primary UART0)
if (UART0_CT & (1 << UART_CT_SIM_MODE)) {
is_simulation = 1;
}
else {
is_simulation = 0;
}
 
neorv32_uart_printf("\n<< CPU/PROCESSOR TEST >>\n");
neorv32_uart_printf("build: "__DATE__" "__TIME__"\n");
 
152,9 → 161,8
neorv32_mtime_set_timecmp(mtime_cmp_max);
 
 
// intro
// fancy intro
// -----------------------------------------------
 
// logo
neorv32_rte_print_logo();
 
388,7 → 396,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] External memory access (@ 0x%x) test: ", cnt_test, (uint32_t)EXT_MEM_BASE);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)) {
cnt_test++;
 
429,12 → 437,12
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
/*
// ----------------------------------------------------------
// Test FENCE.I instruction (instruction buffer / i-cache clear & reload)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Testing FENCE.I operation: ", cnt_test);
neorv32_uart_printf("[%i] FENCE.I test: ", cnt_test);
 
// check if implemented
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1 << CSR_MZEXT_ZIFENCEI)) {
453,8 → 461,8
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
*/
 
 
// ----------------------------------------------------------
// Illegal CSR access (CSR not implemented)
// ----------------------------------------------------------
601,7 → 609,7
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ALIGN (instruction alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ALIGN (instr. alignment) exception test: ", cnt_test);
 
// skip if C-mode is implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) == 0) {
629,7 → 637,7
// Instruction access fault
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ACC (instruction bus access) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ACC (instr. bus access) exception test: ", cnt_test);
cnt_test++;
 
// call unreachable aligned address
647,7 → 655,7
// Illegal instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ILLEG (illegal instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ILLEG (illegal instr.) exception test: ", cnt_test);
 
cnt_test++;
 
673,7 → 681,7
// Illegal compressed instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compressed instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compr. instr.) exception test: ", cnt_test);
 
// skip if C-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) != 0) {
705,7 → 713,7
// Breakpoint instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] BREAK (break instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] BREAK (break instr.) exception test: ", cnt_test);
cnt_test++;
 
asm volatile("EBREAK");
722,7 → 730,7
// Unaligned load address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] L_ALIGN (load address alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] L_ALIGN (load addr alignment) exception test: ", cnt_test);
cnt_test++;
 
// load from unaligned address
758,7 → 766,7
// Unaligned store address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] S_ALIGN (store address alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] S_ALIGN (store addr alignment) exception test: ", cnt_test);
cnt_test++;
 
// store to unaligned address
794,7 → 802,7
// Environment call from M-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from M-mode exception test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from M-mode exception test: ", cnt_test);
cnt_test++;
 
asm volatile("ECALL");
811,7 → 819,7
// Environment call from U-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from U-mode exception test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from U-mode exception test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
874,7 → 882,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MSI (via testbench) interrupt test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// trigger IRQ
902,7 → 910,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MEI (via testbench) interrupt test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// trigger IRQ
964,45 → 972,38
 
 
// ----------------------------------------------------------
// Fast interrupt channel 1 (reserved)
// Fast interrupt channel 1 (CFS)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ1 test (reserved): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ1 test (via CFS): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 2 (CFS)
// Fast interrupt channel 2 (UART0.RX)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ2 test (via CFS): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 3 (UART.RX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ3 test (via UART.RX): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ2 test (via UART0.RX): ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E);
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
uint32_t uart_ct_backup = UART_CT;
// backup current UART0 configuration
tmp_a = UART0_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
// disable UART0 sim_mode if it is enabled
UART0_CT &= ~(1 << UART_CT_SIM_MODE);
 
// trigger UART RX IRQ
// the default test bench connects UART.TXD_O to UART_RXD_I
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
// trigger UART0 RX IRQ
// the default test bench connects UART0.TXD_O to UART0_RXD_I
UART0_DATA = 0; // we need to access the raw HW here, since >UART0_SIM_MODE< might be active
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
1009,13 → 1010,13
asm volatile("nop");
asm volatile("nop");
 
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
// re-enable UART0 sim_mode if it was enabled
UART0_CT = tmp_a;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ2E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_2) {
test_ok();
}
else {
1028,27 → 1029,27
 
 
// ----------------------------------------------------------
// Fast interrupt channel 4 (UART.TX)
// Fast interrupt channel 3 (UART0.TX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ4 test (via UART.TX): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ3 test (via UART0.TX): ", cnt_test);
 
cnt_test++;
 
// UART TX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
// UART0 TX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
volatile uint32_t uart_ct_backup = UART_CT;
// backup current UART0 configuration
tmp_a = UART0_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
// disable UART0 sim_mode if it is enabled
UART0_CT &= ~(1 << UART_CT_SIM_MODE);
 
// trigger UART TX IRQ
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
// trigger UART0 TX IRQ
UART0_DATA = 0; // we need to access the raw HW here, since >UART0_SIM_MODE< might be active
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
1058,11 → 1059,11
asm volatile("nop");
 
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
UART0_CT = tmp_a;
 
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
test_ok();
}
else {
1071,16 → 1072,108
 
 
// ----------------------------------------------------------
// Fast interrupt channel 5 (SPI)
// Fast interrupt channel 4 (UART1.RX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ5 test (via SPI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ4 test (via UART1.RX): ", cnt_test);
 
if (neorv32_uart1_available()) {
cnt_test++;
 
// UART1 RX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
 
// initialize UART1
UART1_CT = 0;
tmp_a = UART0_CT; // copy configuration from UART0
tmp_a &= ~(1 << UART_CT_SIM_MODE); // make sure sim_mode is disabled
UART1_CT = tmp_a;
 
// trigger UART1 RX IRQ
UART1_DATA = 0;
 
// wait for UART1 to finish transmitting
while(neorv32_uart1_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// disable UART1
UART1_CT = 0;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 5 (UART1.TX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ5 test (via UART1.TX): ", cnt_test);
 
if (neorv32_uart1_available()) {
cnt_test++;
 
// UART1 RX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
 
// initialize UART1
UART1_CT = 0;
tmp_a = UART0_CT; // copy configuration from UART0
tmp_a &= ~(1 << UART_CT_SIM_MODE); // make sure sim_mode is disabled
UART1_CT = tmp_a;
 
// trigger UART1 TX IRQ
UART1_DATA = 0;
 
// wait for UART1 to finish transmitting
while(neorv32_uart1_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// disable UART1
UART1_CT = 0;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 6 (SPI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ6 test (via SPI): ", cnt_test);
 
if (neorv32_spi_available()) {
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
 
// configure SPI
neorv32_spi_setup(CLK_PRSC_2, 0, 0);
1093,7 → 1186,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
test_ok();
}
else {
1104,7 → 1197,7
neorv32_spi_disable();
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1112,10 → 1205,10
 
 
// ----------------------------------------------------------
// Fast interrupt channel 6 (TWI)
// Fast interrupt channel 7 (TWI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ6 test (via TWI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ7 test (via TWI): ", cnt_test);
 
if (neorv32_twi_available()) {
cnt_test++;
1123,7 → 1216,7
// configure TWI, fastest clock, no peripheral clock stretching
neorv32_twi_setup(CLK_PRSC_2, 0);
 
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
 
// trigger TWI IRQ
neorv32_twi_generate_start();
1134,7 → 1227,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
test_ok();
}
else {
1143,7 → 1236,7
 
// disable TWI
neorv32_twi_disable();
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1151,12 → 1244,12
 
 
// ----------------------------------------------------------
// Fast interrupt channel 7 (GPIO)
// Fast interrupt channel 8 (GPIO)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ7 test (via GPIO): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ8 test (via GPIO): ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
if (neorv32_gpio_available()) {
cnt_test++;
 
1163,7 → 1256,7
// clear output port
neorv32_gpio_port_set(0);
 
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ8E);
 
// configure GPIO.in(31) for pin-change IRQ
neorv32_gpio_pin_change_config(0x80000000);
1176,7 → 1269,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_8) {
test_ok();
}
else {
1188,7 → 1281,7
 
// clear output port
neorv32_gpio_port_set(0);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ8E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1200,24 → 1293,30
 
 
// ----------------------------------------------------------
// Fast interrupt channel 8..15 (SoC fast IRQ 0..7)
// Fast interrupt channel 9 (reserved)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ9 test: ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 10..15 (SoC fast IRQ 0..5)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ8..15 (SoC fast IRQ 0..7; via testbench) test: ", cnt_test);
neorv32_uart_printf("[%i] FIRQ10..15 (SoC fast IRQ 0..5; via testbench) test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
cnt_test++;
 
// enable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
for (id=CSR_MIE_FIRQ10E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_enable(id);
}
 
// trigger all SoC Fast interrupts at once
neorv32_cpu_dint(); // do not fire yet!
sim_irq_trigger((1 << CSR_MIE_FIRQ8E) | (1 << CSR_MIE_FIRQ9E) | (1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) |
(1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E));
sim_irq_trigger((1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) | (1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E));
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
1224,8 → 1323,7
asm volatile("nop");
 
// make sure all SoC FIRQs have been triggered
tmp_a = (1 << CSR_MIP_FIRQ8P) | (1 << CSR_MIP_FIRQ9P) | (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) |
(1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P);
tmp_a = (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) | (1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P);
 
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) {
neorv32_cpu_eint(); // allow IRQs to fire again
1242,7 → 1340,7
}
 
// disable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
for (id=CSR_MIE_FIRQ10E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_disable(id);
}
}
1257,7 → 1355,7
// Test WFI ("sleep") instructions, wakeup via MTIME
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] WFI (wait for interrupt / sleep instruction) test (wake-up via MTIME): ", cnt_test);
neorv32_uart_printf("[%i] WFI (sleep instruction) test (wake-up via MTIME): ", cnt_test);
 
if (neorv32_mtime_available()) {
cnt_test++;
1349,7 → 1447,7
// ----------------------------------------------------------
// Test physical memory protection
// ----------------------------------------------------------
neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
neorv32_uart_printf("[%i] PMP - Physical memory protection: ", cnt_test);
 
// check if PMP is implemented
if (neorv32_cpu_pmp_get_num_regions() != 0) {
1377,7 → 1475,7
 
 
// ------ EXECUTE: should fail ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] execute test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] execute test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1402,7 → 1500,7
 
 
// ------ LOAD: should work ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] read test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] read test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1427,7 → 1525,7
 
 
// ------ STORE: should fail ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] write test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] write test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1451,8 → 1549,8
}
 
 
// ------ Lock test - pmpcfg0.0 ------
neorv32_uart_printf("[%i] - PMP: pmpcfg0.0 [mode=off] lock test: ", cnt_test);
// ------ Lock test - pmpcfg0.0 / pmpaddr0 ------
neorv32_uart_printf("[%i] PMP: Entry [mode=off] lock test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1462,26 → 1560,10
tmp_a = neorv32_cpu_csr_read(CSR_PMPCFG0);
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // try to re-write CFG content
 
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
test_fail();
}
else {
test_ok();
}
 
 
// ------ Lock test - pmpaddr0 ------
neorv32_uart_printf("[%i] - PMP: pmpaddr0 [mode=off] lock test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked, but entry is deactivated (mode = off)
 
// make sure a locked cfg cannot be written
tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
tmp_b = neorv32_cpu_csr_read(CSR_PMPADDR0);
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xABABCDCD); // try to re-write ADDR content
 
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (tmp_b != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
test_fail();
}
else {
1501,7 → 1583,7
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (succeeding access): ", cnt_test);
 
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
1538,7 → 1620,7
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (failing access): ", cnt_test);
 
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
1571,22 → 1653,22
// HPM reports
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
neorv32_uart_printf("\n\n-- HPM reports (%u HPMs available) --\n", num_hpm_cnts_global);
neorv32_uart_printf("#IR - Total number of instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = HPM_0
//neorv32_uart_printf("#TM - Current system time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = HPM_1
neorv32_uart_printf("#CY - Total number of clk cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = HPM_2
neorv32_uart_printf("#03 - Retired compr. instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
neorv32_uart_printf("#04 - I-fetch wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
neorv32_uart_printf("#05 - I-issue wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
neorv32_uart_printf("#06 - Multi-cyc. ALU wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
neorv32_uart_printf("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
neorv32_uart_printf("#IR - Total number of instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
//neorv32_uart_printf("#TM - Current system time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
neorv32_uart_printf("#CY - Total number of clk cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
neorv32_uart_printf("#03 - Retired compr. instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
neorv32_uart_printf("#04 - I-fetch wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
neorv32_uart_printf("#05 - I-issue wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
neorv32_uart_printf("#06 - Multi-cyc. ALU wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
 
 
// ----------------------------------------------------------
/neorv32/trunk/sw/example/demo_twi/main.c
178,6 → 178,7
neorv32_uart_printf("Select new clock prescaler (0..7): ");
neorv32_uart_scan(terminal_buffer, 2, 1); // 1 hex char plus '\0'
uint8_t prsc = (uint8_t)hexstr_to_uint(terminal_buffer, strlen(terminal_buffer));
 
if ((prsc >= 0) && (prsc < 8)) { // valid?
TWI_CT = 0; // reset
TWI_CT = (1 << TWI_CT_EN) | (prsc << TWI_CT_PRSC0);
189,18 → 190,19
}
 
// print new clock frequency
uint32_t clock = SYSINFO_CLK;
uint32_t div = 0;
switch (prsc) {
case 0: clock = clock / 2; break;
case 1: clock = clock / 4; break;
case 2: clock = clock / 8; break;
case 3: clock = clock / 64; break;
case 4: clock = clock / 128; break;
case 5: clock = clock / 1024; break;
case 6: clock = clock / 2048; break;
case 7: clock = clock / 4096; break;
default: clock = 0; break;
case 0: div = 4 * 2; break;
case 1: div = 4 * 4; break;
case 2: div = 4 * 8; break;
case 3: div = 4 * 64; break;
case 4: div = 4 * 128; break;
case 5: div = 4 * 1024; break;
case 6: div = 4 * 2048; break;
case 7: div = 4 * 4096; break;
default: div = 0; break;
}
uint32_t clock = SYSINFO_CLK / div;
neorv32_uart_printf("New I2C clock: %u Hz\n", clock);
}
 
/neorv32/trunk/sw/lib/include/neorv32.h
708,28 → 708,33
 
 
/**********************************************************************//**
* @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
**************************************************************************/
/**@{*/
/** UART control register (r/w) */
#define UART_CT (*(IO_REG32 0xFFFFFFA0UL))
/** UART receive/transmit data register (r/w) */
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
/** UART0 control register (r/w) */
#define UART0_CT (*(IO_REG32 0xFFFFFFA0UL))
/** UART0 receive/transmit data register (r/w) */
#define UART0_DATA (*(IO_REG32 0xFFFFFFA4UL))
 
/** UART control register bits */
/** UART1 control register (r/w) */
#define UART1_CT (*(IO_REG32 0xFFFFFFD0UL))
/** UART1 receive/transmit data register (r/w) */
#define UART1_DATA (*(IO_REG32 0xFFFFFFD4UL))
 
/** UART0/UART1 control register bits */
enum NEORV32_UART_CT_enum {
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bi, bit 2) */
UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bi, bit 3) */
UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bi, bit 5) */
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bi, bit 6) */
UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bi, bit 7) */
UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bi, bit 8) */
UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0) */
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */
UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bit, bit 2) */
UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bit, bit 3) */
UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bit, bit 4) */
UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bit, bit 4) */
UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bit, bit 5) */
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */
UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */
UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */
UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */
UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */
 
UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
 
743,7 → 748,7
UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
};
 
/** UART receive/transmit data register bits */
/** UART0/UART1 receive/transmit data register bits */
enum NEORV32_UART_DATA_enum {
UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */
UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */
944,7 → 949,7
 
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_EN generic) */
SYSINFO_FEATURES_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
951,7 → 956,8
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
SYSINFO_FEATURES_IO_NCO = 25 /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
SYSINFO_FEATURES_IO_NCO = 25, /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
SYSINFO_FEATURES_IO_UART1 = 26 /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
};
 
/**********************************************************************//**
/neorv32/trunk/sw/lib/include/neorv32_uart.h
36,9 → 36,11
/**********************************************************************//**
* @file neorv32_uart.h
* @author Stephan Nolting
* @brief Universal asynchronous receiver/transmitter (UART) HW driver header file
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file
*
* @note These functions should only be used if the UART unit was synthesized (IO_UART_EN = true).
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions.
*
* @note These functions should only be used if the UART0/UART1 unit was synthesized (IO_UART0_EN = true / IO_UART1_EN = true).
**************************************************************************/
 
#ifndef neorv32_uart_h
47,18 → 49,46
// Libs required by functions
#include <stdarg.h>
 
// prototypes
int neorv32_uart_available(void);
// compatibility wrappers (mapping to primary UART -> UART0)
int neorv32_uart_available(void);
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity);
void neorv32_uart_disable(void);
void neorv32_uart_putc(char c);
int neorv32_uart_tx_busy(void);
int neorv32_uart_tx_busy(void);
char neorv32_uart_getc(void);
int neorv32_uart_char_received(void);
int neorv32_uart_getc_secure(char *data);
int neorv32_uart_char_received(void);
int neorv32_uart_getc_secure(char *data);
char neorv32_uart_char_received_get(void);
void neorv32_uart_print(const char *s);
void neorv32_uart_printf(const char *format, ...);
int neorv32_uart_scan(char *buffer, int max_size, int echo);
int neorv32_uart_scan(char *buffer, int max_size, int echo);
 
// prototypes for UART0 (primary UART)
int neorv32_uart0_available(void);
void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity);
void neorv32_uart0_disable(void);
void neorv32_uart0_putc(char c);
int neorv32_uart0_tx_busy(void);
char neorv32_uart0_getc(void);
int neorv32_uart0_char_received(void);
int neorv32_uart0_getc_secure(char *data);
char neorv32_uart0_char_received_get(void);
void neorv32_uart0_print(const char *s);
void neorv32_uart0_printf(const char *format, ...);
int neorv32_uart0_scan(char *buffer, int max_size, int echo);
 
// prototypes for UART1 (secondary UART)
int neorv32_uart1_available(void);
void neorv32_uart1_setup(uint32_t baudrate, uint8_t parity);
void neorv32_uart1_disable(void);
void neorv32_uart1_putc(char c);
int neorv32_uart1_tx_busy(void);
char neorv32_uart1_getc(void);
int neorv32_uart1_char_received(void);
int neorv32_uart1_getc_secure(char *data);
char neorv32_uart1_char_received_get(void);
void neorv32_uart1_print(const char *s);
void neorv32_uart1_printf(const char *format, ...);
int neorv32_uart1_scan(char *buffer, int max_size, int echo);
 
#endif // neorv32_uart_h
/neorv32/trunk/sw/lib/source/neorv32_rte.c
434,9 → 434,12
neorv32_uart_printf("MTIME - ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
 
neorv32_uart_printf("UART - ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
neorv32_uart_printf("UART0 - ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART0));
 
neorv32_uart_printf("UART1 - ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART1));
 
neorv32_uart_printf("SPI - ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
 
461,18 → 464,18
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Private function to print true or false.
* NEORV32 runtime environment: Private function to print yes or no.
* @note This function is used by neorv32_rte_print_hw_config(void) only.
*
* @param[in] state Print TRUE when !=0, print FALSE when 0
* @param[in] state Print 'yes' when !=0, print '0' when 0
**************************************************************************/
static void __neorv32_rte_print_true_false(int state) {
 
if (state) {
neorv32_uart_print("True\n");
neorv32_uart_print("yes\n");
}
else {
neorv32_uart_print("False\n");
neorv32_uart_print("no\n");
}
}
 
/neorv32/trunk/sw/lib/source/neorv32_uart.c
36,9 → 36,11
/**********************************************************************//**
* @file neorv32_uart.c
* @author Stephan Nolting
* @brief Universal asynchronous receiver/transmitter (UART) HW driver source file.
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver source file.
*
* @note These functions should only be used if the UART unit was synthesized (IO_UART_EN = true).
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions.
*
* @note These functions should only be used if the UART0/UART1 unit was synthesized (IO_UART0_EN = true / IO_UART1_EN = true).
**************************************************************************/
 
#include "neorv32.h"
52,14 → 54,170
/// \endcond
 
 
 
// #################################################################################################
// Compatibility wrappers mapping to UART0 (primary UART)
// #################################################################################################
 
/**********************************************************************//**
* Check if UART unit was synthesized.
* Check if UART0 unit was synthesized.
*
* @return 0 if UART was not synthesized, 1 if UART is available.
* @warning This functions maps to UART0 (primary UART).
*
* @return 0 if UART0 was not synthesized, 1 if UART0 is available.
**************************************************************************/
int neorv32_uart_available(void) {
int neorv32_uart_available(void) { return neorv32_uart0_available(); }
 
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART)) {
 
/**********************************************************************//**
* Enable and configure primary UART (UART0).
*
* @warning This functions maps to UART0 (primary UART).
*
* @note The 'UART0_SIM_MODE' compiler flag will configure UART0 for simulation mode: all UART0 TX data will be redirected to simulation output. Use this for simulations only!
* @note To enable simulation mode add <USER_FLAGS+=-DUART0_SIM_MODE> when compiling.
*
* @warning The baud rate is computed using INTEGER operations (truncation errors might occur).
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] parity Parity configuration (00=off, 10=even, 11=odd).
**************************************************************************/
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity) { neorv32_uart0_setup(baudrate, parity); }
 
 
/**********************************************************************//**
* Disable UART0.
* @warning This functions maps to UART0 (primary UART).
**************************************************************************/
void neorv32_uart_disable(void) { neorv32_uart0_disable(); }
 
 
/**********************************************************************//**
* Send single char via UART0.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart_putc(char c) { neorv32_uart0_putc(c); }
 
 
/**********************************************************************//**
* Check if UART0 TX is busy.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking.
*
* @return 0 if idle, 1 if busy
**************************************************************************/
int neorv32_uart_tx_busy(void) { return neorv32_uart0_tx_busy(); }
 
 
/**********************************************************************//**
* Get char from UART0.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking and does not check for UART frame/parity errors.
*
* @return Received char.
**************************************************************************/
char neorv32_uart_getc(void) { return neorv32_uart0_getc(); }
 
 
/**********************************************************************//**
* Check if UART0 has received a char.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is non-blocking.
* @note Use neorv32_uart0_char_received_get(void) to get the char.
*
* @return =!0 when a char has been received.
**************************************************************************/
int neorv32_uart_char_received(void) { return neorv32_uart0_char_received(); }
 
 
/**********************************************************************//**
* Get char from UART0 (and check errors).
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is non-blocking and checks for frame and parity errors.
*
* @param[in,out] data Received char.
* @return Status code (0=nothing received, 1: char received without errors; -1: char received with frame error; -2: char received with parity error; -3 char received with frame & parity error).
**************************************************************************/
int neorv32_uart_getc_secure(char *data) { return neorv32_uart0_getc_secure(data); }
 
 
/**********************************************************************//**
* Get a received char from UART0.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is non-blocking.
* @note Should only be used in combination with neorv32_uart_char_received(void).
*
* @return Received char.
**************************************************************************/
char neorv32_uart_char_received_get(void) { return neorv32_uart0_char_received_get(); }
 
 
/**********************************************************************//**
* Print string (zero-terminated) via UART0. Print full line break "\r\n" for every '\n'.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking.
*
* @param[in] s Pointer to string.
**************************************************************************/
void neorv32_uart_print(const char *s) { neorv32_uart0_print(s); }
 
 
/**********************************************************************//**
* Custom version of 'printf' function using UART0.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking.
*
* @param[in] format Pointer to format string.
*
* <TABLE>
* <TR><TD>%s</TD><TD>String (array of chars, zero-terminated)</TD></TR>
* <TR><TD>%c</TD><TD>Single char</TD></TR>
* <TR><TD>%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%u</TD><TD>32-bit unsigned number, printed as decimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal</TD></TR>
* </TABLE>
**************************************************************************/
void neorv32_uart_printf(const char *format, ...) { neorv32_uart0_printf(format); }
 
 
/**********************************************************************//**
* Simplified custom version of 'scanf' function for UART0.
*
* @warning This functions maps to UART0 (primary UART).
* @note This function is blocking.
*
* @param[in,out] buffer Pointer to array of chars to store string.
* @param[in] max_size Maximum number of chars to sample.
* @param[in] echo Echo UART input when 1.
* @return Number of chars read.
**************************************************************************/
int neorv32_uart_scan(char *buffer, int max_size, int echo) { return neorv32_uart0_scan(buffer, max_size, echo); }
 
 
 
// #################################################################################################
// Primary UART (UART0)
// #################################################################################################
 
/**********************************************************************//**
* Check if UART0 unit was synthesized.
*
* @return 0 if UART0 was not synthesized, 1 if UART0 is available.
**************************************************************************/
int neorv32_uart0_available(void) {
 
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART0)) {
return 1;
}
else {
69,19 → 227,19
 
 
/**********************************************************************//**
* Enable and configure UART.
* Enable and configure primary UART (UART0).
*
* @note The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only!
* @note To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling.
* @note The 'UART0_SIM_MODE' compiler flag will configure UART0 for simulation mode: all UART0 TX data will be redirected to simulation output. Use this for simulations only!
* @note To enable simulation mode add <USER_FLAGS+=-DUART0_SIM_MODE> when compiling.
*
* @warning The baud rate is computed using INTEGER operations (truncation errors might occur).
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] parity PArity configuration (00=off, 10=even, 11=odd).
* @param[in] parity Parity configuration (00=off, 10=even, 11=odd).
**************************************************************************/
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity) {
void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity) {
 
UART_CT = 0; // reset
UART0_CT = 0; // reset
 
uint32_t clock = SYSINFO_CLK;
uint16_t i = 0; // BAUD rate divisor
121,57 → 279,60
uint32_t parity_config = (uint32_t)(parity & 3);
parity_config = parity_config << UART_CT_PMODE0;
 
/* Enable the UART for SIM mode. */
/* Enable UART0 for SIM mode. */
/* USE THIS ONLY FOR SIMULATION! */
#ifdef UART_SIM_MODE
#warning UART_SIM_MODE enabled! Sending all UART.TX data to text.io simulation output instead of real UART transmitter. Use this for simulations only!
#warning <UART_SIM_MODE> is obsolete (but still supported for compatibility). Please consider using the new flag <UART0_SIM_MODE>.
#endif
#if defined UART0_SIM_MODE || defined UART_SIM_MODE
#warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only!
uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
#else
uint32_t sim_mode = 0;
#endif
 
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode;
UART0_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode;
}
 
 
/**********************************************************************//**
* Disable UART.
* Disable UART0.
**************************************************************************/
void neorv32_uart_disable(void) {
void neorv32_uart0_disable(void) {
 
UART_CT &= ~((uint32_t)(1 << UART_CT_EN));
UART0_CT &= ~((uint32_t)(1 << UART_CT_EN));
}
 
 
/**********************************************************************//**
* Send single char via UART.
* Send single char via UART0.
*
* @note This function is blocking.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart_putc(char c) {
void neorv32_uart0_putc(char c) {
 
#ifdef UART_SIM_MODE
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#if defined UART0_SIM_MODE || defined UART_SIM_MODE
UART0_DATA = ((uint32_t)c) << UART_DATA_LSB;
#else
// wait for previous transfer to finish
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
while ((UART0_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART0_DATA = ((uint32_t)c) << UART_DATA_LSB;
#endif
}
 
 
/**********************************************************************//**
* Check if UART TX is busy.
* Check if UART0 TX is busy.
*
* @note This function is blocking.
*
* @return 0 if idle, 1 if busy
**************************************************************************/
int neorv32_uart_tx_busy(void) {
int neorv32_uart0_tx_busy(void) {
 
if ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0) {
if ((UART0_CT & (1<<UART_CT_TX_BUSY)) != 0) {
return 1;
}
return 0;
179,17 → 340,17
 
 
/**********************************************************************//**
* Get char from UART.
* Get char from UART0.
*
* @note This function is blocking and does not check for UART frame/parity errors.
*
* @return Received char.
**************************************************************************/
char neorv32_uart_getc(void) {
char neorv32_uart0_getc(void) {
 
uint32_t d = 0;
while (1) {
d = UART_DATA;
d = UART0_DATA;
if ((d & (1<<UART_DATA_AVAIL)) != 0) { // char received?
return (char)d;
}
198,7 → 359,7
 
 
/**********************************************************************//**
* Get char from UART (and check errors).
* Get char from UART0 (and check errors).
*
* @note This function is non-blocking and checks for frame and parity errors.
*
205,9 → 366,9
* @param[in,out] data Received char.
* @return Status code (0=nothing received, 1: char received without errors; -1: char received with frame error; -2: char received with parity error; -3 char received with frame & parity error).
**************************************************************************/
int neorv32_uart_getc_secure(char *data) {
int neorv32_uart0_getc_secure(char *data) {
 
uint32_t uart_rx = UART_DATA;
uint32_t uart_rx = UART0_DATA;
if (uart_rx & (1<<UART_DATA_AVAIL)) { // char available at all?
 
int status = 0;
238,16 → 399,16
 
 
/**********************************************************************//**
* Check if UART has received a char.
* Check if UART0 has received a char.
*
* @note This function is non-blocking.
* @note Use neorv32_uart_char_received_get(void) to get the char.
* @note Use neorv32_uart0_char_received_get(void) to get the char.
*
* @return =!0 when a char has been received.
**************************************************************************/
int neorv32_uart_char_received(void) {
int neorv32_uart0_char_received(void) {
 
if ((UART_DATA & (1<<UART_DATA_AVAIL)) != 0) {
if ((UART0_DATA & (1<<UART_DATA_AVAIL)) != 0) {
return 1;
}
else {
257,7 → 418,7
 
 
/**********************************************************************//**
* Get a received char.
* Get a received char from UART0.
*
* @note This function is non-blocking.
* @note Should only be used in combination with neorv32_uart_char_received(void).
264,96 → 425,385
*
* @return Received char.
**************************************************************************/
char neorv32_uart_char_received_get(void) {
char neorv32_uart0_char_received_get(void) {
 
return (char)UART_DATA;
return (char)UART0_DATA;
}
 
 
/**********************************************************************//**
* Print string (zero-terminated) via UART. Print full line break "\r\n" for every '\n'.
* Print string (zero-terminated) via UART0. Print full line break "\r\n" for every '\n'.
*
* @note This function is blocking.
*
* @param[in] s Pointer to string.
**************************************************************************/
void neorv32_uart_print(const char *s) {
void neorv32_uart0_print(const char *s) {
 
char c = 0;
while ((c = *s++)) {
if (c == '\n') {
neorv32_uart_putc('\r');
neorv32_uart0_putc('\r');
}
neorv32_uart_putc(c);
neorv32_uart0_putc(c);
}
}
 
 
/**********************************************************************//**
* Private function for 'neorv32_printf' to convert into decimal.
* Custom version of 'printf' function using UART0.
*
* @param[in] x Unsigned input number.
* @param[in,out] res Pointer for storing the reuslting number string (11 chars).
* @note This function is blocking.
*
* @param[in] format Pointer to format string.
*
* <TABLE>
* <TR><TD>%s</TD><TD>String (array of chars, zero-terminated)</TD></TR>
* <TR><TD>%c</TD><TD>Single char</TD></TR>
* <TR><TD>%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%u</TD><TD>32-bit unsigned number, printed as decimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal</TD></TR>
* </TABLE>
**************************************************************************/
static void __neorv32_uart_itoa(uint32_t x, char *res) {
void neorv32_uart0_printf(const char *format, ...) {
 
static const char numbers[] = "0123456789";
char buffer1[11];
uint16_t i, j;
char c, string_buf[11];
int32_t n;
 
buffer1[10] = '\0';
res[10] = '\0';
va_list a;
va_start(a, format);
 
// convert
for (i=0; i<10; i++) {
buffer1[i] = numbers[x%10];
x /= 10;
while ((c = *format++)) {
if (c == '%') {
c = *format++;
switch (c) {
case 's': // string
neorv32_uart0_print(va_arg(a, char*));
break;
case 'c': // char
neorv32_uart0_putc((char)va_arg(a, int));
break;
case 'i': // 32-bit signed
n = (int32_t)va_arg(a, int32_t);
if (n < 0) {
n = -n;
neorv32_uart0_putc('-');
}
__neorv32_uart_itoa((uint32_t)n, string_buf);
neorv32_uart0_print(string_buf);
break;
case 'u': // 32-bit unsigned
__neorv32_uart_itoa(va_arg(a, uint32_t), string_buf);
neorv32_uart0_print(string_buf);
break;
case 'x': // 32-bit hexadecimal
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
neorv32_uart0_print(string_buf);
break;
default:
return;
}
}
else {
if (c == '\n') {
neorv32_uart0_putc('\r');
}
neorv32_uart0_putc(c);
}
}
va_end(a);
}
 
// delete 'leading' zeros
for (i=9; i!=0; i--) {
if (buffer1[i] == '0')
buffer1[i] = '\0';
else
 
/**********************************************************************//**
* Simplified custom version of 'scanf' function for UART0.
*
* @note This function is blocking.
*
* @param[in,out] buffer Pointer to array of chars to store string.
* @param[in] max_size Maximum number of chars to sample.
* @param[in] echo Echo UART input when 1.
* @return Number of chars read.
**************************************************************************/
int neorv32_uart0_scan(char *buffer, int max_size, int echo) {
 
char c = 0;
int length = 0;
 
while (1) {
c = neorv32_uart0_getc();
if (c == '\b') { // BACKSPACE
if (length != 0) {
if (echo) {
neorv32_uart0_print("\b \b"); // delete last char in console
}
buffer--;
length--;
}
}
else if (c == '\r') // carriage return
break;
else if ((c >= ' ') && (c <= '~') && (length < (max_size-1))) {
if (echo) {
neorv32_uart0_putc(c); // echo
}
*buffer++ = c;
length++;
}
}
*buffer = '\0'; // terminate string
 
// reverse
j = 0;
do {
if (buffer1[i] != '\0')
res[j++] = buffer1[i];
} while (i--);
return length;
}
 
res[j] = '\0'; // terminate result string
 
 
// #################################################################################################
// Secondary UART (UART1)
// #################################################################################################
 
/**********************************************************************//**
* Check if UART1 unit was synthesized.
*
* @return 0 if UART1 was not synthesized, 1 if UART1 is available.
**************************************************************************/
int neorv32_uart1_available(void) {
 
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART1)) {
return 1;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Private function for 'neorv32_printf' to convert into hexadecimal.
* Enable and configure secondary UART (UART1).
*
* @param[in] x Unsigned input number.
* @param[in,out] res Pointer for storing the reuslting number string (9 chars).
* @note The 'UART1_SIM_MODE' compiler flag will configure UART1 for simulation mode: all UART1 TX data will be redirected to simulation output. Use this for simulations only!
* @note To enable simulation mode add <USER_FLAGS+=-DUART1_SIM_MODE> when compiling.
*
* @warning The baud rate is computed using INTEGER operations (truncation errors might occur).
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] parity Parity configuration (00=off, 10=even, 11=odd).
**************************************************************************/
static void __neorv32_uart_tohex(uint32_t x, char *res) {
void neorv32_uart1_setup(uint32_t baudrate, uint8_t parity) {
 
static const char symbols[] = "0123456789abcdef";
UART1_CT = 0; // reset
 
int i;
for (i=0; i<8; i++) { // nibble by bibble
uint32_t num_tmp = x >> (4*i);
res[7-i] = (char)symbols[num_tmp & 0x0f];
uint32_t clock = SYSINFO_CLK;
uint16_t i = 0; // BAUD rate divisor
uint8_t p = 0; // initial prsc = CLK/2
 
// raw clock prescaler
#ifdef __riscv_div
// use div instructions
i = (uint16_t)(clock / (2*baudrate));
#else
// division via repeated subtraction
while (clock >= 2*baudrate) {
clock -= 2*baudrate;
i++;
}
#endif
 
res[8] = '\0'; // terminate result string
// find baud prescaler (12-bit wide))
while (i >= 0x0fff) {
if ((p == 2) || (p == 4))
i >>= 3;
else
i >>= 1;
p++;
}
 
uint32_t clk_prsc = (uint32_t)p;
clk_prsc = clk_prsc << UART_CT_PRSC0;
 
uint32_t baud_prsc = (uint32_t)i;
baud_prsc = baud_prsc - 1;
baud_prsc = baud_prsc << UART_CT_BAUD00;
 
uint32_t uart_en = 1;
uart_en = uart_en << UART_CT_EN;
 
uint32_t parity_config = (uint32_t)(parity & 3);
parity_config = parity_config << UART_CT_PMODE0;
 
/* Enable UART1 for SIM mode. */
/* USE THIS ONLY FOR SIMULATION! */
#ifdef UART1_SIM_MODE
#warning UART1_SIM_MODE (secondary UART) enabled! Sending all UART1.TX data to text.io simulation output instead of real UART1 transmitter. Use this for simulations only!
uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
#else
uint32_t sim_mode = 0;
#endif
 
UART1_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode;
}
 
 
/**********************************************************************//**
* Custom version of 'printf' function.
* Disable UART1.
**************************************************************************/
void neorv32_uart1_disable(void) {
 
UART1_CT &= ~((uint32_t)(1 << UART_CT_EN));
}
 
 
/**********************************************************************//**
* Send single char via UART1.
*
* @note This function is blocking.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart1_putc(char c) {
 
#ifdef UART1_SIM_MODE
UART1_DATA = ((uint32_t)c) << UART_DATA_LSB;
#else
// wait for previous transfer to finish
while ((UART1_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART1_DATA = ((uint32_t)c) << UART_DATA_LSB;
#endif
}
 
 
/**********************************************************************//**
* Check if UART1 TX is busy.
*
* @note This function is blocking.
*
* @return 0 if idle, 1 if busy
**************************************************************************/
int neorv32_uart1_tx_busy(void) {
 
if ((UART1_CT & (1<<UART_CT_TX_BUSY)) != 0) {
return 1;
}
return 0;
}
 
 
/**********************************************************************//**
* Get char from UART1.
*
* @note This function is blocking and does not check for UART frame/parity errors.
*
* @return Received char.
**************************************************************************/
char neorv32_uart1_getc(void) {
 
uint32_t d = 0;
while (1) {
d = UART1_DATA;
if ((d & (1<<UART_DATA_AVAIL)) != 0) { // char received?
return (char)d;
}
}
}
 
 
/**********************************************************************//**
* Get char from UART1 (and check errors).
*
* @note This function is non-blocking and checks for frame and parity errors.
*
* @param[in,out] data Received char.
* @return Status code (0=nothing received, 1: char received without errors; -1: char received with frame error; -2: char received with parity error; -3 char received with frame & parity error).
**************************************************************************/
int neorv32_uart1_getc_secure(char *data) {
 
uint32_t uart_rx = UART1_DATA;
if (uart_rx & (1<<UART_DATA_AVAIL)) { // char available at all?
 
int status = 0;
 
// check for frame error
if (uart_rx & (1<<UART_DATA_FERR)) {
status -= 1;
}
 
// check for parity error
if (uart_rx & (1<<UART_DATA_PERR)) {
status -= 2;
}
 
if (status == 0) {
status = 1;
}
 
// get received byte
*data = (char)uart_rx;
 
return status;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Check if UART1 has received a char.
*
* @note This function is non-blocking.
* @note Use neorv32_uart0_char_received_get(void) to get the char.
*
* @return =!0 when a char has been received.
**************************************************************************/
int neorv32_uart1_char_received(void) {
 
if ((UART1_DATA & (1<<UART_DATA_AVAIL)) != 0) {
return 1;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Get a received char from UART1.
*
* @note This function is non-blocking.
* @note Should only be used in combination with neorv32_uart_char_received(void).
*
* @return Received char.
**************************************************************************/
char neorv32_uart1_char_received_get(void) {
 
return (char)UART1_DATA;
}
 
 
/**********************************************************************//**
* Print string (zero-terminated) via UART1. Print full line break "\r\n" for every '\n'.
*
* @note This function is blocking.
*
* @param[in] s Pointer to string.
**************************************************************************/
void neorv32_uart1_print(const char *s) {
 
char c = 0;
while ((c = *s++)) {
if (c == '\n') {
neorv32_uart1_putc('\r');
}
neorv32_uart1_putc(c);
}
}
 
 
/**********************************************************************//**
* Custom version of 'printf' function using UART1.
*
* @note This function is blocking.
*
* @param[in] format Pointer to format string.
*
* <TABLE>
364,7 → 814,7
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal</TD></TR>
* </TABLE>
**************************************************************************/
void neorv32_uart_printf(const char *format, ...) {
void neorv32_uart1_printf(const char *format, ...) {
 
char c, string_buf[11];
int32_t n;
377,27 → 827,27
c = *format++;
switch (c) {
case 's': // string
neorv32_uart_print(va_arg(a, char*));
neorv32_uart1_print(va_arg(a, char*));
break;
case 'c': // char
neorv32_uart_putc((char)va_arg(a, int));
neorv32_uart1_putc((char)va_arg(a, int));
break;
case 'i': // 32-bit signed
n = (int32_t)va_arg(a, int32_t);
if (n < 0) {
n = -n;
neorv32_uart_putc('-');
neorv32_uart1_putc('-');
}
__neorv32_uart_itoa((uint32_t)n, string_buf);
neorv32_uart_print(string_buf);
neorv32_uart1_print(string_buf);
break;
case 'u': // 32-bit unsigned
__neorv32_uart_itoa(va_arg(a, uint32_t), string_buf);
neorv32_uart_print(string_buf);
neorv32_uart1_print(string_buf);
break;
case 'x': // 32-bit hexadecimal
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
neorv32_uart_print(string_buf);
neorv32_uart1_print(string_buf);
break;
default:
return;
405,9 → 855,9
}
else {
if (c == '\n') {
neorv32_uart_putc('\r');
neorv32_uart1_putc('\r');
}
neorv32_uart_putc(c);
neorv32_uart1_putc(c);
}
}
va_end(a);
415,7 → 865,7
 
 
/**********************************************************************//**
* Simplified custom version of 'scanf' function.
* Simplified custom version of 'scanf' function for UART1.
*
* @note This function is blocking.
*
424,17 → 874,17
* @param[in] echo Echo UART input when 1.
* @return Number of chars read.
**************************************************************************/
int neorv32_uart_scan(char *buffer, int max_size, int echo) {
int neorv32_uart1_scan(char *buffer, int max_size, int echo) {
 
char c = 0;
int length = 0;
 
while (1) {
c = neorv32_uart_getc();
c = neorv32_uart1_getc();
if (c == '\b') { // BACKSPACE
if (length != 0) {
if (echo) {
neorv32_uart_print("\b \b"); // delete last char in console
neorv32_uart1_print("\b \b"); // delete last char in console
}
buffer--;
length--;
444,7 → 894,7
break;
else if ((c >= ' ') && (c <= '~') && (length < (max_size-1))) {
if (echo) {
neorv32_uart_putc(c); // echo
neorv32_uart1_putc(c); // echo
}
*buffer++ = c;
length++;
455,3 → 905,67
return length;
}
 
 
 
// #################################################################################################
// Shared functions
// #################################################################################################
 
/**********************************************************************//**
* Private function for 'neorv32_printf' to convert into decimal.
*
* @param[in] x Unsigned input number.
* @param[in,out] res Pointer for storing the reuslting number string (11 chars).
**************************************************************************/
static void __neorv32_uart_itoa(uint32_t x, char *res) {
 
static const char numbers[] = "0123456789";
char buffer1[11];
uint16_t i, j;
 
buffer1[10] = '\0';
res[10] = '\0';
 
// convert
for (i=0; i<10; i++) {
buffer1[i] = numbers[x%10];
x /= 10;
}
 
// delete 'leading' zeros
for (i=9; i!=0; i--) {
if (buffer1[i] == '0')
buffer1[i] = '\0';
else
break;
}
 
// reverse
j = 0;
do {
if (buffer1[i] != '\0')
res[j++] = buffer1[i];
} while (i--);
 
res[j] = '\0'; // terminate result string
}
 
 
/**********************************************************************//**
* Private function for 'neorv32_printf' to convert into hexadecimal.
*
* @param[in] x Unsigned input number.
* @param[in,out] res Pointer for storing the reuslting number string (9 chars).
**************************************************************************/
static void __neorv32_uart_tohex(uint32_t x, char *res) {
 
static const char symbols[] = "0123456789abcdef";
 
int i;
for (i=0; i<8; i++) { // nibble by bibble
uint32_t num_tmp = x >> (4*i);
res[7-i] = (char)symbols[num_tmp & 0x0f];
}
 
res[8] = '\0'; // terminate result string
}
/neorv32/trunk/CHANGELOG.md
14,6 → 14,9
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 20.02.2021 | 1.5.1.7 | removed `err_o` signal from custom functions subsystem `CFS`; processor *SoC fast interrupt input* `soc_firq_i` reduced to 6 channels (was 8) - mapped to CPU's `FIRQ10` - `FIRQ_15`; added individual fast IRQs for `UART1` "RX complete" and "TX complete" conditions (-> FIRQ4 & FIRQ5); changed FIRQ channels of TWI/SPI/GPIO interrupts |
| 18.02.2021 | 1.5.1.6 | added register buffer for enable signals to processor-internal clock generator; :bug: fixed bug in `sw/example/demo_twi` program: TWI clock speed messsage was wrong (factor 1/4 was missing) |
| 17.02.2021 | 1.5.1.5 | added a second independent UART: new UART is *secondary UART* `UART0`, the "old" UART is now the *primary UART* `UART0`; by default the **primary UART (UART0) is used for all user interface connection**; reworked *fast interrupt* `FIRQ` assignment/priority list - added UART1 RTX (receive *or* send done) fast interrupt; added hardware driver functions for new `UART1` - the "old" `neorv32_uart_*` function calls will map to the primary UART `UART0` for compatibility; renamed compiler flag to enable UART "simulation mode": `UART_SIM_MODE` -> `UART0_SIM_MODE` for primary UART, `UART1_SIM_MODE` for secondary UART (`UART_SIM_MODE` is still supported for compatibility and maps to `UART0_SIM_MODE`); added second simulation UART receiver for `UART1` to testbench; renamed UART simulation output files: `neorv32.testbench_uart.out` -> `neorv32.testbench_uart0.out` (testbench UART0 receiver), new: `neorv32.testbench_uart1.out` (testbench UART1 receiver), `neorv32.uart.sim_mode.text.out` and `neorv32.uart.sim_mode.data.out` -> `neorv32.uart0.sim_mode.text.out` and `neorv32.uart0.sim_mode.data.out` (for `UART0`), new `neorv32.uart1.sim_mode.text.out` and `neorv32.uart1.sim_mode.data.out` (for `UART1`) |
| 13.02.2021 | 1.5.1.4 | `HW_THREAD_ID` generic is now of type `natural`; `mret` instruction now requires an additional cycle to execute; logic optimization of CPU's control logic -> smaller hardware footprint and higher f_max; updated CPU synthesis results; removed top module's generic initialization using `(others => '0')` (targeting [issue #8](https://github.com/stnolting/neorv32/issues/8)) |
| 09.02.2021 | 1.5.1.3 | modified CPU architecture: now using a "pseudo" ALU co-processor to get the result of a CSR read operation into data path, removing one input from register file input mux -> shorter critical path |
| 08.02.2021 | 1.5.1.2 | added new peripheral/IO module: **Numerically-Controlled Oscillator `NCO`**: three independent channels, 20-bit phase accu, 20-bit tuning word, fixed 50% duty cycle mode or pulsed mode; added according HW drivers and example program |
/neorv32/trunk/LICENSE
1,6 → 1,6
BSD 3-Clause License
 
Copyright (c) 2020, Stephan Nolting
Copyright (c) 2021, Stephan Nolting
All rights reserved.
 
Redistribution and use in source and binary forms, with or without
/neorv32/trunk/README.md
1,4 → 1,4
[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)
[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
 
# The NEORV32 RISC-V Processor
 
35,10 → 35,10
 
### Key Features
 
* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
* RISC-V 32-bit `rv32` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
* the [offcial RISC-V compliance tests](#Status) (*passing*)
* the [official RISC-V compliance tests](#Status) (*passing*)
* Configurable RISC-V-compliant CPU extensions
* [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
* [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
55,7 → 55,7
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
* timers (watch dog, RISC-V-compliant machine timer)
* serial interfaces (SPI, TWI, UART)
* serial interfaces (SPI, TWI, UARTs)
* general purpose IO and PWM channels
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
* subsystem for custom co-processors
112,12 → 112,12
* Add data cache?
* Burst mode for the external memory/bus interface?
* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
* RISC-V `K` CPU extension: [Crypto](https://github.com/riscv/riscv-crypto)
* Add template (HW module + SW intrinsics skeleton) for custom instructions?
* Implement further RISC-V CPU extensions?
* More support for FreeRTOS (like *all* traps)?
* More support for FreeRTOS?
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
* ...
* [Ideas?](#ContributeFeedbackQuestions)
 
140,7 → 140,7
* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
* machine system timer (**MTIME**), RISC-V-compliant
* watchdog timer (**WDT**)
* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
* two independent universal asynchronous receiver and transmitter (**UART0** & **UART1**) with fast simulation output option
* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
337,7 → 337,7
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
| UART | Universal asynchronous receiver/transmitter | 176 | 132 | 0 | 0 |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
 
490,9 → 490,9
[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
 
 
### Toolchain
### 1. Get Toolchain
 
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
At first you need a **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
and build the toolchain by yourself, or you can download a prebuilt one and install it.
 
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
503,14 → 503,20
[:octocat: github.com/stnolting/riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt)
 
You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
RISC-V code. They were compiled for more sophisticated machines (`imac`) so the according hardware extensions are *mandatory*
RISC-V code. They were compiled for more sophisticated machines (`rv32imac`) so make sure the according NEORV32 hardware extensions are enabled.
 
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
 
To check everything works fine, make sure `GNU Make` and a native `GCC` compiler are installed.
Test the installation of the RISC-V toolchain by navigating to an [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) like
`sw/example/blink_led` and running:
 
### Dowload the NEORV32 Project
neorv32/sw/example/blink_led$ make check
 
 
### 2. Dowload the NEORV32 Project
 
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
 
$ git clone https://github.com/stnolting/neorv32.git
519,7 → 525,7
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
 
 
### Create a new Hardware Project
### 3. Create a new Hardware Project
 
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
531,7 → 537,7
![neorv32 test setup](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_test_setup.png)
 
 
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART0 lines, clock, reset and some GPIO output signals are
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
 
```vhdl
538,44 → 544,34
entity neorv32_test_setup is
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0' -- UART receive data
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART0 --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data
);
end neorv32_test_setup;
```
 
 
### Check the Toolchain
### 4. Compile an Example Program
 
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
`sw/example/blink_led` and run:
The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
And yes, there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available! :wink:
 
neorv32/sw/example/blink_led$ make check
Simply compile one of these projects using
 
 
### Compiling an Example Program
 
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
*executable* `neorv32_exe.bin` in the same folder:
 
neorv32/sw/example/blink_led$ make clean_all exe
 
This will create a NEORV32 *executable* `neorv32_exe.bin` in the same folder, which you can upload via the bootloader.
 
### Upload the Executable via the Bootloader
 
You can upload a generated executable directly from the command line using the makefile's `upload` target. Replace `/dev/ttyUSB0` with
the according serial port.
### 5. Upload the Executable via the Bootloader
 
sw/exeample/blink_example$ make COM_PORT=/dev/ttyUSB0` upload
 
A more "secure" way is to use a dedicated terminal program. This allows to directly interact with the bootloader console.
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
Connect your FPGA board via UART to your computer and open the according port to interface with the fancy NEORV32 bootloader. The bootloader
uses the following default UART configuration:
 
* 19200 Baud
585,7 → 581,7
* No transmission / flow control protocol (raw bytes only)
* Newline on `\r\n` (carriage return & newline) - also for sent data
 
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
Use the bootloader console to upload the `neorv32_exe.bin` executable gerated during application compiling and run your application.
 
```
<< NEORV32 Bootloader >>

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