URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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Rev 53 → Rev 54
/neorv32/trunk/docs/NEORV32.pdf
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svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_package.vhd
52,15 → 52,15
-- CPU core -- |
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2 |
|
-- "critical" number of PMP regions -- |
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically |
-- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle! |
constant pmp_num_regions_critical_c : natural := 8; |
-- "critical" number of implemented PMP regions -- |
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces |
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length |
constant pmp_num_regions_critical_c : natural := 8; -- default=8 |
|
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050207"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050208"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW |
400,13 → 400,41
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR |
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC |
|
-- RISC-V Floating-Point Formats ---------------------------------------------------------- |
-- RISC-V Floating-Point Stuff ------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precisions (32-bit) |
constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precisions (64-bit) |
constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precisions (16-bit) |
constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precisions (64-bit) |
-- formats -- |
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit) |
constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit) |
constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit) |
constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit) |
|
-- number class flags -- |
constant fp_class_neg_inf_c : natural := 0; -- negative infinity |
constant fp_class_neg_norm_c : natural := 1; -- negative normal number |
constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number |
constant fp_class_neg_zero_c : natural := 3; -- negative zero |
constant fp_class_pos_zero_c : natural := 4; -- positive zero |
constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number |
constant fp_class_pos_norm_c : natural := 6; -- positive normal number |
constant fp_class_pos_inf_c : natural := 7; -- positive infinity |
constant fp_class_snan_c : natural := 8; -- signaling NaN (sNaN) |
constant fp_class_qnan_c : natural := 9; -- quiet NaN (qNaN) |
|
-- exception flags -- |
constant fp_exc_nv_c : natural := 0; -- invalid operation |
constant fp_exc_dz_c : natural := 1; -- divide by zero |
constant fp_exc_of_c : natural := 2; -- overflow |
constant fp_exc_uf_c : natural := 3; -- underflow |
constant fp_exc_nx_c : natural := 4; -- inexact |
|
-- special values (single-precision) -- |
constant fp_single_qnan_c : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN |
constant fp_single_snan_c : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN |
constant fp_single_pos_inf_c : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity |
constant fp_single_neg_inf_c : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity |
constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero |
constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero |
|
-- RISC-V CSR Addresses ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- read/write CSRs -- |
/neorv32/trunk/sw/bootloader/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/bit_manipulation/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/bit_manipulation/neorv32_b_extension_intrinsics.h
44,115 → 44,7
#ifndef neorv32_b_extension_intrinsics_h |
#define neorv32_b_extension_intrinsics_h |
|
/**********************************************************************//** |
* @name Custom instructions helper macros |
**************************************************************************/ |
/**@{*/ |
|
//** Selection helper macro */ |
#define STR1(x) #x |
//** Selection helper macro 2 */ |
#define STR(x) STR1(x) |
|
//** Register address converter */ |
#define GET_REG_ADDR(x) REG_ADDR_##x |
|
#define REG_ADDR_x0 0 /**< register 0 */ |
#define REG_ADDR_x1 1 /**< register 1 */ |
#define REG_ADDR_x2 2 /**< register 2 */ |
#define REG_ADDR_x3 3 /**< register 3 */ |
#define REG_ADDR_x4 4 /**< register 4 */ |
#define REG_ADDR_x5 5 /**< register 5 */ |
#define REG_ADDR_x6 6 /**< register 6 */ |
#define REG_ADDR_x7 7 /**< register 7 */ |
#define REG_ADDR_x8 8 /**< register 8 */ |
#define REG_ADDR_x9 9 /**< register 9 */ |
#define REG_ADDR_x10 10 /**< register 10 */ |
#define REG_ADDR_x11 11 /**< register 11 */ |
#define REG_ADDR_x12 12 /**< register 12 */ |
#define REG_ADDR_x13 13 /**< register 13 */ |
#define REG_ADDR_x14 14 /**< register 14 */ |
#define REG_ADDR_x15 15 /**< register 15 */ |
#define REG_ADDR_x16 16 /**< register 16 */ |
#define REG_ADDR_x17 17 /**< register 17 */ |
#define REG_ADDR_x18 18 /**< register 18 */ |
#define REG_ADDR_x19 19 /**< register 19 */ |
#define REG_ADDR_x20 20 /**< register 20 */ |
#define REG_ADDR_x21 21 /**< register 21 */ |
#define REG_ADDR_x22 22 /**< register 22 */ |
#define REG_ADDR_x23 23 /**< register 23 */ |
#define REG_ADDR_x24 24 /**< register 24 */ |
#define REG_ADDR_x25 25 /**< register 25 */ |
#define REG_ADDR_x26 26 /**< register 26 */ |
#define REG_ADDR_x27 27 /**< register 27 */ |
#define REG_ADDR_x28 28 /**< register 28 */ |
#define REG_ADDR_x29 29 /**< register 29 */ |
#define REG_ADDR_x30 30 /**< register 30 */ |
#define REG_ADDR_x31 31 /**< register 31 */ |
#define REG_ADDR_zero 0 /**< register 0 - according to calling convention */ |
#define REG_ADDR_ra 1 /**< register 1 - according to calling convention */ |
#define REG_ADDR_sp 2 /**< register 2 - according to calling convention */ |
#define REG_ADDR_gp 3 /**< register 3 - according to calling convention */ |
#define REG_ADDR_tp 4 /**< register 4 - according to calling convention */ |
#define REG_ADDR_t0 5 /**< register 5 - according to calling convention */ |
#define REG_ADDR_t1 6 /**< register 6 - according to calling convention */ |
#define REG_ADDR_t2 7 /**< register 7 - according to calling convention */ |
#define REG_ADDR_s0 8 /**< register 8 - according to calling convention */ |
#define REG_ADDR_s1 9 /**< register 9 - according to calling convention */ |
#define REG_ADDR_a0 10 /**< register 10 - according to calling convention */ |
#define REG_ADDR_a1 11 /**< register 11 - according to calling convention */ |
#define REG_ADDR_a2 12 /**< register 12 - according to calling convention */ |
#define REG_ADDR_a3 13 /**< register 13 - according to calling convention */ |
#define REG_ADDR_a4 14 /**< register 14 - according to calling convention */ |
#define REG_ADDR_a5 15 /**< register 15 - according to calling convention */ |
#define REG_ADDR_a6 16 /**< register 16 - according to calling convention */ |
#define REG_ADDR_a7 17 /**< register 17 - according to calling convention */ |
#define REG_ADDR_s2 18 /**< register 18 - according to calling convention */ |
#define REG_ADDR_s3 19 /**< register 19 - according to calling convention */ |
#define REG_ADDR_s4 20 /**< register 20 - according to calling convention */ |
#define REG_ADDR_s5 21 /**< register 21 - according to calling convention */ |
#define REG_ADDR_s6 22 /**< register 22 - according to calling convention */ |
#define REG_ADDR_s7 23 /**< register 23 - according to calling convention */ |
#define REG_ADDR_s8 24 /**< register 24 - according to calling convention */ |
#define REG_ADDR_s9 25 /**< register 25 - according to calling convention */ |
#define REG_ADDR_s10 26 /**< register 26 - according to calling convention */ |
#define REG_ADDR_s11 27 /**< register 27 - according to calling convention */ |
#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */ |
#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */ |
#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */ |
#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */ |
|
//** Construct instruction word (32-bit) for R-type instruction */ |
#define CMD_WORD_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ |
( (opcode & 0x7f) << 0 ) + \ |
( (rd & 0x1f) << 7 ) + \ |
( (rs1 & 0x1f) << 15 ) + \ |
( (rs2 & 0x1f) << 20 ) + \ |
( (funct7 & 0x7f) << 25 ) + \ |
( (funct3 & 0x1f) << 12 ) |
|
//** Construct instruction word (32-bit) for I-type instruction */ |
#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \ |
( (opcode & 0x7f) << 0 ) + \ |
( (rd & 0x1f) << 7 ) + \ |
( (rs1_f5 & 0x1f) << 15 ) + \ |
( (imm12 & 0xfff) << 20 ) + \ |
( (funct3 & 0x1f) << 12 ) |
|
//** Construct custom instruction for R-type instruction */ |
#define CUSTOM_INSTR_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
|
//** Construct custom instruction for R1-type instruction (register + 5-bit immediate/function_select) */ |
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
|
//** Construct custom instruction for I-type instruction */ |
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
/**@}*/ |
|
|
// ################################################################################################ |
// "Intrinsics" |
// ################################################################################################ |
/neorv32/trunk/sw/example/blink_led/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/coremark/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/cpu_test/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_freeRTOS/makefile
254,7 → 254,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_gpio_irq/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_nco/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_neopixel/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_pwm/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_trng/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_twi/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/demo_wdt/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/game_of_life/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/hello_world/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/example/hex_viewer/makefile
181,7 → 181,7
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
/neorv32/trunk/sw/lib/include/neorv32.h
53,6 → 53,10
* Available CPU Control and Status Registers (CSRs) |
**************************************************************************/ |
enum NEORV32_CSR_enum { |
CSR_FFLAGS = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */ |
CSR_FRM = 0x002, /**< 0x002 - frm (r/w): Floating-point dynamic rounding mode */ |
CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/staturs register (frm + fflags) */ |
|
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
1061,6 → 1065,9
// cpu core |
#include "neorv32_cpu.h" |
|
// intrinsics |
#include "neorv32_intrinsics.h" |
|
// neorv32 runtime environment |
#include "neorv32_rte.h" |
|
/neorv32/trunk/sw/lib/include/neorv32_intrinsics.h
0,0 → 1,153
// ################################################################################################# |
// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file neorv32_intrinsics.h |
* @author Stephan Nolting |
* @brief Helper functions and macros for custom "intrinsics" / instructions. |
**************************************************************************/ |
|
#ifndef neorv32_intrinsics_h |
#define neorv32_intrinsics_h |
|
/**********************************************************************//** |
* @name Custom instructions / intrinsics helper macros |
**************************************************************************/ |
/**@{*/ |
|
//** Selection helper macro */ |
#define STR1(x) #x |
//** Selection helper macro 2 */ |
#define STR(x) STR1(x) |
|
//** Register address converter */ |
#define GET_REG_ADDR(x) REG_ADDR_##x |
|
#define REG_ADDR_x0 0 /**< register 0 */ |
#define REG_ADDR_x1 1 /**< register 1 */ |
#define REG_ADDR_x2 2 /**< register 2 */ |
#define REG_ADDR_x3 3 /**< register 3 */ |
#define REG_ADDR_x4 4 /**< register 4 */ |
#define REG_ADDR_x5 5 /**< register 5 */ |
#define REG_ADDR_x6 6 /**< register 6 */ |
#define REG_ADDR_x7 7 /**< register 7 */ |
#define REG_ADDR_x8 8 /**< register 8 */ |
#define REG_ADDR_x9 9 /**< register 9 */ |
#define REG_ADDR_x10 10 /**< register 10 */ |
#define REG_ADDR_x11 11 /**< register 11 */ |
#define REG_ADDR_x12 12 /**< register 12 */ |
#define REG_ADDR_x13 13 /**< register 13 */ |
#define REG_ADDR_x14 14 /**< register 14 */ |
#define REG_ADDR_x15 15 /**< register 15 */ |
#define REG_ADDR_x16 16 /**< register 16 */ |
#define REG_ADDR_x17 17 /**< register 17 */ |
#define REG_ADDR_x18 18 /**< register 18 */ |
#define REG_ADDR_x19 19 /**< register 19 */ |
#define REG_ADDR_x20 20 /**< register 20 */ |
#define REG_ADDR_x21 21 /**< register 21 */ |
#define REG_ADDR_x22 22 /**< register 22 */ |
#define REG_ADDR_x23 23 /**< register 23 */ |
#define REG_ADDR_x24 24 /**< register 24 */ |
#define REG_ADDR_x25 25 /**< register 25 */ |
#define REG_ADDR_x26 26 /**< register 26 */ |
#define REG_ADDR_x27 27 /**< register 27 */ |
#define REG_ADDR_x28 28 /**< register 28 */ |
#define REG_ADDR_x29 29 /**< register 29 */ |
#define REG_ADDR_x30 30 /**< register 30 */ |
#define REG_ADDR_x31 31 /**< register 31 */ |
#define REG_ADDR_zero 0 /**< register 0 - according to calling convention */ |
#define REG_ADDR_ra 1 /**< register 1 - according to calling convention */ |
#define REG_ADDR_sp 2 /**< register 2 - according to calling convention */ |
#define REG_ADDR_gp 3 /**< register 3 - according to calling convention */ |
#define REG_ADDR_tp 4 /**< register 4 - according to calling convention */ |
#define REG_ADDR_t0 5 /**< register 5 - according to calling convention */ |
#define REG_ADDR_t1 6 /**< register 6 - according to calling convention */ |
#define REG_ADDR_t2 7 /**< register 7 - according to calling convention */ |
#define REG_ADDR_s0 8 /**< register 8 - according to calling convention */ |
#define REG_ADDR_s1 9 /**< register 9 - according to calling convention */ |
#define REG_ADDR_a0 10 /**< register 10 - according to calling convention */ |
#define REG_ADDR_a1 11 /**< register 11 - according to calling convention */ |
#define REG_ADDR_a2 12 /**< register 12 - according to calling convention */ |
#define REG_ADDR_a3 13 /**< register 13 - according to calling convention */ |
#define REG_ADDR_a4 14 /**< register 14 - according to calling convention */ |
#define REG_ADDR_a5 15 /**< register 15 - according to calling convention */ |
#define REG_ADDR_a6 16 /**< register 16 - according to calling convention */ |
#define REG_ADDR_a7 17 /**< register 17 - according to calling convention */ |
#define REG_ADDR_s2 18 /**< register 18 - according to calling convention */ |
#define REG_ADDR_s3 19 /**< register 19 - according to calling convention */ |
#define REG_ADDR_s4 20 /**< register 20 - according to calling convention */ |
#define REG_ADDR_s5 21 /**< register 21 - according to calling convention */ |
#define REG_ADDR_s6 22 /**< register 22 - according to calling convention */ |
#define REG_ADDR_s7 23 /**< register 23 - according to calling convention */ |
#define REG_ADDR_s8 24 /**< register 24 - according to calling convention */ |
#define REG_ADDR_s9 25 /**< register 25 - according to calling convention */ |
#define REG_ADDR_s10 26 /**< register 26 - according to calling convention */ |
#define REG_ADDR_s11 27 /**< register 27 - according to calling convention */ |
#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */ |
#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */ |
#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */ |
#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */ |
|
//** Construct instruction word (32-bit) for R-type instruction */ |
#define CMD_WORD_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ |
( (opcode & 0x7f) << 0 ) + \ |
( (rd & 0x1f) << 7 ) + \ |
( (rs1 & 0x1f) << 15 ) + \ |
( (rs2 & 0x1f) << 20 ) + \ |
( (funct7 & 0x7f) << 25 ) + \ |
( (funct3 & 0x1f) << 12 ) |
|
//** Construct instruction word (32-bit) for I-type instruction */ |
#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \ |
( (opcode & 0x7f) << 0 ) + \ |
( (rd & 0x1f) << 7 ) + \ |
( (rs1_f5 & 0x1f) << 15 ) + \ |
( (imm12 & 0xfff) << 20 ) + \ |
( (funct3 & 0x1f) << 12 ) |
|
//** Construct custom instruction for R-type instruction */ |
#define CUSTOM_INSTR_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
|
//** Construct custom instruction for R1-type instruction (register + 5-bit immediate/function_select) */ |
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
|
//** Construct custom instruction for I-type instruction */ |
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \ |
asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); |
/**@}*/ |
|
#endif // neorv32_intrinsics_h |
/neorv32/trunk/CHANGELOG.md
12,8 → 12,19
Leading zeros are optional. Example: `CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12`. The version number is globally |
defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/neorv32_package.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_package.vhd). |
|
|
### Version History |
|
* :bug: = bug-fix |
* :sparkles: = new feature |
* :warning: = major change |
* :lock: = security issue |
* :rocket: = release |
|
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 21.03.2021 | 1.5.2.8 | :bug: fixed problem with linking `math.h` library in makefile; added floating-point-related global definitions to main VHDL package; added intrinsic core library file `sw/lib/include/neorv32_intrinsics.h` - intrinsic library support for CPU extensions, which are not yet supported by the upstream GCC, are based on this | |
| 18.03.2021 | 1.5.2.7 | :bug: fixed bug in `sw/common/crt0.S` dummy exception handler (wrong order of register push/pop); changed upcoming floating-point extension (orignally `F` extension) to `Zfinx` extension (-> [RISC-V `Zfinx` spec](https://github.com/riscv/riscv-zfinx)) - updated CPU infrastructure | |
| 16.03.2021 | 1.5.2.6 | reworked atomic/exclusive memory access interface: removed CPU's `i_bus_lock_o` and `i_bus_lock_o` signal (was always zero anyway); removed top's `wb_lock_o` signal; added *exclusive access request* to Wishbone tag signal `wb_tag_o` (is not one bit wider); added more details to NEORV32.pdf regarding excluisve/atomic memory accesses (interface/protocol) | |
| 09.03.2021 | 1.5.2.5 | added bit-manipulation `Zba` sub-extension (shifted-adds: `SH1ADD` `SH2ADD` `SH3ADD`) | |
/neorv32/trunk/README.md
21,6 → 21,8
|
## Overview |
|
 |
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based |
on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC |
designs or as stand-alone custom microcontroller. |
117,8 → 119,6
|
### NEORV32 Processor Features |
|
 |
|
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup |
is highly customizable via the processor's top generics and already provides the following *optional* modules: |
|
174,7 → 174,7
* :warning: this extension has not been officially ratified yet! |
* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip) |
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec |
* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)) |
* Support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)) |
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`) |
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]` |
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD` |