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impl_1
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!*.bin
/neorv32/trunk/boards/UPduino_v2/README.md
0,0 → 1,126
# NEORV32 Example Setup for the tinyVision.ai "UPduino v2" FPGA Board
 
 
This example setup turns the UPduino v2.0 / v2.1 board, which features a Lattice iCE40 UltraPlus FPGA, into a small-scale NEORV32 *microcontroller*.
The processor setup provides 64kB of data and isntruction memory, an RTOS-capable CPU (privileged architecture) and a set of standard peripherals like UART, TWI and SPI.
There is also a **pre-compiled bitstream available** (`neorv32_upduino_v2_impl_1.bin`).
 
:information_source: The UPduino v2/v2.1 board is obsolete. However, it is backwards compatible to the
[**new UPduino v3 FPGA board** (see on Tindie)](https://www.tindie.com/stores/tinyvision_ai/?ref=offsite_badges&utm_source=sellers_vr2045&utm_medium=badges&utm_campaign=badge_medium).
 
:warning: Be careful when using the FPGA's PLL since the power supply of the UPduino v2 board has some issues
([see here](https://tinyvision.ai/blogs/processing-at-the-edge/ground-trampolines-and-phase-locked-loops)).
 
 
* FPGA Board: :books: [tinyVision.ai Inc. UPduino v2.0 FPGA Board (GitHub)](https://github.com/gtjennings1/UPDuino_v2_0), :credit_card: buy on [Tindie (obsolete)](https://www.tindie.com/products/tinyvision_ai/upduino-v21-low-cost-fpga-board/)
* FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I`
* Toolchain: Lattice Radiant (tested with Radiant version 2.1.0), using **Sinplify Pro Synthesis**
* Top entity: [`neorv32_upduino_v2_top.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v2/neorv32_upduino_v2_top.vhd) (instantiates NEORV32 top)
 
### NEORV32 Configuration
 
* CPU: `rv32imac_Zicsr` (reduced counter width: _CPU_CNT_WIDTH_ = 36)
* Memory: 64kB instruction memory (internal IMEM), 64kB data memory (internal DMEM), 4kB bootloader ROM
* Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG`
* Tested with version [`1.5.4.11`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
 
 
:information_source: This setup uses optimized platform-specific memory modules for the internal data and instruction memories (DMEM & IMEM). Each memory uses two
UltraPlus SPRAM primitives (total memory size per memory = 2 x 32kB = 64kB). VHDL source file for platform-specific IMEM: [`neorv32_imem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v2/neorv32_imem.ice40up_spram.vhd);
VHDL source file for platform-specific DMEM: [`neorv32_dmem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v2/neorv32_dmem.ice40up_spram.vhd).
These platform-specific memories are used *instead* of the default platform-agnostic modules from the core's `rtl/core` folder.
 
 
### Interface Signals
 
:information_source: See [`neorv32_upduino_v2.pdc`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v2/neorv32_upduino_v2.pdc)
for the FPGA pin mapping.
 
* Clock: 24 MHz from on-chip HF oscillator
* Reset: via low-active `rstn_i` input
* on-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)
 
| Top Entity Signal | FPGA Pin | Package Pin | Board Header Pin |
|:--------------------------|:----------:|:------------:|:-----------------|
| `pwm_o(0)` (red) | RGB2 | 41 | - |
| `pwm_o(1)` (green) | RGB0 | 39 | - |
| `pwm_o(2)` (blue) | RGB1 | 40 | - |
| `rstn_i` | IOB_22A | 12 | JP6-1 |
| `gpio_i(0)` | IOB_3B_G6 | 44 | JP6-9 |
| `gpio_i(1)` | IOB_8A | 4 | JP6-10 |
| `gpio_i(2)` | IOB_9B | 3 | JP6-11 |
| `gpio_i(3)` | IOB_4A | 48 | JP6-12 |
| `gpio_o(0)` (status LED) | IOB_5B | 45 | JP6-13 |
| `gpio_o(1)` | IOB_2A | 47 | JP6-14 |
| `gpio_o(2)` | IOB_0A | 46 | JP6-15 |
| `gpio_o(3)` | IOB_6A | 2 | JP6-16 |
| `flash_csn_o` (spi_cs[0]) | IOB_35B | 16 | - |
| `flash_sck_o` | IOB_34A | 15 | - |
| `flash_sdo_o` | IOB_32A | 14 | - |
| `flash_sdi_i` | IOB_33B | 17 | - |
| `twi_sda_io` | IOT_42B | 31 | JP5-9 |
| `twi_scl_io` | IOT_45A_G1 | 37 | JP5-10 |
| `spi_sdo_o` | IOT_44B | 34 | JP5-11 |
| `spi_sck_o` | IOT_49A | 43 | JP5-12 |
| `spi_csn_o` (spi_cs[1]) | IOT_48B | 36 | JP5-13 |
| `spi_sdi_i` | IOT_51A | 42 | JP5-14 |
| `uart_txd_o` (uart0) | IOT_50B | 38 | JP5-15 |
| `uart_rxd_i` (uart0) | IOT_41A | 28 | JP5-16 |
 
:information_source: The TWI signals (`twi_sda_io` and `twi_scl_io`) and the reset input (`rstn_i`) require an external pull-up resistor. GPIO output 0 (`gpio_o(0)`) is used as output for a high-active status LED driven by the bootloader.
 
 
### FPGA Utilization
 
```
Number of slice registers: 1972 out of 5280 (37%)
Number of I/O registers: 7 out of 117 (6%)
Number of LUT4s: 5123 out of 5280 (97%)
Number of IO sites used: 24 out of 39 (62%)
Number of DSPs: 0 out of 8 (0%)
Number of I2Cs: 0 out of 2 (0%)
Number of High Speed OSCs: 1 out of 1 (100%)
Number of Low Speed OSCs: 0 out of 1 (0%)
Number of RGB PWM: 0 out of 1 (0%)
Number of RGB Drivers: 1 out of 1 (100%)
Number of SCL FILTERs: 0 out of 2 (0%)
Number of SRAMs: 4 out of 4 (100%)
Number of WARMBOOTs: 0 out of 1 (0%)
Number of SPIs: 0 out of 2 (0%)
Number of EBRs: 12 out of 30 (40%)
Number of PLLs: 0 out of 1 (0%)
```
 
## How To Run
 
#### FPGA Setup
 
1. start Lattice Radiant (in GUI mode)
2. click on "open project" and select `neorv32_upduino_v2.rdf` in this folder
3. click the :arrow_forward: button to synthesize, map, place and route the design and to generate a programming file
4. when done open the programmer (for example via "Tools" -> "Programmer")
5. in the programmer double click on the field under "Operation" (_fast configuration_ should be the default) and select "External SPI Memory" as "Target Memory" (and select the correct SPI Flash)
6. click on "Program Device"
 
 
#### NEORV32 Software Framework Modification
 
In order to use the features provided by this setup, minor *optional* changes can be made to the default NEORV32 setup.
 
To use the full 64kB capacity of the DMEM and IMEM, the linker script has to be modified. Open the linker script (`sw/common/neorv32.ld`) and change the default `LENGTH` assignments of `rom` and `ram` to 64kB (modify the RIGHT-most value only, see below):
 
```
rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 4*1024 : 64*1024
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64*1024
```
 
If you want to use the on-board SPI flash also for storing (and automatically booting) NEORV32 software applications you need to configure the default bootloader base address of the
software image in order to prevent overriding the FPGA bitstream. Open the bootloader source code (`sw/bootloader/bootloader.c`) and modify the following definition (see below).
You will need to re-compile (and re-install) the bootloader. This will also require to rerun synthesis.
 
```c
/** SPI flash boot image base address (warning! address might wrap-around!) */
#define SPI_FLASH_BOOT_ADR (0x00020000)
```
 
You will need to recompile the bootloader and re-do FPGA synthesis.
/neorv32/trunk/boards/UPduino_v2/neorv32_dmem.ice40up_spram.vhd
0,0 → 1,161
-- #################################################################################################
-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size DMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
library iCE40UP;
use iCE40UP.components.all;
 
entity neorv32_dmem is
generic (
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
DMEM_SIZE : natural := 64*1024 -- processor-internal instruction memory size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_dmem;
 
architecture neorv32_dmem_rtl of neorv32_dmem is
 
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
 
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
 
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
 
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
 
 
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
dmem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_lo, -- I
MASKWE => spram_be_lo, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
 
dmem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_hi, -- I
MASKWE => spram_be_hi, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
 
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
 
buffer_ff: process(clk_i)
begin
-- sanity check --
if (DMEM_SIZE > 64*1024) then
assert false report "DMEM has a physical size of 64kB. Logical size must be less or equal." severity error;
end if;
-- buffer --
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
 
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
 
 
end neorv32_dmem_rtl;
/neorv32/trunk/boards/UPduino_v2/neorv32_imem.ice40up_spram.vhd
0,0 → 1,166
-- #################################################################################################
-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size IMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
library iCE40UP;
use iCE40UP.components.all;
 
entity neorv32_imem is
generic (
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
IMEM_SIZE : natural := 64*1024; -- processor-internal instruction memory size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLOADER_EN : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_imem;
 
architecture neorv32_imem_rtl of neorv32_imem is
 
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
 
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
 
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
 
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
 
 
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_lo, -- I
MASKWE => spram_be_lo, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
 
imem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_hi, -- I
MASKWE => spram_be_hi, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
 
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
 
buffer_ff: process(clk_i)
begin
-- sanity check --
if (IMEM_AS_ROM = true) or (BOOTLOADER_EN = false) then
assert false report "ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity error;
end if;
if (IMEM_SIZE > 64*1024) then
assert false report "IMEM has a physical size of 64kB. Logical size must be less or equal." severity error;
end if;
-- buffer --
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
 
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
 
 
end neorv32_imem_rtl;
/neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2.pdc
0,0 → 1,42
## Clock (on-chip hf oscillator)
#create_clock -period 41.666666 -name hf_osc_clk [get_nets hf_osc_clk]
 
## Reset (low-active)
ldc_set_location -site {12} [get_ports rstn_i]
 
## UART (uart0)
ldc_set_location -site {38} [get_ports uart_txd_o]
ldc_set_location -site {28} [get_ports uart_rxd_i]
 
## SPI - on-board flash
ldc_set_location -site {14} [get_ports flash_sdo_o]
ldc_set_location -site {15} [get_ports flash_sck_o]
ldc_set_location -site {16} [get_ports flash_csn_o]
ldc_set_location -site {17} [get_ports flash_sdi_i]
 
## SPI - user port
ldc_set_location -site {34} [get_ports spi_sdo_o]
ldc_set_location -site {43} [get_ports spi_sck_o]
ldc_set_location -site {36} [get_ports spi_csn_o]
ldc_set_location -site {42} [get_ports spi_sdi_i]
 
## TWI
ldc_set_location -site {31} [get_ports twi_sda_io]
ldc_set_location -site {37} [get_ports twi_scl_io]
 
## GPIO - input
ldc_set_location -site {44} [get_ports {gpio_i[0]}]
ldc_set_location -site {4} [get_ports {gpio_i[1]}]
ldc_set_location -site {3} [get_ports {gpio_i[2]}]
ldc_set_location -site {48} [get_ports {gpio_i[3]}]
 
## GPIO - output
ldc_set_location -site {45} [get_ports {gpio_o[0]}]
ldc_set_location -site {47} [get_ports {gpio_o[1]}]
ldc_set_location -site {46} [get_ports {gpio_o[2]}]
ldc_set_location -site {2} [get_ports {gpio_o[3]}]
 
## RGB power LED
ldc_set_location -site {39} [get_ports {pwm_o[0]}]
ldc_set_location -site {40} [get_ports {pwm_o[1]}]
ldc_set_location -site {41} [get_ports {pwm_o[2]}]
/neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2.rdf
0,0 → 1,113
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/neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_impl_1.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_impl_1.bin
neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_impl_1.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_top.vhd =================================================================== --- neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_top.vhd (nonexistent) +++ neorv32/trunk/boards/UPduino_v2/neorv32_upduino_v2_top.vhd (revision 58) @@ -0,0 +1,324 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v2" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library iCE40UP; +use iCE40UP.components.all; -- for device primitives + +entity neorv32_upduino_v2_top is + port ( + -- Reset (low-active) -- + rstn_i : in std_ulogic; + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- SPI to on-board flash -- + flash_sck_o : out std_ulogic; + flash_sdo_o : out std_ulogic; + flash_sdi_i : in std_ulogic; + flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) + -- SPI to IO pins -- + spi_sck_o : out std_ulogic; + spi_sdo_o : out std_ulogic; + spi_sdi_i : in std_ulogic; + spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) + -- TWI -- + twi_sda_io : inout std_logic; + twi_scl_io : inout std_logic; + -- GPIO -- + gpio_i : in std_ulogic_vector(3 downto 0); + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_ulogic_vector(2 downto 0) + ); +end neorv32_upduino_v2_top; + +architecture neorv32_upduino_v2_top_rtl of neorv32_upduino_v2_top is + + -- On-chip oscillator -- + constant F_CLOCK : natural := 24000000; -- on-chip HF-OSC output clock frequency in Hz + signal hf_osc_clk : std_logic; + + -- System reset generator -- + signal sys_reset_cnt : std_ulogic_vector(8 downto 0) := (others => '0'); + + -- CPU -- + signal cpu_clk : std_ulogic; + signal cpu_rstn : std_ulogic; + + -- internal IO connection -- + signal con_pwm : std_ulogic_vector(03 downto 0); + signal con_gpio_o : std_ulogic_vector(31 downto 0); + signal con_gpio_i : std_ulogic_vector(31 downto 0); + signal con_spi_sck : std_ulogic; + signal con_spi_sdi : std_ulogic; + signal con_spi_sdo : std_ulogic; + signal con_spi_csn : std_ulogic_vector(07 downto 0); + + -- Misc -- + signal pwm_drive : std_logic_vector(2 downto 0); + signal pwm_driven : std_ulogic_vector(2 downto 0); + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : HSOSC + generic map ( + CLKHF_DIV => "0b01" -- 24 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + cpu_clk <= std_ulogic(hf_osc_clk); + + + -- System Reset Generator ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + sys_reset_generator: process(rstn_i, cpu_clk) + begin + if (rstn_i = '0') then + sys_reset_cnt <= (others => '0'); + elsif rising_edge(cpu_clk) then + if (sys_reset_cnt(sys_reset_cnt'left) = '0') then + sys_reset_cnt <= std_ulogic_vector(unsigned(sys_reset_cnt) + 1); + end if; + end if; + end process sys_reset_generator; + + cpu_rstn <= sys_reset_cnt(sys_reset_cnt'left); + + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => F_CLOCK, -- clock frequency of clk_i in Hz + BOOTLOADER_EN => true, -- implement processor-internal bootloader? + USER_CODE => x"0001ce40", -- custom user code + HW_THREAD_ID => 0, -- hardware thread id (32-bit) + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => false, -- implement bit manipulation extensions? + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => false, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN => false, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => false, -- use barrel shifter for shift operations + TINY_SHIFT_EN => false, -- use tiny (single-bit) shifter for shift operations + CPU_CNT_WIDTH => 36, -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => 0, -- number of regions (0..64) + PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => 0, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => 40, -- total size of HPM counters (1..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => 64*1024, -- size of processor-internal instruction memory in bytes + MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM + + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => 64*1024, -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN => false, -- implement instruction cache + ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface -- + MEM_EXT_EN => false, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => true, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => true, -- implement two-wire interface (TWI)? + IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)? + IO_WDT_EN => true, -- implement watch dog timer (WDT)? + IO_TRNG_EN => true, -- implement true random number generator (TRNG)? + IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NCO_EN => false, -- implement numerically-controlled oscillator (NCO)? + IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? + ) + port map ( + -- Global control -- + clk_i => cpu_clk, -- global clock, rising edge + rstn_i => cpu_rstn, -- global reset, low-active, async + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => open, -- request tag + wb_adr_o => open, -- address + wb_dat_i => (others => '0'), -- read data + wb_dat_o => open, -- write data + wb_we_o => open, -- read/write + wb_sel_o => open, -- byte enable + wb_stb_o => open, -- strobe + wb_cyc_o => open, -- valid cycle + wb_lock_o => open, -- exclusive access request + wb_ack_i => '0', -- transfer acknowledge + wb_err_i => '0', -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + gpio_i => con_gpio_i, -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart_txd_o, -- UART0 send data + uart0_rxd_i => uart_rxd_i, -- UART0 receive data + uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => open, -- UART1 send data + uart1_rxd_i => '0', -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => con_spi_sck, -- SPI serial clock + spi_sdo_o => con_spi_sdo, -- controller data out, peripheral data in + spi_sdi_i => con_spi_sdi, -- controller data in, peripheral data out + spi_csn_o => con_spi_csn, -- SPI CS + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, -- twi serial data line + twi_scl_io => twi_scl_io, -- twi serial clock line + + -- PWM (available if IO_PWM_EN = true) -- + pwm_o => con_pwm, -- pwm channels + + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs conduit + cfs_out_o => open, -- custom CFS outputs conduit + + -- NCO output (available if IO_NCO_EN = true) -- + nco_o => open, -- numerically-controlled oscillator channels + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + + -- system time input from external MTIME (available if IO_MTIME_EN = false) -- + mtime_i => (others => '0'), -- current system time + + -- Interrupts -- + nm_irq_i => '0', -- non-maskable interrupt + soc_firq_i => (others => '0'), -- fast interrupt channels + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- SPI: on-board flash -- + flash_sck_o <= con_spi_sck; + flash_sdo_o <= con_spi_sdo; + flash_csn_o <= con_spi_csn(0); + + -- SPI: user port -- + spi_sck_o <= con_spi_sck; + spi_sdo_o <= con_spi_sdo; + spi_csn_o <= con_spi_csn(1); + + -- SPI sdi read-back -- + con_spi_sdi <= flash_sdi_i when (con_spi_csn(0) = '0') else spi_sdi_i; + + -- GPIO -- + gpio_o <= con_gpio_o(3 downto 0); + con_gpio_i(03 downto 0) <= gpio_i; + con_gpio_i(31 downto 4) <= (others => '0'); + + -- RGB -- + -- bit 0: red - pwm channel 0 + -- bit 1: green - pwm channel 1 + -- bit 2: blue - pwm channel 2 + pwm_drive <= std_logic_vector(con_pwm(2 downto 0)); + + RGB_inst: RGB + generic map ( + CURRENT_MODE => "1", + RGB0_CURRENT => "0b000001", + RGB1_CURRENT => "0b000001", + RGB2_CURRENT => "0b000001" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => pwm_drive(1), -- I - green + RGB1PWM => pwm_drive(2), -- I - blue + RGB2PWM => pwm_drive(0), -- I - red + RGB2 => pwm_driven(2), -- O - red + RGB1 => pwm_driven(1), -- O - blue + RGB0 => pwm_driven(0) -- O - green + ); + + pwm_o <= std_ulogic_vector(pwm_driven); + + +end neorv32_upduino_v2_top_rtl; Index: neorv32/trunk/boards/README.md =================================================================== --- neorv32/trunk/boards/README.md (revision 57) +++ neorv32/trunk/boards/README.md (revision 58) @@ -1,19 +1,18 @@ # Exemplary FPGA Board Setups -**:construction: This page is still under construction :construction:** +This folder provides exemplary NEORV32 SoC setups for different FPGA platforms/boards. You can directly use one of the provided setups +or use them as starting point to build your own setup. -This folder provides exemplary NEORV32 SoC setups for different FPGA platforms/boards. You can use one of the setups to directly get started -or as a starting point to build your own setup. - Project maintainers may make pull requests against this repository to add or link their setups. | Setup | Board | FPGA | Author | -|:-----:|:------|:------|:------:| +|:------|:------|:------|:-------| +| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32/tree/master/boards/de0-nano-test-setup) | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [stnolting](https://github.com/stnolting) | +| :file_folder: [`UPduino_v2`](https://github.com/stnolting/neorv32/tree/master/boards/UPduino_v2) | [tinyVision.ai Inc. UPduino `v2.0`](https://www.tindie.com/products/tinyvision_ai/upduino-v21-low-cost-fpga-board/) (/`v2.1`/`v3`) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`| [stnolting](https://github.com/stnolting) | | :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32/tree/master/boards/arty-a7-35-test-setup) | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) | Xilinx Artix-7 `XC7A35TICSG324-1L` | [stnolting](https://github.com/stnolting) | | :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/boards/nexys-a7-test-setup) | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | | :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/boards/nexys-a7-test-setup) | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) | Xilinx Artix-7 `XC7A100TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | -| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32/tree/master/boards/de0-nano-test-setup) | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [stnolting](https://github.com/stnolting) | ### Adding Your Project Setup
/neorv32/trunk/docs/NEORV32.legacy.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/docs/NEORV32.legacy.pdf
neorv32/trunk/docs/NEORV32.legacy.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: neorv32/trunk/docs/figures/neorv32_processor.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/src_adoc/cpu.adoc =================================================================== --- neorv32/trunk/docs/src_adoc/cpu.adoc (revision 57) +++ neorv32/trunk/docs/src_adoc/cpu.adoc (revision 58) @@ -6,11 +6,11 @@ **Key Features** * 32-bit pipelined/multi-cycle in-order `rv32` RISC-V CPU -* Optional RISC-V extensions: `rv32[i/e][m][a][c][b][Zfinx]` + `[u][Zicsr][Zifencei]` +* Optional RISC-V extensions: `rv32[i/e][m][a][c][b][u]` + `[Zfinx][Zicsr][Zifencei]` * Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications – passes the official RISC-V Architecture Tests (v2+) * Official RISC-V open-source architecture ID -* Safe execution hardware (see section 2.7. Execution Safety); among other things, the CPU supports all traps from the RISC-V specifications -(including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions +* Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts and 1 non-maskable interrupt +* Supports most of the traps from the RISC-V specifications (including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions * Optional physical memory configuration (PMP), compatible to the RISC-V specifications * Optional hardware performance monitors (HPM) for application benchmarking * Separated interfaces for instruction fetch and data access (merged into single bus via a bus switch for @@ -206,11 +206,14 @@ interface provides big- and little-endian configurations. See section <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information. [IMPORTANT] -The `misa` CSR is read-only. It reflects the synthesized CPU extensions. Hence, all implemented +The `misa` CSR is read-only. It shows the synthesized CPU extensions. Hence, all implemented CPU extensions are always active and cannot be enabled/disabled dynamically during runtime. Any write access to it (in machine mode) is ignored and will not cause any exception or side-effects. [IMPORTANT] +The `mip` CSR is read-only. Pending IRQs can be cleared using the `mie` CSR. + +[IMPORTANT] The physical memory protection (see section <<_machine_physical_memory_protection>>) only supports the modes _OFF_ and _NAPOT_ yet and a minimal granularity of 8 bytes per region. @@ -281,6 +284,8 @@ | `d_bus_priv_o` | 2 | out | current CPU privilege level 4+^| **System Time** | `time_i` | 64 | in | system time input (from MTIME) +4+^| **Non-Maskable Interrupt** +| `nm_irq_i` | 1 | in | non-maskable interrupt 4+^| **Interrupts (RISC-V-compatible)** | `msw_irq_i` | 1 | in | RISC-V machine software interrupt | `mext_irq_i` | 1 | in | RISC-V machine external interrupt @@ -719,11 +724,19 @@ **Custom Fast Interrupt Request Lines** -As a custom extension, the NEORV32 CPU features 16 fast interrupt request lines via the `firq_i` CPU top +As a custom extension, the NEORV32 CPU features 16 fast interrupt request lines via the `firq_i` CPU (/Processor) top entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also -provide custom trap codes. +provide custom trap codes in `mcause`. +**Non-Maskable Interrupt** + +The NEORV32 CPU features a single non-maskable interrupt source via the `nm_irq_i` CPU (/Processor) top +entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled at all (even not in interrupt service routines). +Hence, it does _not_ provide configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible +`mcause` value `0x80000000` is used to indicate the non-maskable interrupt. + + <<< // #################################################################################################################### :sectnums!: @@ -734,36 +747,36 @@ [options="header",grid="rows"] |======================= | Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval` -| 1 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_ +| 1 | `0x80000000` | 1.0 | _TRAP_CODE_NMI_ | non-maskable interrupt | _I-PC_ | _0_ | 2 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_ -| 2 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_ -| 3 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt (from mtime) | _I-PC_ | _0_ -| 4 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel | _I-PC_ | _0_ -| 5 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel | _I-PC_ | _0_ -| 6 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel | _I-PC_ | _0_ -| 7 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel | _I-PC_ | _0_ -| 8 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel | _I-PC_ | _0_ -| 9 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel | _I-PC_ | _0_ -| 10 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel | _I-PC_ | _0_ -| 11 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel | _I-PC_ | _0_ -| 12 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel | _I-PC_ | _0_ -| 13 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel | _I-PC_ | _0_ -| 14 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel | _I-PC_ | _0_ -| 15 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel | _I-PC_ | _0_ -| 16 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel | _I-PC_ | _0_ -| 17 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel | _I-PC_ | _0_ -| 18 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel | _I-PC_ | _0_ -| 19 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel | _I-PC_ | _0_ -| 20 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_ -| 21 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_ -| 22 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_ -| 23 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (ECALL in machine-mode) | _PC_ | _PC_ -| 24 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode(ECALL in user-mode) | _PC_ | _PC_ -| 25 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_ -| 26 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_ -| 27 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_ -| 28 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_ -| 29 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | lad access fault | _B-ADR_ | _B-ADR_ +| 3 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_ +| 4 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt (from mtime) | _I-PC_ | _0_ +| 5 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel | _I-PC_ | _0_ +| 6 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel | _I-PC_ | _0_ +| 7 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel | _I-PC_ | _0_ +| 8 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel | _I-PC_ | _0_ +| 9 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel | _I-PC_ | _0_ +| 10 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel | _I-PC_ | _0_ +| 11 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel | _I-PC_ | _0_ +| 12 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel | _I-PC_ | _0_ +| 13 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel | _I-PC_ | _0_ +| 14 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel | _I-PC_ | _0_ +| 15 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel | _I-PC_ | _0_ +| 16 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel | _I-PC_ | _0_ +| 17 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel | _I-PC_ | _0_ +| 18 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel | _I-PC_ | _0_ +| 19 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel | _I-PC_ | _0_ +| 20 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel | _I-PC_ | _0_ +| 21 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_ +| 22 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_ +| 23 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_ +| 24 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (ECALL in machine-mode) | _PC_ | _PC_ +| 25 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode(ECALL in user-mode) | _PC_ | _PC_ +| 26 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_ +| 27 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_ +| 28 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_ +| 29 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_ +| 30 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | lad access fault | _B-ADR_ | _B-ADR_ |======================= **Notes**
/neorv32/trunk/docs/src_adoc/cpu_csr.adoc
55,7 → 55,7
* `S` - have a constrained compatibility; for example not all specified bits are available
 
.NEORV32 Control and Status Registers (CSRs)
[cols="<1,<2,<2,^1,<3,^1"]
[cols="<4,<6,<11,^3,<11,^3"]
[options="header"]
|=======================
| Address | Name [ASM] | Name [C] | R/W | Function | Note
69,13 → 69,13
| 0x304 | `mie` | _CSR_MIE_ | r/w | Machine interrupt enable register | `C`
| 0x305 | `mtvec` | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
| 0x306 | `mcounteren` | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `S`
| 0x310 | `mstatush` | _CSR_MSTATUSH_ | r/- | Machine status register – high word | `SR`
| 0x310 | `mstatush` | _CSR_MSTATUSH_ | r/- | Machine status register – high word | `RS`
6+^| **<<_machine_trap_handling>>**
| 0x340 | `mscratch` | _CSR_MSCRATCH_ | r/w | Machine scratch register |
| 0x341 | `mepc` | _CSR_MEPC_ | r/w | Machine exception program counter |
| 0x342 | `mcause` | _CSR_MCAUSE_ | r/w | Machine trap cause | `C`
| 0x343 | `mtval` | _CSR_MTVAL_ | r/w | Machine bad address or instruction |
| 0x344 | `mip` | _CSR_MIP_ | r/w | Machine interrupt pending register | `C`
| 0x344 | `mip` | _CSR_MIP_ | r/- | Machine interrupt pending register | `CR`
6+^| **<<_machine_physical_memory_protection>>**
| 0x3a0 .. 0x3af | `pmpcfg0` .. `pmpcfg15` | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `S`
| 0x3b0 .. 0x3ef | `pmpaddr0` .. `pmpaddr63`| _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
379,9 → 379,10
[frame="topbot",grid="none"]
|======
| 0x344 | **Machine interrupt Pending** | `mip`
3+| Reset value: _UNDEFINED_
3+| The `mip` CSR is compatible to the RISC-V specifications and provides custom extensions. It shows pending interrupts. Any pending interrupt can
be cleared by writing zero to the according bit(s). The following CSR bits are implemented (all remaining bits are always zero and are read-only).
3+| Reset value: _0x00000000_
3+| The `mip` CSR is _partly_ compatible to the RISC-V specifications and also provides custom extensions. It shows currently pending interrupts. Since this register is
read-only, pending interrupt can only be cleared by disabling and re-enabling the according `mie` CSr bit. Writing to this CSR will
raise an illegal instruction exception. The following CSR bits are implemented (all remaining bits are always zero and are read-only).
|======
 
.Machine interrupt pending register
389,10 → 390,10
[options="header",grid="rows"]
|=======================
| Bit | Name [C] | R/W | Function
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/w | fast interrupt channel 15..0 pending
| 11 | _CSR_MIP_MEIP_ | r/w | machine _external_ interrupt pending
| 7 | _CSR_MIP_MTIP_ | r/w | machine _timer_ interrupt pending
| 3 | _CSR_MIP_MSIP_ | r/w | machine _software_ interrupt pending
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/- | fast interrupt channel 15..0 pending
| 11 | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending
| 7 | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending
| 3 | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending
|=======================
 
 
407,7 → 408,7
 
[TIP]
If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
exception** is triggered. The according CSRs are read-only and always return zero.
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
 
[IMPORTANT]
The RISC-V-compatible NEORV32 physical memory protection only implements the _NAPOT_
568,11 → 569,11
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
according `[m]hpmcounter*[h]` and `mhpmevent*` CSRs.
 
The total size of the HPMs can be configured before syntheis via the _HPM_CNT_WIDTH_ generic (1..64-bit).
The total size of the HPMs can be configured before synthesis via the _HPM_CNT_WIDTH_ generic (1..64-bit).
 
[TIP]
If trying to access an HPM-related CSR beyond _HPM_NUM_CNTS_ **no illegal instruction exception is
triggered**. The according CSRs are read-only and always return zero.
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
 
[NOTE]
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
774,4 → 775,6
| 5 | _CPU_MZEXT_ZFINX_ | r/- | `Zfinx` extensions available (enabled via _CPU_EXTENSION_RISCV_Zfinx_ generic)
| 6 | _CPU_MZEXT_ZXSCNT_ | r/- | custom extension: "Small CPU counters": `cycle[h]` & `instret[h]` CSRs have less than 64-bit when set (when _CPU_CNT_WIDTH_ generic is less than 64).
| 7 | _CPU_MZEXT_ZXNOCNT_ | r/- | custom extension: "NO CPU counters": `cycle[h]` & `instret[h]` CSRs are not available at all when set (when _CPU_CNT_WIDTH_ generic is 0).
| 8 | _CSR_MZEXT_PMP_ | r/- | PMP (physical memory protection) extension available (_PMP_NUM_REGIONS_ generic > 0) when set (r/-)
| 9 | _CSR_MZEXT_HPM_ | r/- | HPM (hardware performance monitors) extension available (_HPM_NUM_CNTS_ generic > 0) when set (r/-)
|=======================
/neorv32/trunk/docs/src_adoc/neorv32.adoc
2,7 → 2,7
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.4.8
:revnumber: v1.5.5.0
:doctype: book
:sectnums:
:icons: image
/neorv32/trunk/docs/src_adoc/overview.adoc
209,33 → 209,34
[cols="<2,<8"]
[grid="topbot"]
|=======================
| Hardware version: | `1.5.2.4`
| Hardware version: | `1.5.4.9`
| Top entity: | `rtl/core/neorv32_top.vhd`
|=======================
 
.Hardware utilization by the processor modules
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
[cols="<2,<8,>1,>1,>2,>1"]
[options="header",grid="rows"]
|=======================
| Module | Description | LEs | FFs | MEM bits | DSPs
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0
| BUSSWITCH | Bus mux for CPU instr. and data interfaces | 65 | 8 | 0 | 0
| iCACHE | Instruction cache (4 blocks, 256 bytes per block) | 234 | 156 | 8192 | 0
| CFS | Custom functions subsystem | - | - | - | -
| DMEM | Processor-internal data memory (8kB) | 6 | 2 | 65536 | 0
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
| MTIME | Machine system timer | 274 | 166 | 0 | 0
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0
| SYSINFO | System configuration information memory | 10 | 10 | 0 | 0
| TRNG | True random number generator | 132 | 105 | 0 | 0
| TWI | Two-wire interface | 77 | 44 | 0 | 0
| UART0/1 | Universal asynchronous receiver/transmitter | 176 | 132 | 0 | 0
| WDT | Watchdog timer | 60 | 45 | 0 | 0
| WISHBONE | External memory interface | 129 | 104 | 0 | 0
| Module | Description | LEs | FFs | MEM bits | DSPs
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0
| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0
| CFS | Custom functions subsystem | - | - | - | -
| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
| MTIME | Machine system timer | 289 | 200 | 0 | 0
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0
| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0
| TRNG | True random number generator | 132 | 105 | 0 | 0
| TWI | Two-wire interface | 77 | 44 | 0 | 0
| UART0/1 | Universal asynchronous receiver/transmitter o/1 | 176 | 132 | 0 | 0
| WDT | Watchdog timer | 60 | 45 | 0 | 0
| WISHBONE | External memory interface | 129 | 104 | 0 | 0
|=======================
 
 
/neorv32/trunk/docs/src_adoc/soc.adoc
94,6 → 94,7
4+^| **System time input from external MTIME unit**
| `mtime_i` | 32 | in | machine timer time (to `time[h]` CSRs) from external _MTIME_ unit if the processor-internal <<_machine_system_timer_mtime,**MTIME**>> unit is NOT used
4+^| **Interrupts**
| `nm_irq_i` | 1 | in | non-maskable interrupt
| `soc_firq_i` | 6 | in | platform fast interrupt channels (custom)
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V)
314,7 → 315,8
|======
| **PMP_NUM_REGIONS** | _natural_ | 0
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
protection logic will be implemented at all.
protection logic will be implemented at all. Setting _PMP_NUM_REGIONS_ > 0 will set the _CSR_MZEXT_PMP_ flag
in the `mzext` CSR.
|======
 
 
337,7 → 339,8
|======
| **HPM_NUM_CNTS** | _natural_ | 0
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
hardware performance monitor logic will be implemented at all.
hardware performance monitor logic will be implemented at all. Setting _HPM_NUM_CNTS_ > 0 will set the _CSR_MZEXT_HPM_ flag
in the `mzext` CSR.
|======
 
 
612,6 → 615,11
:sectnums:
=== Processor Interrupts
 
[TIP]
The interrupt request signals have specific `mip` CSR bits (see <<_machine_trap_setup>>), specifc
`mie` CSR bits (see <<_machine_trap_handling>>) and specifc `mcause` CSR trap codes and trap
priorities (see <<_traps_exceptions_and_interrupts>>).
 
**RISC-V Standard Interrupts**
 
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
625,11 → 633,6
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
(`FIRQ0` – `FIRQ15`).
 
[TIP]
The fast interrupt request signals have custom `mip` CSR bits (see <<_machine_trap_setup>>), custom
`mie` CSR bits (see <<_machine_trap_handling>>) and custom `mcause` CSR trap codes and trap
priories (see <<_traps_exceptions_and_interrupts>>).
 
The fast interrupt request signals are divided into two groups. The FIRQs with higher priority (FIRQ0 –
FIRQ9) are dedicated for processor-internal usage. The FIRQs with lower priority (FIRQ10 – FIRQ15) are
available for custom usage via the processor's top entity signal `soc_firq_i`.
654,7 → 657,12
| 10:15 | `soc_firq_i(5:0)` | Custom platform use; available via processor's top signal
|=======================
 
**Non-Maskable Interrupt**
 
The NEORV32 features a single non-maskable interrupt source via the `nm_irq_i` top
entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled. Hence, it does _not_ provide
configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible `mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
 
<<<
// ####################################################################################################################
:sectnums:
670,6 → 678,10
.NEORV32 processor - address space (default configuration)
image::../figures/address_space.png[900]
 
[TIP]
These four memory regions are handled by the linker when compiling a NEORV32 executable.
See section <<_executable_image_format>> for more information.
 
**Address Space Layout**
 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
/neorv32/trunk/docs/src_adoc/soc_pwm.adoc
46,7 → 46,7
 
[TIP]
A more sophisticated frequency generation option is provided by by the numerically-controlled oscillator
module (see section <<_numerically_controller-oscillator_nco>>).
module (see section <<_numerically_controller_oscillator_nco>>).
 
<<<
.PWM register map
/neorv32/trunk/docs/src_adoc/software.adoc
207,6 → 207,7
example: `$ make MARCH=-march=rv32ic clean_all exe`
 
 
 
<<<
// ####################################################################################################################
:sectnums:
213,13 → 214,34
=== Executable Image Format
 
When all the application sources have been compiled and linked, a final executable file has to be generated.
For this purpose, the makefile uses the NEORV32-specific linker script `sw/common/neorv32.ld` to link
all the sections into only four final sections: `.text`, `.rodata`, `.data` and `.bss`. These four section contain
everything required for the application to run:
For this purpose, the makefile uses the NEORV32-specific linker script `sw/common/neorv32.ld`. This linker script defines three memory sections:
`rom`, `ram` and `iodev`. These sections have specific access attributes: Read access (`r`), write access (`w`) and executable (`x`).
 
.Linker memory sections
[cols="<2,^1,<7"]
[options="header",grid="rows"]
|=======================
| Memory section | Attributes | Description
| `rom` | `rx` | Instruction memory (IMEM) **OR** bootloader ROM
| `ram` | `rwx` | Data memory (DMEM)
| `iodev` | `rw` | Memory-mapped IO/peripheral devices
|=======================
 
The `iodev` section is reserved for processor-internal memory-mapped IO and peripheral devices. The linker does not use this section at all
and just passes the start and end adresses of this section to the start-up code `crt0.S` (see next section).
 
[NOTE]
The `rom` region is used to place the instructions of "normal" applications. If the bootloader is being compiled, the makefile defines the `make_bootloader`
symbol, which changes the _ORIGIN_ (base address) and _LENGTH_ (size) attributes of the `rom` region according to the BOOTROM definitions.
 
The linker maps all the regions from the compiled object files into only four final sections: `.text`, `.rodata`, `.data` and `.bss`
using the specified memory section. These four regions contain everything required for the application to run:
 
.Executable regions
[cols="<1,<9"]
[grid="none"]
[options="header",grid="rows"]
|=======================
| Region | Description
| `.text` | Executable instructions generated from the start-up code and all application sources.
| `.rodata` | Constants (like strings) from the application; also the initial data for initialized variables.
| `.data` | This section is required for the address generation of fixed (= global) variables only.
255,7 → 277,22
provides a simple protection against data transmission or storage errors.
 
 
=== Start-Up Code (crt0)
 
The CPU (and also the processor) requires a minimal start-up and initialization code o bring the CPU (and the SoC) into a stable and initialized state before the
acutal application can be executed. This start-up code is located in `sw/common/crt0.S` and is automatically linked with _every_ application program.
The `crt0.S` is directly executed right after a reset and performs the following operations:
 
* Initialize integer registers `x1 - x31` (or `x1 - x15` when using the `E` CPU extension) to a defined value.
* Initialize all CPU core CSRs and also install a default "dummy" trap handler for _all_ traps.
* Initialize the global pointer `gp` and the stack pointer `sp` according to the `.data` segment layout provided by the linker script.
* Clear IO area: Write zero to all memory-mapped registers within the IO region (`iodev` section). If certain devices have not been implemented, a bus access fault exception will occur. This exception is captured by the dummy trap handler.
* Clear the `.bss` section defined by the linker script.
* Copy read-only data from the `.text` section to the `.data` section to set initialized variables.
* Call the application's `main` function (with no arguments: `argc` = `argv` = 0).
* If the `main` function returns, the processor goes to an endless sleep mode (using a simple loop or via the `wfi` instruction if available).
 
 
<<<
// ####################################################################################################################
:sectnums:
466,37 → 503,13
:sectnums:
=== NEORV32 Runtime Environment
 
The NEORV32 provides a minimal runtime environment (RTE) that mainly takes care of two things:
The NEORV32 provides a minimal runtime environment (RTE) that takes care of a stable
and _safe_ execution environment by handling _all_ traps (including interrupts).
 
* clean application start
* stable and _safe_ execution environment (e.g. handling of exceptions/interrupts)
 
[NOTE]
Performance or latency-optimized applications or embedded operating systems should use a custom
trap management.
Using the RTE is **optional**. The RTE provides a simple and comfortable way of delegating traps while making sure that all traps (even though they are not
explicitly used by the application) are handled correctly. Performance-optimized applications or embedded operating systems should not use the RTE for delegating traps.
 
 
:sectnums:
==== CRT0 Start-Up Code
 
The initial part of the runtime environment is the `sw/common/crt0.S` application start-up code. This piece
of code is automatically linked with every application program and represents the starting point for every
application - regardless if you are using the actual RTE in your application or not. The start-up code is directly executed after a reset.
Ir performs the following operations to bring the CPU (and the SoC) into a stable and initialized state:
 
* Initialize integer registers `x1` – `x15`/`x31`.
* Initialize all CPU core CSRs.
* Initialize the global pointer `gp` and the stack pointer `sp` according to the `.data` segment layout provided by the linker script.
* Clear IO area: Write zero to all memory-mapped registers within the IO region. If certain devices have not been implemented, a bus access fault exception will occur. This exception is captured by a simple dummy handler in the start-up code.
* Clear the `.bss` section defined by the linker script.
* Copy read-only data from the `.text` section to the `.data` section to set initialized variables.
* Call the application's `main` function (with no arguments).
* If the `main` function returns, the processor goes to an endless sleep mode (using a simple loop or via the `wfi` instruction if available).
 
 
:sectnums:
==== Using the NEORV32 Runtime Environment (RTE) in Your Application
 
When execution enters the application's `main` function, the actual runtime environment is responsible for catching all implemented exceptions
and interrupts. To activate the NEORV32 RTE execute the following function:
 
/neorv32/trunk/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1071) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1062) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
15,1070 → 15,1061
00000004 => x"00000293",
00000005 => x"00000313",
00000006 => x"00000393",
00000007 => x"00000413",
00000008 => x"00000493",
00000009 => x"00000713",
00000010 => x"00000793",
00000011 => x"00000517",
00000012 => x"10c50513",
00000013 => x"30551073",
00000014 => x"34151073",
00000015 => x"34301073",
00000016 => x"34201073",
00000017 => x"30001073",
00000018 => x"30401073",
00000019 => x"30601073",
00000020 => x"ffa00593",
00000021 => x"32059073",
00000022 => x"b0001073",
00000023 => x"b8001073",
00000024 => x"b0201073",
00000025 => x"b8201073",
00000026 => x"00000813",
00000027 => x"00000893",
00000028 => x"00000913",
00000029 => x"00000993",
00000030 => x"00000a13",
00000031 => x"00000a93",
00000032 => x"00000b13",
00000033 => x"00000b93",
00000034 => x"00000c13",
00000035 => x"00000c93",
00000036 => x"00000d13",
00000037 => x"00000d93",
00000038 => x"00000e13",
00000039 => x"00000e93",
00000040 => x"00000f13",
00000041 => x"00000f93",
00000042 => x"80002117",
00000043 => x"f5410113",
00000044 => x"ffc17113",
00000045 => x"00010413",
00000046 => x"80000197",
00000047 => x"74818193",
00000048 => x"f0000593",
00000049 => x"0005a023",
00000050 => x"00458593",
00000051 => x"feb01ce3",
00000052 => x"80000597",
00000053 => x"f3058593",
00000054 => x"87418613",
00000055 => x"00c5d863",
00000056 => x"00058023",
00000057 => x"00158593",
00000058 => x"ff5ff06f",
00000059 => x"00001597",
00000060 => x"fd058593",
00000061 => x"80000617",
00000062 => x"f0c60613",
00000063 => x"80000697",
00000064 => x"f0468693",
00000065 => x"00d65c63",
00000066 => x"00058703",
00000067 => x"00e60023",
00000068 => x"00158593",
00000069 => x"00160613",
00000070 => x"fedff06f",
00000071 => x"00000513",
00000072 => x"00000593",
00000073 => x"060000ef",
00000074 => x"30047073",
00000075 => x"00000013",
00000076 => x"10500073",
00000077 => x"0000006f",
00000078 => x"ff810113",
00000079 => x"00812023",
00000080 => x"00912223",
00000081 => x"34202473",
00000082 => x"02044663",
00000083 => x"34102473",
00000084 => x"00041483",
00000085 => x"0034f493",
00000086 => x"00240413",
00000087 => x"34141073",
00000088 => x"00300413",
00000089 => x"00941863",
00000090 => x"34102473",
00000091 => x"00240413",
00000092 => x"34141073",
00000093 => x"00012403",
00000094 => x"00412483",
00000095 => x"00810113",
00000096 => x"30200073",
00000097 => x"00005537",
00000098 => x"ff010113",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"730000ef",
00000104 => x"16d000ef",
00000105 => x"02050063",
00000106 => x"4a8000ef",
00000107 => x"00000513",
00000108 => x"4fc000ef",
00000109 => x"00001537",
00000110 => x"d5050513",
00000111 => x"780000ef",
00000112 => x"020000ef",
00000113 => x"00001537",
00000114 => x"d2c50513",
00000115 => x"770000ef",
00000116 => x"00c12083",
00000117 => x"00000513",
00000118 => x"01010113",
00000119 => x"00008067",
00000120 => x"ff010113",
00000121 => x"00000513",
00000122 => x"00812423",
00000123 => x"00112623",
00000124 => x"00000413",
00000125 => x"129000ef",
00000126 => x"0ff47513",
00000127 => x"121000ef",
00000128 => x"0c800513",
00000129 => x"14d000ef",
00000130 => x"00140413",
00000131 => x"fedff06f",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
00000135 => x"02612a23",
00000136 => x"02712823",
00000137 => x"02a12623",
00000138 => x"02b12423",
00000139 => x"02c12223",
00000140 => x"02d12023",
00000141 => x"00e12e23",
00000142 => x"00f12c23",
00000143 => x"01012a23",
00000144 => x"01112823",
00000145 => x"01c12623",
00000146 => x"01d12423",
00000147 => x"01e12223",
00000148 => x"01f12023",
00000149 => x"34102773",
00000150 => x"34071073",
00000151 => x"342027f3",
00000152 => x"0807c863",
00000153 => x"00071683",
00000154 => x"00300593",
00000155 => x"0036f693",
00000156 => x"00270613",
00000157 => x"00b69463",
00000158 => x"00470613",
00000159 => x"34161073",
00000160 => x"00b00713",
00000161 => x"04f77a63",
00000162 => x"48c00793",
00000163 => x"000780e7",
00000164 => x"03c12083",
00000165 => x"03812283",
00000166 => x"03412303",
00000167 => x"03012383",
00000168 => x"02c12503",
00000169 => x"02812583",
00000170 => x"02412603",
00000171 => x"02012683",
00000172 => x"01c12703",
00000173 => x"01812783",
00000174 => x"01412803",
00000175 => x"01012883",
00000176 => x"00c12e03",
00000177 => x"00812e83",
00000178 => x"00412f03",
00000179 => x"00012f83",
00000180 => x"04010113",
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"d6c70713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
00000188 => x"80000737",
00000189 => x"ffd74713",
00000190 => x"00e787b3",
00000191 => x"01c00713",
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d9c70713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
00000199 => x"800007b7",
00000200 => x"0007a783",
00000201 => x"f69ff06f",
00000202 => x"800007b7",
00000203 => x"0047a783",
00000204 => x"f5dff06f",
00000205 => x"800007b7",
00000206 => x"0087a783",
00000207 => x"f51ff06f",
00000208 => x"800007b7",
00000209 => x"00c7a783",
00000210 => x"f45ff06f",
00000211 => x"8101a783",
00000212 => x"f3dff06f",
00000213 => x"8141a783",
00000214 => x"f35ff06f",
00000215 => x"8181a783",
00000216 => x"f2dff06f",
00000217 => x"81c1a783",
00000218 => x"f25ff06f",
00000219 => x"8201a783",
00000220 => x"f1dff06f",
00000221 => x"8241a783",
00000222 => x"f15ff06f",
00000223 => x"8281a783",
00000224 => x"f0dff06f",
00000225 => x"82c1a783",
00000226 => x"f05ff06f",
00000227 => x"8301a783",
00000228 => x"efdff06f",
00000229 => x"8341a783",
00000230 => x"ef5ff06f",
00000231 => x"8381a783",
00000232 => x"eedff06f",
00000233 => x"83c1a783",
00000234 => x"ee5ff06f",
00000235 => x"8401a783",
00000236 => x"eddff06f",
00000237 => x"8441a783",
00000238 => x"ed5ff06f",
00000239 => x"8481a783",
00000240 => x"ecdff06f",
00000241 => x"84c1a783",
00000242 => x"ec5ff06f",
00000243 => x"8501a783",
00000244 => x"ebdff06f",
00000245 => x"8541a783",
00000246 => x"eb5ff06f",
00000247 => x"8581a783",
00000248 => x"eadff06f",
00000249 => x"85c1a783",
00000250 => x"ea5ff06f",
00000251 => x"8601a783",
00000252 => x"e9dff06f",
00000253 => x"8641a783",
00000254 => x"e95ff06f",
00000255 => x"8681a783",
00000256 => x"e8dff06f",
00000257 => x"86c1a783",
00000258 => x"e85ff06f",
00000259 => x"8701a783",
00000260 => x"e7dff06f",
00000261 => x"00000000",
00000262 => x"00000000",
00000263 => x"fe010113",
00000264 => x"01212823",
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"e1050513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"4f4000ef",
00000275 => x"08c48493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"478000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
00000286 => x"01412483",
00000287 => x"01012903",
00000288 => x"00c12983",
00000289 => x"02010113",
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"e1450513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"498000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
00000301 => x"05778493",
00000302 => x"00f76463",
00000303 => x"03078493",
00000304 => x"00b00793",
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"fa070713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
00000312 => x"800007b7",
00000313 => x"00b78713",
00000314 => x"12e40663",
00000315 => x"02876663",
00000316 => x"00378713",
00000317 => x"10e40463",
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f7450513",
00000322 => x"434000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
00000326 => x"ff07c793",
00000327 => x"00f407b3",
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"f6450513",
00000332 => x"40c000ef",
00000333 => x"00048513",
00000334 => x"3a8000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"e1c50513",
00000338 => x"3f4000ef",
00000339 => x"00001537",
00000340 => x"f8c50513",
00000341 => x"3e8000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f9450513",
00000346 => x"3d4000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"ffc50513",
00000354 => x"01010113",
00000355 => x"3b00006f",
00000356 => x"00001537",
00000357 => x"e3c50513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"e5850513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"e6c50513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e7850513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e9050513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"ea450513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"ec050513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"ed450513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"ef450513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"f1450513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"f3050513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"f4850513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
00000394 => x"800007b7",
00000395 => x"00078793",
00000396 => x"00251513",
00000397 => x"00a78533",
00000398 => x"48c00793",
00000399 => x"00f52023",
00000400 => x"00000513",
00000401 => x"00008067",
00000402 => x"00100513",
00000403 => x"00008067",
00000404 => x"ff010113",
00000405 => x"00112623",
00000406 => x"00812423",
00000407 => x"00912223",
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"fd050513",
00000412 => x"2cc000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
00000416 => x"01d00493",
00000417 => x"00040513",
00000418 => x"00140413",
00000419 => x"0ff47413",
00000420 => x"f91ff0ef",
00000421 => x"fe9418e3",
00000422 => x"00c12083",
00000423 => x"00812403",
00000424 => x"00412483",
00000425 => x"01010113",
00000426 => x"00008067",
00000427 => x"ff010113",
00000428 => x"00112623",
00000429 => x"00812423",
00000430 => x"30102673",
00000431 => x"400005b7",
00000432 => x"10058593",
00000433 => x"00b677b3",
00000434 => x"00000413",
00000435 => x"00b78c63",
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"00450513",
00000440 => x"3f8000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
00000444 => x"01010113",
00000445 => x"00008067",
00000446 => x"fd010113",
00000447 => x"02812423",
00000448 => x"02912223",
00000449 => x"03212023",
00000450 => x"01312e23",
00000451 => x"01412c23",
00000452 => x"02112623",
00000453 => x"01512a23",
00000454 => x"00001a37",
00000455 => x"00050493",
00000456 => x"00058413",
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"09ca0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"58c000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"528000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
00000474 => x"fcf996e3",
00000475 => x"00090693",
00000476 => x"00900713",
00000477 => x"03000613",
00000478 => x"0096c583",
00000479 => x"00070793",
00000480 => x"fff70713",
00000481 => x"01071713",
00000482 => x"01075713",
00000483 => x"00c59a63",
00000484 => x"000684a3",
00000485 => x"fff68693",
00000486 => x"fe0710e3",
00000487 => x"00000793",
00000488 => x"00f907b3",
00000489 => x"00000593",
00000490 => x"0007c703",
00000491 => x"00070c63",
00000492 => x"00158693",
00000493 => x"00b405b3",
00000494 => x"00e58023",
00000495 => x"01069593",
00000496 => x"0105d593",
00000497 => x"fff78713",
00000498 => x"02f91863",
00000499 => x"00b40433",
00000500 => x"00040023",
00000501 => x"02c12083",
00000502 => x"02812403",
00000503 => x"02412483",
00000504 => x"02012903",
00000505 => x"01c12983",
00000506 => x"01812a03",
00000507 => x"01412a83",
00000508 => x"03010113",
00000509 => x"00008067",
00000510 => x"00070793",
00000511 => x"fadff06f",
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"0a860613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
00000519 => x"00f607b3",
00000520 => x"0007c783",
00000521 => x"00470713",
00000522 => x"fff68693",
00000523 => x"00f680a3",
00000524 => x"ff0712e3",
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002703",
00000529 => x"00151513",
00000530 => x"00000793",
00000531 => x"04a77463",
00000532 => x"000016b7",
00000533 => x"00000713",
00000534 => x"ffe68693",
00000535 => x"04f6e663",
00000536 => x"00367613",
00000537 => x"0035f593",
00000538 => x"fff78793",
00000539 => x"01461613",
00000540 => x"00c7e7b3",
00000541 => x"01659593",
00000542 => x"01871713",
00000543 => x"00b7e7b3",
00000544 => x"00e7e7b3",
00000545 => x"10000737",
00000546 => x"00e7e7b3",
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00000857 => x"000007b4",
00000858 => x"000007c0",
00000859 => x"000007cc",
00000860 => x"000007d4",
00000861 => x"000007dc",
00000862 => x"000007e4",
00000863 => x"000007ec",
00000864 => x"00000708",
00000865 => x"00000708",
00000866 => x"000007f4",
00000867 => x"000007fc",
00000868 => x"00000708",
00000869 => x"00000708",
00000870 => x"00000804",
00000871 => x"00000708",
00000872 => x"00000708",
00000873 => x"00000708",
00000874 => x"0000080c",
00000875 => x"00000708",
00000876 => x"00000708",
00000877 => x"00000708",
00000878 => x"00000814",
00000879 => x"00000708",
00000880 => x"00000708",
00000881 => x"00000708",
00000882 => x"00000708",
00000883 => x"0000081c",
00000884 => x"00000824",
00000885 => x"0000082c",
00000886 => x"00000834",
00000887 => x"0000083c",
00000888 => x"00000844",
00000889 => x"0000084c",
00000890 => x"00000854",
00000891 => x"0000085c",
00000892 => x"00000864",
00000893 => x"0000086c",
00000894 => x"00000874",
00000895 => x"0000087c",
00000896 => x"00000884",
00000897 => x"0000088c",
00000898 => x"00000894",
00000899 => x"00007830",
00000900 => x"4554523c",
00000901 => x"0000203e",
00000902 => x"74736e49",
00000903 => x"74637572",
00000904 => x"206e6f69",
00000905 => x"72646461",
00000906 => x"20737365",
00000907 => x"6173696d",
00000908 => x"6e67696c",
00000909 => x"00006465",
00000910 => x"74736e49",
00000911 => x"74637572",
00000912 => x"206e6f69",
00000913 => x"65636361",
00000914 => x"66207373",
00000915 => x"746c7561",
00000916 => x"00000000",
00000917 => x"656c6c49",
00000918 => x"206c6167",
00000919 => x"74736e69",
00000920 => x"74637572",
00000921 => x"006e6f69",
00000922 => x"61657242",
00000923 => x"696f706b",
00000924 => x"0000746e",
00000925 => x"64616f4c",
00000926 => x"64646120",
00000927 => x"73736572",
00000928 => x"73696d20",
00000929 => x"67696c61",
00000930 => x"0064656e",
00000931 => x"64616f4c",
00000932 => x"63636120",
00000933 => x"20737365",
00000934 => x"6c756166",
00000935 => x"00000074",
00000936 => x"726f7453",
00000937 => x"64612065",
00000938 => x"73657264",
00000939 => x"696d2073",
00000940 => x"696c6173",
00000941 => x"64656e67",
00000942 => x"00000000",
00000943 => x"726f7453",
00000944 => x"63612065",
00000945 => x"73736563",
00000946 => x"75616620",
00000947 => x"0000746c",
00000948 => x"69766e45",
00000949 => x"6d6e6f72",
00000950 => x"20746e65",
00000951 => x"6c6c6163",
00000952 => x"6f726620",
00000953 => x"2d55206d",
00000954 => x"65646f6d",
00000955 => x"00000000",
00000956 => x"69766e45",
00000957 => x"6d6e6f72",
00000958 => x"20746e65",
00000959 => x"6c6c6163",
00000960 => x"6f726620",
00000961 => x"2d4d206d",
00000962 => x"65646f6d",
00000963 => x"00000000",
00000964 => x"6863614d",
00000965 => x"20656e69",
00000966 => x"74666f73",
00000967 => x"65726177",
00000968 => x"746e6920",
00000969 => x"75727265",
00000970 => x"00007470",
00000971 => x"6863614d",
00000972 => x"20656e69",
00000973 => x"656d6974",
00000974 => x"6e692072",
00000975 => x"72726574",
00000976 => x"00747075",
00000977 => x"6863614d",
00000978 => x"20656e69",
00000979 => x"65747865",
00000980 => x"6c616e72",
00000981 => x"746e6920",
00000982 => x"75727265",
00000983 => x"00007470",
00000984 => x"74736146",
00000985 => x"746e6920",
00000986 => x"75727265",
00000987 => x"00207470",
00000988 => x"6e6b6e55",
00000989 => x"206e776f",
00000990 => x"70617274",
00000991 => x"75616320",
00000992 => x"203a6573",
00000993 => x"00000000",
00000994 => x"50204020",
00000995 => x"00003d43",
00000996 => x"544d202c",
00000997 => x"3d4c4156",
00000998 => x"00000000",
00000999 => x"000009c0",
00001000 => x"00000a10",
00001001 => x"00000a1c",
00001002 => x"00000a28",
00001003 => x"00000a34",
00001004 => x"00000a40",
00001005 => x"00000a4c",
00001006 => x"00000a58",
00001007 => x"00000a64",
00001008 => x"00000980",
00001009 => x"00000980",
00001010 => x"00000a70",
00001011 => x"4554523c",
00001012 => x"4157203e",
00001013 => x"4e494e52",
00001014 => x"43202147",
00001015 => x"43205550",
00001016 => x"73205253",
00001017 => x"65747379",
00001018 => x"6f6e206d",
00001019 => x"76612074",
00001020 => x"616c6961",
00001021 => x"21656c62",
00001022 => x"522f3c20",
00001023 => x"003e4554",
00001024 => x"5241570a",
00001025 => x"474e494e",
00001026 => x"57532021",
00001027 => x"4153495f",
00001028 => x"65662820",
00001029 => x"72757461",
00001030 => x"72207365",
00001031 => x"69757165",
00001032 => x"29646572",
00001033 => x"20737620",
00001034 => x"495f5748",
00001035 => x"28204153",
00001036 => x"74616566",
00001037 => x"73657275",
00001038 => x"61766120",
00001039 => x"62616c69",
00001040 => x"2029656c",
00001041 => x"6d73696d",
00001042 => x"68637461",
00001043 => x"57530a21",
00001044 => x"4153495f",
00001045 => x"30203d20",
00001046 => x"20782578",
00001047 => x"6d6f6328",
00001048 => x"656c6970",
00001049 => x"6c662072",
00001050 => x"29736761",
00001051 => x"5f57480a",
00001052 => x"20415349",
00001053 => x"7830203d",
00001054 => x"28207825",
00001055 => x"6173696d",
00001056 => x"72736320",
00001057 => x"000a0a29",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"42413938",
00001061 => x"46454443",
others => x"00000000"
);
 
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1021) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1022) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
15,1020 → 15,1021
00000004 => x"00000293",
00000005 => x"00000313",
00000006 => x"00000393",
00000007 => x"00000413",
00000008 => x"00000493",
00000009 => x"00000713",
00000010 => x"00000793",
00000011 => x"80012117",
00000012 => x"fd010113",
00000013 => x"ffc17113",
00000014 => x"00010413",
00000015 => x"80010197",
00000016 => x"7c418193",
00000017 => x"00000517",
00000018 => x"0b450513",
00000019 => x"30551073",
00000020 => x"34151073",
00000021 => x"34301073",
00000022 => x"34201073",
00000023 => x"30001073",
00000024 => x"30401073",
00000025 => x"30601073",
00000026 => x"ffa00593",
00000027 => x"32059073",
00000028 => x"b0001073",
00000029 => x"b8001073",
00000030 => x"b0201073",
00000031 => x"b8201073",
00000032 => x"f0000593",
00000033 => x"0005a023",
00000034 => x"00458593",
00000035 => x"feb01ce3",
00000036 => x"80010597",
00000037 => x"f7058593",
00000038 => x"80818613",
00000039 => x"00c5d863",
00000040 => x"00058023",
00000041 => x"00158593",
00000042 => x"ff5ff06f",
00000043 => x"00001597",
00000044 => x"f4858593",
00000045 => x"80010617",
00000046 => x"f4c60613",
00000047 => x"80010697",
00000048 => x"f4468693",
00000049 => x"00d65c63",
00000050 => x"00058703",
00000051 => x"00e60023",
00000052 => x"00158593",
00000053 => x"00160613",
00000054 => x"fedff06f",
00000055 => x"00000513",
00000056 => x"00000593",
00000057 => x"060000ef",
00000058 => x"30047073",
00000059 => x"00000013",
00000060 => x"10500073",
00000061 => x"0000006f",
00000062 => x"ff810113",
00000063 => x"00812023",
00000064 => x"00912223",
00000065 => x"34202473",
00000066 => x"02044663",
00000067 => x"34102473",
00000068 => x"00041483",
00000069 => x"0034f493",
00000070 => x"00240413",
00000071 => x"34141073",
00000072 => x"00300413",
00000073 => x"00941863",
00000074 => x"34102473",
00000075 => x"00240413",
00000076 => x"34141073",
00000077 => x"00012403",
00000078 => x"00412483",
00000079 => x"00810113",
00000080 => x"30200073",
00000081 => x"800007b7",
00000082 => x"0007a023",
00000083 => x"fd010113",
00000084 => x"8001a223",
00000085 => x"02812423",
00000086 => x"fe002403",
00000087 => x"026267b7",
00000088 => x"02112623",
00000089 => x"02912223",
00000090 => x"03212023",
00000091 => x"01312e23",
00000092 => x"01412c23",
00000093 => x"01512a23",
00000094 => x"01612823",
00000095 => x"01712623",
00000096 => x"01812423",
00000097 => x"9ff78793",
00000098 => x"00000613",
00000099 => x"00000593",
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"389000ef",
00000104 => x"00100513",
00000105 => x"429000ef",
00000106 => x"00005537",
00000107 => x"00000613",
00000108 => x"00000593",
00000109 => x"b0050513",
00000110 => x"2b5000ef",
00000111 => x"1d1000ef",
00000112 => x"00245793",
00000113 => x"00a78533",
00000114 => x"00f537b3",
00000115 => x"00b785b3",
00000116 => x"1e9000ef",
00000117 => x"ffff07b7",
00000118 => x"4d478793",
00000119 => x"30579073",
00000120 => x"08000793",
00000121 => x"30479073",
00000122 => x"30046073",
00000123 => x"00000013",
00000007 => x"00000713",
00000008 => x"00000793",
00000009 => x"80012117",
00000010 => x"fd810113",
00000011 => x"ffc17113",
00000012 => x"00010413",
00000013 => x"80010197",
00000014 => x"7cc18193",
00000015 => x"00000517",
00000016 => x"0c050513",
00000017 => x"30551073",
00000018 => x"34151073",
00000019 => x"34301073",
00000020 => x"34201073",
00000021 => x"30001073",
00000022 => x"30401073",
00000023 => x"30601073",
00000024 => x"ffa00593",
00000025 => x"32059073",
00000026 => x"b0001073",
00000027 => x"b8001073",
00000028 => x"b0201073",
00000029 => x"b8201073",
00000030 => x"00010417",
00000031 => x"e8840413",
00000032 => x"00010497",
00000033 => x"f8048493",
00000034 => x"00042023",
00000035 => x"00440413",
00000036 => x"fe941ce3",
00000037 => x"80010597",
00000038 => x"f6c58593",
00000039 => x"80818613",
00000040 => x"00c5d863",
00000041 => x"00058023",
00000042 => x"00158593",
00000043 => x"ff5ff06f",
00000044 => x"00001597",
00000045 => x"f4858593",
00000046 => x"80010617",
00000047 => x"f4860613",
00000048 => x"80010697",
00000049 => x"f4068693",
00000050 => x"00d65c63",
00000051 => x"00058703",
00000052 => x"00e60023",
00000053 => x"00158593",
00000054 => x"00160613",
00000055 => x"fedff06f",
00000056 => x"00000513",
00000057 => x"00000593",
00000058 => x"060000ef",
00000059 => x"30047073",
00000060 => x"00000013",
00000061 => x"10500073",
00000062 => x"0000006f",
00000063 => x"ff810113",
00000064 => x"00812023",
00000065 => x"00912223",
00000066 => x"34202473",
00000067 => x"02044663",
00000068 => x"34102473",
00000069 => x"00041483",
00000070 => x"0034f493",
00000071 => x"00240413",
00000072 => x"34141073",
00000073 => x"00300413",
00000074 => x"00941863",
00000075 => x"34102473",
00000076 => x"00240413",
00000077 => x"34141073",
00000078 => x"00012403",
00000079 => x"00412483",
00000080 => x"00810113",
00000081 => x"30200073",
00000082 => x"800007b7",
00000083 => x"0007a023",
00000084 => x"fd010113",
00000085 => x"8001a223",
00000086 => x"02812423",
00000087 => x"fe002403",
00000088 => x"026267b7",
00000089 => x"02112623",
00000090 => x"02912223",
00000091 => x"03212023",
00000092 => x"01312e23",
00000093 => x"01412c23",
00000094 => x"01512a23",
00000095 => x"01612823",
00000096 => x"01712623",
00000097 => x"01812423",
00000098 => x"9ff78793",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"00200513",
00000102 => x"0087f463",
00000103 => x"00400513",
00000104 => x"389000ef",
00000105 => x"00100513",
00000106 => x"429000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
00000110 => x"b0050513",
00000111 => x"2b5000ef",
00000112 => x"1d1000ef",
00000113 => x"00245793",
00000114 => x"00a78533",
00000115 => x"00f537b3",
00000116 => x"00b785b3",
00000117 => x"1e9000ef",
00000118 => x"ffff07b7",
00000119 => x"4d878793",
00000120 => x"30579073",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"f0850513",
00000127 => x"315000ef",
00000128 => x"f1302573",
00000129 => x"260000ef",
00000130 => x"ffff1537",
00000131 => x"f4050513",
00000132 => x"301000ef",
00000133 => x"fe002503",
00000134 => x"24c000ef",
00000135 => x"ffff1537",
00000136 => x"f4850513",
00000137 => x"2ed000ef",
00000138 => x"fe402503",
00000139 => x"238000ef",
00000140 => x"ffff1537",
00000141 => x"f5050513",
00000142 => x"2d9000ef",
00000143 => x"30102573",
00000144 => x"224000ef",
00000145 => x"ffff1537",
00000146 => x"f5850513",
00000147 => x"2c5000ef",
00000148 => x"fc002573",
00000149 => x"210000ef",
00000150 => x"ffff1537",
00000151 => x"f6050513",
00000152 => x"2b1000ef",
00000153 => x"fe802503",
00000154 => x"ffff14b7",
00000155 => x"00341413",
00000156 => x"1f4000ef",
00000157 => x"ffff1537",
00000158 => x"f6850513",
00000159 => x"295000ef",
00000160 => x"ff802503",
00000161 => x"1e0000ef",
00000162 => x"f7048513",
00000163 => x"285000ef",
00000164 => x"ff002503",
00000165 => x"1d0000ef",
00000166 => x"ffff1537",
00000167 => x"f7c50513",
00000168 => x"271000ef",
00000169 => x"ffc02503",
00000170 => x"1bc000ef",
00000171 => x"f7048513",
00000172 => x"261000ef",
00000173 => x"ff402503",
00000174 => x"1ac000ef",
00000175 => x"ffff1537",
00000176 => x"f8450513",
00000177 => x"24d000ef",
00000178 => x"0c5000ef",
00000179 => x"00a404b3",
00000180 => x"0084b433",
00000181 => x"00b40433",
00000182 => x"1dd000ef",
00000183 => x"02050263",
00000184 => x"ffff1537",
00000185 => x"fb050513",
00000186 => x"229000ef",
00000187 => x"0e5000ef",
00000188 => x"02300793",
00000189 => x"02f51263",
00000190 => x"00000513",
00000191 => x"0180006f",
00000192 => x"08d000ef",
00000193 => x"fc85eae3",
00000194 => x"00b41463",
00000195 => x"fc9566e3",
00000196 => x"00100513",
00000197 => x"5e8000ef",
00000198 => x"0b4000ef",
00000199 => x"ffff1937",
00000200 => x"ffff19b7",
00000201 => x"02300a13",
00000202 => x"07200a93",
00000203 => x"06800b13",
00000204 => x"07500b93",
00000205 => x"ffff14b7",
00000206 => x"ffff1c37",
00000207 => x"fbc90513",
00000208 => x"1d1000ef",
00000209 => x"161000ef",
00000210 => x"00050413",
00000211 => x"135000ef",
00000212 => x"ec098513",
00000213 => x"1bd000ef",
00000214 => x"fb4400e3",
00000215 => x"01541863",
00000216 => x"ffff02b7",
00000217 => x"00028067",
00000218 => x"fd5ff06f",
00000219 => x"01641663",
00000220 => x"05c000ef",
00000221 => x"fc9ff06f",
00000222 => x"00000513",
00000223 => x"03740063",
00000224 => x"07300793",
00000225 => x"00f41663",
00000226 => x"688000ef",
00000227 => x"fb1ff06f",
00000228 => x"06c00793",
00000229 => x"00f41863",
00000230 => x"00100513",
00000231 => x"3fc000ef",
00000232 => x"f9dff06f",
00000233 => x"06500793",
00000234 => x"00f41663",
00000235 => x"02c000ef",
00000236 => x"f8dff06f",
00000237 => x"03f00793",
00000238 => x"fc4c0513",
00000239 => x"00f40463",
00000240 => x"fd848513",
00000241 => x"14d000ef",
00000242 => x"f75ff06f",
00000243 => x"ffff1537",
00000244 => x"dd450513",
00000245 => x"13d0006f",
00000246 => x"800007b7",
00000247 => x"0007a783",
00000248 => x"00079863",
00000249 => x"ffff1537",
00000250 => x"e3850513",
00000251 => x"1250006f",
00000252 => x"ff010113",
00000253 => x"00112623",
00000254 => x"30047073",
00000255 => x"00000013",
00000125 => x"00000013",
00000126 => x"ffff1537",
00000127 => x"f0c50513",
00000128 => x"315000ef",
00000129 => x"f1302573",
00000130 => x"260000ef",
00000131 => x"ffff1537",
00000132 => x"f4450513",
00000133 => x"301000ef",
00000134 => x"fe002503",
00000135 => x"24c000ef",
00000136 => x"ffff1537",
00000137 => x"f4c50513",
00000138 => x"2ed000ef",
00000139 => x"fe402503",
00000140 => x"238000ef",
00000141 => x"ffff1537",
00000142 => x"f5450513",
00000143 => x"2d9000ef",
00000144 => x"30102573",
00000145 => x"224000ef",
00000146 => x"ffff1537",
00000147 => x"f5c50513",
00000148 => x"2c5000ef",
00000149 => x"fc002573",
00000150 => x"210000ef",
00000151 => x"ffff1537",
00000152 => x"f6450513",
00000153 => x"2b1000ef",
00000154 => x"fe802503",
00000155 => x"ffff14b7",
00000156 => x"00341413",
00000157 => x"1f4000ef",
00000158 => x"ffff1537",
00000159 => x"f6c50513",
00000160 => x"295000ef",
00000161 => x"ff802503",
00000162 => x"1e0000ef",
00000163 => x"f7448513",
00000164 => x"285000ef",
00000165 => x"ff002503",
00000166 => x"1d0000ef",
00000167 => x"ffff1537",
00000168 => x"f8050513",
00000169 => x"271000ef",
00000170 => x"ffc02503",
00000171 => x"1bc000ef",
00000172 => x"f7448513",
00000173 => x"261000ef",
00000174 => x"ff402503",
00000175 => x"1ac000ef",
00000176 => x"ffff1537",
00000177 => x"f8850513",
00000178 => x"24d000ef",
00000179 => x"0c5000ef",
00000180 => x"00a404b3",
00000181 => x"0084b433",
00000182 => x"00b40433",
00000183 => x"1dd000ef",
00000184 => x"02050263",
00000185 => x"ffff1537",
00000186 => x"fb450513",
00000187 => x"229000ef",
00000188 => x"0e5000ef",
00000189 => x"02300793",
00000190 => x"02f51263",
00000191 => x"00000513",
00000192 => x"0180006f",
00000193 => x"08d000ef",
00000194 => x"fc85eae3",
00000195 => x"00b41463",
00000196 => x"fc9566e3",
00000197 => x"00100513",
00000198 => x"5e8000ef",
00000199 => x"0b4000ef",
00000200 => x"ffff1937",
00000201 => x"ffff19b7",
00000202 => x"02300a13",
00000203 => x"07200a93",
00000204 => x"06800b13",
00000205 => x"07500b93",
00000206 => x"ffff14b7",
00000207 => x"ffff1c37",
00000208 => x"fc090513",
00000209 => x"1d1000ef",
00000210 => x"161000ef",
00000211 => x"00050413",
00000212 => x"135000ef",
00000213 => x"ec498513",
00000214 => x"1bd000ef",
00000215 => x"fb4400e3",
00000216 => x"01541863",
00000217 => x"ffff02b7",
00000218 => x"00028067",
00000219 => x"fd5ff06f",
00000220 => x"01641663",
00000221 => x"05c000ef",
00000222 => x"fc9ff06f",
00000223 => x"00000513",
00000224 => x"03740063",
00000225 => x"07300793",
00000226 => x"00f41663",
00000227 => x"688000ef",
00000228 => x"fb1ff06f",
00000229 => x"06c00793",
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00000849 => x"fa800793",
00000850 => x"00b56533",
00000851 => x"0007a023",
00000852 => x"10056513",
00000853 => x"00a7a023",
00000854 => x"00008067",
00000855 => x"fa800713",
00000856 => x"00072683",
00000857 => x"00757793",
00000858 => x"00100513",
00000859 => x"00f51533",
00000860 => x"00d56533",
00000861 => x"00a72023",
00000862 => x"00008067",
00000863 => x"fa800713",
00000864 => x"00072683",
00000865 => x"00757513",
00000866 => x"00100793",
00000867 => x"00a797b3",
00000868 => x"fff7c793",
00000869 => x"00d7f7b3",
00000870 => x"00f72023",
00000871 => x"00008067",
00000872 => x"faa02623",
00000873 => x"fa802783",
00000874 => x"fe07cee3",
00000875 => x"fac02503",
00000876 => x"00008067",
00000877 => x"f8400713",
00000878 => x"00072683",
00000879 => x"00100793",
00000880 => x"00a797b3",
00000881 => x"00d7c7b3",
00000882 => x"00f72023",
00000883 => x"00008067",
00000884 => x"f8a02223",
00000885 => x"00008067",
00000886 => x"69617641",
00000887 => x"6c62616c",
00000888 => x"4d432065",
00000889 => x"0a3a7344",
00000890 => x"203a6820",
00000891 => x"706c6548",
00000892 => x"3a72200a",
00000893 => x"73655220",
00000894 => x"74726174",
00000895 => x"3a75200a",
00000896 => x"6c705520",
00000897 => x"0a64616f",
00000898 => x"203a7320",
00000899 => x"726f7453",
00000900 => x"6f742065",
00000901 => x"616c6620",
00000902 => x"200a6873",
00000903 => x"4c203a6c",
00000904 => x"2064616f",
00000905 => x"6d6f7266",
00000906 => x"616c6620",
00000907 => x"200a6873",
00000908 => x"45203a65",
00000909 => x"75636578",
00000910 => x"00006574",
00000911 => x"65206f4e",
00000912 => x"75636578",
00000913 => x"6c626174",
00000914 => x"76612065",
00000915 => x"616c6961",
00000916 => x"2e656c62",
00000917 => x"00000000",
00000918 => x"746f6f42",
00000919 => x"2e676e69",
00000920 => x"0a0a2e2e",
00000921 => x"00000000",
00000922 => x"52450a07",
00000923 => x"5f524f52",
00000924 => x"00000000",
00000925 => x"00007830",
00000926 => x"58450a0a",
00000927 => x"54504543",
00000928 => x"204e4f49",
00000929 => x"7561636d",
00000930 => x"003d6573",
00000931 => x"70204020",
00000932 => x"00003d63",
00000933 => x"69617741",
00000934 => x"676e6974",
00000935 => x"6f656e20",
00000936 => x"32337672",
00000937 => x"6578655f",
00000938 => x"6e69622e",
00000939 => x"202e2e2e",
00000940 => x"00000000",
00000941 => x"64616f4c",
00000942 => x"2e676e69",
00000943 => x"00202e2e",
00000944 => x"00004b4f",
00000945 => x"0000000a",
00000946 => x"74697257",
00000947 => x"78302065",
00000948 => x"00000000",
00000949 => x"74796220",
00000950 => x"74207365",
00000951 => x"5053206f",
00000952 => x"6c662049",
00000953 => x"20687361",
00000954 => x"78302040",
00000955 => x"00000000",
00000956 => x"7928203f",
00000957 => x"20296e2f",
00000958 => x"00000000",
00000959 => x"616c460a",
00000960 => x"6e696873",
00000961 => x"2e2e2e67",
00000962 => x"00000020",
00000963 => x"0a0a0a0a",
00000964 => x"4e203c3c",
00000965 => x"56524f45",
00000966 => x"42203233",
00000967 => x"6c746f6f",
00000968 => x"6564616f",
00000969 => x"3e3e2072",
00000970 => x"4c420a0a",
00000971 => x"203a5644",
00000972 => x"20727041",
00000973 => x"32203033",
00000974 => x"0a313230",
00000975 => x"3a565748",
00000976 => x"00002020",
00000977 => x"4b4c430a",
00000978 => x"0020203a",
00000979 => x"4553550a",
00000980 => x"00203a52",
00000981 => x"53494d0a",
00000982 => x"00203a41",
00000983 => x"58455a0a",
00000984 => x"00203a54",
00000985 => x"4f52500a",
00000986 => x"00203a43",
00000987 => x"454d490a",
00000988 => x"00203a4d",
00000989 => x"74796220",
00000990 => x"40207365",
00000991 => x"00000020",
00000992 => x"454d440a",
00000993 => x"00203a4d",
00000994 => x"75410a0a",
00000995 => x"6f626f74",
00000996 => x"6920746f",
00000997 => x"3828206e",
00000998 => x"202e7329",
00000999 => x"73657250",
00001000 => x"656b2073",
00001001 => x"6f742079",
00001002 => x"6f626120",
00001003 => x"0a2e7472",
00001004 => x"00000000",
00001005 => x"726f6241",
00001006 => x"2e646574",
00001007 => x"00000a0a",
00001008 => x"444d430a",
00001009 => x"00203e3a",
00001010 => x"53207962",
00001011 => x"68706574",
00001012 => x"4e206e61",
00001013 => x"69746c6f",
00001014 => x"0000676e",
00001015 => x"61766e49",
00001016 => x"2064696c",
00001017 => x"00444d43",
00001018 => x"33323130",
00001019 => x"37363534",
00001020 => x"62613938",
00001021 => x"66656463",
others => x"00000000"
);
 
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
111,6 → 111,8
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- non-maskable interrupt --
nm_irq_i : in std_ulogic := '0'; -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
259,6 → 261,8
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
-- non-maskable interrupt --
nm_irq_i => nm_irq_i, -- nmi
-- fast interrupts (custom) --
firq_i => firq_i, -- fast interrupt trigger
firq_ack_o => firq_ack_o, -- fast interrupt acknowledge mask
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
92,6 → 92,8
-- FPU interface --
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
-- non-maskable interrupt --
nm_irq_i : in std_ulogic;
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
236,7 → 238,6
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
firq_sync : std_ulogic_vector(15 downto 0);
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
exc_ack : std_ulogic; -- acknowledge all exceptions
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
266,11 → 267,9
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_ctrl_rd_t is array (0 to 63) of std_ulogic_vector(7 downto 0);
type pmp_addr_rd_t is array (0 to 63) of std_ulogic_vector(data_width_c-1 downto 0);
type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0); -- 32-bit, plus 1-bit overflow
type mhpmcnth_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0); -- 32-bit
type mhpmevent_rd_t is array (0 to 29) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
type mhpmcnth_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
type csr_t is record
300,9 → 299,6
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
--
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
--
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
priv_m_mode : std_ulogic; -- CPU in M-mode
priv_u_mode : std_ulogic; -- CPU in u-mode
313,7 → 309,6
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)
--
mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
mhpmevent_rd : mhpmevent_rd_t; -- mhpmevent*: actual read data
--
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
--
330,7 → 325,6
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
pmpcfg_rd : pmp_ctrl_rd_t; -- physical memory protection - actual read data
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
pmpaddr_rd : pmp_addr_rd_t; -- physical memory protection - actual read data
--
frm : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode
fflags : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags
708,7 → 702,7
-- PC update --
if (execute_engine.pc_we = '1') then
if (execute_engine.pc_mux_sel = '0') then
execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment OR trap enter/exit
else
execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
end if;
947,7 → 941,7
when DISPATCH => -- Get new command from instruction issue engine
-- ------------------------------------------------------------
-- housekeeping --
execute_engine.is_cp_op_nxt <= '0'; -- no compressed instruction yet
execute_engine.is_cp_op_nxt <= '0'; -- no co-processor operation yet
-- PC update --
execute_engine.pc_mux_sel <= '0'; -- linear next PC
-- IR update --
1289,17 → 1283,14
-- -------------------------------------------------------------------------------------------
csr_access_check: process(execute_engine.i_reg, csr)
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
variable csr_mcounteren_hpm_v : std_ulogic_vector(31 downto 0); -- max 29 HPM counters, plus 3 LSB-aligned dummy bits
begin
-- is this CSR instruction really going to write/read to/from a CSR? --
-- is this CSR instruction really going to write to a CSR? --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
csr_wacc_v := '1'; -- always write CSR
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
else
else -- clear/set
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
-- csr_racc_v := '1'; -- always read CSR
end if;
 
-- low privilege level access to hpm counters? --
1311,11 → 1302,16
end if;
 
-- check CSR access --
csr_acc_valid <= '0'; -- default = invalid access
case csr.addr is
 
-- user floating-point CSRs --
-- floating-point CSRs --
when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- full access for everyone if Zfinx extension is implemented
if (CPU_EXTENSION_RISCV_Zfinx = true) then
csr_acc_valid <= '1'; -- full access for everyone if Zfinx extension is implemented
else
NULL;
end if;
 
-- machine trap setup --
when csr_mstatus_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mstatush_c =>
1322,13 → 1318,19
csr_acc_valid <= csr.priv_m_mode; -- M-mode only, NOTE: MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
 
-- machine trap handling --
when csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mtval_c | csr_mip_c =>
when csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mtval_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mip_c => -- NOTE: MIP is read-only in the NEORV32
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- physical memory protection - address --
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
1339,17 → 1341,17
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- machine counters/timers --
when csr_mcycle_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access if implemented
when csr_mcycleh_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access if implemented
when csr_minstret_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access if implemented
when csr_minstreth_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access if implemented
when csr_mcycle_c | csr_minstret_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access valid if really implemented
when csr_mcycleh_c | csr_minstreth_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access valid if really implemented
 
when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c | -- LOW
csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
1361,7 → 1363,11
csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- user counters/timers --
when csr_cycle_c =>
1386,7 → 1392,11
csr_hpmcounter15h_c | csr_hpmcounter16h_c | csr_hpmcounter17h_c | csr_hpmcounter18h_c | csr_hpmcounter19h_c | csr_hpmcounter20h_c |
csr_hpmcounter21h_c | csr_hpmcounter22h_c | csr_hpmcounter23h_c | csr_hpmcounter24h_c | csr_hpmcounter25h_c | csr_hpmcounter26h_c |
csr_hpmcounter27h_c | csr_hpmcounter28h_c | csr_hpmcounter29h_c | csr_hpmcounter30h_c | csr_hpmcounter31h_c =>
csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(to_integer(unsigned(csr.addr(4 downto 0))))); -- M-mode, U-mode if authorized, read-only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(to_integer(unsigned(csr.addr(4 downto 0))))); -- M-mode, U-mode if authorized, read-only
else
NULL;
end if;
 
-- machine counter setup --
when csr_mcountinhibit_c =>
1397,17 → 1407,19
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- machine information registers --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c =>
-- machine information registers & custom (NEORV32-specific) read-only CSRs --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mzext_c =>
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
-- custom (NEORV32-specific) read-only CSRs --
when csr_mzext_c =>
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- undefined / not implemented --
when others =>
csr_acc_valid <= '0'; -- invalid access
NULL; -- invalid access
end case;
end process csr_access_check;
 
1644,11 → 1656,11
if (rstn_i = '0') then
trap_ctrl.exc_buf <= (others => '0');
trap_ctrl.irq_buf <= (others => def_rst_val_c);
trap_ctrl.irq_buf(interrupt_nm_irq_c) <= '0'; -- NMI
trap_ctrl.exc_ack <= '0';
trap_ctrl.irq_ack <= (others => '0');
trap_ctrl.env_start <= '0';
trap_ctrl.cause <= (others => def_rst_val_c);
trap_ctrl.firq_sync <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- exception buffer: misaligned load/store/instruction address
1664,14 → 1676,15
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
-- interrupt buffer: non-maskable interrupt
trap_ctrl.irq_buf(interrupt_nm_irq_c) <= (trap_ctrl.irq_buf(interrupt_nm_irq_c) or nm_irq_i) and (not trap_ctrl.irq_ack(interrupt_nm_irq_c));
-- interrupt buffer: machine software/external/timer interrupt
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
-- interrupt buffer: NEORV32-specific fast interrupts
trap_ctrl.firq_sync <= firq_i;
for i in 0 to 15 loop
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or trap_ctrl.firq_sync(i)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c+i) or csr.mip_clear(interrupt_firq_0_c+i)));
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or firq_i(i)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c+i));
end loop;
-- trap control --
if (trap_ctrl.env_start = '0') then -- no started trap handler
1678,7 → 1691,7
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- trap triggered!
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
trap_ctrl.exc_ack <= '1'; -- clear execption
trap_ctrl.exc_ack <= '1'; -- clear exception
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- clear interrupt with interrupt ACK mask
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
end if;
1697,9 → 1710,6
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
 
-- current pending interrupts (for CSR.MIP register) --
csr.mip_status <= trap_ctrl.irq_buf;
 
-- acknowledge mask output --
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_15_c downto interrupt_firq_0_c);
 
1709,14 → 1719,22
trap_priority: process(trap_ctrl)
begin
-- defaults --
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.cause_nxt <= (others => '-');
trap_ctrl.irq_ack_nxt <= (others => '0');
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
-- here we do need a specific acknowledge mask since several sources can trigger at once
-- ----------------------------------------------------------------------------------------
 
-- interrupt: 1.0 non-maskable interrupt --
if (trap_ctrl.irq_buf(interrupt_nm_irq_c) = '1') then
trap_ctrl.cause_nxt <= trap_nmi_c;
trap_ctrl.irq_ack_nxt(interrupt_nm_irq_c) <= '1';
 
 
-- interrupt: 1.11 machine external interrupt --
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
trap_ctrl.cause_nxt <= trap_mei_c;
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
 
1812,9 → 1830,11
trap_ctrl.irq_ack_nxt(interrupt_firq_15_c) <= '1';
 
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
-- here we do not need a specific acknowledge mask since only one exception (the one
-- with highest priority) is evaluated at once
-- ----------------------------------------------------------------------------------------
 
-- exception: 0.1 instruction access fault --
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
1857,11 → 1877,6
-- exception: 0.5 load access fault --
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
trap_ctrl.cause_nxt <= trap_lbe_c;
 
-- not implemented --
else
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.irq_ack_nxt <= (others => '0');
end if;
end process trap_priority;
1914,7 → 1929,6
csr.mepc <= (others => def_rst_val_c);
csr.mcause <= (others => def_rst_val_c);
csr.mtval <= (others => def_rst_val_c);
csr.mip_clear <= (others => def_rst_val_c);
--
csr.pmpcfg <= (others => (others => '0'));
csr.pmpaddr <= (others => (others => def_rst_val_c));
1936,8 → 1950,6
elsif rising_edge(clk_i) then
-- write access? --
csr.we <= csr.we_nxt;
-- defaults --
csr.mip_clear <= (others => '0');
 
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- --------------------------------------------------------------------------------
2020,15 → 2032,6
if (csr.addr(3 downto 0) = csr_mtval_c(3 downto 0)) then
csr.mtval <= csr.wdata;
end if;
-- R/W: mip - machine interrupt pending --
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
for i in 0 to 15 loop -- fast interrupt channels 0..15
csr.mip_clear(interrupt_firq_0_c+i) <= not csr.wdata(16+i);
end loop; -- i
end if;
end if;
 
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
2213,18 → 2216,13
end if;
end process pmp_output;
 
-- PMP read dummy --
-- PMP config read dummy --
pmp_rd_dummy: process(csr)
begin
csr.pmpcfg_rd <= (others => (others => '0'));
csr.pmpaddr_rd <= (others => (others => '0'));
if (PMP_NUM_REGIONS /= 0) then
for i in 0 to PMP_NUM_REGIONS-1 loop
csr.pmpcfg_rd(i) <= csr.pmpcfg(i);
csr.pmpaddr_rd(i) <= csr.pmpaddr(i);
if (csr.pmpcfg(i)(4 downto 3) = "00") then -- mode = off
csr.pmpaddr_rd(i)(index_size_f(PMP_MIN_GRANULARITY)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end loop; -- i
end if;
end process pmp_rd_dummy;
2251,7 → 2249,7
elsif rising_edge(clk_i) then
 
-- [m]cycle --
csr.mcycle(csr.mcycle'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mcycle(csr.mcycle'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.mcycle <= (others => '0');
mcycle_msb <= '0';
2264,7 → 2262,7
end if;
 
-- [m]cycleh --
csr.mcycleh(csr.mcycleh'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mcycleh(csr.mcycleh'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_hi_width_c = 0) then
csr.mcycleh <= (others => '0');
elsif (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
2274,7 → 2272,7
end if;
 
-- [m]instret --
csr.minstret(csr.minstret'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.minstret(csr.minstret'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.minstret <= (others => '0');
minstret_msb <= '0';
2298,7 → 2296,7
 
-- [machine] hardware performance monitors (counters) --
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmcounter(i)(csr.mhpmcounter(i)'left downto hpm_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mhpmcounter(i)(csr.mhpmcounter(i)'left downto hpm_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_lo_width_c = 0) then
csr.mhpmcounter(i) <= (others => '0');
mhpmcounter_msb(i) <= '0';
2314,7 → 2312,7
end if;
 
-- [m]hpmcounter*h --
csr.mhpmcounterh(i)(csr.mhpmcounterh(i)'left downto hpm_cnt_hi_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mhpmcounterh(i)(csr.mhpmcounterh(i)'left downto hpm_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_hi_width_c = 0) then
csr.mhpmcounterh(i) <= (others => '0');
else
2329,15 → 2327,13
end if;
end process csr_counters;
 
-- hpm read dummy --
-- hpm counters read dummy --
hpm_rd_dummy: process(csr)
begin
csr.mhpmevent_rd <= (others => (others => '0'));
csr.mhpmcounter_rd <= (others => (others => '0'));
csr.mhpmcounterh_rd <= (others => (others => '0'));
if (HPM_NUM_CNTS /= 0) then
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmevent_rd(i) <= csr.mhpmevent(i);
if (hpm_cnt_lo_width_c > 0) then
csr.mhpmcounter_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0);
end if;
2406,23 → 2402,26
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
case csr.addr is
 
-- user floating-point CSRs --
-- floating-point CSRs --
-- --------------------------------------------------------------------
when csr_fflags_c => -- R/W: fflags - floating-point (FPU) exception flags
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(4 downto 0) <= csr.fflags;
else
NULL;
end if;
when csr_frm_c => -- R/W: frm - floating-point (FPU) rounding mode
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(2 downto 0) <= csr.frm;
else
NULL;
end if;
when csr_fcsr_c => -- R/W: fcsr - floating-point (FPU) control/status (frm + fflags)
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(7 downto 5) <= csr.frm;
csr.rdata(4 downto 0) <= csr.fflags;
else
NULL;
end if;
 
-- machine trap setup --
2455,8 → 2454,9
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when csr_mcounteren_c => -- R/W: machine counter enable register
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
if (CPU_EXTENSION_RISCV_U = false) then -- this CSR is hardwired to zero if user mode is not implemented
NULL;
else
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
2473,97 → 2473,97
csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
csr.rdata <= csr.mtval;
when csr_mip_c => -- R/W: mip - machine interrupt pending
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
when csr_mip_c => -- R/-: mip - machine interrupt pending
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
for i in 0 to 15 loop -- fast interrupt channels 0..15 pending
csr.rdata(16+i) <= csr.mip_status(interrupt_firq_0_c+i);
csr.rdata(16+i) <= trap_ctrl.irq_buf(interrupt_firq_0_c+i);
end loop; -- i
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
when csr_pmpcfg3_c => csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); -- R/W: pmpcfg3
when csr_pmpcfg4_c => csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); -- R/W: pmpcfg4
when csr_pmpcfg5_c => csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); -- R/W: pmpcfg5
when csr_pmpcfg6_c => csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); -- R/W: pmpcfg6
when csr_pmpcfg7_c => csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); -- R/W: pmpcfg7
when csr_pmpcfg8_c => csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); -- R/W: pmpcfg8
when csr_pmpcfg9_c => csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); -- R/W: pmpcfg9
when csr_pmpcfg10_c => csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); -- R/W: pmpcfg10
when csr_pmpcfg11_c => csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); -- R/W: pmpcfg11
when csr_pmpcfg12_c => csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); -- R/W: pmpcfg12
when csr_pmpcfg13_c => csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); -- R/W: pmpcfg13
when csr_pmpcfg14_c => csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); -- R/W: pmpcfg14
when csr_pmpcfg15_c => csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); -- R/W: pmpcfg15
when csr_pmpcfg0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); else NULL; end if; -- R/W: pmpcfg0
when csr_pmpcfg1_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); else NULL; end if; -- R/W: pmpcfg1
when csr_pmpcfg2_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); else NULL; end if; -- R/W: pmpcfg2
when csr_pmpcfg3_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); else NULL; end if; -- R/W: pmpcfg3
when csr_pmpcfg4_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); else NULL; end if; -- R/W: pmpcfg4
when csr_pmpcfg5_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); else NULL; end if; -- R/W: pmpcfg5
when csr_pmpcfg6_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); else NULL; end if; -- R/W: pmpcfg6
when csr_pmpcfg7_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); else NULL; end if; -- R/W: pmpcfg7
when csr_pmpcfg8_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); else NULL; end if; -- R/W: pmpcfg8
when csr_pmpcfg9_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); else NULL; end if; -- R/W: pmpcfg9
when csr_pmpcfg10_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); else NULL; end if; -- R/W: pmpcfg10
when csr_pmpcfg11_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); else NULL; end if; -- R/W: pmpcfg11
when csr_pmpcfg12_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); else NULL; end if; -- R/W: pmpcfg12
when csr_pmpcfg13_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); else NULL; end if; -- R/W: pmpcfg13
when csr_pmpcfg14_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); else NULL; end if; -- R/W: pmpcfg14
when csr_pmpcfg15_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); else NULL; end if; -- R/W: pmpcfg15
 
-- physical memory protection - addresses --
when csr_pmpaddr0_c => csr.rdata <= csr.pmpaddr_rd(00); -- R/W: pmpaddr0
when csr_pmpaddr1_c => csr.rdata <= csr.pmpaddr_rd(01); -- R/W: pmpaddr1
when csr_pmpaddr2_c => csr.rdata <= csr.pmpaddr_rd(02); -- R/W: pmpaddr2
when csr_pmpaddr3_c => csr.rdata <= csr.pmpaddr_rd(03); -- R/W: pmpaddr3
when csr_pmpaddr4_c => csr.rdata <= csr.pmpaddr_rd(04); -- R/W: pmpaddr4
when csr_pmpaddr5_c => csr.rdata <= csr.pmpaddr_rd(05); -- R/W: pmpaddr5
when csr_pmpaddr6_c => csr.rdata <= csr.pmpaddr_rd(06); -- R/W: pmpaddr6
when csr_pmpaddr7_c => csr.rdata <= csr.pmpaddr_rd(07); -- R/W: pmpaddr7
when csr_pmpaddr8_c => csr.rdata <= csr.pmpaddr_rd(08); -- R/W: pmpaddr8
when csr_pmpaddr9_c => csr.rdata <= csr.pmpaddr_rd(09); -- R/W: pmpaddr9
when csr_pmpaddr10_c => csr.rdata <= csr.pmpaddr_rd(10); -- R/W: pmpaddr10
when csr_pmpaddr11_c => csr.rdata <= csr.pmpaddr_rd(11); -- R/W: pmpaddr11
when csr_pmpaddr12_c => csr.rdata <= csr.pmpaddr_rd(12); -- R/W: pmpaddr12
when csr_pmpaddr13_c => csr.rdata <= csr.pmpaddr_rd(13); -- R/W: pmpaddr13
when csr_pmpaddr14_c => csr.rdata <= csr.pmpaddr_rd(14); -- R/W: pmpaddr14
when csr_pmpaddr15_c => csr.rdata <= csr.pmpaddr_rd(15); -- R/W: pmpaddr15
when csr_pmpaddr16_c => csr.rdata <= csr.pmpaddr_rd(16); -- R/W: pmpaddr16
when csr_pmpaddr17_c => csr.rdata <= csr.pmpaddr_rd(17); -- R/W: pmpaddr17
when csr_pmpaddr18_c => csr.rdata <= csr.pmpaddr_rd(18); -- R/W: pmpaddr18
when csr_pmpaddr19_c => csr.rdata <= csr.pmpaddr_rd(19); -- R/W: pmpaddr19
when csr_pmpaddr20_c => csr.rdata <= csr.pmpaddr_rd(20); -- R/W: pmpaddr20
when csr_pmpaddr21_c => csr.rdata <= csr.pmpaddr_rd(21); -- R/W: pmpaddr21
when csr_pmpaddr22_c => csr.rdata <= csr.pmpaddr_rd(22); -- R/W: pmpaddr22
when csr_pmpaddr23_c => csr.rdata <= csr.pmpaddr_rd(23); -- R/W: pmpaddr23
when csr_pmpaddr24_c => csr.rdata <= csr.pmpaddr_rd(24); -- R/W: pmpaddr24
when csr_pmpaddr25_c => csr.rdata <= csr.pmpaddr_rd(25); -- R/W: pmpaddr25
when csr_pmpaddr26_c => csr.rdata <= csr.pmpaddr_rd(26); -- R/W: pmpaddr26
when csr_pmpaddr27_c => csr.rdata <= csr.pmpaddr_rd(27); -- R/W: pmpaddr27
when csr_pmpaddr28_c => csr.rdata <= csr.pmpaddr_rd(28); -- R/W: pmpaddr28
when csr_pmpaddr29_c => csr.rdata <= csr.pmpaddr_rd(29); -- R/W: pmpaddr29
when csr_pmpaddr30_c => csr.rdata <= csr.pmpaddr_rd(30); -- R/W: pmpaddr30
when csr_pmpaddr31_c => csr.rdata <= csr.pmpaddr_rd(31); -- R/W: pmpaddr31
when csr_pmpaddr32_c => csr.rdata <= csr.pmpaddr_rd(32); -- R/W: pmpaddr32
when csr_pmpaddr33_c => csr.rdata <= csr.pmpaddr_rd(33); -- R/W: pmpaddr33
when csr_pmpaddr34_c => csr.rdata <= csr.pmpaddr_rd(34); -- R/W: pmpaddr34
when csr_pmpaddr35_c => csr.rdata <= csr.pmpaddr_rd(35); -- R/W: pmpaddr35
when csr_pmpaddr36_c => csr.rdata <= csr.pmpaddr_rd(36); -- R/W: pmpaddr36
when csr_pmpaddr37_c => csr.rdata <= csr.pmpaddr_rd(37); -- R/W: pmpaddr37
when csr_pmpaddr38_c => csr.rdata <= csr.pmpaddr_rd(38); -- R/W: pmpaddr38
when csr_pmpaddr39_c => csr.rdata <= csr.pmpaddr_rd(39); -- R/W: pmpaddr39
when csr_pmpaddr40_c => csr.rdata <= csr.pmpaddr_rd(40); -- R/W: pmpaddr40
when csr_pmpaddr41_c => csr.rdata <= csr.pmpaddr_rd(41); -- R/W: pmpaddr41
when csr_pmpaddr42_c => csr.rdata <= csr.pmpaddr_rd(42); -- R/W: pmpaddr42
when csr_pmpaddr43_c => csr.rdata <= csr.pmpaddr_rd(43); -- R/W: pmpaddr43
when csr_pmpaddr44_c => csr.rdata <= csr.pmpaddr_rd(44); -- R/W: pmpaddr44
when csr_pmpaddr45_c => csr.rdata <= csr.pmpaddr_rd(45); -- R/W: pmpaddr45
when csr_pmpaddr46_c => csr.rdata <= csr.pmpaddr_rd(46); -- R/W: pmpaddr46
when csr_pmpaddr47_c => csr.rdata <= csr.pmpaddr_rd(47); -- R/W: pmpaddr47
when csr_pmpaddr48_c => csr.rdata <= csr.pmpaddr_rd(48); -- R/W: pmpaddr48
when csr_pmpaddr49_c => csr.rdata <= csr.pmpaddr_rd(49); -- R/W: pmpaddr49
when csr_pmpaddr50_c => csr.rdata <= csr.pmpaddr_rd(50); -- R/W: pmpaddr50
when csr_pmpaddr51_c => csr.rdata <= csr.pmpaddr_rd(51); -- R/W: pmpaddr51
when csr_pmpaddr52_c => csr.rdata <= csr.pmpaddr_rd(52); -- R/W: pmpaddr52
when csr_pmpaddr53_c => csr.rdata <= csr.pmpaddr_rd(53); -- R/W: pmpaddr53
when csr_pmpaddr54_c => csr.rdata <= csr.pmpaddr_rd(54); -- R/W: pmpaddr54
when csr_pmpaddr55_c => csr.rdata <= csr.pmpaddr_rd(55); -- R/W: pmpaddr55
when csr_pmpaddr56_c => csr.rdata <= csr.pmpaddr_rd(56); -- R/W: pmpaddr56
when csr_pmpaddr57_c => csr.rdata <= csr.pmpaddr_rd(57); -- R/W: pmpaddr57
when csr_pmpaddr58_c => csr.rdata <= csr.pmpaddr_rd(58); -- R/W: pmpaddr58
when csr_pmpaddr59_c => csr.rdata <= csr.pmpaddr_rd(59); -- R/W: pmpaddr59
when csr_pmpaddr60_c => csr.rdata <= csr.pmpaddr_rd(60); -- R/W: pmpaddr60
when csr_pmpaddr61_c => csr.rdata <= csr.pmpaddr_rd(61); -- R/W: pmpaddr61
when csr_pmpaddr62_c => csr.rdata <= csr.pmpaddr_rd(62); -- R/W: pmpaddr62
when csr_pmpaddr63_c => csr.rdata <= csr.pmpaddr_rd(63); -- R/W: pmpaddr63
when csr_pmpaddr0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpaddr(00); else NULL; end if; -- R/W: pmpaddr0
when csr_pmpaddr1_c => if (PMP_NUM_REGIONS > 01) then csr.rdata <= csr.pmpaddr(01); else NULL; end if; -- R/W: pmpaddr1
when csr_pmpaddr2_c => if (PMP_NUM_REGIONS > 02) then csr.rdata <= csr.pmpaddr(02); else NULL; end if; -- R/W: pmpaddr2
when csr_pmpaddr3_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpaddr(03); else NULL; end if; -- R/W: pmpaddr3
when csr_pmpaddr4_c => if (PMP_NUM_REGIONS > 04) then csr.rdata <= csr.pmpaddr(04); else NULL; end if; -- R/W: pmpaddr4
when csr_pmpaddr5_c => if (PMP_NUM_REGIONS > 05) then csr.rdata <= csr.pmpaddr(05); else NULL; end if; -- R/W: pmpaddr5
when csr_pmpaddr6_c => if (PMP_NUM_REGIONS > 06) then csr.rdata <= csr.pmpaddr(06); else NULL; end if; -- R/W: pmpaddr6
when csr_pmpaddr7_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpaddr(07); else NULL; end if; -- R/W: pmpaddr7
when csr_pmpaddr8_c => if (PMP_NUM_REGIONS > 08) then csr.rdata <= csr.pmpaddr(08); else NULL; end if; -- R/W: pmpaddr8
when csr_pmpaddr9_c => if (PMP_NUM_REGIONS > 09) then csr.rdata <= csr.pmpaddr(09); else NULL; end if; -- R/W: pmpaddr9
when csr_pmpaddr10_c => if (PMP_NUM_REGIONS > 10) then csr.rdata <= csr.pmpaddr(10); else NULL; end if; -- R/W: pmpaddr10
when csr_pmpaddr11_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpaddr(11); else NULL; end if; -- R/W: pmpaddr11
when csr_pmpaddr12_c => if (PMP_NUM_REGIONS > 12) then csr.rdata <= csr.pmpaddr(12); else NULL; end if; -- R/W: pmpaddr12
when csr_pmpaddr13_c => if (PMP_NUM_REGIONS > 13) then csr.rdata <= csr.pmpaddr(13); else NULL; end if; -- R/W: pmpaddr13
when csr_pmpaddr14_c => if (PMP_NUM_REGIONS > 14) then csr.rdata <= csr.pmpaddr(14); else NULL; end if; -- R/W: pmpaddr14
when csr_pmpaddr15_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpaddr(15); else NULL; end if; -- R/W: pmpaddr15
when csr_pmpaddr16_c => if (PMP_NUM_REGIONS > 16) then csr.rdata <= csr.pmpaddr(16); else NULL; end if; -- R/W: pmpaddr16
when csr_pmpaddr17_c => if (PMP_NUM_REGIONS > 17) then csr.rdata <= csr.pmpaddr(17); else NULL; end if; -- R/W: pmpaddr17
when csr_pmpaddr18_c => if (PMP_NUM_REGIONS > 18) then csr.rdata <= csr.pmpaddr(18); else NULL; end if; -- R/W: pmpaddr18
when csr_pmpaddr19_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpaddr(19); else NULL; end if; -- R/W: pmpaddr19
when csr_pmpaddr20_c => if (PMP_NUM_REGIONS > 20) then csr.rdata <= csr.pmpaddr(20); else NULL; end if; -- R/W: pmpaddr20
when csr_pmpaddr21_c => if (PMP_NUM_REGIONS > 21) then csr.rdata <= csr.pmpaddr(21); else NULL; end if; -- R/W: pmpaddr21
when csr_pmpaddr22_c => if (PMP_NUM_REGIONS > 22) then csr.rdata <= csr.pmpaddr(22); else NULL; end if; -- R/W: pmpaddr22
when csr_pmpaddr23_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpaddr(23); else NULL; end if; -- R/W: pmpaddr23
when csr_pmpaddr24_c => if (PMP_NUM_REGIONS > 24) then csr.rdata <= csr.pmpaddr(24); else NULL; end if; -- R/W: pmpaddr24
when csr_pmpaddr25_c => if (PMP_NUM_REGIONS > 25) then csr.rdata <= csr.pmpaddr(25); else NULL; end if; -- R/W: pmpaddr25
when csr_pmpaddr26_c => if (PMP_NUM_REGIONS > 26) then csr.rdata <= csr.pmpaddr(26); else NULL; end if; -- R/W: pmpaddr26
when csr_pmpaddr27_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpaddr(27); else NULL; end if; -- R/W: pmpaddr27
when csr_pmpaddr28_c => if (PMP_NUM_REGIONS > 28) then csr.rdata <= csr.pmpaddr(28); else NULL; end if; -- R/W: pmpaddr28
when csr_pmpaddr29_c => if (PMP_NUM_REGIONS > 29) then csr.rdata <= csr.pmpaddr(29); else NULL; end if; -- R/W: pmpaddr29
when csr_pmpaddr30_c => if (PMP_NUM_REGIONS > 30) then csr.rdata <= csr.pmpaddr(30); else NULL; end if; -- R/W: pmpaddr30
when csr_pmpaddr31_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpaddr(31); else NULL; end if; -- R/W: pmpaddr31
when csr_pmpaddr32_c => if (PMP_NUM_REGIONS > 32) then csr.rdata <= csr.pmpaddr(32); else NULL; end if; -- R/W: pmpaddr32
when csr_pmpaddr33_c => if (PMP_NUM_REGIONS > 33) then csr.rdata <= csr.pmpaddr(33); else NULL; end if; -- R/W: pmpaddr33
when csr_pmpaddr34_c => if (PMP_NUM_REGIONS > 34) then csr.rdata <= csr.pmpaddr(34); else NULL; end if; -- R/W: pmpaddr34
when csr_pmpaddr35_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpaddr(35); else NULL; end if; -- R/W: pmpaddr35
when csr_pmpaddr36_c => if (PMP_NUM_REGIONS > 36) then csr.rdata <= csr.pmpaddr(36); else NULL; end if; -- R/W: pmpaddr36
when csr_pmpaddr37_c => if (PMP_NUM_REGIONS > 37) then csr.rdata <= csr.pmpaddr(37); else NULL; end if; -- R/W: pmpaddr37
when csr_pmpaddr38_c => if (PMP_NUM_REGIONS > 38) then csr.rdata <= csr.pmpaddr(38); else NULL; end if; -- R/W: pmpaddr38
when csr_pmpaddr39_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpaddr(39); else NULL; end if; -- R/W: pmpaddr39
when csr_pmpaddr40_c => if (PMP_NUM_REGIONS > 40) then csr.rdata <= csr.pmpaddr(40); else NULL; end if; -- R/W: pmpaddr40
when csr_pmpaddr41_c => if (PMP_NUM_REGIONS > 41) then csr.rdata <= csr.pmpaddr(41); else NULL; end if; -- R/W: pmpaddr41
when csr_pmpaddr42_c => if (PMP_NUM_REGIONS > 42) then csr.rdata <= csr.pmpaddr(42); else NULL; end if; -- R/W: pmpaddr42
when csr_pmpaddr43_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpaddr(43); else NULL; end if; -- R/W: pmpaddr43
when csr_pmpaddr44_c => if (PMP_NUM_REGIONS > 44) then csr.rdata <= csr.pmpaddr(44); else NULL; end if; -- R/W: pmpaddr44
when csr_pmpaddr45_c => if (PMP_NUM_REGIONS > 45) then csr.rdata <= csr.pmpaddr(45); else NULL; end if; -- R/W: pmpaddr45
when csr_pmpaddr46_c => if (PMP_NUM_REGIONS > 46) then csr.rdata <= csr.pmpaddr(46); else NULL; end if; -- R/W: pmpaddr46
when csr_pmpaddr47_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpaddr(47); else NULL; end if; -- R/W: pmpaddr47
when csr_pmpaddr48_c => if (PMP_NUM_REGIONS > 48) then csr.rdata <= csr.pmpaddr(48); else NULL; end if; -- R/W: pmpaddr48
when csr_pmpaddr49_c => if (PMP_NUM_REGIONS > 49) then csr.rdata <= csr.pmpaddr(49); else NULL; end if; -- R/W: pmpaddr49
when csr_pmpaddr50_c => if (PMP_NUM_REGIONS > 50) then csr.rdata <= csr.pmpaddr(50); else NULL; end if; -- R/W: pmpaddr50
when csr_pmpaddr51_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpaddr(51); else NULL; end if; -- R/W: pmpaddr51
when csr_pmpaddr52_c => if (PMP_NUM_REGIONS > 52) then csr.rdata <= csr.pmpaddr(52); else NULL; end if; -- R/W: pmpaddr52
when csr_pmpaddr53_c => if (PMP_NUM_REGIONS > 53) then csr.rdata <= csr.pmpaddr(53); else NULL; end if; -- R/W: pmpaddr53
when csr_pmpaddr54_c => if (PMP_NUM_REGIONS > 54) then csr.rdata <= csr.pmpaddr(54); else NULL; end if; -- R/W: pmpaddr54
when csr_pmpaddr55_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpaddr(55); else NULL; end if; -- R/W: pmpaddr55
when csr_pmpaddr56_c => if (PMP_NUM_REGIONS > 56) then csr.rdata <= csr.pmpaddr(56); else NULL; end if; -- R/W: pmpaddr56
when csr_pmpaddr57_c => if (PMP_NUM_REGIONS > 57) then csr.rdata <= csr.pmpaddr(57); else NULL; end if; -- R/W: pmpaddr57
when csr_pmpaddr58_c => if (PMP_NUM_REGIONS > 58) then csr.rdata <= csr.pmpaddr(58); else NULL; end if; -- R/W: pmpaddr58
when csr_pmpaddr59_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpaddr(59); else NULL; end if; -- R/W: pmpaddr59
when csr_pmpaddr60_c => if (PMP_NUM_REGIONS > 60) then csr.rdata <= csr.pmpaddr(60); else NULL; end if; -- R/W: pmpaddr60
when csr_pmpaddr61_c => if (PMP_NUM_REGIONS > 61) then csr.rdata <= csr.pmpaddr(61); else NULL; end if; -- R/W: pmpaddr61
when csr_pmpaddr62_c => if (PMP_NUM_REGIONS > 62) then csr.rdata <= csr.pmpaddr(62); else NULL; end if; -- R/W: pmpaddr62
when csr_pmpaddr63_c => if (PMP_NUM_REGIONS > 63) then csr.rdata <= csr.pmpaddr(63); else NULL; end if; -- R/W: pmpaddr63
 
-- machine counter setup --
-- --------------------------------------------------------------------
2573,110 → 2573,112
csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
 
-- machine performance-monitoring event selector --
when csr_mhpmevent3_c => csr.rdata(csr.mhpmevent_rd(00)'left downto 0) <= csr.mhpmevent_rd(00); -- R/W: mhpmevent3
when csr_mhpmevent4_c => csr.rdata(csr.mhpmevent_rd(01)'left downto 0) <= csr.mhpmevent_rd(01); -- R/W: mhpmevent4
when csr_mhpmevent5_c => csr.rdata(csr.mhpmevent_rd(02)'left downto 0) <= csr.mhpmevent_rd(02); -- R/W: mhpmevent5
when csr_mhpmevent6_c => csr.rdata(csr.mhpmevent_rd(03)'left downto 0) <= csr.mhpmevent_rd(03); -- R/W: mhpmevent6
when csr_mhpmevent7_c => csr.rdata(csr.mhpmevent_rd(04)'left downto 0) <= csr.mhpmevent_rd(04); -- R/W: mhpmevent7
when csr_mhpmevent8_c => csr.rdata(csr.mhpmevent_rd(05)'left downto 0) <= csr.mhpmevent_rd(05); -- R/W: mhpmevent8
when csr_mhpmevent9_c => csr.rdata(csr.mhpmevent_rd(06)'left downto 0) <= csr.mhpmevent_rd(06); -- R/W: mhpmevent9
when csr_mhpmevent10_c => csr.rdata(csr.mhpmevent_rd(07)'left downto 0) <= csr.mhpmevent_rd(07); -- R/W: mhpmevent10
when csr_mhpmevent11_c => csr.rdata(csr.mhpmevent_rd(08)'left downto 0) <= csr.mhpmevent_rd(08); -- R/W: mhpmevent11
when csr_mhpmevent12_c => csr.rdata(csr.mhpmevent_rd(09)'left downto 0) <= csr.mhpmevent_rd(09); -- R/W: mhpmevent12
when csr_mhpmevent13_c => csr.rdata(csr.mhpmevent_rd(10)'left downto 0) <= csr.mhpmevent_rd(10); -- R/W: mhpmevent13
when csr_mhpmevent14_c => csr.rdata(csr.mhpmevent_rd(11)'left downto 0) <= csr.mhpmevent_rd(11); -- R/W: mhpmevent14
when csr_mhpmevent15_c => csr.rdata(csr.mhpmevent_rd(12)'left downto 0) <= csr.mhpmevent_rd(12); -- R/W: mhpmevent15
when csr_mhpmevent16_c => csr.rdata(csr.mhpmevent_rd(13)'left downto 0) <= csr.mhpmevent_rd(13); -- R/W: mhpmevent16
when csr_mhpmevent17_c => csr.rdata(csr.mhpmevent_rd(14)'left downto 0) <= csr.mhpmevent_rd(14); -- R/W: mhpmevent17
when csr_mhpmevent18_c => csr.rdata(csr.mhpmevent_rd(15)'left downto 0) <= csr.mhpmevent_rd(15); -- R/W: mhpmevent18
when csr_mhpmevent19_c => csr.rdata(csr.mhpmevent_rd(16)'left downto 0) <= csr.mhpmevent_rd(16); -- R/W: mhpmevent19
when csr_mhpmevent20_c => csr.rdata(csr.mhpmevent_rd(17)'left downto 0) <= csr.mhpmevent_rd(17); -- R/W: mhpmevent20
when csr_mhpmevent21_c => csr.rdata(csr.mhpmevent_rd(18)'left downto 0) <= csr.mhpmevent_rd(18); -- R/W: mhpmevent21
when csr_mhpmevent22_c => csr.rdata(csr.mhpmevent_rd(19)'left downto 0) <= csr.mhpmevent_rd(19); -- R/W: mhpmevent22
when csr_mhpmevent23_c => csr.rdata(csr.mhpmevent_rd(20)'left downto 0) <= csr.mhpmevent_rd(20); -- R/W: mhpmevent23
when csr_mhpmevent24_c => csr.rdata(csr.mhpmevent_rd(21)'left downto 0) <= csr.mhpmevent_rd(21); -- R/W: mhpmevent24
when csr_mhpmevent25_c => csr.rdata(csr.mhpmevent_rd(22)'left downto 0) <= csr.mhpmevent_rd(22); -- R/W: mhpmevent25
when csr_mhpmevent26_c => csr.rdata(csr.mhpmevent_rd(23)'left downto 0) <= csr.mhpmevent_rd(23); -- R/W: mhpmevent26
when csr_mhpmevent27_c => csr.rdata(csr.mhpmevent_rd(24)'left downto 0) <= csr.mhpmevent_rd(24); -- R/W: mhpmevent27
when csr_mhpmevent28_c => csr.rdata(csr.mhpmevent_rd(25)'left downto 0) <= csr.mhpmevent_rd(25); -- R/W: mhpmevent28
when csr_mhpmevent29_c => csr.rdata(csr.mhpmevent_rd(26)'left downto 0) <= csr.mhpmevent_rd(26); -- R/W: mhpmevent29
when csr_mhpmevent30_c => csr.rdata(csr.mhpmevent_rd(27)'left downto 0) <= csr.mhpmevent_rd(27); -- R/W: mhpmevent30
when csr_mhpmevent31_c => csr.rdata(csr.mhpmevent_rd(28)'left downto 0) <= csr.mhpmevent_rd(28); -- R/W: mhpmevent31
when csr_mhpmevent3_c => if (HPM_NUM_CNTS > 00) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(00); else NULL; end if; -- R/W: mhpmevent3
when csr_mhpmevent4_c => if (HPM_NUM_CNTS > 01) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(01); else NULL; end if; -- R/W: mhpmevent4
when csr_mhpmevent5_c => if (HPM_NUM_CNTS > 02) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(02); else NULL; end if; -- R/W: mhpmevent5
when csr_mhpmevent6_c => if (HPM_NUM_CNTS > 03) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(03); else NULL; end if; -- R/W: mhpmevent6
when csr_mhpmevent7_c => if (HPM_NUM_CNTS > 04) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(04); else NULL; end if; -- R/W: mhpmevent7
when csr_mhpmevent8_c => if (HPM_NUM_CNTS > 05) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(05); else NULL; end if; -- R/W: mhpmevent8
when csr_mhpmevent9_c => if (HPM_NUM_CNTS > 06) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(06); else NULL; end if; -- R/W: mhpmevent9
when csr_mhpmevent10_c => if (HPM_NUM_CNTS > 07) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(07); else NULL; end if; -- R/W: mhpmevent10
when csr_mhpmevent11_c => if (HPM_NUM_CNTS > 08) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(08); else NULL; end if; -- R/W: mhpmevent11
when csr_mhpmevent12_c => if (HPM_NUM_CNTS > 09) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(09); else NULL; end if; -- R/W: mhpmevent12
when csr_mhpmevent13_c => if (HPM_NUM_CNTS > 10) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(10); else NULL; end if; -- R/W: mhpmevent13
when csr_mhpmevent14_c => if (HPM_NUM_CNTS > 11) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(11); else NULL; end if; -- R/W: mhpmevent14
when csr_mhpmevent15_c => if (HPM_NUM_CNTS > 12) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(12); else NULL; end if; -- R/W: mhpmevent15
when csr_mhpmevent16_c => if (HPM_NUM_CNTS > 13) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(13); else NULL; end if; -- R/W: mhpmevent16
when csr_mhpmevent17_c => if (HPM_NUM_CNTS > 14) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(14); else NULL; end if; -- R/W: mhpmevent17
when csr_mhpmevent18_c => if (HPM_NUM_CNTS > 15) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(15); else NULL; end if; -- R/W: mhpmevent18
when csr_mhpmevent19_c => if (HPM_NUM_CNTS > 16) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(16); else NULL; end if; -- R/W: mhpmevent19
when csr_mhpmevent20_c => if (HPM_NUM_CNTS > 17) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(17); else NULL; end if; -- R/W: mhpmevent20
when csr_mhpmevent21_c => if (HPM_NUM_CNTS > 18) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(18); else NULL; end if; -- R/W: mhpmevent21
when csr_mhpmevent22_c => if (HPM_NUM_CNTS > 19) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(19); else NULL; end if; -- R/W: mhpmevent22
when csr_mhpmevent23_c => if (HPM_NUM_CNTS > 20) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(20); else NULL; end if; -- R/W: mhpmevent23
when csr_mhpmevent24_c => if (HPM_NUM_CNTS > 21) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(21); else NULL; end if; -- R/W: mhpmevent24
when csr_mhpmevent25_c => if (HPM_NUM_CNTS > 22) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(22); else NULL; end if; -- R/W: mhpmevent25
when csr_mhpmevent26_c => if (HPM_NUM_CNTS > 23) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(23); else NULL; end if; -- R/W: mhpmevent26
when csr_mhpmevent27_c => if (HPM_NUM_CNTS > 24) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(24); else NULL; end if; -- R/W: mhpmevent27
when csr_mhpmevent28_c => if (HPM_NUM_CNTS > 25) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(25); else NULL; end if; -- R/W: mhpmevent28
when csr_mhpmevent29_c => if (HPM_NUM_CNTS > 26) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(26); else NULL; end if; -- R/W: mhpmevent29
when csr_mhpmevent30_c => if (HPM_NUM_CNTS > 27) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(27); else NULL; end if; -- R/W: mhpmevent30
when csr_mhpmevent31_c => if (HPM_NUM_CNTS > 28) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(28); else NULL; end if; -- R/W: mhpmevent31
 
-- counters and timers --
when csr_cycle_c | csr_mcycle_c => -- (R)/(W): [m]cycle: Cycle counter LOW
csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0);
if (cpu_cnt_lo_width_c > 0) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
if (cpu_cnt_hi_width_c > 0) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
 
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
if (cpu_cnt_lo_width_c > 0) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
if (cpu_cnt_hi_width_c > 0) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
 
when csr_time_c => -- (R)/-: time: System time LOW (from MTIME unit)
csr.rdata <= time_i(31 downto 0);
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0);
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0);
when csr_timeh_c => -- (R)/-: timeh: System time HIGH (from MTIME unit)
csr.rdata <= time_i(63 downto 32);
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0);
 
-- hardware performance counters --
when csr_hpmcounter3_c | csr_mhpmcounter3_c => csr.rdata <= csr.mhpmcounter_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3 - low
when csr_hpmcounter4_c | csr_mhpmcounter4_c => csr.rdata <= csr.mhpmcounter_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4 - low
when csr_hpmcounter5_c | csr_mhpmcounter5_c => csr.rdata <= csr.mhpmcounter_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5 - low
when csr_hpmcounter6_c | csr_mhpmcounter6_c => csr.rdata <= csr.mhpmcounter_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6 - low
when csr_hpmcounter7_c | csr_mhpmcounter7_c => csr.rdata <= csr.mhpmcounter_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7 - low
when csr_hpmcounter8_c | csr_mhpmcounter8_c => csr.rdata <= csr.mhpmcounter_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8 - low
when csr_hpmcounter9_c | csr_mhpmcounter9_c => csr.rdata <= csr.mhpmcounter_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9 - low
when csr_hpmcounter10_c | csr_mhpmcounter10_c => csr.rdata <= csr.mhpmcounter_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10 - low
when csr_hpmcounter11_c | csr_mhpmcounter11_c => csr.rdata <= csr.mhpmcounter_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11 - low
when csr_hpmcounter12_c | csr_mhpmcounter12_c => csr.rdata <= csr.mhpmcounter_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12 - low
when csr_hpmcounter13_c | csr_mhpmcounter13_c => csr.rdata <= csr.mhpmcounter_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13 - low
when csr_hpmcounter14_c | csr_mhpmcounter14_c => csr.rdata <= csr.mhpmcounter_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14 - low
when csr_hpmcounter15_c | csr_mhpmcounter15_c => csr.rdata <= csr.mhpmcounter_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15 - low
when csr_hpmcounter16_c | csr_mhpmcounter16_c => csr.rdata <= csr.mhpmcounter_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16 - low
when csr_hpmcounter17_c | csr_mhpmcounter17_c => csr.rdata <= csr.mhpmcounter_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17 - low
when csr_hpmcounter18_c | csr_mhpmcounter18_c => csr.rdata <= csr.mhpmcounter_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18 - low
when csr_hpmcounter19_c | csr_mhpmcounter19_c => csr.rdata <= csr.mhpmcounter_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19 - low
when csr_hpmcounter20_c | csr_mhpmcounter20_c => csr.rdata <= csr.mhpmcounter_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20 - low
when csr_hpmcounter21_c | csr_mhpmcounter21_c => csr.rdata <= csr.mhpmcounter_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21 - low
when csr_hpmcounter22_c | csr_mhpmcounter22_c => csr.rdata <= csr.mhpmcounter_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22 - low
when csr_hpmcounter23_c | csr_mhpmcounter23_c => csr.rdata <= csr.mhpmcounter_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23 - low
when csr_hpmcounter24_c | csr_mhpmcounter24_c => csr.rdata <= csr.mhpmcounter_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24 - low
when csr_hpmcounter25_c | csr_mhpmcounter25_c => csr.rdata <= csr.mhpmcounter_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25 - low
when csr_hpmcounter26_c | csr_mhpmcounter26_c => csr.rdata <= csr.mhpmcounter_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26 - low
when csr_hpmcounter27_c | csr_mhpmcounter27_c => csr.rdata <= csr.mhpmcounter_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27 - low
when csr_hpmcounter28_c | csr_mhpmcounter28_c => csr.rdata <= csr.mhpmcounter_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28 - low
when csr_hpmcounter29_c | csr_mhpmcounter29_c => csr.rdata <= csr.mhpmcounter_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29 - low
when csr_hpmcounter30_c | csr_mhpmcounter30_c => csr.rdata <= csr.mhpmcounter_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30 - low
when csr_hpmcounter31_c | csr_mhpmcounter31_c => csr.rdata <= csr.mhpmcounter_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31 - low
when csr_hpmcounter3_c | csr_mhpmcounter3_c => if (HPM_NUM_CNTS > 00) then csr.rdata <= csr.mhpmcounter_rd(00); else NULL; end if; -- (R)/(W): [m]hpmcounter3 - low
when csr_hpmcounter4_c | csr_mhpmcounter4_c => if (HPM_NUM_CNTS > 01) then csr.rdata <= csr.mhpmcounter_rd(01); else NULL; end if; -- (R)/(W): [m]hpmcounter4 - low
when csr_hpmcounter5_c | csr_mhpmcounter5_c => if (HPM_NUM_CNTS > 02) then csr.rdata <= csr.mhpmcounter_rd(02); else NULL; end if; -- (R)/(W): [m]hpmcounter5 - low
when csr_hpmcounter6_c | csr_mhpmcounter6_c => if (HPM_NUM_CNTS > 03) then csr.rdata <= csr.mhpmcounter_rd(03); else NULL; end if; -- (R)/(W): [m]hpmcounter6 - low
when csr_hpmcounter7_c | csr_mhpmcounter7_c => if (HPM_NUM_CNTS > 04) then csr.rdata <= csr.mhpmcounter_rd(04); else NULL; end if; -- (R)/(W): [m]hpmcounter7 - low
when csr_hpmcounter8_c | csr_mhpmcounter8_c => if (HPM_NUM_CNTS > 05) then csr.rdata <= csr.mhpmcounter_rd(05); else NULL; end if; -- (R)/(W): [m]hpmcounter8 - low
when csr_hpmcounter9_c | csr_mhpmcounter9_c => if (HPM_NUM_CNTS > 06) then csr.rdata <= csr.mhpmcounter_rd(06); else NULL; end if; -- (R)/(W): [m]hpmcounter9 - low
when csr_hpmcounter10_c | csr_mhpmcounter10_c => if (HPM_NUM_CNTS > 07) then csr.rdata <= csr.mhpmcounter_rd(07); else NULL; end if; -- (R)/(W): [m]hpmcounter10 - low
when csr_hpmcounter11_c | csr_mhpmcounter11_c => if (HPM_NUM_CNTS > 08) then csr.rdata <= csr.mhpmcounter_rd(08); else NULL; end if; -- (R)/(W): [m]hpmcounter11 - low
when csr_hpmcounter12_c | csr_mhpmcounter12_c => if (HPM_NUM_CNTS > 09) then csr.rdata <= csr.mhpmcounter_rd(09); else NULL; end if; -- (R)/(W): [m]hpmcounter12 - low
when csr_hpmcounter13_c | csr_mhpmcounter13_c => if (HPM_NUM_CNTS > 10) then csr.rdata <= csr.mhpmcounter_rd(10); else NULL; end if; -- (R)/(W): [m]hpmcounter13 - low
when csr_hpmcounter14_c | csr_mhpmcounter14_c => if (HPM_NUM_CNTS > 11) then csr.rdata <= csr.mhpmcounter_rd(11); else NULL; end if; -- (R)/(W): [m]hpmcounter14 - low
when csr_hpmcounter15_c | csr_mhpmcounter15_c => if (HPM_NUM_CNTS > 12) then csr.rdata <= csr.mhpmcounter_rd(12); else NULL; end if; -- (R)/(W): [m]hpmcounter15 - low
when csr_hpmcounter16_c | csr_mhpmcounter16_c => if (HPM_NUM_CNTS > 13) then csr.rdata <= csr.mhpmcounter_rd(13); else NULL; end if; -- (R)/(W): [m]hpmcounter16 - low
when csr_hpmcounter17_c | csr_mhpmcounter17_c => if (HPM_NUM_CNTS > 14) then csr.rdata <= csr.mhpmcounter_rd(14); else NULL; end if; -- (R)/(W): [m]hpmcounter17 - low
when csr_hpmcounter18_c | csr_mhpmcounter18_c => if (HPM_NUM_CNTS > 15) then csr.rdata <= csr.mhpmcounter_rd(15); else NULL; end if; -- (R)/(W): [m]hpmcounter18 - low
when csr_hpmcounter19_c | csr_mhpmcounter19_c => if (HPM_NUM_CNTS > 16) then csr.rdata <= csr.mhpmcounter_rd(16); else NULL; end if; -- (R)/(W): [m]hpmcounter19 - low
when csr_hpmcounter20_c | csr_mhpmcounter20_c => if (HPM_NUM_CNTS > 17) then csr.rdata <= csr.mhpmcounter_rd(17); else NULL; end if; -- (R)/(W): [m]hpmcounter20 - low
when csr_hpmcounter21_c | csr_mhpmcounter21_c => if (HPM_NUM_CNTS > 18) then csr.rdata <= csr.mhpmcounter_rd(18); else NULL; end if; -- (R)/(W): [m]hpmcounter21 - low
when csr_hpmcounter22_c | csr_mhpmcounter22_c => if (HPM_NUM_CNTS > 19) then csr.rdata <= csr.mhpmcounter_rd(19); else NULL; end if; -- (R)/(W): [m]hpmcounter22 - low
when csr_hpmcounter23_c | csr_mhpmcounter23_c => if (HPM_NUM_CNTS > 20) then csr.rdata <= csr.mhpmcounter_rd(20); else NULL; end if; -- (R)/(W): [m]hpmcounter23 - low
when csr_hpmcounter24_c | csr_mhpmcounter24_c => if (HPM_NUM_CNTS > 21) then csr.rdata <= csr.mhpmcounter_rd(21); else NULL; end if; -- (R)/(W): [m]hpmcounter24 - low
when csr_hpmcounter25_c | csr_mhpmcounter25_c => if (HPM_NUM_CNTS > 22) then csr.rdata <= csr.mhpmcounter_rd(22); else NULL; end if; -- (R)/(W): [m]hpmcounter25 - low
when csr_hpmcounter26_c | csr_mhpmcounter26_c => if (HPM_NUM_CNTS > 23) then csr.rdata <= csr.mhpmcounter_rd(23); else NULL; end if; -- (R)/(W): [m]hpmcounter26 - low
when csr_hpmcounter27_c | csr_mhpmcounter27_c => if (HPM_NUM_CNTS > 24) then csr.rdata <= csr.mhpmcounter_rd(24); else NULL; end if; -- (R)/(W): [m]hpmcounter27 - low
when csr_hpmcounter28_c | csr_mhpmcounter28_c => if (HPM_NUM_CNTS > 25) then csr.rdata <= csr.mhpmcounter_rd(25); else NULL; end if; -- (R)/(W): [m]hpmcounter28 - low
when csr_hpmcounter29_c | csr_mhpmcounter29_c => if (HPM_NUM_CNTS > 26) then csr.rdata <= csr.mhpmcounter_rd(26); else NULL; end if; -- (R)/(W): [m]hpmcounter29 - low
when csr_hpmcounter30_c | csr_mhpmcounter30_c => if (HPM_NUM_CNTS > 27) then csr.rdata <= csr.mhpmcounter_rd(27); else NULL; end if; -- (R)/(W): [m]hpmcounter30 - low
when csr_hpmcounter31_c | csr_mhpmcounter31_c => if (HPM_NUM_CNTS > 28) then csr.rdata <= csr.mhpmcounter_rd(28); else NULL; end if; -- (R)/(W): [m]hpmcounter31 - low
 
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => csr.rdata <= csr.mhpmcounterh_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3h - high
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => csr.rdata <= csr.mhpmcounterh_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4h - high
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => csr.rdata <= csr.mhpmcounterh_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5h - high
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => csr.rdata <= csr.mhpmcounterh_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6h - high
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => csr.rdata <= csr.mhpmcounterh_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7h - high
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => csr.rdata <= csr.mhpmcounterh_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8h - high
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => csr.rdata <= csr.mhpmcounterh_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9h - high
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => csr.rdata <= csr.mhpmcounterh_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10h - high
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => csr.rdata <= csr.mhpmcounterh_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11h - high
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => csr.rdata <= csr.mhpmcounterh_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12h - high
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => csr.rdata <= csr.mhpmcounterh_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13h - high
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => csr.rdata <= csr.mhpmcounterh_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14h - high
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => csr.rdata <= csr.mhpmcounterh_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15h - high
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => csr.rdata <= csr.mhpmcounterh_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16h - high
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => csr.rdata <= csr.mhpmcounterh_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17h - high
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => csr.rdata <= csr.mhpmcounterh_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18h - high
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => csr.rdata <= csr.mhpmcounterh_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19h - high
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => csr.rdata <= csr.mhpmcounterh_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20h - high
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => csr.rdata <= csr.mhpmcounterh_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21h - high
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => csr.rdata <= csr.mhpmcounterh_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22h - high
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => csr.rdata <= csr.mhpmcounterh_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23h - high
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => csr.rdata <= csr.mhpmcounterh_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24h - high
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => csr.rdata <= csr.mhpmcounterh_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25h - high
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => csr.rdata <= csr.mhpmcounterh_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26h - high
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => csr.rdata <= csr.mhpmcounterh_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27h - high
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => csr.rdata <= csr.mhpmcounterh_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28h - high
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => csr.rdata <= csr.mhpmcounterh_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29h - high
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => csr.rdata <= csr.mhpmcounterh_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30h - high
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => csr.rdata <= csr.mhpmcounterh_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31h - high
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => if (HPM_NUM_CNTS > 00) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(00); else NULL; end if; -- (R)/(W): [m]hpmcounter3h - high
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => if (HPM_NUM_CNTS > 01) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(01); else NULL; end if; -- (R)/(W): [m]hpmcounter4h - high
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => if (HPM_NUM_CNTS > 02) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(02); else NULL; end if; -- (R)/(W): [m]hpmcounter5h - high
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => if (HPM_NUM_CNTS > 03) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(03); else NULL; end if; -- (R)/(W): [m]hpmcounter6h - high
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => if (HPM_NUM_CNTS > 04) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(04); else NULL; end if; -- (R)/(W): [m]hpmcounter7h - high
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => if (HPM_NUM_CNTS > 05) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(05); else NULL; end if; -- (R)/(W): [m]hpmcounter8h - high
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => if (HPM_NUM_CNTS > 06) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(06); else NULL; end if; -- (R)/(W): [m]hpmcounter9h - high
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => if (HPM_NUM_CNTS > 07) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(07); else NULL; end if; -- (R)/(W): [m]hpmcounter10h - high
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => if (HPM_NUM_CNTS > 08) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(08); else NULL; end if; -- (R)/(W): [m]hpmcounter11h - high
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => if (HPM_NUM_CNTS > 09) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(09); else NULL; end if; -- (R)/(W): [m]hpmcounter12h - high
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => if (HPM_NUM_CNTS > 10) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(10); else NULL; end if; -- (R)/(W): [m]hpmcounter13h - high
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => if (HPM_NUM_CNTS > 11) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(11); else NULL; end if; -- (R)/(W): [m]hpmcounter14h - high
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => if (HPM_NUM_CNTS > 12) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(12); else NULL; end if; -- (R)/(W): [m]hpmcounter15h - high
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => if (HPM_NUM_CNTS > 13) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(13); else NULL; end if; -- (R)/(W): [m]hpmcounter16h - high
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => if (HPM_NUM_CNTS > 14) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(14); else NULL; end if; -- (R)/(W): [m]hpmcounter17h - high
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => if (HPM_NUM_CNTS > 15) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(15); else NULL; end if; -- (R)/(W): [m]hpmcounter18h - high
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => if (HPM_NUM_CNTS > 16) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(16); else NULL; end if; -- (R)/(W): [m]hpmcounter19h - high
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => if (HPM_NUM_CNTS > 17) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(17); else NULL; end if; -- (R)/(W): [m]hpmcounter20h - high
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => if (HPM_NUM_CNTS > 18) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(18); else NULL; end if; -- (R)/(W): [m]hpmcounter21h - high
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => if (HPM_NUM_CNTS > 19) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(19); else NULL; end if; -- (R)/(W): [m]hpmcounter22h - high
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => if (HPM_NUM_CNTS > 20) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(20); else NULL; end if; -- (R)/(W): [m]hpmcounter23h - high
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => if (HPM_NUM_CNTS > 21) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(21); else NULL; end if; -- (R)/(W): [m]hpmcounter24h - high
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => if (HPM_NUM_CNTS > 22) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(22); else NULL; end if; -- (R)/(W): [m]hpmcounter25h - high
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => if (HPM_NUM_CNTS > 23) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(23); else NULL; end if; -- (R)/(W): [m]hpmcounter26h - high
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => if (HPM_NUM_CNTS > 24) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(24); else NULL; end if; -- (R)/(W): [m]hpmcounter27h - high
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => if (HPM_NUM_CNTS > 25) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(25); else NULL; end if; -- (R)/(W): [m]hpmcounter28h - high
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => if (HPM_NUM_CNTS > 26) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(26); else NULL; end if; -- (R)/(W): [m]hpmcounter29h - high
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => if (HPM_NUM_CNTS > 27) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(27); else NULL; end if; -- (R)/(W): [m]hpmcounter30h - high
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => if (HPM_NUM_CNTS > 28) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(28); else NULL; end if; -- (R)/(W): [m]hpmcounter31h - high
 
-- machine information registers --
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
2706,10 → 2708,12
csr.rdata(6) <= '1'; -- Zxscnt (custom)
csr.rdata(7) <= '0'; -- Zxnocnt (custom)
end if;
csr.rdata(8) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP (physical memory protection)
csr.rdata(9) <= bool_to_ulogic_f(boolean(HPM_NUM_CNTS > 0)); -- HPM (hardware performance monitors)
 
-- undefined/unavailable --
when others =>
csr.rdata <= (others => '0'); -- not implemented
NULL; -- not implemented
 
end case;
end if;
/neorv32/trunk/rtl/core/neorv32_cpu_decompressor.vhd
81,7 → 81,7
ci_illegal_o <= '0';
ci_instr32_o <= (others => '0');
 
-- 22-bit sign-extended immediate for J/JAL --
-- helper: 22-bit sign-extended immediate for J/JAL --
imm20_v := (others => ci_instr16_i(12)); -- sign extension
imm20_v(00):= '0';
imm20_v(01):= ci_instr16_i(3);
96,7 → 96,7
imm20_v(10):= ci_instr16_i(8);
imm20_v(11):= ci_instr16_i(12);
 
-- 12-bit sign-extended immediate for branches --
-- helper: 12-bit sign-extended immediate for branches --
imm12_v := (others => ci_instr16_i(12)); -- sign extension
imm12_v(00):= '0';
imm12_v(01):= ci_instr16_i(3);
/neorv32/trunk/rtl/core/neorv32_cpu_regfile.vhd
121,10 → 121,8
-- valid RF write access? --
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
 
-- destination address --
-- access addresses --
dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
 
-- access addresses --
opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
 
/neorv32/trunk/rtl/core/neorv32_package.vhd
83,7 → 83,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050408"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050500"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
171,7 → 171,7
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
 
-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) --
constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
constant uart0_size_c : natural := 2*4; -- module's address space in bytes
constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
203,7 → 203,7
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
 
-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
constant uart1_size_c : natural := 2*4; -- module's address space in bytes
constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
233,11 → 233,11
constant ctrl_rf_rs2_adr2_c : natural := 8; -- source register 2 address bit 2
constant ctrl_rf_rs2_adr3_c : natural := 9; -- source register 2 address bit 3
constant ctrl_rf_rs2_adr4_c : natural := 10; -- source register 2 address bit 4
constant ctrl_rf_rd_adr0_c : natural := 11; -- destiantion register address bit 0
constant ctrl_rf_rd_adr1_c : natural := 12; -- destiantion register address bit 1
constant ctrl_rf_rd_adr2_c : natural := 13; -- destiantion register address bit 2
constant ctrl_rf_rd_adr3_c : natural := 14; -- destiantion register address bit 3
constant ctrl_rf_rd_adr4_c : natural := 15; -- destiantion register address bit 4
constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
constant ctrl_rf_r0_we_c : natural := 17; -- force write access and force rd=r0
-- alu --
581,6 → 581,12
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
---- debug mode registers --
--constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
--constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
--constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
--constant csr_dsratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
--constant csr_dsratch1_c : std_ulogic_vector(11 downto 0) := x"7b3";
-- machine counters/timers --
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
766,6 → 772,7
constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
-- RISC-V compliant interrupts (async. exceptions) --
constant trap_nmi_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: non-maskable interrupt
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
803,27 → 810,28
--
constant exception_width_c : natural := 10; -- length of this list in bits
-- interrupt source bits --
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7
constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8
constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9
constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10
constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11
constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12
constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13
constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14
constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15
constant interrupt_nm_irq_c : natural := 0; -- non-maskable interrupt
constant interrupt_msw_irq_c : natural := 1; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 2; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 3; -- machine external interrupt
constant interrupt_firq_0_c : natural := 4; -- fast interrupt channel 0
constant interrupt_firq_1_c : natural := 5; -- fast interrupt channel 1
constant interrupt_firq_2_c : natural := 6; -- fast interrupt channel 2
constant interrupt_firq_3_c : natural := 7; -- fast interrupt channel 3
constant interrupt_firq_4_c : natural := 8; -- fast interrupt channel 4
constant interrupt_firq_5_c : natural := 9; -- fast interrupt channel 5
constant interrupt_firq_6_c : natural := 10; -- fast interrupt channel 6
constant interrupt_firq_7_c : natural := 11; -- fast interrupt channel 7
constant interrupt_firq_8_c : natural := 12; -- fast interrupt channel 8
constant interrupt_firq_9_c : natural := 13; -- fast interrupt channel 9
constant interrupt_firq_10_c : natural := 14; -- fast interrupt channel 10
constant interrupt_firq_11_c : natural := 15; -- fast interrupt channel 11
constant interrupt_firq_12_c : natural := 16; -- fast interrupt channel 12
constant interrupt_firq_13_c : natural := 17; -- fast interrupt channel 13
constant interrupt_firq_14_c : natural := 18; -- fast interrupt channel 14
constant interrupt_firq_15_c : natural := 19; -- fast interrupt channel 15
--
constant interrupt_width_c : natural := 19; -- length of this list in bits
constant interrupt_width_c : natural := 20; -- length of this list in bits
 
-- CPU Privilege Modes --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
975,6 → 983,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
1042,6 → 1051,8
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- non-maskable interrupt --
nm_irq_i : in std_ulogic := '0'; -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
1101,6 → 1112,8
-- FPU interface --
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
-- non-maskable interrupt --
nm_irq_i : in std_ulogic;
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
/neorv32/trunk/rtl/core/neorv32_top.vhd
179,6 → 179,7
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
 
-- Interrupts --
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
455,6 → 456,8
d_bus_priv_o => cpu_d.priv, -- privilege level
-- system time input from MTIME --
time_i => mtime_time, -- current system time
-- non-maskable interrupt --
nm_irq_i => nm_irq_i, -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt request
485,12 → 488,17
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
 
-- fast interrupts - platform level (for custom use) --
fast_irq(10) <= soc_firq_i(0);
fast_irq(11) <= soc_firq_i(1);
fast_irq(12) <= soc_firq_i(2);
fast_irq(13) <= soc_firq_i(3);
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
soc_firq_sync: process(clk_i)
begin
if rising_edge(clk_i) then -- make sure they are sync
fast_irq(10) <= soc_firq_i(0);
fast_irq(11) <= soc_firq_i(1);
fast_irq(12) <= soc_firq_i(2);
fast_irq(13) <= soc_firq_i(3);
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
end if;
end process soc_firq_sync;
 
-- CFS IRQ acknowledge --
cfs_irq_ack <= fast_irq_ack(1);
/neorv32/trunk/rtl/top_templates/neorv32_test_setup.vhd
178,6 → 178,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i => (others => '0'), -- current system time
-- Interrupts --
nm_irq_i => '0', -- non-maskable interrupt
soc_firq_i => (others => '0'), -- fast interrupt channels
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => '0', -- machine software interrupt
/neorv32/trunk/rtl/top_templates/neorv32_top_axi4lite.vhd
167,6 → 167,7
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o : out std_logic; -- async serial data line
-- Interrupts --
nm_irq_i : in std_logic := '0'; -- non-maskable interrupt
soc_firq_i : in std_logic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
msw_irq_i : in std_logic := '0'; -- machine software interrupt
mext_irq_i : in std_logic := '0' -- machine external interrupt
209,6 → 210,7
--
signal neoled_o_int : std_ulogic;
--
signal nm_irq_i_int : std_ulogic;
signal soc_firq_i_int : std_ulogic_vector(05 downto 0);
signal msw_irq_i_int : std_ulogic;
signal mext_irq_i_int : std_ulogic;
362,6 → 364,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i => (others => '0'), -- current system time
-- Interrupts --
nm_irq_i => nm_irq_i_int, -- non-maskable interrupt
soc_firq_i => soc_firq_i_int, -- fast interrupt channels
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => msw_irq_i_int, -- machine software interrupt
/neorv32/trunk/rtl/top_templates/neorv32_top_stdlogic.vhd
151,6 → 151,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
nm_irq_i : in std_logic := '0'; -- non-maskable interrupt
soc_firq_i : in std_logic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_logic := '0'; -- machine software interrupt
211,6 → 212,7
--
signal mtime_i_int : std_ulogic_vector(63 downto 0);
--
signal nm_irq_i_int : std_ulogic;
signal soc_firq_i_int : std_ulogic_vector(05 downto 0);
signal mtime_irq_i_int : std_ulogic;
signal msw_irq_i_int : std_ulogic;
332,6 → 334,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i => mtime_i_int, -- current system time
-- Interrupts --
nm_irq_i => nm_irq_i_int, -- non-maskable interrupt
soc_firq_i => soc_firq_i_int, -- fast interrupt channels
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => msw_irq_i_int, -- machine software interrupt
/neorv32/trunk/sim/neorv32_tb.vhd
120,8 → 120,8
signal spi_data : std_ulogic;
 
-- irq --
signal msi_ring, mei_ring : std_ulogic;
signal soc_firq_ring : std_ulogic_vector(5 downto 0);
signal msi_ring, mei_ring, nmi_ring : std_ulogic;
signal soc_firq_ring : std_ulogic_vector(5 downto 0);
 
-- Wishbone bus --
type wishbone_t is record
209,10 → 209,10
TINY_SHIFT_EN => false, -- use tiny (single-bit) shifter for shift operations
CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => 4, -- number of regions (0..64)
PMP_NUM_REGIONS => 5, -- number of regions (0..64)
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29)
HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH => 40, -- total size of HPM counters (1..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
298,6 → 298,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i => (others => '0'), -- current system time
-- Interrupts --
nm_irq_i => nmi_ring, -- non-maskable interrupt
soc_firq_i => soc_firq_ring, -- fast interrupt channels
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
msw_irq_i => msi_ring, -- machine software interrupt
596,10 → 597,12
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
wb_irq.err <= '0';
-- trigger IRQ using CSR.MIE bit layout --
nmi_ring <= '0';
msi_ring <= '0';
mei_ring <= '0';
soc_firq_ring <= (others => '0');
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
nmi_ring <= wb_irq.wdata(00); -- non-maskable interrupt
msi_ring <= wb_irq.wdata(03); -- machine software interrupt
mei_ring <= wb_irq.wdata(11); -- machine software interrupt
--
/neorv32/trunk/sw/common/crt0.S
38,10 → 38,6
.global _start
 
 
// IO region
.equ IO_BEGIN, 0xFFFFFF00 // start of processor-internal IO region
 
 
_start:
.cfi_startproc
.cfi_undefined ra
58,8 → 54,8
addi x5, x0, 0
addi x6, x0, 0
addi x7, x0, 0
addi x8, x0, 0
addi x9, x0, 0
//addi x8, x0, 0
//addi x9, x0, 0
//addi x10, x0, 0
//addi x11, x0, 0
//addi x12, x0, 0
104,11 → 100,11
 
// stop all counters except for [m]cycle[h] and [m]instret[h]
li x11, ~5
csrw mcountinhibit, x11
csrw 0x320, x11 // mcountinhibit (literal address for lagacy toolchain compatibility)
 
// clear cycle counters
csrw mcycle, zero
csrw mcycleh, zero
csrw mcycle, zero
csrw mcycleh, zero
 
// clear instruction counters
csrw minstret, zero
152,12 → 148,13
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
__crt0_reset_io:
li x11, IO_BEGIN // start of processor-internal IO region
la x8, __ctr0_io_space_begin // start of processor-internal IO region
la x9, __ctr0_io_space_end // end of processor-internal IO region
 
__crt0_reset_io_loop:
sw zero, 0(x11)
addi x11, x11, 4
bne zero, x11, __crt0_reset_io_loop
sw zero, 0(x8)
addi x8, x8, 4
bne x8, x9, __crt0_reset_io_loop
 
 
// *********************************************************
/neorv32/trunk/sw/common/neorv32.ld
3,7 → 3,7
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License # */
/* # # */
/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */
/* # # */
/* # Redistribution and use in source and binary forms, with or without modification, are # */
/* # permitted provided that the following conditions are met: # */
48,14 → 48,20
 
/* ************************************************************************* */
/* NEORV32 memory configuration. */
/* Make sure this is sync with your processor/memory hardware configuration. */
/* Make sure this is sync with your processor/memory hardware configuration! */
/* ************************************************************************* */
/* "rom" : instruction memory (IMEM) / bootloader ROM */
/* "ram" : data memory (DMEM) */
/* "iodev" : peripheral/IO devices (not used here; passed to crt0) */
/* ************************************************************************* */
MEMORY
{
/* "rom" section: first value of ORIGIN/LENGHT => bootloader ROM; second value of ORIGIN/LENGHT => instruction memory */
/* "rom" section: first value of ORIGIN/LENGTH => bootloader ROM; second value of ORIGIN/LENGTH => instruction memory */
 
rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 4*1024 : 16*1024
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024
rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 4*1024 : 16*1024
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024
iodev (rw) : ORIGIN = 0xFFFFFF00, LENGTH = 256
 
}
/* ************************************************************************* */
 
285,10 → 291,12
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
 
 
/* Provide further symbols for neorv32 crt0.elf */
/* Provide further symbols for neorv32 crt0 */
PROVIDE(__crt0_bss_start = __bss_start);
PROVIDE(__crt0_bss_end = __BSS_END__);
PROVIDE(__crt0_copy_data_src_begin = __etext + SIZEOF(.rodata));
PROVIDE(__crt0_copy_data_dst_begin = __DATA_BEGIN__);
PROVIDE(__crt0_copy_data_dst_end = __DATA_BEGIN__ + SIZEOF(.data));
PROVIDE(__ctr0_io_space_begin = ORIGIN(iodev));
PROVIDE(__ctr0_io_space_end = ORIGIN(iodev) + LENGTH(iodev));
}
/neorv32/trunk/sw/example/cpu_test/main.c
278,31 → 278,37
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] mcounteren.cy CSR: ", cnt_test);
 
cnt_test++;
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
cnt_test++;
 
// do not allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
// do not allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
 
// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
neorv32_cpu_goto_user_mode();
{
// access to cycle CSR is no longer allowed
tmp_a = neorv32_cpu_csr_read(CSR_CYCLE);
}
// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
neorv32_cpu_goto_user_mode();
{
// access to cycle CSR is no longer allowed
tmp_a = neorv32_cpu_csr_read(CSR_CYCLE);
}
 
// make sure there was an illegal instruction trap
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
if (tmp_a == 0) { // make sure user-level code CANNOT read locked CSR content!
test_ok();
// make sure there was an illegal instruction trap
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
if (tmp_a == 0) { // make sure user-level code CANNOT read locked CSR content!
test_ok();
}
else {
test_fail();
}
}
else {
test_fail();
}
}
else {
test_fail();
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
540,54 → 546,6
 
 
// ----------------------------------------------------------
// Test clearing pending interrupt (via mip CSR)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Clear pending IRQ (via mip CSR) test (from MTIME): ", cnt_test);
 
if (neorv32_mtime_available()) {
cnt_test++;
 
// disable global interrupts
neorv32_cpu_dint();
 
// force MTIME IRQ
neorv32_mtime_set_timecmp(0);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// no more mtime interrupts
neorv32_mtime_set_timecmp(-1);
 
 
if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP)) { // make sure MTIP is pending
 
neorv32_cpu_csr_write(CSR_MIP, 0); // just clear all pending IRQs
neorv32_cpu_eint(); // re-enable global interrupts
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
neorv32_uart_printf("IRQ triggered! ");
test_fail();
}
}
else {
neorv32_uart_printf("MTIP not pending! ");
test_fail();
}
 
// re-enable global interrupts
neorv32_cpu_eint();
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
923,6 → 881,34
 
 
// ----------------------------------------------------------
// Non-maskable interrupt (NMI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] NMI (via testbench) IRQ: ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// trigger IRQ
sim_irq_trigger(1 << 0);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_NMI) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 0 (WDT)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
/neorv32/trunk/sw/lib/include/neorv32.h
100,7 → 100,7
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
CSR_MIP = 0x344, /**< 0x344 - mip (r/-): Machine interrupt pending register */
 
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
511,7 → 511,9
CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
CSR_MZEXT_ZXNOCNT = 7 /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
CSR_MZEXT_PMP = 8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
CSR_MZEXT_HPM = 9 /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
};
 
 
553,6 → 555,7
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
TRAP_CODE_NMI = 0x80000000, /**< 1.0: Non-maskable interrupt */
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
/neorv32/trunk/sw/lib/include/neorv32_rte.h
56,25 → 56,26
RTE_TRAP_S_ACCESS = 7, /**< Store (bus) access fault */
RTE_TRAP_UENV_CALL = 8, /**< Environment call from user mode (ECALL instruction) */
RTE_TRAP_MENV_CALL = 9, /**< Environment call from machine mode (ECALL instruction) */
RTE_TRAP_MSI = 10, /**< Machine software interrupt */
RTE_TRAP_MTI = 11, /**< Machine timer interrupt */
RTE_TRAP_MEI = 12, /**< Machine external interrupt */
RTE_TRAP_FIRQ_0 = 13, /**< Fast interrupt channel 0 */
RTE_TRAP_FIRQ_1 = 14, /**< Fast interrupt channel 1 */
RTE_TRAP_FIRQ_2 = 15, /**< Fast interrupt channel 2 */
RTE_TRAP_FIRQ_3 = 16, /**< Fast interrupt channel 3 */
RTE_TRAP_FIRQ_4 = 17, /**< Fast interrupt channel 4 */
RTE_TRAP_FIRQ_5 = 18, /**< Fast interrupt channel 5 */
RTE_TRAP_FIRQ_6 = 19, /**< Fast interrupt channel 6 */
RTE_TRAP_FIRQ_7 = 20, /**< Fast interrupt channel 7 */
RTE_TRAP_FIRQ_8 = 21, /**< Fast interrupt channel 8 */
RTE_TRAP_FIRQ_9 = 22, /**< Fast interrupt channel 9 */
RTE_TRAP_FIRQ_10 = 23, /**< Fast interrupt channel 10 */
RTE_TRAP_FIRQ_11 = 24, /**< Fast interrupt channel 11 */
RTE_TRAP_FIRQ_12 = 25, /**< Fast interrupt channel 12 */
RTE_TRAP_FIRQ_13 = 26, /**< Fast interrupt channel 13 */
RTE_TRAP_FIRQ_14 = 27, /**< Fast interrupt channel 14 */
RTE_TRAP_FIRQ_15 = 28 /**< Fast interrupt channel 15 */
RTE_TRAP_NMI = 10, /**< Non-maskable interrupt */
RTE_TRAP_MSI = 11, /**< Machine software interrupt */
RTE_TRAP_MTI = 12, /**< Machine timer interrupt */
RTE_TRAP_MEI = 13, /**< Machine external interrupt */
RTE_TRAP_FIRQ_0 = 14, /**< Fast interrupt channel 0 */
RTE_TRAP_FIRQ_1 = 15, /**< Fast interrupt channel 1 */
RTE_TRAP_FIRQ_2 = 16, /**< Fast interrupt channel 2 */
RTE_TRAP_FIRQ_3 = 17, /**< Fast interrupt channel 3 */
RTE_TRAP_FIRQ_4 = 18, /**< Fast interrupt channel 4 */
RTE_TRAP_FIRQ_5 = 19, /**< Fast interrupt channel 5 */
RTE_TRAP_FIRQ_6 = 20, /**< Fast interrupt channel 6 */
RTE_TRAP_FIRQ_7 = 21, /**< Fast interrupt channel 7 */
RTE_TRAP_FIRQ_8 = 22, /**< Fast interrupt channel 8 */
RTE_TRAP_FIRQ_9 = 23, /**< Fast interrupt channel 9 */
RTE_TRAP_FIRQ_10 = 24, /**< Fast interrupt channel 10 */
RTE_TRAP_FIRQ_11 = 25, /**< Fast interrupt channel 11 */
RTE_TRAP_FIRQ_12 = 26, /**< Fast interrupt channel 12 */
RTE_TRAP_FIRQ_13 = 27, /**< Fast interrupt channel 13 */
RTE_TRAP_FIRQ_14 = 28, /**< Fast interrupt channel 14 */
RTE_TRAP_FIRQ_15 = 29 /**< Fast interrupt channel 15 */
};
 
 
81,7 → 82,7
/**********************************************************************//**
* NEORV32 runtime environment: Number of available traps.
**************************************************************************/
#define NEORV32_RTE_NUM_TRAPS 29
#define NEORV32_RTE_NUM_TRAPS 30
 
 
// prototypes
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
331,6 → 331,11
**************************************************************************/
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
 
// PMP implemented at all?
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_PMP)) == 0) {
return 0;
}
 
uint32_t i = 0;
 
// try setting R bit in all PMPCFG CSRs
587,10 → 592,15
*
* @warning This function overrides all available mhpmcounter* CSRs.
*
* @return Returns number of available HPM counters (..29).
* @return Returns number of available HPM counters (0..29).
**************************************************************************/
uint32_t neorv32_cpu_hpm_get_counters(void) {
 
// HPMs implemented at all?
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) {
return 0;
}
 
// inhibit all HPM counters
uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
tmp |= 0xfffffff8;
665,10 → 675,15
*
* @warning This function overrides mhpmcounter3[h] CSRs.
*
* @return Size of HPM counter bits (1-64).
* @return Size of HPM counter bits (1-64, 0 if not implemented at all).
**************************************************************************/
uint32_t neorv32_cpu_hpm_get_size(void) {
 
// HPMs implemented at all?
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) {
return 0;
}
 
// inhibt auto-update
asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTEREN_HPM3));
 
/neorv32/trunk/sw/lib/source/neorv32_rte.c
45,7 → 45,7
/**********************************************************************//**
* The >private< trap vector look-up table of the NEORV32 RTE.
**************************************************************************/
static uint32_t __neorv32_rte_vector_lut[29] __attribute__((unused)); // trap handler vector table
static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table
 
// private functions
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
167,6 → 167,7
case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
case TRAP_CODE_UENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
case TRAP_CODE_NMI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_NMI]; break;
case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
273,9 → 274,9
 
// Processor - general stuff
neorv32_uart_printf("\n=== << General >> ===\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
neorv32_uart_printf("Dedicated HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET));
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
neorv32_uart_printf("Full HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET));
 
 
// CPU configuration
371,7 → 372,7
}
 
// check hardware performance monitors
neorv32_uart_printf("HPM Counters: %ux, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
neorv32_uart_printf("HPM Counters: %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
 
 
// Memory configuration
/neorv32/trunk/CHANGELOG.md
24,6 → 24,11
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 10.05.2021 | [**:rocket:1.5.5.0**](https://github.com/stnolting/neorv32/releases/tag/v1.5.5.0) | **New release** |
| 10.05.2021 | 1.5.4.12 | :warning: `mip` CSR is now read-only (pending IRQs can be cleared by disabling (and re-enabling) the according `mie` bit), writing to `mip` will raise an illegal instruction exception; :sparkles: added non-maskable interrupt (NMI), top entity port `nm_irq_i`; added new NMI to NEORV32 runtime environment |
| 09.05.2021 | 1.5.4.11 | added new flags to `mzext` CSR: *CSR_MZEXT_PMP* (set if at least 1 PMP region is implemented at all), *CSR_MZEXT_HPM* (set if at least 1 HPM counter is implemented) |
| 03.05.2021 | 1.5.4.10 | minor code clean-ups; moved FIRQ synchronization registers to top, removed sync FFs for processor-internal sources; |
| 30.04.2021 | 1.5.4.9 | moved definitions of IO area from `crt0.S` to linker script; reworked CPU's CSR access system - highly reducing area overhead (removing decoding logic of not implemented CSRs by heavily using VHDL's `NULL` statement in `case` constructs) |
| 29.04.2021 | 1.5.4.8 | minor edits in CPU instruction fetch engine; reduced **processor-internal bus timeout** (`max_proc_int_response_time_c`) to 15 cycles; added flag to SYSINGO module (`SYSINFO_FEATURES_HW_RESET`) to check if a dedicated hardware reset of all core register is implemented (via package's `dedicated_reset_c` constant) |
| 28.04.2021 | 1.5.4.7 | :bug: fixed bug in instruction cache (iCACHE) when using two sets - `ICACHE_ASSOCIATIVITY` = 2: cache was corrupting the non-active set |
| 26.04.2021 | 1.5.4.6 | optimized CPU's instruction fetch unit: less overhead for branches, reduced unit's hardware complexity |
/neorv32/trunk/README.md
113,11 → 113,11
 
| Project component | CI status |
|:----------------- |:----------|
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
| Build data sheet from `asciidoc` sources | [![Build Data Sheet](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [![riscv-arch-test](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
| Build data sheet from [`asciidoc` sources](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc) | [![Build Data Sheet](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [![riscv-arch-test](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
 
 
## Features
288,6 → 288,7
* Environment call from U-mode (via `ecall` instruction in user mode)
* Environment call from M-mode (via `ecall` instruction in machine mode)
* Supported interrupts:
* RISC-V non-maskable interrupt `nmi` (via external signal)
* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
* RISC-V machine software interrupt `msi` (via external signal)
* RISC-V machine external interrupt `mei` (via external signal)
325,6 → 326,7
 
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
* `mip` CSR is read-only - pending IRQs can be cleared using `mie`
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all remaining AMO operations
 
363,28 → 365,30
 
### NEORV32 Processor-Internal Peripherals and Memories
 
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
Results generated for hardware version [`1.5.4.9`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
(mandatory core modules in **bold**).
 
| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-------------:|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
| CFS | Custom functions subsystem | - | - | - | - |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
| NEOLED | Smart LED Interface (NeoPixel-compatibile) [4x FIFO] | 347 | 309 | 0 | 0 |
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
|:--------------|:----------------------------------------------------|----:|----:|------------:|-------------:|
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0 |
| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0 |
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0 |
| CFS | Custom functions subsystem | - | - | - | - |
| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0 |
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0 |
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0 |
| MTIME | Machine system timer | 289 | 200 | 0 | 0 |
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0 |
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0 |
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0 |
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
| TWI | Two-wire interface | 77 | 44 | 0 | 0 |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
 
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