OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/neorv32_clic.vhd File deleted
/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin>
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
 
library ieee;
use ieee.std_logic_1164.all;
8,1211 → 8,1009
 
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00930001",
00000001 => x"81130000",
00000002 => x"01930000",
00000003 => x"82130001",
00000004 => x"02930001",
00000005 => x"83130002",
00000006 => x"03930002",
00000007 => x"84130003",
00000008 => x"04930003",
00000009 => x"85130004",
00000010 => x"05930004",
00000011 => x"86130005",
00000012 => x"06930005",
00000013 => x"87130006",
00000014 => x"07930006",
00000015 => x"88130007",
00000016 => x"08930007",
00000017 => x"89130008",
00000018 => x"09930008",
00000019 => x"8a130009",
00000020 => x"0a930009",
00000021 => x"8b13000a",
00000022 => x"0b93000a",
00000023 => x"8c13000b",
00000024 => x"0c93000b",
00000025 => x"8d13000c",
00000026 => x"0d93000c",
00000027 => x"8e13000d",
00000028 => x"0e93000d",
00000029 => x"8f13000e",
00000030 => x"0f93000e",
00000031 => x"0001000f",
00000000 => x"00000093",
00000001 => x"00008113",
00000002 => x"00010193",
00000003 => x"00018213",
00000004 => x"00020293",
00000005 => x"00028313",
00000006 => x"00030393",
00000007 => x"00038413",
00000008 => x"00040493",
00000009 => x"00048513",
00000010 => x"00050593",
00000011 => x"00058613",
00000012 => x"00060693",
00000013 => x"00068713",
00000014 => x"00070793",
00000015 => x"00078813",
00000016 => x"00080893",
00000017 => x"00088913",
00000018 => x"00090993",
00000019 => x"00098a13",
00000020 => x"000a0a93",
00000021 => x"000a8b13",
00000022 => x"000b0b93",
00000023 => x"000b8c13",
00000024 => x"000c0c93",
00000025 => x"000c8d13",
00000026 => x"000d0d93",
00000027 => x"000d8e13",
00000028 => x"000e0e93",
00000029 => x"000e8f13",
00000030 => x"000f0f93",
00000031 => x"00000013",
00000032 => x"ff402583",
00000033 => x"ffc02603",
00000034 => x"00c58133",
00000035 => x"04131171",
00000036 => x"01970001",
00000037 => x"81938000",
00000038 => x"05977ee1",
00000039 => x"85930000",
00000040 => x"90730965",
00000041 => x"25833055",
00000042 => x"0617ff40",
00000043 => x"06130000",
00000044 => x"06931506",
00000045 => x"c1900200",
00000046 => x"16fd0591",
00000047 => x"fed01de3",
00000048 => x"f8000593",
00000049 => x"0005a023",
00000050 => x"1de30591",
00000051 => x"0597feb0",
00000052 => x"85938000",
00000053 => x"8613fba5",
00000054 => x"d66382c1",
00000055 => x"802300c5",
00000056 => x"05850005",
00000057 => x"1597bfdd",
00000058 => x"85930000",
00000059 => x"06171e65",
00000060 => x"06138000",
00000061 => x"0697f926",
00000062 => x"86938000",
00000063 => x"5963f926",
00000064 => x"870300d6",
00000065 => x"00230005",
00000066 => x"058500e6",
00000067 => x"bfc50605",
00000068 => x"00000513",
00000069 => x"00000593",
00000070 => x"0ee000ef",
00000071 => x"30047073",
00000072 => x"10500073",
00000073 => x"0013a001",
00000074 => x"00130000",
00000075 => x"00010000",
00000076 => x"f8810113",
00000077 => x"c20ec006",
00000078 => x"c616c412",
00000079 => x"ca1ec81a",
00000080 => x"ce26cc22",
00000081 => x"d22ed02a",
00000082 => x"d636d432",
00000083 => x"da3ed83a",
00000084 => x"de46dc42",
00000085 => x"c2cec0ca",
00000086 => x"c6d6c4d2",
00000087 => x"cadec8da",
00000088 => x"cee6cce2",
00000089 => x"d2eed0ea",
00000090 => x"d6f6d4f2",
00000091 => x"dafed8fa",
00000092 => x"342022f3",
00000093 => x"00f2f313",
00000094 => x"2083030a",
00000095 => x"9306ff40",
00000096 => x"341020f3",
00000097 => x"0002cd63",
00000098 => x"00009283",
00000099 => x"00300393",
00000100 => x"0072f2b3",
00000101 => x"96630089",
00000102 => x"00890072",
00000103 => x"0313a019",
00000104 => x"22830403",
00000105 => x"11710003",
00000106 => x"80e7c006",
00000107 => x"40820002",
00000108 => x"90730111",
00000109 => x"40823410",
00000110 => x"42224192",
00000111 => x"434242b2",
00000112 => x"446243d2",
00000113 => x"550244f2",
00000114 => x"56225592",
00000115 => x"574256b2",
00000116 => x"586257d2",
00000117 => x"490658f2",
00000118 => x"4a264996",
00000119 => x"4b464ab6",
00000120 => x"4c664bd6",
00000121 => x"5d064cf6",
00000122 => x"5e265d96",
00000123 => x"5f465eb6",
00000124 => x"01135fd6",
00000125 => x"00730781",
00000126 => x"80823020",
00000127 => x"00000000",
00000128 => x"00000000",
00000129 => x"71390000",
00000130 => x"dc22de06",
00000131 => x"d84ada26",
00000132 => x"d452d64e",
00000133 => x"00efd256",
00000134 => x"00631230",
00000135 => x"00ef0c05",
00000136 => x"0c632fb0",
00000137 => x"00ef0a05",
00000138 => x"08630410",
00000139 => x"65150a05",
00000140 => x"45814601",
00000141 => x"b0050513",
00000142 => x"10b000ef",
00000143 => x"45814501",
00000144 => x"031000ef",
00000145 => x"557d55fd",
00000146 => x"063000ef",
00000147 => x"05136505",
00000148 => x"00efd9c5",
00000149 => x"00ef16f0",
00000150 => x"00ef0090",
00000151 => x"650560a0",
00000152 => x"db850513",
00000153 => x"00ef4481",
00000154 => x"059315b0",
00000155 => x"450177e0",
00000156 => x"842a232d",
00000157 => x"77e00593",
00000158 => x"23054505",
00000159 => x"0593942a",
00000160 => x"450977e0",
00000161 => x"942a2b19",
00000162 => x"77e00593",
00000163 => x"2331450d",
00000164 => x"0593942a",
00000165 => x"451177e0",
00000166 => x"942a2309",
00000167 => x"77e00593",
00000168 => x"29e54515",
00000169 => x"0593942a",
00000170 => x"451977e0",
00000171 => x"942a21fd",
00000172 => x"77e00593",
00000173 => x"21d5451d",
00000174 => x"0593942a",
00000175 => x"452d77e0",
00000176 => x"942a29e9",
00000177 => x"77e00593",
00000178 => x"29c1455d",
00000179 => x"c005942a",
00000180 => x"05136505",
00000181 => x"00efdd05",
00000182 => x"50f20eb0",
00000183 => x"54d25462",
00000184 => x"59b25942",
00000185 => x"5a925a22",
00000186 => x"61214501",
00000187 => x"05938082",
00000188 => x"450177e0",
00000189 => x"22f000ef",
00000190 => x"c509842a",
00000191 => x"05136505",
00000192 => x"bfd1de45",
00000193 => x"30046073",
00000194 => x"650554fd",
00000195 => x"8291a423",
00000196 => x"dfc50513",
00000197 => x"a4236985",
00000198 => x"00ef8291",
00000199 => x"85130a70",
00000200 => x"00efe0c9",
00000201 => x"650509f0",
00000202 => x"e2050513",
00000203 => x"8291a423",
00000204 => x"091000ef",
00000205 => x"e0c98513",
00000206 => x"089000ef",
00000207 => x"05136505",
00000208 => x"00efe305",
00000209 => x"17b707f0",
00000210 => x"87931bcd",
00000211 => x"90732347",
00000212 => x"47b7b007",
00000213 => x"87930003",
00000214 => x"90734557",
00000215 => x"2773b807",
00000216 => x"76c1b000",
00000217 => x"06b78f75",
00000218 => x"12631bcd",
00000219 => x"277332d7",
00000220 => x"1e63b800",
00000221 => x"650530f7",
00000222 => x"e4050513",
00000223 => x"045000ef",
00000224 => x"65054485",
00000225 => x"e4c50513",
00000226 => x"039000ef",
00000227 => x"112247b7",
00000228 => x"49978793",
00000229 => x"b0279073",
00000230 => x"000907b7",
00000231 => x"907307c5",
00000232 => x"2773b827",
00000233 => x"76c1b020",
00000234 => x"06b78f75",
00000235 => x"18631122",
00000236 => x"27732ed7",
00000237 => x"1463b820",
00000238 => x"65052ef7",
00000239 => x"e4050513",
00000240 => x"001000ef",
00000241 => x"65050485",
00000242 => x"e5c50513",
00000243 => x"7f4000ef",
00000244 => x"c01027f3",
00000245 => x"2af3c83e",
00000246 => x"79c1c810",
00000247 => x"0137fa33",
00000248 => x"00efca56",
00000249 => x"f9b36aa0",
00000250 => x"116300a9",
00000251 => x"9f632d3a",
00000252 => x"65052aba",
00000253 => x"e4050513",
00000254 => x"7c8000ef",
00000255 => x"65050485",
00000256 => x"051359fd",
00000257 => x"a423e6c5",
00000258 => x"00ef8331",
00000259 => x"000f7b60",
00000260 => x"100f0ff0",
00000261 => x"a7830000",
00000262 => x"80638281",
00000263 => x"65052b37",
00000264 => x"e4450513",
00000265 => x"79c000ef",
00000266 => x"65050405",
00000267 => x"051357fd",
00000268 => x"a423e7c5",
00000269 => x"00ef82f1",
00000270 => x"27f378a0",
00000271 => x"8b913010",
00000272 => x"28079b63",
00000273 => x"97824789",
00000274 => x"8281a783",
00000275 => x"26079e63",
00000276 => x"05136505",
00000277 => x"00efe405",
00000278 => x"048576a0",
00000279 => x"65054995",
00000280 => x"051357fd",
00000281 => x"a423eb85",
00000282 => x"00ef82f1",
00000283 => x"07937560",
00000284 => x"9782f000",
00000285 => x"8281a703",
00000286 => x"15634785",
00000287 => x"650526f7",
00000288 => x"e4050513",
00000289 => x"73c000ef",
00000290 => x"65050485",
00000291 => x"051357fd",
00000292 => x"a423ec85",
00000293 => x"00ef82f1",
00000294 => x"07b772a0",
00000295 => x"87938000",
00000296 => x"80e70807",
00000297 => x"a7030007",
00000298 => x"47898281",
00000299 => x"24f71363",
00000300 => x"05136505",
00000301 => x"00efe405",
00000302 => x"048570a0",
00000303 => x"57fd6505",
00000304 => x"ed850513",
00000305 => x"82f1a423",
00000306 => x"6f8000ef",
00000307 => x"a7039002",
00000308 => x"478d8281",
00000309 => x"22f71663",
00000310 => x"05136505",
00000311 => x"00efe405",
00000312 => x"04856e20",
00000313 => x"57fd6505",
00000314 => x"ee850513",
00000315 => x"82f1a423",
00000316 => x"6d0000ef",
00000317 => x"00202003",
00000318 => x"8281a703",
00000319 => x"18634791",
00000320 => x"650520f7",
00000321 => x"e4050513",
00000322 => x"6b8000ef",
00000323 => x"65050485",
00000324 => x"051357fd",
00000325 => x"a423ef85",
00000326 => x"00ef82f1",
00000327 => x"27836a60",
00000328 => x"c63ef000",
00000329 => x"8281a703",
00000330 => x"19634795",
00000331 => x"65051ef7",
00000332 => x"e4050513",
00000333 => x"68c000ef",
00000334 => x"65050485",
00000335 => x"051357fd",
00000336 => x"a423f085",
00000337 => x"00ef82f1",
00000338 => x"212367a0",
00000339 => x"a7030000",
00000340 => x"47998281",
00000341 => x"1cf71b63",
00000342 => x"05136505",
00000343 => x"00efe405",
00000344 => x"04856620",
00000345 => x"57fd6505",
00000346 => x"f1850513",
00000347 => x"82f1a423",
00000348 => x"650000ef",
00000349 => x"f0002023",
00000350 => x"8281a703",
00000351 => x"1d63479d",
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00000353 => x"e4050513",
00000354 => x"638000ef",
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00000357 => x"a423f285",
00000358 => x"00ef82f1",
00000359 => x"00736260",
00000360 => x"a7030000",
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00000367 => x"f3850513",
00000368 => x"82f1a423",
00000369 => x"5fc000ef",
00000370 => x"45814501",
00000371 => x"4de000ef",
00000372 => x"00010001",
00000373 => x"00010001",
00000374 => x"8281a703",
00000375 => x"800007b7",
00000376 => x"1863079d",
00000377 => x"650516f7",
00000378 => x"e4050513",
00000379 => x"5d4000ef",
00000380 => x"55fd0485",
00000381 => x"00ef557d",
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00000383 => x"051357fd",
00000384 => x"a423f485",
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00000386 => x"45015ba0",
00000387 => x"76e000ef",
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00000389 => x"00010001",
00000390 => x"8281a703",
00000391 => x"800007b7",
00000392 => x"1e6307ad",
00000393 => x"650512f7",
00000394 => x"e4050513",
00000395 => x"594000ef",
00000396 => x"65050485",
00000397 => x"051357fd",
00000398 => x"a423f585",
00000399 => x"00ef82f1",
00000400 => x"21a95820",
00000401 => x"051387aa",
00000402 => x"37b33e85",
00000403 => x"95be00f5",
00000404 => x"29a109ad",
00000405 => x"10500073",
00000406 => x"8281a703",
00000407 => x"800007b7",
00000408 => x"0463079d",
00000409 => x"650510f7",
00000410 => x"e4450513",
00000411 => x"554000ef",
00000412 => x"65050405",
00000413 => x"862686a2",
00000414 => x"051385ce",
00000415 => x"00eff685",
00000416 => x"1a635420",
00000417 => x"65050e04",
00000418 => x"f8c50513",
00000419 => x"6505b1a9",
00000420 => x"e4450513",
00000421 => x"52c000ef",
00000422 => x"44054481",
00000423 => x"6505b1dd",
00000424 => x"e4450513",
00000425 => x"51c000ef",
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00000444 => x"6505bb69",
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00000464 => x"04054820",
00000465 => x"6505b5a9",
00000466 => x"e4450513",
00000467 => x"04052995",
00000468 => x"6505b5a5",
00000469 => x"e4450513",
00000470 => x"040521a5",
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00000484 => x"6505a905",
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00000487 => x"c226c422",
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00000593 => x"25833591",
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00000596 => x"14050513",
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00000599 => x"25032495",
00000600 => x"8941fe80",
00000601 => x"65053515",
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00000619 => x"3be98d61",
00000620 => x"05136505",
00000621 => x"24291dc5",
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/neorv32_bootloader_image.vhd
27,1005 → 27,1010
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00000925 => x"52450a07",
00000926 => x"00005f52",
00000927 => x"6e6b6e75",
00000928 => x"006e776f",
00000929 => x"00007830",
00000930 => x"58450a0a",
00000931 => x"54504543",
00000932 => x"3a4e4f49",
00000933 => x"00000020",
00000934 => x"30204020",
00000935 => x"00000078",
00000936 => x"69617741",
00000937 => x"676e6974",
00000938 => x"6f656e20",
00000939 => x"32337672",
00000940 => x"6578655f",
00000941 => x"6e69622e",
00000942 => x"202e2e2e",
00000943 => x"00000000",
00000944 => x"64616f4c",
00000945 => x"2e676e69",
00000946 => x"00202e2e",
00000947 => x"00004b4f",
00000948 => x"74697257",
00000949 => x"78302065",
00000950 => x"00000000",
00000951 => x"74796220",
00000952 => x"74207365",
00000953 => x"5053206f",
00000954 => x"6c662049",
00000955 => x"20687361",
00000956 => x"78302040",
00000957 => x"00000000",
00000958 => x"7928203f",
00000959 => x"20296e2f",
00000960 => x"00000000",
00000961 => x"616c460a",
00000962 => x"6e696873",
00000963 => x"2e2e2e67",
00000964 => x"00000020",
00000965 => x"0a0a0a0a",
00000966 => x"4e203c3c",
00000967 => x"56524f45",
00000968 => x"42203233",
00000969 => x"6c746f6f",
00000970 => x"6564616f",
00000971 => x"3e3e2072",
00000972 => x"4c420a0a",
00000973 => x"203a5644",
00000974 => x"206c754a",
00000975 => x"32203532",
00000976 => x"0a303230",
00000977 => x"3a565748",
00000978 => x"00002020",
00000979 => x"4b4c430a",
00000980 => x"0020203a",
00000981 => x"0a7a4820",
00000982 => x"52455355",
00000983 => x"0000203a",
00000984 => x"53494d0a",
00000985 => x"00203a41",
00000986 => x"4e4f430a",
00000987 => x"00203a46",
00000988 => x"454d490a",
00000989 => x"00203a4d",
00000990 => x"75410a0a",
00000991 => x"6f626f74",
00000992 => x"6920746f",
00000993 => x"7338206e",
00000994 => x"7250202e",
00000995 => x"20737365",
00000996 => x"2079656b",
00000997 => x"61206f74",
00000998 => x"74726f62",
00000999 => x"00000a2e",
00001000 => x"0000000a",
00001001 => x"726f6241",
00001002 => x"2e646574",
00001003 => x"00000a0a",
00001004 => x"444d430a",
00001005 => x"00203e3a",
00001006 => x"53207962",
00001007 => x"68706574",
00001008 => x"4e206e61",
00001009 => x"69746c6f",
00001010 => x"0000676e",
00001011 => x"61766e49",
00001012 => x"2064696c",
00001013 => x"00444d43",
00001014 => x"33323130",
00001015 => x"37363534",
00001016 => x"42413938",
00001017 => x"46454443",
00000990 => x"74796220",
00000991 => x"40207365",
00000992 => x"00000020",
00000993 => x"454d440a",
00000994 => x"00203a4d",
00000995 => x"75410a0a",
00000996 => x"6f626f74",
00000997 => x"6920746f",
00000998 => x"7338206e",
00000999 => x"7250202e",
00001000 => x"20737365",
00001001 => x"2079656b",
00001002 => x"61206f74",
00001003 => x"74726f62",
00001004 => x"00000a2e",
00001005 => x"0000000a",
00001006 => x"726f6241",
00001007 => x"2e646574",
00001008 => x"00000a0a",
00001009 => x"444d430a",
00001010 => x"00203e3a",
00001011 => x"53207962",
00001012 => x"68706574",
00001013 => x"4e206e61",
00001014 => x"69746c6f",
00001015 => x"0000676e",
00001016 => x"61766e49",
00001017 => x"2064696c",
00001018 => x"00444d43",
00001019 => x"33323130",
00001020 => x"37363534",
00001021 => x"42413938",
00001022 => x"46454443",
others => x"00000000"
);
 
/neorv32_cpu.vhd
52,8 → 52,8
generic (
-- General --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
60,41 → 60,43
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: External memory interface --
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
-- Bus Interface --
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
);
end neorv32_cpu;
 
166,10 → 168,12
-- csr interface --
csr_wdata_i => alu_res, -- CSR write data
csr_rdata_o => csr_rdata, -- CSR read data
-- external interrupt --
msw_irq_i => msw_irq_i, -- software interrupt
clic_irq_i => clic_irq_i, -- CLIC interrupt request
-- interrupts (risc-v compliant) --
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
-- fast interrupts (custom) --
firq_i => firq_i,
-- system time input from MTIME --
time_i => time_i, -- current system time
-- bus access exceptions --
272,7 → 276,7
neorv32_cpu_bus_inst: neorv32_cpu_bus
generic map (
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after which a valid bus access will timeout
)
port map (
-- global control --
/neorv32_cpu_bus.vhd
44,7 → 44,7
entity neorv32_cpu_bus is
generic (
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
113,7 → 113,7
wr_req : std_ulogic; -- write access in progress
err_align : std_ulogic; -- alignment error
err_bus : std_ulogic; -- bus access error
timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
end record;
signal i_arbiter, d_arbiter : bus_arbiter_t;
 
271,7 → 271,7
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
i_arbiter.err_align <= i_misaligned;
i_arbiter.err_bus <= '0';
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
else -- in progress
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
326,7 → 326,7
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
d_arbiter.err_align <= d_misaligned;
d_arbiter.err_bus <= '0';
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
else -- in progress
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
/neorv32_cpu_control.vhd
77,10 → 77,12
-- csr data interface --
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
-- external interrupt --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(3 downto 0);
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- bus access exceptions --
168,8 → 170,8
exc_ack : std_ulogic; -- acknowledge all exceptions
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
cause : std_ulogic_vector(4 downto 0); -- trap ID (for "mcause"), only for hw
cause_nxt : std_ulogic_vector(4 downto 0);
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw
cause_nxt : std_ulogic_vector(5 downto 0);
--
env_start : std_ulogic; -- start trap handler env
env_start_ack : std_ulogic; -- start of trap handler acknowledged
199,9 → 201,10
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
633,17 → 636,14
trap_ctrl.instr_ma <= ipb.rdata(33); -- misaligned instruction fetch address
trap_ctrl.instr_be <= ipb.rdata(34); -- bus access fault druing instrucion fetch
illegal_compressed <= ipb.rdata(35); -- invalid decompressed instruction
if (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34) or ipb.rdata(35)) = '1') then -- exception/interrupt?
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0);
execute_engine.pc_nxt <= ipb.raddr; -- the PC according to the current instruction
-- ipb.rdata(35) is not immediately checked here!
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34)) = '1') then
execute_engine.state_nxt <= TRAP;
else
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0);
execute_engine.pc_nxt <= ipb.raddr; -- the PC according to the current instruction
if (execute_engine.sleep = '1') then
execute_engine.state_nxt <= TRAP;
else
execute_engine.state_nxt <= EXECUTE;
end if;
execute_engine.state_nxt <= EXECUTE;
end if;
end if;
 
1074,10 → 1074,15
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
-- interrupt buffer: machine software/external/timer interrupt
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
-- interrupt buffer (RISC-V compliant): machine software/external/timer interrupt
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
-- interrupt buffer (custom): fast interrupts
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c));
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c));
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c));
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c));
 
-- trap control --
if (trap_ctrl.env_start = '0') then -- no started trap handler
1131,6 → 1136,27
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
 
 
-- interrupt: 1.16 fast interrupt channel 0 --
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq0_c;
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
 
-- interrupt: 1.17 fast interrupt channel 1 --
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq1_c;
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
 
-- interrupt: 1.18 fast interrupt channel 2 --
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq2_c;
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
 
-- interrupt: 1.19 fast interrupt channel 3 --
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq3_c;
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
 
 
-- the following traps are caused by synchronous exceptions
-- here we do not need a specific acknowledge mask since only one exception (the one
-- with highest priority) can trigger at once
1150,7 → 1176,7
 
-- trap/fault: 0.11 environment call from M-mode --
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
trap_ctrl.cause_nxt <= trap_env_c;
trap_ctrl.cause_nxt <= trap_menv_c;
 
-- trap/fault: 0.3 breakpoint --
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
1198,6 → 1224,7
csr.mie_msie <= '0';
csr.mie_meie <= '0';
csr.mie_mtie <= '0';
csr.mie_firqe <= (others => '0');
csr.mtvec <= (others => '0');
csr.mscratch <= (others => '0');
csr.mepc <= (others => '0');
1221,9 → 1248,14
csr.mstatus_mie <= csr_wdata_i(03);
csr.mstatus_mpie <= csr_wdata_i(07);
when x"4" => -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
csr.mie_msie <= csr_wdata_i(03); -- machine SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- machine TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- machine EXT IRQ enable
--
csr.mie_firqe(0) <= csr_wdata_i(16); -- fast interrupt channel 0
csr.mie_firqe(1) <= csr_wdata_i(17); -- fast interrupt channel 1
csr.mie_firqe(2) <= csr_wdata_i(18); -- fast interrupt channel 2
csr.mie_firqe(3) <= csr_wdata_i(19); -- fast interrupt channel 3
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when others =>
1237,8 → 1269,6
csr.mscratch <= csr_wdata_i;
when x"1" => -- R/W: mepc - machine exception program counter
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0';
when x"2" => -- R/W: mcause - machine trap cause
csr.mcause <= csr_wdata_i;
when x"3" => -- R/W: mtval - machine bad address or instruction
csr.mtval <= csr_wdata_i;
when others =>
1250,20 → 1280,20
-- automatic update by hardware --
else
 
-- machine exception PC & trap value register --
-- machine exception PC & machine trap value register --
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
csr.mcause <= trap_ctrl.cause(4) & "000" & x"000000" & trap_ctrl.cause(3 downto 0);
if (trap_ctrl.cause(4) = '1') then -- for INTERRUPTS only (is mcause(31))
csr.mcause <= trap_ctrl.cause(trap_ctrl.cause'left) & "000" & x"00000" & "000" & trap_ctrl.cause(4 downto 0);
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS only (is mcause(31))
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
else -- for EXCEPTIONS (according to their priority)
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
if (trap_ctrl.cause(3 downto 0) = trap_iba_c(3 downto 0)) or -- instr access error OR
(trap_ctrl.cause(3 downto 0) = trap_ima_c(3 downto 0)) or -- misaligned instruction OR
(trap_ctrl.cause(3 downto 0) = trap_brk_c(3 downto 0)) or -- breakpoint OR
(trap_ctrl.cause(3 downto 0) = trap_env_c(3 downto 0)) then -- env call OR
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instr access error OR
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction OR
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- env call OR
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
elsif (trap_ctrl.cause(3 downto 0) = trap_iil_c(3 downto 0)) then -- illegal instruction
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
else -- load/store misalignments/access errors
csr.mtval <= mar_i; -- faulting data access address
1307,13 → 1337,19
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
csr_rdata_o(23) <= '1'; -- X CPU extension (non-std extensions)
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
when x"304" => -- R/W: mie - machine interrupt-enable register
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
csr_rdata_o(03) <= csr.mie_msie; -- machine software IRQ enable
csr_rdata_o(07) <= csr.mie_mtie; -- machine timer IRQ enable
csr_rdata_o(11) <= csr.mie_meie; -- machine external IRQ enable
--
csr_rdata_o(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
csr_rdata_o(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
csr_rdata_o(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
csr_rdata_o(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
 
1322,7 → 1358,7
csr_rdata_o <= csr.mscratch;
when x"341" => -- R/W: mepc - machine exception program counter
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0';
when x"342" => -- R/W: mcause - machine trap cause
when x"342" => -- R/-: mcause - machine trap cause
csr_rdata_o <= csr.mcause;
when x"343" => -- R/W: mtval - machine bad address or instruction
csr_rdata_o <= csr.mtval;
1330,6 → 1366,11
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
--
csr_rdata_o(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c);
csr_rdata_o(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c);
csr_rdata_o(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c);
csr_rdata_o(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c);
 
-- counter and timers --
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020006"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030000"; -- no touchy!
 
-- Helper Functions -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
76,10 → 76,9
constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
 
-- Core-Local Interrupt Controller (CLIC) --
constant clic_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
constant clic_size_c : natural := 1*4; -- bytes, fixed!
constant clic_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(clic_base_c) + x"00000000");
-- RESERVED --
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
--constant ???_size_c : natural := 1*4; -- bytes, fixed!
 
-- Watch Dog Timer (WDT) --
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
317,18 → 316,25
 
-- Trap ID Codes --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt
-- risc-v compliant --
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode
--
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt
-- custom --
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3
 
-- CPU Control Exception System -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
342,12 → 348,18
constant exception_lalign_c : natural := 6; -- load address misaligned
constant exception_saccess_c : natural := 7; -- store access fault
constant exception_laccess_c : natural := 8; -- load access fault
--
constant exception_width_c : natural := 9; -- length of this list in bits
-- interrupt source bits --
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
constant interrupt_width_c : natural := 3; -- length of this list in bits
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
--
constant interrupt_width_c : natural := 7; -- length of this list in bits
 
-- Clock Generator -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
398,7 → 410,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
428,7 → 439,7
-- SPI --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI --
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
436,8 → 447,8
-- PWM --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- Interrupts --
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
end component;
 
447,8 → 458,8
generic (
-- General --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
455,41 → 466,43
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: External memory interface --
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
-- Bus Interface --
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
);
end component;
 
529,10 → 542,12
-- csr interface --
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
-- external interrupt --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(3 downto 0);
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- bus access exceptions --
620,7 → 635,7
component neorv32_cpu_bus
generic (
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
821,27 → 836,6
);
end component;
 
-- Component: Core Local Interrupt Controller (CLIC) --------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_clic
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- cpu interrupt --
cpu_irq_o : out std_ulogic; -- trigger CPU's external IRQ
-- external interrupt lines --
ext_irq_i : in std_ulogic_vector(07 downto 0); -- IRQ, triggering on HIGH level
ext_ack_o : out std_ulogic_vector(07 downto 0) -- acknowledge
);
end component;
 
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_wdt
1064,7 → 1058,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
/neorv32_sysinfo.vhd
69,7 → 69,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
125,6 → 124,7
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
sysinfo_mem(2)(15 downto 05) <= (others => '0'); -- reserved
-- IO
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
133,9 → 133,10
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
sysinfo_mem(2)(23) <= '0';
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
 
-- SYSINFO(3): reserved --
sysinfo_mem(3) <= (others => '0'); -- reserved - maybe for technology-specific configuration options?
/neorv32_top.vhd
80,7 → 80,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
110,16 → 109,16
-- SPI (available if IO_SPI_USE = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_USE = true) --
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
-- PWM (available if IO_PWM_USE = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- Interrupts (available if IO_CLIC_USE = true) --
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- Interrupts --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
end neorv32_top;
 
191,8 → 190,6
signal pwm_ack : std_ulogic;
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal wdt_ack : std_ulogic;
signal clic_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal clic_ack : std_ulogic;
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal trng_ack : std_ulogic;
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
202,9 → 199,7
 
-- IRQs --
signal mtime_irq : std_ulogic;
signal clic_irq : std_ulogic;
signal clic_xirq : std_ulogic_vector(7 downto 0);
signal clic_xack : std_ulogic_vector(7 downto 0);
signal fast_irq : std_ulogic_vector(3 downto 0);
signal gpio_irq : std_ulogic;
signal wdt_irq : std_ulogic;
signal uart_irq : std_ulogic;
256,10 → 251,6
if (CPU_EXTENSION_RISCV_Zicsr = false) then
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
end if;
-- core local interrupt controller --
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error;
end if;
 
-- memory layout notifier --
if (MEM_ISPACE_BASE /= x"00000000") then
339,8 → 330,8
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Memory configuration: External memory interface --
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
-- Bus Interface --
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
)
port map (
-- global control --
370,13 → 361,25
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
-- system time input from MTIME --
time_i => mtime_time, -- current system time
-- external interrupts --
msw_irq_i => '0', -- software interrupt
clic_irq_i => clic_irq, -- CLIC interrupt request
mtime_irq_i => mtime_irq -- machine timer interrupt
-- interrupts (risc-v compliant) --
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt request
mtime_irq_i => mtime_irq, -- machine timer interrupt
-- fast interrupts (custom) --
firq_i => fast_irq
);
 
-- advanced memory control --
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- fast interrupts --
fast_irq(0) <= wdt_irq; -- highest priority
fast_irq(1) <= gpio_irq;
fast_irq(2) <= uart_irq;
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI
 
 
-- CPU Crossbar Switch --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_busswitch_inst: neorv32_busswitch
420,19 → 423,15
p_bus_err_i => p_bus.err -- bus transfer error
);
 
-- advanced memory control --
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- process bus: CPU data input --
-- processor bus: CPU data input --
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
 
-- process bus: CPU data ACK input --
-- processor bus: CPU data ACK input --
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack);
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or devnull_ack or sysinfo_ack);
 
-- process bus: CPU data bus error input --
-- processor bus: CPU data bus error input --
p_bus.err <= wishbone_err;
 
 
615,52 → 614,6
end generate;
 
 
-- Core-Local Interrupt Controller (CLIC) -------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_clic_inst_true:
if (IO_CLIC_USE = true) generate
neorv32_clic_inst: neorv32_clic
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => clic_rdata, -- data out
ack_o => clic_ack, -- transfer acknowledge
-- cpu interrupt --
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
-- external interrupt lines --
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level
ext_ack_o => clic_xack -- acknowledge
);
end generate;
 
-- CLIC interrupt channels and priority --
clic_xirq(0) <= wdt_irq; -- highest priority
clic_xirq(1) <= '0'; -- reserved
clic_xirq(2) <= gpio_irq;
clic_xirq(3) <= uart_irq;
clic_xirq(4) <= spi_irq;
clic_xirq(5) <= twi_irq;
clic_xirq(6) <= ext_irq_i(0);
clic_xirq(7) <= ext_irq_i(1); -- lowest priority
 
-- external interrupt request acknowledge --
ext_ack_o(0) <= clic_xack(6);
ext_ack_o(1) <= clic_xack(7);
 
neorv32_clic_inst_false:
if (IO_CLIC_USE = false) generate
clic_rdata <= (others => '0');
clic_ack <= '0';
clic_irq <= '0';
clic_xack <= (others => '0');
end generate;
 
 
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_wdt_inst_true:
952,7 → 905,6
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
)

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