OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/neorv32_cfu.vhd File deleted
/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 665) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 668) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"99858593",
00000052 => x"9a458593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
242,7 → 242,7
00000231 => x"00112e23",
00000232 => x"01c00413",
00000233 => x"2ec000ef",
00000234 => x"a5448493",
00000234 => x"a6048493",
00000235 => x"ffc00993",
00000236 => x"008957b3",
00000237 => x"00f7f793",
280,13 → 280,13
00000269 => x"0400006f",
00000270 => x"00001737",
00000271 => x"00279793",
00000272 => x"9ac70713",
00000272 => x"9b870713",
00000273 => x"00e787b3",
00000274 => x"0007a783",
00000275 => x"00078067",
00000276 => x"00001737",
00000277 => x"00241793",
00000278 => x"9f070713",
00000278 => x"9fc70713",
00000279 => x"00e787b3",
00000280 => x"0007a783",
00000281 => x"00078067",
294,12 → 294,12
00000283 => x"82450513",
00000284 => x"220000ef",
00000285 => x"00001537",
00000286 => x"99c50513",
00000286 => x"9a850513",
00000287 => x"214000ef",
00000288 => x"34002573",
00000289 => x"ef5ff0ef",
00000290 => x"00001537",
00000291 => x"9a050513",
00000291 => x"9ac50513",
00000292 => x"200000ef",
00000293 => x"34302573",
00000294 => x"ee1ff0ef",
306,7 → 306,7
00000295 => x"00812403",
00000296 => x"00c12083",
00000297 => x"00001537",
00000298 => x"a4c50513",
00000298 => x"a5850513",
00000299 => x"01010113",
00000300 => x"1e00006f",
00000301 => x"00001537",
373,7 → 373,7
00000362 => x"301027f3",
00000363 => x"00079863",
00000364 => x"00001537",
00000365 => x"a2050513",
00000365 => x"a2c50513",
00000366 => x"0d8000ef",
00000367 => x"1e000793",
00000368 => x"30579073",
622,57 → 622,60
00000611 => x"00000000",
00000612 => x"6e6b6e55",
00000613 => x"206e776f",
00000614 => x"00000000",
00000615 => x"00204020",
00000616 => x"544d202c",
00000617 => x"3d4c4156",
00000618 => x"00000000",
00000619 => x"00000514",
00000620 => x"00000420",
00000621 => x"00000420",
00000622 => x"00000420",
00000623 => x"00000520",
00000614 => x"70617274",
00000615 => x"75616320",
00000616 => x"203a6573",
00000617 => x"00000000",
00000618 => x"00204020",
00000619 => x"544d202c",
00000620 => x"3d4c4156",
00000621 => x"00000000",
00000622 => x"00000514",
00000623 => x"00000420",
00000624 => x"00000420",
00000625 => x"00000420",
00000626 => x"00000420",
00000627 => x"0000052c",
00000626 => x"00000520",
00000627 => x"00000420",
00000628 => x"00000420",
00000629 => x"00000420",
00000630 => x"00000420",
00000630 => x"0000052c",
00000631 => x"00000420",
00000632 => x"00000538",
00000633 => x"00000544",
00000634 => x"00000550",
00000635 => x"0000055c",
00000636 => x"00000468",
00000637 => x"000004b4",
00000638 => x"000004c0",
00000639 => x"000004cc",
00000640 => x"000004d8",
00000641 => x"000004e4",
00000642 => x"000004f0",
00000643 => x"000004fc",
00000644 => x"00000420",
00000645 => x"00000420",
00000646 => x"00000420",
00000647 => x"00000508",
00000648 => x"4554523c",
00000649 => x"4157203e",
00000650 => x"4e494e52",
00000651 => x"43202147",
00000652 => x"43205550",
00000653 => x"73205253",
00000654 => x"65747379",
00000655 => x"6f6e206d",
00000656 => x"76612074",
00000657 => x"616c6961",
00000658 => x"21656c62",
00000659 => x"522f3c20",
00000660 => x"003e4554",
00000661 => x"33323130",
00000662 => x"37363534",
00000663 => x"42413938",
00000664 => x"46454443",
00000632 => x"00000420",
00000633 => x"00000420",
00000634 => x"00000420",
00000635 => x"00000538",
00000636 => x"00000544",
00000637 => x"00000550",
00000638 => x"0000055c",
00000639 => x"00000468",
00000640 => x"000004b4",
00000641 => x"000004c0",
00000642 => x"000004cc",
00000643 => x"000004d8",
00000644 => x"000004e4",
00000645 => x"000004f0",
00000646 => x"000004fc",
00000647 => x"00000420",
00000648 => x"00000420",
00000649 => x"00000420",
00000650 => x"00000508",
00000651 => x"4554523c",
00000652 => x"4157203e",
00000653 => x"4e494e52",
00000654 => x"43202147",
00000655 => x"43205550",
00000656 => x"73205253",
00000657 => x"65747379",
00000658 => x"6f6e206d",
00000659 => x"76612074",
00000660 => x"616c6961",
00000661 => x"21656c62",
00000662 => x"522f3c20",
00000663 => x"003e4554",
00000664 => x"33323130",
00000665 => x"37363534",
00000666 => x"42413938",
00000667 => x"46454443",
others => x"00000000"
);
 
/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1013) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1022) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"f4858593",
00000036 => x"f6c58593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
101,18 → 101,18
00000090 => x"00200513",
00000091 => x"0087f463",
00000092 => x"00400513",
00000093 => x"389000ef",
00000093 => x"3b5000ef",
00000094 => x"00005537",
00000095 => x"00000613",
00000096 => x"00000593",
00000097 => x"b0050513",
00000098 => x"271000ef",
00000099 => x"229000ef",
00000098 => x"291000ef",
00000099 => x"249000ef",
00000100 => x"00245793",
00000101 => x"00a78533",
00000102 => x"00f537b3",
00000103 => x"00b785b3",
00000104 => x"241000ef",
00000104 => x"261000ef",
00000105 => x"ffff07b7",
00000106 => x"49478793",
00000107 => x"30579073",
120,158 → 120,158
00000109 => x"30479073",
00000110 => x"30046073",
00000111 => x"00100513",
00000112 => x"3fd000ef",
00000112 => x"429000ef",
00000113 => x"ffff1537",
00000114 => x"800007b7",
00000115 => x"eec50513",
00000115 => x"f1450513",
00000116 => x"0007a023",
00000117 => x"2d1000ef",
00000118 => x"12d000ef",
00000117 => x"2fd000ef",
00000118 => x"14d000ef",
00000119 => x"ffff1537",
00000120 => x"f2450513",
00000121 => x"2c1000ef",
00000120 => x"f4c50513",
00000121 => x"2ed000ef",
00000122 => x"fe002503",
00000123 => x"238000ef",
00000124 => x"ffff1537",
00000125 => x"f2c50513",
00000126 => x"2ad000ef",
00000125 => x"f5450513",
00000126 => x"2d9000ef",
00000127 => x"fe402503",
00000128 => x"224000ef",
00000129 => x"ffff1537",
00000130 => x"f3850513",
00000131 => x"299000ef",
00000130 => x"f6050513",
00000131 => x"2c5000ef",
00000132 => x"30102573",
00000133 => x"210000ef",
00000134 => x"ffff1537",
00000135 => x"f4050513",
00000136 => x"285000ef",
00000135 => x"f6850513",
00000136 => x"2b1000ef",
00000137 => x"fe802503",
00000138 => x"ffff14b7",
00000139 => x"00341413",
00000140 => x"1f4000ef",
00000141 => x"ffff1537",
00000142 => x"f4850513",
00000143 => x"269000ef",
00000142 => x"f7050513",
00000143 => x"295000ef",
00000144 => x"ff802503",
00000145 => x"ffff1937",
00000146 => x"1dc000ef",
00000147 => x"f5048513",
00000148 => x"255000ef",
00000149 => x"ff002503",
00000150 => x"1cc000ef",
00000151 => x"ffff1537",
00000152 => x"f5c50513",
00000153 => x"241000ef",
00000154 => x"ffc02503",
00000155 => x"1b8000ef",
00000156 => x"f5048513",
00000157 => x"231000ef",
00000158 => x"ff402503",
00000159 => x"1a8000ef",
00000160 => x"ffff1537",
00000161 => x"f6450513",
00000162 => x"21d000ef",
00000163 => x"129000ef",
00000164 => x"00a404b3",
00000165 => x"0084b433",
00000166 => x"00b40433",
00000167 => x"fa402783",
00000168 => x"0607d263",
00000169 => x"ffff1537",
00000170 => x"f9050513",
00000171 => x"1f9000ef",
00000172 => x"ffff1937",
00000173 => x"0d4000ef",
00000174 => x"ffff19b7",
00000175 => x"07200a13",
00000176 => x"06800a93",
00000177 => x"07500b13",
00000178 => x"07300b93",
00000179 => x"ffff14b7",
00000180 => x"ffff1c37",
00000181 => x"f9c90513",
00000182 => x"1cd000ef",
00000183 => x"1b9000ef",
00000184 => x"00050413",
00000185 => x"1a1000ef",
00000186 => x"f8c98513",
00000187 => x"1b9000ef",
00000188 => x"03441e63",
00000189 => x"30047073",
00000190 => x"ffff02b7",
00000191 => x"00028067",
00000192 => x"0000006f",
00000193 => x"0b1000ef",
00000194 => x"f885eae3",
00000195 => x"00b41463",
00000196 => x"f89566e3",
00000197 => x"00100513",
00000198 => x"434000ef",
00000199 => x"f8c90513",
00000200 => x"185000ef",
00000201 => x"070000ef",
00000202 => x"f75ff06f",
00000203 => x"01541663",
00000204 => x"058000ef",
00000205 => x"fa1ff06f",
00000145 => x"1e0000ef",
00000146 => x"f7848513",
00000147 => x"285000ef",
00000148 => x"ff002503",
00000149 => x"1d0000ef",
00000150 => x"ffff1537",
00000151 => x"f8450513",
00000152 => x"271000ef",
00000153 => x"ffc02503",
00000154 => x"1bc000ef",
00000155 => x"f7848513",
00000156 => x"261000ef",
00000157 => x"ff402503",
00000158 => x"1ac000ef",
00000159 => x"ffff1537",
00000160 => x"f8c50513",
00000161 => x"24d000ef",
00000162 => x"14d000ef",
00000163 => x"00a404b3",
00000164 => x"0084b433",
00000165 => x"00b40433",
00000166 => x"fa402783",
00000167 => x"0207d263",
00000168 => x"ffff1537",
00000169 => x"fb450513",
00000170 => x"229000ef",
00000171 => x"219000ef",
00000172 => x"02300793",
00000173 => x"02f51263",
00000174 => x"00000513",
00000175 => x"0180006f",
00000176 => x"115000ef",
00000177 => x"fc85eae3",
00000178 => x"00b41463",
00000179 => x"fc9566e3",
00000180 => x"00100513",
00000181 => x"5a8000ef",
00000182 => x"0b4000ef",
00000183 => x"ffff1937",
00000184 => x"ffff19b7",
00000185 => x"02300a13",
00000186 => x"07200a93",
00000187 => x"06800b13",
00000188 => x"07500b93",
00000189 => x"ffff14b7",
00000190 => x"ffff1c37",
00000191 => x"fc090513",
00000192 => x"1d1000ef",
00000193 => x"1b1000ef",
00000194 => x"00050413",
00000195 => x"199000ef",
00000196 => x"ecc98513",
00000197 => x"1bd000ef",
00000198 => x"fb4400e3",
00000199 => x"01541863",
00000200 => x"ffff02b7",
00000201 => x"00028067",
00000202 => x"fd5ff06f",
00000203 => x"01641663",
00000204 => x"05c000ef",
00000205 => x"fc9ff06f",
00000206 => x"00000513",
00000207 => x"01640e63",
00000208 => x"01741663",
00000209 => x"644000ef",
00000210 => x"f8dff06f",
00000211 => x"06c00793",
00000212 => x"00f41863",
00000213 => x"00100513",
00000214 => x"3f4000ef",
00000215 => x"f79ff06f",
00000216 => x"06500793",
00000217 => x"00f41663",
00000218 => x"02c000ef",
00000219 => x"f69ff06f",
00000220 => x"03f00793",
00000221 => x"fa4c0513",
00000222 => x"00f40463",
00000223 => x"fb848513",
00000224 => x"125000ef",
00000225 => x"f51ff06f",
00000226 => x"ffff1537",
00000227 => x"dc450513",
00000228 => x"1150006f",
00000229 => x"800007b7",
00000230 => x"0007a783",
00000231 => x"00079863",
00000232 => x"ffff1537",
00000233 => x"e2850513",
00000234 => x"0fd0006f",
00000235 => x"ff010113",
00000236 => x"00112623",
00000237 => x"30047073",
00000238 => x"ffff1537",
00000239 => x"e4450513",
00000240 => x"0e5000ef",
00000241 => x"fa002783",
00000242 => x"fe07cee3",
00000243 => x"b0001073",
00000244 => x"b8001073",
00000245 => x"b0201073",
00000246 => x"b8201073",
00000247 => x"ff002783",
00000248 => x"00078067",
00000249 => x"0000006f",
00000250 => x"ff010113",
00000251 => x"00812423",
00000252 => x"00050413",
00000253 => x"ffff1537",
00000254 => x"e5450513",
00000255 => x"00112623",
00000256 => x"0a5000ef",
00000257 => x"03040513",
00000258 => x"0ff57513",
00000259 => x"079000ef",
00000260 => x"30047073",
00000261 => x"00100513",
00000262 => x"1a5000ef",
00000263 => x"10500073",
00000207 => x"03740063",
00000208 => x"07300793",
00000209 => x"00f41663",
00000210 => x"660000ef",
00000211 => x"fb1ff06f",
00000212 => x"06c00793",
00000213 => x"00f41863",
00000214 => x"00100513",
00000215 => x"3f0000ef",
00000216 => x"f9dff06f",
00000217 => x"06500793",
00000218 => x"00f41663",
00000219 => x"02c000ef",
00000220 => x"f8dff06f",
00000221 => x"03f00793",
00000222 => x"fc8c0513",
00000223 => x"00f40463",
00000224 => x"fdc48513",
00000225 => x"14d000ef",
00000226 => x"f75ff06f",
00000227 => x"ffff1537",
00000228 => x"df050513",
00000229 => x"13d0006f",
00000230 => x"800007b7",
00000231 => x"0007a783",
00000232 => x"00079863",
00000233 => x"ffff1537",
00000234 => x"e5450513",
00000235 => x"1250006f",
00000236 => x"ff010113",
00000237 => x"00112623",
00000238 => x"30047073",
00000239 => x"ffff1537",
00000240 => x"e7050513",
00000241 => x"10d000ef",
00000242 => x"fa002783",
00000243 => x"fe07cee3",
00000244 => x"b0001073",
00000245 => x"b8001073",
00000246 => x"b0201073",
00000247 => x"b8201073",
00000248 => x"ff002783",
00000249 => x"00078067",
00000250 => x"0000006f",
00000251 => x"ff010113",
00000252 => x"00812423",
00000253 => x"00050413",
00000254 => x"ffff1537",
00000255 => x"e8050513",
00000256 => x"00112623",
00000257 => x"0cd000ef",
00000258 => x"03040513",
00000259 => x"0ff57513",
00000260 => x"095000ef",
00000261 => x"30047073",
00000262 => x"00100513",
00000263 => x"1cd000ef",
00000264 => x"0000006f",
00000265 => x"fe010113",
00000266 => x"01212823",
278,14 → 278,14
00000267 => x"00050913",
00000268 => x"ffff1537",
00000269 => x"00912a23",
00000270 => x"e7450513",
00000270 => x"e9850513",
00000271 => x"ffff14b7",
00000272 => x"00812c23",
00000273 => x"01312623",
00000274 => x"00112e23",
00000275 => x"01c00413",
00000276 => x"055000ef",
00000277 => x"fc448493",
00000276 => x"081000ef",
00000277 => x"fe848493",
00000278 => x"ffc00993",
00000279 => x"008957b3",
00000280 => x"00f7f793",
292,7 → 292,7
00000281 => x"00f487b3",
00000282 => x"0007c503",
00000283 => x"ffc40413",
00000284 => x"015000ef",
00000284 => x"035000ef",
00000285 => x"ff3414e3",
00000286 => x"01c12083",
00000287 => x"01812403",
324,14 → 324,14
00000313 => x"00778793",
00000314 => x"06f41a63",
00000315 => x"00000513",
00000316 => x"0b1000ef",
00000317 => x"6c0000ef",
00000316 => x"0dd000ef",
00000317 => x"6e0000ef",
00000318 => x"fe002783",
00000319 => x"0027d793",
00000320 => x"00a78533",
00000321 => x"00f537b3",
00000322 => x"00b785b3",
00000323 => x"6d4000ef",
00000323 => x"6f4000ef",
00000324 => x"03c12403",
00000325 => x"04c12083",
00000326 => x"04812283",
355,29 → 355,29
00000344 => x"00100513",
00000345 => x"02f40863",
00000346 => x"ffff1537",
00000347 => x"e6050513",
00000348 => x"734000ef",
00000347 => x"e8c50513",
00000348 => x"760000ef",
00000349 => x"00040513",
00000350 => x"eadff0ef",
00000351 => x"ffff1537",
00000352 => x"e7050513",
00000353 => x"720000ef",
00000352 => x"e9450513",
00000353 => x"74c000ef",
00000354 => x"34102573",
00000355 => x"e99ff0ef",
00000356 => x"00500513",
00000357 => x"e55ff0ef",
00000357 => x"e59ff0ef",
00000358 => x"ff010113",
00000359 => x"00000513",
00000360 => x"00112623",
00000361 => x"00812423",
00000362 => x"7a0000ef",
00000362 => x"7cc000ef",
00000363 => x"00500513",
00000364 => x"7dc000ef",
00000364 => x"009000ef",
00000365 => x"00000513",
00000366 => x"7d4000ef",
00000366 => x"001000ef",
00000367 => x"00050413",
00000368 => x"00000513",
00000369 => x"7a4000ef",
00000369 => x"7d0000ef",
00000370 => x"00c12083",
00000371 => x"0ff47513",
00000372 => x"00812403",
387,14 → 387,14
00000376 => x"00000513",
00000377 => x"00112623",
00000378 => x"00812423",
00000379 => x"75c000ef",
00000379 => x"788000ef",
00000380 => x"09e00513",
00000381 => x"798000ef",
00000381 => x"7c4000ef",
00000382 => x"00000513",
00000383 => x"790000ef",
00000383 => x"7bc000ef",
00000384 => x"00050413",
00000385 => x"00000513",
00000386 => x"760000ef",
00000386 => x"78c000ef",
00000387 => x"00c12083",
00000388 => x"0ff47513",
00000389 => x"00812403",
403,13 → 403,13
00000392 => x"ff010113",
00000393 => x"00000513",
00000394 => x"00112623",
00000395 => x"71c000ef",
00000395 => x"748000ef",
00000396 => x"00600513",
00000397 => x"758000ef",
00000397 => x"784000ef",
00000398 => x"00c12083",
00000399 => x"00000513",
00000400 => x"01010113",
00000401 => x"7240006f",
00000401 => x"7500006f",
00000402 => x"ff010113",
00000403 => x"00812423",
00000404 => x"00050413",
416,30 → 416,30
00000405 => x"01055513",
00000406 => x"0ff57513",
00000407 => x"00112623",
00000408 => x"72c000ef",
00000408 => x"758000ef",
00000409 => x"00845513",
00000410 => x"0ff57513",
00000411 => x"720000ef",
00000411 => x"74c000ef",
00000412 => x"0ff47513",
00000413 => x"00812403",
00000414 => x"00c12083",
00000415 => x"01010113",
00000416 => x"70c0006f",
00000416 => x"7380006f",
00000417 => x"ff010113",
00000418 => x"00812423",
00000419 => x"00050413",
00000420 => x"00000513",
00000421 => x"00112623",
00000422 => x"6b0000ef",
00000422 => x"6dc000ef",
00000423 => x"00300513",
00000424 => x"6ec000ef",
00000424 => x"718000ef",
00000425 => x"00040513",
00000426 => x"fa1ff0ef",
00000427 => x"00000513",
00000428 => x"6dc000ef",
00000428 => x"708000ef",
00000429 => x"00050413",
00000430 => x"00000513",
00000431 => x"6ac000ef",
00000431 => x"6d8000ef",
00000432 => x"00c12083",
00000433 => x"0ff47513",
00000434 => x"00812403",
458,7 → 458,7
00000447 => x"00000413",
00000448 => x"00400a13",
00000449 => x"02091e63",
00000450 => x"58c000ef",
00000450 => x"5ac000ef",
00000451 => x"00a481a3",
00000452 => x"00140413",
00000453 => x"fff48493",
489,12 → 489,12
00000478 => x"00847413",
00000479 => x"00040663",
00000480 => x"00400513",
00000481 => x"c65ff0ef",
00000481 => x"c69ff0ef",
00000482 => x"00050493",
00000483 => x"02051863",
00000484 => x"ffff1537",
00000485 => x"e7850513",
00000486 => x"50c000ef",
00000485 => x"e9c50513",
00000486 => x"538000ef",
00000487 => x"008005b7",
00000488 => x"00048513",
00000489 => x"f31ff0ef",
504,8 → 504,8
00000493 => x"00000513",
00000494 => x"fcdff06f",
00000495 => x"ffff1537",
00000496 => x"e9850513",
00000497 => x"4e0000ef",
00000496 => x"ebc50513",
00000497 => x"50c000ef",
00000498 => x"e15ff0ef",
00000499 => x"fc0518e3",
00000500 => x"00300513",
529,8 → 529,8
00000518 => x"00200513",
00000519 => x"f60414e3",
00000520 => x"ffff1537",
00000521 => x"ea450513",
00000522 => x"47c000ef",
00000521 => x"ec850513",
00000522 => x"4a8000ef",
00000523 => x"02c12083",
00000524 => x"02812403",
00000525 => x"800007b7",
553,474 → 553,483
00000542 => x"f95ff06f",
00000543 => x"ff010113",
00000544 => x"00112623",
00000545 => x"00812423",
00000546 => x"00912223",
00000547 => x"00058413",
00000548 => x"00050493",
00000549 => x"d8dff0ef",
00000550 => x"00000513",
00000551 => x"4ac000ef",
00000552 => x"00200513",
00000553 => x"4e8000ef",
00000554 => x"00048513",
00000555 => x"d9dff0ef",
00000556 => x"00040513",
00000557 => x"4d8000ef",
00000545 => x"ec9ff0ef",
00000546 => x"ffff1537",
00000547 => x"ecc50513",
00000548 => x"440000ef",
00000549 => x"b05ff0ef",
00000550 => x"0000006f",
00000551 => x"ff010113",
00000552 => x"00112623",
00000553 => x"00812423",
00000554 => x"00912223",
00000555 => x"00058413",
00000556 => x"00050493",
00000557 => x"d6dff0ef",
00000558 => x"00000513",
00000559 => x"4ac000ef",
00000560 => x"cd9ff0ef",
00000561 => x"00157513",
00000562 => x"fe051ce3",
00000563 => x"00c12083",
00000564 => x"00812403",
00000565 => x"00412483",
00000566 => x"01010113",
00000567 => x"00008067",
00000568 => x"fe010113",
00000569 => x"00812c23",
00000570 => x"00912a23",
00000571 => x"01212823",
00000572 => x"00112e23",
00000573 => x"00b12623",
00000574 => x"00300413",
00000575 => x"00350493",
00000576 => x"fff00913",
00000577 => x"00c10793",
00000578 => x"008787b3",
00000579 => x"0007c583",
00000580 => x"40848533",
00000581 => x"fff40413",
00000582 => x"f65ff0ef",
00000583 => x"ff2414e3",
00000584 => x"01c12083",
00000585 => x"01812403",
00000586 => x"01412483",
00000587 => x"01012903",
00000588 => x"02010113",
00000589 => x"00008067",
00000590 => x"ff010113",
00000591 => x"00112623",
00000592 => x"00812423",
00000593 => x"00050413",
00000594 => x"cd9ff0ef",
00000595 => x"00000513",
00000596 => x"3f8000ef",
00000597 => x"0d800513",
00000598 => x"434000ef",
00000599 => x"00040513",
00000600 => x"ce9ff0ef",
00000601 => x"00000513",
00000602 => x"400000ef",
00000603 => x"c2dff0ef",
00000604 => x"00157513",
00000605 => x"fe051ce3",
00000606 => x"00c12083",
00000607 => x"00812403",
00000608 => x"01010113",
00000609 => x"00008067",
00000610 => x"fe010113",
00000611 => x"800007b7",
00000612 => x"00812c23",
00000613 => x"0007a403",
00000614 => x"00112e23",
00000615 => x"00912a23",
00000616 => x"01212823",
00000617 => x"01312623",
00000618 => x"01412423",
00000619 => x"01512223",
00000620 => x"02041863",
00000621 => x"ffff1537",
00000622 => x"e2850513",
00000623 => x"01812403",
00000624 => x"01c12083",
00000625 => x"01412483",
00000626 => x"01012903",
00000627 => x"00c12983",
00000628 => x"00812a03",
00000629 => x"00412a83",
00000630 => x"02010113",
00000631 => x"2c80006f",
00000632 => x"ffff1537",
00000633 => x"ea850513",
00000634 => x"2bc000ef",
00000635 => x"00040513",
00000636 => x"a35ff0ef",
00000637 => x"ffff1537",
00000638 => x"eb450513",
00000639 => x"2a8000ef",
00000640 => x"00800537",
00000641 => x"a21ff0ef",
00000642 => x"ffff1537",
00000643 => x"ed050513",
00000644 => x"294000ef",
00000645 => x"280000ef",
00000646 => x"00050493",
00000647 => x"268000ef",
00000648 => x"07900793",
00000649 => x"0af49e63",
00000650 => x"bb5ff0ef",
00000651 => x"00051663",
00000652 => x"00300513",
00000653 => x"9b5ff0ef",
00000654 => x"ffff1537",
00000655 => x"edc50513",
00000656 => x"01045493",
00000657 => x"260000ef",
00000658 => x"00148493",
00000659 => x"00800937",
00000660 => x"fff00993",
00000661 => x"00010a37",
00000662 => x"fff48493",
00000663 => x"07349063",
00000664 => x"4788d5b7",
00000665 => x"afe58593",
00000666 => x"00800537",
00000667 => x"e75ff0ef",
00000668 => x"00800537",
00000669 => x"00040593",
00000670 => x"00450513",
00000671 => x"e65ff0ef",
00000672 => x"ff002a03",
00000673 => x"008009b7",
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00000675 => x"00000493",
00000676 => x"00000913",
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00000678 => x"01548533",
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00000682 => x"412005b3",
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00000747 => x"0ff57513",
00000748 => x"f9dff06f",
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00000751 => x"f9002703",
00000752 => x"f9402683",
00000753 => x"fed79ae3",
00000754 => x"00e12023",
00000755 => x"00f12223",
00000756 => x"00012503",
00000757 => x"00412583",
00000758 => x"01010113",
00000759 => x"00008067",
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00000763 => x"00a6a023",
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00000766 => x"fa002023",
00000767 => x"fe002683",
00000768 => x"00151513",
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00000778 => x"01e61613",
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00000831 => x"00757513",
00000832 => x"00177793",
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00000838 => x"00e69793",
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00000840 => x"00f567b3",
00000841 => x"00d61613",
00000842 => x"00c7e7b3",
00000843 => x"00959593",
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00000847 => x"1007e793",
00000848 => x"00f82023",
00000849 => x"00008067",
00000850 => x"fa800713",
00000851 => x"00072683",
00000852 => x"00757793",
00000853 => x"00100513",
00000854 => x"00f51533",
00000855 => x"00d56533",
00000856 => x"00a72023",
00000857 => x"00008067",
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00000859 => x"00072683",
00000860 => x"00757513",
00000861 => x"00100793",
00000862 => x"00a797b3",
00000863 => x"fff7c793",
00000864 => x"00d7f7b3",
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00000866 => x"00008067",
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00000868 => x"fa802783",
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00000870 => x"fac02503",
00000871 => x"00008067",
00000872 => x"f8400713",
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00000875 => x"00a797b3",
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00000880 => x"00008067",
00000881 => x"69617641",
00000882 => x"6c62616c",
00000883 => x"4d432065",
00000884 => x"0a3a7344",
00000885 => x"203a6820",
00000886 => x"706c6548",
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00000893 => x"203a7320",
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00000904 => x"75636578",
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00000920 => x"58450a0a",
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/neorv32_cfu0.vhd
0,0 → 1,182
-- #################################################################################################
-- # << NEORV32 - Custom Function Unit 0 (CFU0) >> #
-- # ********************************************************************************************* #
-- # For tightly-coupled custom co-processors. Provides four memory mapped interface registers. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cfu0 is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
-- custom io --
-- ...
);
end neorv32_cfu0;
 
architecture neorv32_cfu0_rtl of neorv32_cfu0 is
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(cfu0_size_c); -- low address boundary bit
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
signal rd_en : std_ulogic; -- read enable
 
-- default CFU interface registers --
type cfu0_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0);
signal cfu0_reg_in : cfu0_regs_t; -- interface registers for WRITE
signal cfu0_reg_out : cfu0_regs_t; -- interface registers for READ
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- These assignments are required to check if the CFU is accessed at all.
-- Do NOT modify this for your custom application (unless you really know what you are doing).
 
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfu0_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= cfu0_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
 
 
-- Clock System ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- The processor top unit implements a clock generator providing 8 "derived clocks"
-- Actually, these signals must not be used as direct clock signals, but as clock enable signals.
 
-- The following clock divider rates are available:
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
 
-- For instance, if you want to drive a system at MAIN_CLK/8, you can use the following construct:
 
-- if (rstn_i = '0') then -- async and low-active reset
-- ...
-- elsif rising_edge(clk_i) then -- Always use the main clock for all clock processes!
-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
-- ...
-- end if;
-- end if;
 
-- The clkgen_i input clocks are available when at least one IO/peripheral device requires the clocks generated by the
-- clock generator. The CFU can enable the clock generator via the clkgen_en_o signal.
-- Make sure to deactivate clkgen_en_o if no clocks are required to reduce power consumption.
 
clkgen_en_o <= '0'; -- not used for this minimal example
 
 
-- Read/Write Access ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO
-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)
-- will trigger a store access fault exception.
--
-- All register of every unit are cleared during the processor boot sequence by the default crt0.S code.
-- Make cfu_reg0_addr_c the CFU's control register. This register is cleared first during booting.
-- If the control register is cleared, no actions should be taken when writing to other CFU registers.
--
-- The CFU provides 4 memory-mapped interface register. For instance, these could be used to provide
-- a <status register> for status information, a <data register< for reading/writing from/to a data FIFO, a <command register>
-- for issueing commands and a <control register> for global control of the unit.
--
rw_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- transfer ack --
ack_o <= wr_en or rd_en; -- required for the CPU to check the CFU is answering a bus read OR write request
 
-- write access --
if (wr_en = '1') then
case addr is
when cfu0_reg0_addr_c => cfu0_reg_in(0) <= data_i; -- for example: control register
when cfu0_reg1_addr_c => cfu0_reg_in(1) <= data_i; -- for example: data in/out fifo
when cfu0_reg2_addr_c => cfu0_reg_in(2) <= data_i; -- for example: command fifo
when cfu0_reg3_addr_c => cfu0_reg_in(3) <= data_i; -- for example: status register
when others => NULL;
end case;
end if;
 
-- read access --
data_o <= (others => '0'); -- make sure the output is zero if there is no actual read access
if (rd_en = '1') then
case addr is
when cfu0_reg0_addr_c => data_o <= cfu0_reg_out(0);
when cfu0_reg1_addr_c => data_o <= cfu0_reg_out(1);
when cfu0_reg2_addr_c => data_o <= cfu0_reg_out(2);
when cfu0_reg3_addr_c => data_o <= cfu0_reg_out(3);
when others => data_o <= (others => '0');
end case;
end if;
end if;
end process rw_access;
 
 
-- CFU Core -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- This is where the actual functionality can be implemented.
-- In this example we are just implementing 4 r/W registers.
 
cfu0_reg_out(0) <= cfu0_reg_in(0);
cfu0_reg_out(1) <= cfu0_reg_in(1);
cfu0_reg_out(2) <= cfu0_reg_in(2);
cfu0_reg_out(3) <= cfu0_reg_in(3);
 
 
end neorv32_cfu0_rtl;
/neorv32_cfu1.vhd
0,0 → 1,182
-- #################################################################################################
-- # << NEORV32 - Custom Function Unit 1 (CFU1) >> #
-- # ********************************************************************************************* #
-- # For tightly-coupled custom co-processors. Provides four memory mapped interface registers. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cfu1 is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
-- custom io --
-- ...
);
end neorv32_cfu1;
 
architecture neorv32_cfu1_rtl of neorv32_cfu1 is
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(cfu1_size_c); -- low address boundary bit
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
signal rd_en : std_ulogic; -- read enable
 
-- default CFU interface registers --
type cfu1_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0);
signal cfu1_reg_in : cfu1_regs_t; -- interface registers for WRITE
signal cfu1_reg_out : cfu1_regs_t; -- interface registers for READ
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- These assignments are required to check if the CFU is accessed at all.
-- Do NOT modify this for your custom application (unless you really know what you are doing).
 
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfu1_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= cfu1_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
 
 
-- Clock System ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- The processor top unit implements a clock generator providing 8 "derived clocks"
-- Actually, these signals must not be used as direct clock signals, but as clock enable signals.
 
-- The following clock divider rates are available:
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
 
-- For instance, if you want to drive a system at MAIN_CLK/8, you can use the following construct:
 
-- if (rstn_i = '0') then -- async and low-active reset
-- ...
-- elsif rising_edge(clk_i) then -- Always use the main clock for all clock processes!
-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
-- ...
-- end if;
-- end if;
 
-- The clkgen_i input clocks are available when at least one IO/peripheral device requires the clocks generated by the
-- clock generator. The CFU can enable the clock generator via the clkgen_en_o signal.
-- Make sure to deactivate clkgen_en_o if no clocks are required to reduce power consumption.
 
clkgen_en_o <= '0'; -- not used for this minimal example
 
 
-- Read/Write Access ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO
-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)
-- will trigger a store access fault exception.
--
-- All register of every unit are cleared during the processor boot sequence by the default crt0.S code.
-- Make cfu_reg0_addr_c the CFU's control register. This register is cleared first during booting.
-- If the control register is cleared, no actions should be taken when writing to other CFU registers.
--
-- The CFU provides 4 memory-mapped interface register. For instance, these could be used to provide
-- a <status register> for status information, a <data register< for reading/writing from/to a data FIFO, a <command register>
-- for issueing commands and a <control register> for global control of the unit.
--
rw_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- transfer ack --
ack_o <= wr_en or rd_en; -- required for the CPU to check the CFU is answering a bus read OR write request
 
-- write access --
if (wr_en = '1') then
case addr is
when cfu1_reg0_addr_c => cfu1_reg_in(0) <= data_i; -- for example: control register
when cfu1_reg1_addr_c => cfu1_reg_in(1) <= data_i; -- for example: data in/out fifo
when cfu1_reg2_addr_c => cfu1_reg_in(2) <= data_i; -- for example: command fifo
when cfu1_reg3_addr_c => cfu1_reg_in(3) <= data_i; -- for example: status register
when others => NULL;
end case;
end if;
 
-- read access --
data_o <= (others => '0'); -- make sure the output is zero if there is no actual read access
if (rd_en = '1') then
case addr is
when cfu1_reg0_addr_c => data_o <= cfu1_reg_out(0);
when cfu1_reg1_addr_c => data_o <= cfu1_reg_out(1);
when cfu1_reg2_addr_c => data_o <= cfu1_reg_out(2);
when cfu1_reg3_addr_c => data_o <= cfu1_reg_out(3);
when others => data_o <= (others => '0');
end case;
end if;
end if;
end process rw_access;
 
 
-- CFU Core -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- This is where the actual functionality can be implemented.
-- In this example we are just implementing 4 r/W registers.
 
cfu1_reg_out(0) <= cfu1_reg_in(0);
cfu1_reg_out(1) <= cfu1_reg_in(1);
cfu1_reg_out(2) <= cfu1_reg_in(2);
cfu1_reg_out(3) <= cfu1_reg_in(3);
 
 
end neorv32_cfu1_rtl;
/neorv32_cpu.vhd
64,6 → 64,7
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
243,7 → 244,8
-- -------------------------------------------------------------------------------------------
neorv32_cpu_alu_inst: neorv32_cpu_alu
generic map (
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
)
port map (
-- global control --
/neorv32_cpu_alu.vhd
44,7 → 44,8
 
entity neorv32_cpu_alu is
generic (
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
);
port (
-- global control --
88,13 → 89,16
 
-- shifter --
type shifter_t is record
cmd : std_ulogic;
cmd_ff : std_ulogic;
start : std_ulogic;
run : std_ulogic;
halt : std_ulogic;
cnt : std_ulogic_vector(4 downto 0);
sreg : std_ulogic_vector(data_width_c-1 downto 0);
cmd : std_ulogic;
cmd_ff : std_ulogic;
start : std_ulogic;
run : std_ulogic;
halt : std_ulogic;
cnt : std_ulogic_vector(4 downto 0);
sreg : std_ulogic_vector(data_width_c-1 downto 0);
-- for barrel shifter only --
bs_a_in : std_ulogic_vector(4 downto 0);
bs_d_in : std_ulogic_vector(data_width_c-1 downto 0);
end record;
signal shifter : shifter_t;
 
158,40 → 162,117
end process binary_arithmetic_core;
 
 
-- Iterative Shifter Unit -----------------------------------------------------------------
-- Shifter Unit ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shifter_unit: process(rstn_i, clk_i)
variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
begin
if (rstn_i = '0') then
shifter.sreg <= (others => '0');
shifter.cnt <= (others => '0');
shifter.cmd_ff <= '0';
if (FAST_SHIFT_EN = true) then
shifter.bs_d_in <= (others => '0');
shifter.bs_a_in <= (others => '0');
end if;
elsif rising_edge(clk_i) then
shifter.cmd_ff <= shifter.cmd;
if (shifter.start = '1') then -- trigger new shift
shifter.sreg <= opa; -- shift operand
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
elsif (shifter.run = '1') then -- running shift
-- coarse shift: multiples of 4 --
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
 
-- --------------------------------------------------------------------------------
-- Iterative shifter (small but slow) (default)
-- --------------------------------------------------------------------------------
if (FAST_SHIFT_EN = false) then
 
if (shifter.start = '1') then -- trigger new shift
shifter.sreg <= opa; -- shift operand
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
elsif (shifter.run = '1') then -- running shift
-- coarse shift: multiples of 4 --
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
end if;
-- fine shift: single shifts, 0..3 times --
else
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
end if;
end if;
-- fine shift: single shifts, 0..3 times --
end if;
 
-- --------------------------------------------------------------------------------
-- Barrel shifter (huge but fast)
-- --------------------------------------------------------------------------------
else
 
-- operands and cycle control --
if (shifter.start = '1') then -- trigger new shift
shifter.bs_d_in <= opa; -- shift data
shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
shifter.cnt <= (others => '0');
end if;
 
-- convert left shifts to right shifts --
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
bs_input_v := bit_rev_f(shifter.bs_d_in); -- reverse bit order of input operand
else
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
end if;
bs_input_v := shifter.bs_d_in;
end if;
-- shift >> 16 --
if (shifter.bs_a_in(4) = '1') then
bs_level_4_v(31 downto 16) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
bs_level_4_v(15 downto 00) := (bs_input_v(31 downto 16));
else
bs_level_4_v := bs_input_v;
end if;
-- shift >> 8 --
if (shifter.bs_a_in(3) = '1') then
bs_level_3_v(31 downto 24) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
bs_level_3_v(23 downto 00) := (bs_level_4_v(31 downto 8));
else
bs_level_3_v := bs_level_4_v;
end if;
-- shift >> 4 --
if (shifter.bs_a_in(2) = '1') then
bs_level_2_v(31 downto 28) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
bs_level_2_v(27 downto 00) := (bs_level_3_v(31 downto 4));
else
bs_level_2_v := bs_level_3_v;
end if;
-- shift >> 2 --
if (shifter.bs_a_in(1) = '1') then
bs_level_1_v(31 downto 30) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
bs_level_1_v(29 downto 00) := (bs_level_2_v(31 downto 2));
else
bs_level_1_v := bs_level_2_v;
end if;
-- shift >> 1 --
if (shifter.bs_a_in(0) = '1') then
bs_level_0_v(31 downto 31) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
bs_level_0_v(30 downto 00) := (bs_level_1_v(31 downto 1));
else
bs_level_0_v := bs_level_1_v;
end if;
-- re-convert original left shifts --
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then
shifter.sreg <= bit_rev_f(bs_level_0_v);
else
shifter.sreg <= bs_level_0_v;
end if;
end if;
end if;
end process shifter_unit;
/neorv32_cpu_control.vhd
131,6 → 131,7
--
w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
match : std_ulogic;
empty : std_ulogic;
full : std_ulogic;
--
392,9 → 393,9
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0))));
 
-- status --
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
 
ipb.match <= '1' when (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
ipb.free <= not ipb.full;
ipb.avail <= not ipb.empty;
 
550,7 → 551,7
instruction_buffer_data: process(clk_i)
begin
if rising_edge(clk_i) then
if (i_buf.we = '1') and (ipb.clear = '0') then
if (i_buf.we = '1') and (i_buf.clear = '0') then
i_buf.rdata <= i_buf.wdata;
end if;
end if;
597,7 → 598,7
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
imm_o(00) <= '0';
when opcode_syscsr_c => -- CSR-immediate
when opcode_syscsr_c => -- CSR-immediate (uimm5)
imm_o(31 downto 05) <= (others => '0');
imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);
when others => -- I-immediate
799,13 → 800,14
 
when TRAP => -- Start trap environment (also used as cpu sleep state)
-- ------------------------------------------------------------
fetch_engine.reset <= '1';
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
if (trap_ctrl.env_start = '1') then -- check here again if we came directly from DISPATCH
trap_ctrl.env_start_ack <= '1';
execute_engine.pc_nxt <= csr.mtvec;
execute_engine.sleep_nxt <= '0'; -- waky waky
execute_engine.state_nxt <= SYS_WAIT;
-- stay here for sleep
if (trap_ctrl.env_start = '1') then -- trap triggered?
fetch_engine.reset <= '1';
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
trap_ctrl.env_start_ack <= '1';
execute_engine.pc_nxt <= csr.mtvec;
execute_engine.sleep_nxt <= '0'; -- waky waky
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
when EXECUTE => -- Decode and execute instruction
1482,6 → 1484,13
csr.mtval <= (others => '0');
csr.pmpcfg <= (others => (others => '0'));
csr.pmpaddr <= (others => (others => '0'));
--
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
elsif rising_edge(clk_i) then
 
-- write access? --
1660,10 → 1669,63
end if;
end if;
 
-- --------------------------------------------------------------------------------
-- Counter CSRs
-- --------------------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zicsr = true) then
 
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
csr.mcycle(31 downto 0) <= csr.wdata;
csr.mcycle(32) <= '0';
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
end if;
 
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
 
-- minstret (instret) --
minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
csr.minstret(31 downto 0) <= csr.wdata;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
 
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
end if;
end if;
end process csr_write_access;
 
-- CPU's current privilege level --
priv_mode_o <= csr.privilege;
 
-- PMP output --
pmp_output: process(csr)
begin
pmp_addr_o <= (others => (others => '0'));
pmp_ctrl_o <= (others => (others => '0'));
if (PMP_USE = true) then
for i in 0 to PMP_NUM_REGIONS-1 loop
pmp_addr_o(i) <= csr.pmpaddr(i) & "00";
pmp_ctrl_o(i) <= csr.pmpcfg(i);
end loop; -- i
end if;
end process pmp_output;
 
 
-- Control and Status Registers Read Access -----------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_read_access: process(clk_i)
1842,8 → 1904,8
-- machine information registers --
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
csr.rdata <= (others => '0');
when csr_marchid_c => -- R/-: marchid - architecture ID
csr.rdata(4 downto 0) <= "10011"; -- official open-source arch ID
when csr_marchid_c => -- R/-: marchid - arch ID
csr.rdata(4 downto 0) <= "10011"; -- official RISC-V open-source arch ID
when csr_mimpid_c => -- R/-: mimpid - implementation ID
csr.rdata <= hw_version_c; -- NEORV32 hardware version
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
1867,69 → 1929,5
-- CSR read data output --
csr_rdata_o <= csr.rdata;
 
-- CPU's current privilege level --
priv_mode_o <= csr.privilege;
 
-- PMP output --
pmp_output: process(csr)
begin
pmp_addr_o <= (others => (others => '0'));
pmp_ctrl_o <= (others => (others => '0'));
if (PMP_USE = true) then
for i in 0 to PMP_NUM_REGIONS-1 loop
pmp_addr_o(i) <= csr.pmpaddr(i) & "00";
pmp_ctrl_o(i) <= csr.pmpcfg(i);
end loop; -- i
end if;
end process pmp_output;
 
 
-- RISC-V Counter CSRs --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_counters: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
elsif rising_edge(clk_i) then
 
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
csr.mcycle(31 downto 0) <= csr.wdata;
csr.mcycle(32) <= '0';
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
end if;
 
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
 
-- minstret (instret) --
minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
csr.minstret(31 downto 0) <= csr.wdata;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
 
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
end if;
end process csr_counters;
 
 
end neorv32_cpu_control_rtl;
/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040502"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040509"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
 
74,14 → 74,11
 
-- Processor-Internal Address Space Layout ------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Internal Instruction Memory (IMEM) --
constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
--> size is configured via top's generic
-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
--> sizea are configured via top's generic
 
-- Internal Data Memory (DMEM) --
constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
--> size is configured via top's generic
 
-- Internal Bootloader ROM --
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
constant boot_rom_size_c : natural := 4*1024; -- bytes
140,17 → 137,21
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
 
-- RESERVED --
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
--constant ???_size_c : natural := 4*4; -- bytes
-- Custom Functions Unit 0 (CFU0) --
constant cfu0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
constant cfu0_size_c : natural := 4*4; -- bytes
constant cfu0_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
constant cfu0_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
constant cfu0_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
constant cfu0_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
 
-- Custom Functions Unit (CFU) --
constant cfu_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
constant cfu_size_c : natural := 4*4; -- bytes
constant cfu_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
constant cfu_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
constant cfu_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
constant cfu_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
-- Custom Functions Unit 1 (CFU1) --
constant cfu1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
constant cfu1_size_c : natural := 4*4; -- bytes
constant cfu1_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
constant cfu1_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
constant cfu1_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
constant cfu1_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
 
-- System Information Memory (SYSINFO) --
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
455,15 → 456,16
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
479,44 → 481,46
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
);
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- Wishbone bus interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO --
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
-- SPI --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI --
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
-- PWM --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- Interrupts --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
end component;
 
536,6 → 540,7
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
664,7 → 669,8
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_alu
generic (
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
);
port (
-- global control --
1095,9 → 1101,9
);
end component;
 
-- Component: Custom Functions Unit (CFU) -------------------------------------------------
-- Component: Custom Functions Unit 0 (CFU0) ----------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cfu
component neorv32_cfu0
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
1110,14 → 1116,33
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
-- interrupt --
irq_o : out std_ulogic
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
-- custom io --
-- ...
);
end component;
 
-- Component: Custom Functions Unit 1 (CFU1) ----------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cfu1
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
-- custom io --
-- ...
);
end component;
 
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_sysinfo
1144,7 → 1169,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU_USE : boolean := true -- implement custom functions unit (CFU)?
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)?
);
port (
-- host access --
/neorv32_sysinfo.vhd
66,7 → 66,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU_USE : boolean := true -- implement custom functions unit (CFU)?
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)?
);
port (
-- host access --
130,10 → 131,11
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- watch dog timer (WDT) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFU_USE); -- custom functions unit (CFU) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFU0_USE); -- custom functions unit 0 (CFU0) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- true random number generator (TRNG) implemented?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_USE); -- custom functions unit 1 (CFU1) implemented?
--
sysinfo_mem(2)(31 downto 25) <= (others => '0'); -- reserved
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
 
-- SYSINFO(3): reserved --
sysinfo_mem(3) <= (others => '0'); -- reserved
/neorv32_top.vhd
60,6 → 60,7
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
83,44 → 84,46
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
);
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO (available if IO_GPIO_USE = true) --
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_USE = true) --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
-- SPI (available if IO_SPI_USE = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_USE = true) --
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
-- PWM (available if IO_PWM_USE = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- Interrupts --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
end neorv32_top;
 
151,7 → 154,8
signal spi_cg_en : std_ulogic;
signal twi_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
signal cfu_cg_en : std_ulogic;
signal cfu0_cg_en : std_ulogic;
signal cfu1_cg_en : std_ulogic;
 
-- bus interface --
type bus_interface_t is record
199,8 → 203,10
signal wdt_ack : std_ulogic;
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal trng_ack : std_ulogic;
signal cfu_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal cfu_ack : std_ulogic;
signal cfu0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal cfu0_ack : std_ulogic;
signal cfu1_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal cfu1_ack : std_ulogic;
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal sysinfo_ack : std_ulogic;
 
212,7 → 218,6
signal uart_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal cfu_irq : std_ulogic;
 
-- misc --
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
279,7 → 284,7
clk_div_ff <= (others => '0');
elsif rising_edge(clk_i) then
-- fresh clocks anyone? --
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfu_cg_en) = '1') then
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfu0_cg_en or cfu1_cg_en) = '1') then
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
end if;
clk_div_ff <= clk_div;
318,6 → 323,7
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => PMP_USE, -- implement PMP?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (max 8)
364,9 → 370,9
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- fast interrupts --
fast_irq(0) <= wdt_irq; -- highest priority
fast_irq(1) <= gpio_irq or cfu_irq; -- can be triggered by GPIO pin-change or CFU
fast_irq(2) <= uart_irq;
fast_irq(0) <= wdt_irq; -- highest priority, watchdog timeout interrupt
fast_irq(1) <= gpio_irq; -- GPIO input pin-change interrupt
fast_irq(2) <= uart_irq; -- UART TX done or RX complete interrupt
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI
 
 
415,11 → 421,11
 
-- processor bus: CPU data input --
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfu_rdata or sysinfo_rdata);
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfu0_rdata or cfu1_rdata or sysinfo_rdata);
 
-- processor bus: CPU data ACK input --
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfu_ack or sysinfo_ack);
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfu0_ack or cfu1_ack or sysinfo_ack);
 
-- processor bus: CPU data bus error input --
p_bus.err <= wishbone_err;
666,7 → 672,7
mtime_rdata <= (others => '0');
mtime_time <= (others => '0');
mtime_ack <= '0';
mtime_irq <= '0';
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
end generate;
 
 
835,11 → 841,11
end generate;
 
 
-- Custom Functions Unit (CFU) ------------------------------------------------------------
-- Custom Functions Unit 0 (CFU0) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cfu_inst_true:
if (IO_CFU_USE = true) generate
neorv32_cfu_inst: neorv32_cfu
neorv32_cfu0_inst_true:
if (IO_CFU0_USE = true) generate
neorv32_cfu0_inst: neorv32_cfu0
port map (
-- host access --
clk_i => clk_i, -- global clock line
848,27 → 854,55
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => cfu_rdata, -- data out
ack_o => cfu_ack, -- transfer acknowledge
data_o => cfu0_rdata, -- data out
ack_o => cfu0_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => cfu_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- "clock" inputs
-- interrupt --
irq_o => cfu_irq
clkgen_en_o => cfu0_cg_en, -- enable clock generator
clkgen_i => clk_gen -- "clock" inputs
-- custom io --
-- ...
);
end generate;
 
neorv32_cfu_inst_false:
if (IO_CFU_USE = false) generate
cfu_rdata <= (others => '0');
cfu_ack <= '0';
cfu_cg_en <= '0';
cfu_irq <= '0';
neorv32_cfu0_inst_false:
if (IO_CFU0_USE = false) generate
cfu0_rdata <= (others => '0');
cfu0_ack <= '0';
cfu0_cg_en <= '0';
end generate;
 
 
-- Custom Functions Unit 1 (CFU1) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cfu1_inst_true:
if (IO_CFU1_USE = true) generate
neorv32_cfu1_inst: neorv32_cfu1
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active, use as async
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => cfu1_rdata, -- data out
ack_o => cfu1_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => cfu1_cg_en, -- enable clock generator
clkgen_i => clk_gen -- "clock" inputs
-- custom io --
-- ...
);
end generate;
 
neorv32_cfu1_inst_false:
if (IO_CFU1_USE = false) generate
cfu1_rdata <= (others => '0');
cfu1_ack <= '0';
cfu1_cg_en <= '0';
end generate;
 
 
-- System Configuration Information Memory (SYSINFO) --------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_sysinfo_inst: neorv32_sysinfo
895,7 → 929,8
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_CFU_USE => IO_CFU_USE -- implement custom functions unit (CFU)?
IO_CFU0_USE => IO_CFU0_USE, -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE => IO_CFU1_USE -- implement custom functions unit 1 (CFU1)?
)
port map (
-- host access --

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