OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /neorv32/trunk/rtl/core
    from Rev 42 to Rev 44
    Reverse comparison

Rev 42 → Rev 44

/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin>
 
library ieee;
use ieee.std_logic_1164.all;
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 807) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 4082) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
35,786 → 35,4061
00000024 => x"00000e93",
00000025 => x"00000f13",
00000026 => x"00000f93",
00000027 => x"00002537",
00000028 => x"80050513",
00000029 => x"30051073",
00000030 => x"30401073",
00000031 => x"80002117",
00000032 => x"f8010113",
00000033 => x"ffc17113",
00000034 => x"00010413",
00000035 => x"80000197",
00000036 => x"77418193",
00000037 => x"00000597",
00000038 => x"0a458593",
00000039 => x"30559073",
00000040 => x"f8000593",
00000041 => x"0005a023",
00000042 => x"00458593",
00000043 => x"feb01ce3",
00000044 => x"80000597",
00000045 => x"f5058593",
00000046 => x"84418613",
00000047 => x"00c5d863",
00000048 => x"00058023",
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"bd058593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
00000056 => x"f2468693",
00000057 => x"00d65c63",
00000058 => x"00058703",
00000059 => x"00e60023",
00000060 => x"00158593",
00000061 => x"00160613",
00000062 => x"fedff06f",
00000063 => x"00000513",
00000064 => x"00000593",
00000065 => x"b0001073",
00000066 => x"b8001073",
00000067 => x"b0201073",
00000068 => x"b8201073",
00000069 => x"3063d073",
00000070 => x"32001073",
00000071 => x"80000637",
00000072 => x"34261073",
00000073 => x"060000ef",
00000074 => x"30047073",
00000075 => x"00000013",
00000076 => x"10500073",
00000077 => x"0000006f",
00000078 => x"ff810113",
00000079 => x"00812023",
00000080 => x"00912223",
00000081 => x"34202473",
00000082 => x"02044663",
00000083 => x"34102473",
00000084 => x"00041483",
00000085 => x"0034f493",
00000086 => x"00240413",
00000087 => x"34141073",
00000088 => x"00300413",
00000089 => x"00941863",
00000090 => x"34102473",
00000091 => x"00240413",
00000092 => x"34141073",
00000093 => x"00012483",
00000094 => x"00412403",
00000095 => x"00810113",
00000096 => x"30200073",
00000097 => x"00005537",
00000098 => x"ff010113",
00000099 => x"00000693",
00000100 => x"00000613",
00000101 => x"00000593",
00000102 => x"b0050513",
00000103 => x"00112623",
00000104 => x"4a4000ef",
00000105 => x"5a0000ef",
00000106 => x"00050c63",
00000107 => x"43c000ef",
00000108 => x"00001537",
00000109 => x"98450513",
00000110 => x"534000ef",
00000111 => x"020000ef",
00000112 => x"00001537",
00000113 => x"96050513",
00000114 => x"524000ef",
00000115 => x"00c12083",
00000116 => x"00000513",
00000117 => x"01010113",
00000118 => x"00008067",
00000119 => x"ff010113",
00000120 => x"00000513",
00000121 => x"00812423",
00000122 => x"00112623",
00000123 => x"00000413",
00000124 => x"564000ef",
00000125 => x"0ff47513",
00000126 => x"55c000ef",
00000127 => x"0c800513",
00000128 => x"588000ef",
00000129 => x"00140413",
00000130 => x"fedff06f",
00000131 => x"00000000",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
00000135 => x"02612a23",
00000136 => x"02712823",
00000137 => x"02a12623",
00000138 => x"02b12423",
00000139 => x"02c12223",
00000140 => x"02d12023",
00000141 => x"00e12e23",
00000142 => x"00f12c23",
00000143 => x"01012a23",
00000144 => x"01112823",
00000145 => x"01c12623",
00000146 => x"01d12423",
00000147 => x"01e12223",
00000148 => x"01f12023",
00000149 => x"34102773",
00000150 => x"34071073",
00000151 => x"342027f3",
00000152 => x"0807c863",
00000153 => x"00071683",
00000154 => x"00300593",
00000155 => x"0036f693",
00000156 => x"00270613",
00000157 => x"00b69463",
00000158 => x"00470613",
00000159 => x"34161073",
00000160 => x"00b00713",
00000161 => x"04f77a63",
00000162 => x"42c00793",
00000163 => x"000780e7",
00000164 => x"03c12083",
00000165 => x"03812283",
00000166 => x"03412303",
00000167 => x"03012383",
00000168 => x"02c12503",
00000169 => x"02812583",
00000170 => x"02412603",
00000171 => x"02012683",
00000172 => x"01c12703",
00000173 => x"01812783",
00000174 => x"01412803",
00000175 => x"01012883",
00000176 => x"00c12e03",
00000177 => x"00812e83",
00000178 => x"00412f03",
00000179 => x"00012f83",
00000180 => x"04010113",
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"9a070713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
00000188 => x"80000737",
00000189 => x"ffd74713",
00000190 => x"00e787b3",
00000191 => x"01000713",
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"9d070713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
00000199 => x"800007b7",
00000200 => x"0007a783",
00000201 => x"f69ff06f",
00000202 => x"800007b7",
00000203 => x"0047a783",
00000204 => x"f5dff06f",
00000205 => x"800007b7",
00000206 => x"0087a783",
00000207 => x"f51ff06f",
00000208 => x"800007b7",
00000209 => x"00c7a783",
00000210 => x"f45ff06f",
00000211 => x"8101a783",
00000212 => x"f3dff06f",
00000213 => x"8141a783",
00000214 => x"f35ff06f",
00000215 => x"8181a783",
00000216 => x"f2dff06f",
00000217 => x"81c1a783",
00000218 => x"f25ff06f",
00000219 => x"8201a783",
00000220 => x"f1dff06f",
00000221 => x"8241a783",
00000222 => x"f15ff06f",
00000223 => x"8281a783",
00000224 => x"f0dff06f",
00000225 => x"82c1a783",
00000226 => x"f05ff06f",
00000227 => x"8301a783",
00000228 => x"efdff06f",
00000229 => x"8341a783",
00000230 => x"ef5ff06f",
00000231 => x"8381a783",
00000232 => x"eedff06f",
00000233 => x"83c1a783",
00000234 => x"ee5ff06f",
00000235 => x"8401a783",
00000236 => x"eddff06f",
00000237 => x"00000000",
00000238 => x"00000000",
00000239 => x"fe010113",
00000240 => x"01212823",
00000241 => x"00050913",
00000242 => x"00001537",
00000243 => x"00912a23",
00000244 => x"a1450513",
00000245 => x"000014b7",
00000246 => x"00812c23",
00000247 => x"01312623",
00000248 => x"00112e23",
00000249 => x"01c00413",
00000250 => x"304000ef",
00000251 => x"c8c48493",
00000252 => x"ffc00993",
00000253 => x"008957b3",
00000254 => x"00f7f793",
00000255 => x"00f487b3",
00000256 => x"0007c503",
00000257 => x"ffc40413",
00000258 => x"2d4000ef",
00000259 => x"ff3414e3",
00000260 => x"01c12083",
00000261 => x"01812403",
00000262 => x"01412483",
00000263 => x"01012903",
00000264 => x"00c12983",
00000265 => x"02010113",
00000266 => x"00008067",
00000267 => x"00001537",
00000268 => x"ff010113",
00000269 => x"a1850513",
00000270 => x"00112623",
00000271 => x"00812423",
00000272 => x"2ac000ef",
00000273 => x"34202473",
00000274 => x"00b00793",
00000275 => x"0487f463",
00000276 => x"800007b7",
00000277 => x"ffd7c793",
00000278 => x"00f407b3",
00000279 => x"01000713",
00000280 => x"00f77e63",
00000281 => x"00001537",
00000282 => x"bb850513",
00000283 => x"280000ef",
00000284 => x"00040513",
00000285 => x"f49ff0ef",
00000286 => x"0400006f",
00000287 => x"00001737",
00000288 => x"00279793",
00000289 => x"be470713",
00000290 => x"00e787b3",
00000291 => x"0007a783",
00000292 => x"00078067",
00000293 => x"00001737",
00000294 => x"00241793",
00000295 => x"c2870713",
00000296 => x"00e787b3",
00000297 => x"0007a783",
00000298 => x"00078067",
00000299 => x"00001537",
00000300 => x"a2050513",
00000301 => x"238000ef",
00000302 => x"00001537",
00000303 => x"bd050513",
00000304 => x"22c000ef",
00000305 => x"34002573",
00000306 => x"ef5ff0ef",
00000307 => x"00001537",
00000308 => x"bd850513",
00000309 => x"218000ef",
00000310 => x"34302573",
00000311 => x"ee1ff0ef",
00000312 => x"00812403",
00000313 => x"00c12083",
00000314 => x"00001537",
00000315 => x"c8450513",
00000316 => x"01010113",
00000317 => x"1f80006f",
00000318 => x"00001537",
00000319 => x"a4050513",
00000320 => x"fb5ff06f",
00000321 => x"00001537",
00000322 => x"a5c50513",
00000323 => x"fa9ff06f",
00000324 => x"00001537",
00000325 => x"a7050513",
00000326 => x"f9dff06f",
00000327 => x"00001537",
00000328 => x"a7c50513",
00000329 => x"f91ff06f",
00000330 => x"00001537",
00000331 => x"a9450513",
00000332 => x"f85ff06f",
00000333 => x"00001537",
00000334 => x"aa850513",
00000335 => x"f79ff06f",
00000336 => x"00001537",
00000337 => x"ac450513",
00000338 => x"f6dff06f",
00000339 => x"00001537",
00000340 => x"ad850513",
00000341 => x"f61ff06f",
00000342 => x"00001537",
00000343 => x"af850513",
00000344 => x"f55ff06f",
00000345 => x"00001537",
00000346 => x"b1850513",
00000347 => x"f49ff06f",
00000348 => x"00001537",
00000349 => x"b3450513",
00000350 => x"f3dff06f",
00000351 => x"00001537",
00000352 => x"b4c50513",
00000353 => x"f31ff06f",
00000354 => x"00001537",
00000355 => x"b6850513",
00000356 => x"f25ff06f",
00000357 => x"00001537",
00000358 => x"b7c50513",
00000359 => x"f19ff06f",
00000360 => x"00001537",
00000361 => x"b9050513",
00000362 => x"f0dff06f",
00000363 => x"00001537",
00000364 => x"ba450513",
00000365 => x"f01ff06f",
00000366 => x"01000793",
00000367 => x"02a7e263",
00000368 => x"800007b7",
00000369 => x"00078793",
00000370 => x"00251513",
00000371 => x"00a78533",
00000372 => x"42c00793",
00000373 => x"00f52023",
00000374 => x"00000513",
00000375 => x"00008067",
00000376 => x"00100513",
00000377 => x"00008067",
00000378 => x"ff010113",
00000379 => x"00112623",
00000380 => x"00812423",
00000381 => x"00912223",
00000382 => x"301027f3",
00000383 => x"00079863",
00000384 => x"00001537",
00000385 => x"c5850513",
00000386 => x"0e4000ef",
00000387 => x"21000793",
00000388 => x"30579073",
00000389 => x"00000413",
00000390 => x"01100493",
00000391 => x"00040513",
00000392 => x"00140413",
00000393 => x"0ff47413",
00000394 => x"f91ff0ef",
00000395 => x"fe9418e3",
00000396 => x"00c12083",
00000397 => x"00812403",
00000398 => x"00412483",
00000399 => x"01010113",
00000400 => x"00008067",
00000401 => x"fa002023",
00000402 => x"fe002803",
00000403 => x"00151513",
00000404 => x"00000713",
00000405 => x"04a87863",
00000406 => x"00001537",
00000407 => x"00000793",
00000408 => x"ffe50513",
00000409 => x"04e56a63",
00000410 => x"0016f693",
00000411 => x"00167613",
00000412 => x"01879793",
00000413 => x"01e69693",
00000414 => x"0035f593",
00000415 => x"00d7e7b3",
00000416 => x"01d61613",
00000417 => x"00c7e7b3",
00000418 => x"01659593",
00000419 => x"00b7e7b3",
00000420 => x"00e7e7b3",
00000421 => x"10000737",
00000422 => x"00e7e7b3",
00000423 => x"faf02023",
00000424 => x"00008067",
00000425 => x"00170793",
00000426 => x"01079713",
00000427 => x"40a80833",
00000428 => x"01075713",
00000429 => x"fa1ff06f",
00000430 => x"ffe78813",
00000431 => x"0fd87813",
00000432 => x"00081a63",
00000433 => x"00375713",
00000434 => x"00178793",
00000435 => x"0ff7f793",
00000436 => x"f95ff06f",
00000437 => x"00175713",
00000438 => x"ff1ff06f",
00000439 => x"fa002783",
00000440 => x"fe07cee3",
00000441 => x"faa02223",
00000442 => x"00008067",
00000443 => x"ff010113",
00000444 => x"00812423",
00000445 => x"01212023",
00000446 => x"00112623",
00000447 => x"00912223",
00000448 => x"00050413",
00000449 => x"00a00913",
00000450 => x"00044483",
00000451 => x"00140413",
00000452 => x"00049e63",
00000453 => x"00c12083",
00000454 => x"00812403",
00000455 => x"00412483",
00000456 => x"00012903",
00000457 => x"01010113",
00000458 => x"00008067",
00000459 => x"01249663",
00000460 => x"00d00513",
00000461 => x"fa9ff0ef",
00000462 => x"00048513",
00000463 => x"fa1ff0ef",
00000464 => x"fc9ff06f",
00000465 => x"fe802503",
00000466 => x"01055513",
00000467 => x"00157513",
00000468 => x"00008067",
00000469 => x"f8a02223",
00000470 => x"00008067",
00000471 => x"ff010113",
00000472 => x"c80026f3",
00000473 => x"c0002773",
00000474 => x"c80027f3",
00000475 => x"fed79ae3",
00000476 => x"00e12023",
00000477 => x"00f12223",
00000478 => x"00012503",
00000479 => x"00412583",
00000480 => x"01010113",
00000481 => x"00008067",
00000482 => x"fe010113",
00000483 => x"00112e23",
00000484 => x"00812c23",
00000485 => x"00912a23",
00000486 => x"00a12623",
00000487 => x"fc1ff0ef",
00000488 => x"00050493",
00000489 => x"fe002503",
00000490 => x"00058413",
00000491 => x"3e800593",
00000492 => x"104000ef",
00000493 => x"00c12603",
00000494 => x"00000693",
00000495 => x"00000593",
00000496 => x"05c000ef",
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00000500 => x"00850433",
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00000507 => x"01412483",
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00000525 => x"00050693",
00000526 => x"00000713",
00000527 => x"00000793",
00000528 => x"00000813",
00000529 => x"0016fe13",
00000530 => x"00171e93",
00000531 => x"000e0c63",
00000532 => x"01060e33",
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00000547 => x"00088593",
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00000688 => x"00000000",
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00003748 => x"7361204d",
00003749 => x"4d4f5220",
00003750 => x"0000203a",
00003751 => x"61746144",
00003752 => x"73616220",
00003753 => x"64612065",
00003754 => x"73657264",
00003755 => x"20203a73",
00003756 => x"78302020",
00003757 => x"000a7825",
00003758 => x"65746e49",
00003759 => x"6c616e72",
00003760 => x"454d4420",
00003761 => x"20203a4d",
00003762 => x"20202020",
00003763 => x"00002020",
00003764 => x"4d454d44",
00003765 => x"7a697320",
00003766 => x"20203a65",
00003767 => x"20202020",
00003768 => x"20202020",
00003769 => x"75252020",
00003770 => x"74796220",
00003771 => x"000a7365",
00003772 => x"65746e49",
00003773 => x"6c616e72",
00003774 => x"632d6920",
00003775 => x"65686361",
00003776 => x"2020203a",
00003777 => x"00002020",
00003778 => x"0000202d",
00003779 => x"62207525",
00003780 => x"73657479",
00003781 => x"75252820",
00003782 => x"74657320",
00003783 => x"2c297328",
00003784 => x"20752520",
00003785 => x"636f6c62",
00003786 => x"2973286b",
00003787 => x"72657020",
00003788 => x"74657320",
00003789 => x"7525202c",
00003790 => x"74796220",
00003791 => x"70207365",
00003792 => x"62207265",
00003793 => x"6b636f6c",
00003794 => x"00202c29",
00003795 => x"772d7525",
00003796 => x"73207961",
00003797 => x"612d7465",
00003798 => x"636f7373",
00003799 => x"69746169",
00003800 => x"000a6576",
00003801 => x"6c6c7566",
00003802 => x"73612d79",
00003803 => x"69636f73",
00003804 => x"76697461",
00003805 => x"00000a65",
00003806 => x"746f6f42",
00003807 => x"64616f6c",
00003808 => x"203a7265",
00003809 => x"20202020",
00003810 => x"20202020",
00003811 => x"00002020",
00003812 => x"2e747845",
00003813 => x"73756220",
00003814 => x"746e6920",
00003815 => x"61667265",
00003816 => x"203a6563",
00003817 => x"00002020",
00003818 => x"2e747845",
00003819 => x"73756220",
00003820 => x"646e4520",
00003821 => x"6e6e6169",
00003822 => x"3a737365",
00003823 => x"00002020",
00003824 => x"2d2d0a0a",
00003825 => x"50202d2d",
00003826 => x"65636f72",
00003827 => x"726f7373",
00003828 => x"50202d20",
00003829 => x"70697265",
00003830 => x"61726568",
00003831 => x"2d20736c",
00003832 => x"0a2d2d2d",
00003833 => x"00000000",
00003834 => x"4f495047",
00003835 => x"202d2020",
00003836 => x"00000000",
00003837 => x"4d49544d",
00003838 => x"202d2045",
00003839 => x"00000000",
00003840 => x"54524155",
00003841 => x"202d2020",
00003842 => x"00000000",
00003843 => x"20495053",
00003844 => x"202d2020",
00003845 => x"00000000",
00003846 => x"20495754",
00003847 => x"202d2020",
00003848 => x"00000000",
00003849 => x"204d5750",
00003850 => x"202d2020",
00003851 => x"00000000",
00003852 => x"20544457",
00003853 => x"202d2020",
00003854 => x"00000000",
00003855 => x"474e5254",
00003856 => x"202d2020",
00003857 => x"00000000",
00003858 => x"30554643",
00003859 => x"202d2020",
00003860 => x"00000000",
00003861 => x"31554643",
00003862 => x"202d2020",
00003863 => x"00000000",
00003864 => x"20656854",
00003865 => x"524f454e",
00003866 => x"20323356",
00003867 => x"636f7250",
00003868 => x"6f737365",
00003869 => x"72502072",
00003870 => x"63656a6f",
00003871 => x"6f430a74",
00003872 => x"69727970",
00003873 => x"20746867",
00003874 => x"31323032",
00003875 => x"7453202c",
00003876 => x"61687065",
00003877 => x"6f4e206e",
00003878 => x"6e69746c",
00003879 => x"53420a67",
00003880 => x"2d332044",
00003881 => x"75616c43",
00003882 => x"4c206573",
00003883 => x"6e656369",
00003884 => x"680a6573",
00003885 => x"73707474",
00003886 => x"672f2f3a",
00003887 => x"75687469",
00003888 => x"6f632e62",
00003889 => x"74732f6d",
00003890 => x"746c6f6e",
00003891 => x"2f676e69",
00003892 => x"726f656e",
00003893 => x"0a323376",
00003894 => x"0000000a",
00003895 => x"5241570a",
00003896 => x"474e494e",
00003897 => x"57532021",
00003898 => x"4153495f",
00003899 => x"65662820",
00003900 => x"72757461",
00003901 => x"72207365",
00003902 => x"69757165",
00003903 => x"29646572",
00003904 => x"20737620",
00003905 => x"495f5748",
00003906 => x"28204153",
00003907 => x"74616566",
00003908 => x"73657275",
00003909 => x"61766120",
00003910 => x"62616c69",
00003911 => x"2029656c",
00003912 => x"6d73696d",
00003913 => x"68637461",
00003914 => x"57530a21",
00003915 => x"4153495f",
00003916 => x"30203d20",
00003917 => x"20782578",
00003918 => x"6d6f6328",
00003919 => x"656c6970",
00003920 => x"6c662072",
00003921 => x"29736761",
00003922 => x"5f57480a",
00003923 => x"20415349",
00003924 => x"7830203d",
00003925 => x"28207825",
00003926 => x"6173696d",
00003927 => x"72736320",
00003928 => x"000a0a29",
00003929 => x"00000000",
00003930 => x"00000000",
00003931 => x"00000180",
00003932 => x"00000000",
00003933 => x"00000000",
00003934 => x"00000000",
00003935 => x"00000180",
00003936 => x"318c0000",
00003937 => x"60c7fc7f",
00003938 => x"87f8c0c7",
00003939 => x"f87f8180",
00003940 => x"ffff0000",
00003941 => x"f0cc00c0",
00003942 => x"cc0cc0cc",
00003943 => x"0cc0c183",
00003944 => x"c003c000",
00003945 => x"d8cc00c0",
00003946 => x"cc0cc0c0",
00003947 => x"0c018180",
00003948 => x"c7e30000",
00003949 => x"cccff8c0",
00003950 => x"cff8c0c0",
00003951 => x"f8060183",
00003952 => x"c7e3c000",
00003953 => x"c6cc00c0",
00003954 => x"cc306180",
00003955 => x"0c180180",
00003956 => x"c7e30000",
00003957 => x"c3cc00c0",
00003958 => x"cc18330c",
00003959 => x"0c600183",
00003960 => x"c003c000",
00003961 => x"c187fc7f",
00003962 => x"8c0c0c07",
00003963 => x"f8ffc180",
00003964 => x"ffff0000",
00003965 => x"00000000",
00003966 => x"00000000",
00003967 => x"00000180",
00003968 => x"318c0000",
00003969 => x"00000000",
00003970 => x"00000000",
00003971 => x"00000180",
00003972 => x"00000000",
00003973 => x"33323130",
00003974 => x"37363534",
00003975 => x"42413938",
00003976 => x"46454443",
00003977 => x"33323130",
00003978 => x"37363534",
00003979 => x"00003938",
00003980 => x"33323130",
00003981 => x"37363534",
00003982 => x"62613938",
00003983 => x"66656463",
00003984 => x"00000000",
00003985 => x"000020f8",
00003986 => x"00002104",
00003987 => x"00002110",
00003988 => x"0000211c",
00003989 => x"00002128",
00003990 => x"00002134",
00003991 => x"00002140",
00003992 => x"0000214c",
00003993 => x"00002158",
00003994 => x"00002164",
00003995 => x"00002170",
00003996 => x"0000217c",
00003997 => x"00002188",
00003998 => x"00002194",
00003999 => x"000021a0",
00004000 => x"000021b4",
00004001 => x"000021bc",
00004002 => x"000021c4",
00004003 => x"000021cc",
00004004 => x"000021d4",
00004005 => x"000021dc",
00004006 => x"000021e4",
00004007 => x"000021ec",
00004008 => x"000021f4",
00004009 => x"000021fc",
00004010 => x"00002204",
00004011 => x"0000220c",
00004012 => x"00002214",
00004013 => x"0000221c",
00004014 => x"00002224",
00004015 => x"0000222c",
00004016 => x"0000224c",
00004017 => x"00002254",
00004018 => x"0000225c",
00004019 => x"00002264",
00004020 => x"0000226c",
00004021 => x"00002274",
00004022 => x"0000227c",
00004023 => x"00002284",
00004024 => x"0000228c",
00004025 => x"00002294",
00004026 => x"0000229c",
00004027 => x"000022a4",
00004028 => x"000022ac",
00004029 => x"000022b4",
00004030 => x"000022bc",
00004031 => x"000022c4",
00004032 => x"000022cc",
00004033 => x"000022d4",
00004034 => x"000022dc",
00004035 => x"000022e4",
00004036 => x"000022ec",
00004037 => x"000022f4",
00004038 => x"000022fc",
00004039 => x"00002304",
00004040 => x"0000230c",
00004041 => x"00002314",
00004042 => x"0000231c",
00004043 => x"00002324",
00004044 => x"0000232c",
00004045 => x"00002334",
00004046 => x"0000233c",
00004047 => x"00002344",
00004048 => x"0000234c",
00004049 => x"00002354",
00004050 => x"0000235c",
00004051 => x"00002364",
00004052 => x"0000236c",
00004053 => x"00002374",
00004054 => x"0000237c",
00004055 => x"00002384",
00004056 => x"0000238c",
00004057 => x"00002394",
00004058 => x"0000239c",
00004059 => x"000023a4",
00004060 => x"000023ac",
00004061 => x"000023b4",
00004062 => x"000023bc",
00004063 => x"000023d4",
00004064 => x"000023e0",
00004065 => x"000023ec",
00004066 => x"000023f8",
00004067 => x"00002404",
00004068 => x"00002410",
00004069 => x"0000241c",
00004070 => x"00002428",
00004071 => x"00002434",
00004072 => x"00002440",
00004073 => x"0000244c",
00004074 => x"00002458",
00004075 => x"00002464",
00004076 => x"00002470",
00004077 => x"0000247c",
00004078 => x"3407d073",
00004079 => x"00008067",
00004080 => x"00000001",
00004081 => x"00008067",
others => x"00000000"
);
 
/neorv32_bootloader_image.vhd
948,9 → 948,9
00000937 => x"3e3e2072",
00000938 => x"4c420a0a",
00000939 => x"203a5644",
00000940 => x"20636544",
00000941 => x"32203932",
00000942 => x"0a303230",
00000940 => x"206e614a",
00000941 => x"32203131",
00000942 => x"0a313230",
00000943 => x"3a565748",
00000944 => x"00002020",
00000945 => x"4b4c430a",
/neorv32_cpu.vhd
9,7 → 9,6
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
-- # * neorv32_cpu_regfile.vhd - Data register file #
-- # #
-- # * neorv32_package.vhd - Main CPU/processor package file #
-- # #
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
60,6 → 59,7
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
124,7 → 124,6
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_opb : std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand b
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
161,8 → 160,6
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- PMP requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- HPM CNT requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Performance monitors (HMP) require CPU_EXTENSION_RISCV_Zicsr extension." severity error;
 
-- Bus timeout --
assert not (BUS_TIMEOUT < 2) report "NEORV32 CPU CONFIG ERROR! Invalid bus access timeout value <BUS_TIMEOUT>. Has to be >= 2." severity error;
172,6 → 169,9
-- A extension - only lr.w and sc.w supported yet --
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports >lr.w< and >sc.w< instructions yet." severity warning;
 
-- Bit manipulation notifier --
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) only supports 'base' instruction sub-set (Zbb) yet and is still 'unofficial' (not-ratified)." severity warning;
 
-- PMP regions check --
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
-- PMP granulartiy --
184,6 → 184,8
assert not (HPM_NUM_CNTS > 29) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
-- HPM counters notifier --
assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters." severity note;
-- HPM CNT requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Performance monitors (HMP) require CPU_EXTENSION_RISCV_Zicsr extension." severity error;
 
 
-- Control Unit ---------------------------------------------------------------------------
195,6 → 197,7
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
289,7 → 292,6
cmp_o => alu_cmp, -- comparator status
res_o => alu_res, -- ALU result
add_o => alu_add, -- address computation result
opb_o => alu_opb, -- ALU operand B
-- co-processor interface --
cp0_start_o => cp0_start, -- trigger co-processor 0
cp0_data_i => cp0_data, -- co-processor 0 result
338,7 → 340,7
end generate;
 
 
-- Co-Processor 1: Atomic Memory Access (SC - store-conditional) --------------------------
-- Co-Processor 1: Atomic Memory Access, SC - store-conditional ('M' extension) -----------
-- -------------------------------------------------------------------------------------------
atomic_op_cp: process(cp1_start, ctrl)
begin
362,16 → 364,36
 
-- Co-Processor 2: Not implemented (yet) --------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- control: ctrl cp2_start
-- inputs: rs1 rs2 alu_cmp alu_opb
cp2_data <= (others => '0');
cp2_valid <= cp2_start; -- to make sure CPU does not get stalled if there is an accidental access
neorv32_cpu_cp_bitmanip_inst_true:
if (CPU_EXTENSION_RISCV_B = true) generate
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
start_i => cp2_start, -- trigger operation
-- data input --
cmp_i => alu_cmp, -- comparator status
rs1_i => rs1, -- rf source 1
rs2_i => rs2, -- rf source 2
-- result and status --
res_o => cp2_data, -- operation result
valid_o => cp2_valid -- data output valid
);
end generate;
 
neorv32_cpu_cp_bitmanip_inst_false:
if (CPU_EXTENSION_RISCV_B = false) generate
cp2_data <= (others => '0');
cp2_valid <= cp2_start; -- to make sure CPU does not get stalled if there is an accidental access
end generate;
 
 
-- Co-Processor 3: Not implemented (yet) --------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- control: ctrl cp3_start
-- inputs: rs1 rs2 alu_cmp alu_opb
-- inputs: rs1 rs2 alu_cmp
cp3_data <= (others => '0');
cp3_valid <= cp3_start; -- to make sure CPU does not get stalled if there is an accidental access
 
/neorv32_cpu_alu.vhd
5,7 → 5,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
60,7 → 60,6
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B
-- co-processor interface --
cp0_start_o : out std_ulogic; -- trigger co-processor 0
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
127,8 → 126,6
-- -------------------------------------------------------------------------------------------
opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
--
opb_o <= opb;
 
 
-- Comparator Unit ------------------------------------------------------------------------
/neorv32_cpu_control.vhd
4,7 → 4,8
-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
-- # handling controller and the RISC-V status and control register set (CSRs). #
-- # handling controller and the RISC-V status and control register set (CSRs) including the #
-- # hardware performance monitor counters. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
51,6 → 52,7
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
165,6 → 167,17
end record;
signal cmd_issue : cmd_issue_t;
 
-- instruction decoding helper logic --
type decode_aux_t is record
alu_immediate : std_ulogic;
rs1_is_r0 : std_ulogic;
is_atomic_lr : std_ulogic;
is_atomic_sc : std_ulogic;
is_bitmanip_imm : std_ulogic;
is_bitmanip_reg : std_ulogic;
end record;
signal decode_aux : decode_aux_t;
 
-- instruction execution engine --
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
type execute_engine_t is record
721,6 → 734,7
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
-- instruction's function blocks (for co-processors) --
ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c);
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
-- locked bus operation (for atomica memory operations) --
728,15 → 742,68
end process ctrl_output;
 
 
-- Decoding Helper Logic ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
decode_helper: process(execute_engine)
begin
-- defaults --
decode_aux.alu_immediate <= '0';
decode_aux.rs1_is_r0 <= '0';
decode_aux.is_atomic_lr <= '0';
decode_aux.is_atomic_sc <= '0';
decode_aux.is_bitmanip_imm <= '0';
decode_aux.is_bitmanip_reg <= '0';
 
-- is immediate ALU operation? --
decode_aux.alu_immediate <= not execute_engine.i_reg(instr_opcode_msb_c-1);
 
-- is rs1 == r0? --
decode_aux.rs1_is_r0 <= not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
 
-- is atomic load-reservate/store-conditional? --
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
end if;
 
-- is BITMANIP.Zbb instruction? --
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
-- immediate operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
(
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- PCNT
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
)
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0000111")) or -- GORCI.b 7 (orc.b)
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0011000")) then -- GREVI.-8 (rev8)
decode_aux.is_bitmanip_imm <= '1';
end if;
-- register operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- PACK
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
(
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
)
) then
decode_aux.is_bitmanip_reg <= '1';
end if;
end process decode_helper;
 
 
-- Execute Engine FSM Comb ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
execute_engine_fsm_comb: process(execute_engine, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid,
execute_engine_fsm_comb: process(execute_engine, decode_aux, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid,
alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
variable alu_immediate_v : std_ulogic;
variable rs1_is_r0_v : std_ulogic;
variable opcode_v : std_ulogic_vector(6 downto 0);
variable is_atomic_lr_v : std_ulogic;
variable is_atomic_sc_v : std_ulogic;
variable opcode_v : std_ulogic_vector(6 downto 0);
begin
-- arbiter defaults --
execute_engine.state_nxt <= execute_engine.state;
790,30 → 857,15
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
 
-- is immediate ALU operation? --
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
 
-- is rs1 == r0? --
rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
 
-- is atomic load-reservate/store-conditional? --
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
is_atomic_lr_v := not execute_engine.i_reg(instr_funct5_lsb_c);
is_atomic_sc_v := execute_engine.i_reg(instr_funct5_lsb_c);
else
is_atomic_lr_v := '0';
is_atomic_sc_v := '0';
end if;
 
 
-- state machine --
case execute_engine.state is
 
when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) ((and to init r0 with zero if it is a physical register))
when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) [and to init r0 with zero if it is a physical register]
-- ------------------------------------------------------------
-- set reg_file's r0 to zero --
if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read)
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR-read)
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0
end if;
--
865,7 → 917,7
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
ctrl_nxt(ctrl_alu_opb_mux_c) <= decode_aux.alu_immediate; -- use IMM as ALU.OPB for immediate operations
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
 
-- ALU arithmetic operation type and ADD/SUB --
877,7 → 929,7
end if;
 
-- ADD/SUB --
if ((alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
if ((decode_aux.alu_immediate = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
892,12 → 944,19
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
end case;
 
-- co-processor (cp) access? --
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- just in case a mul/div operation
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op?
-- co-processor MULDIV operation? --
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV CP op?
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
-- ALU operation - function select --
-- co-processor bit manipulation operation? --
elsif (CPU_EXTENSION_RISCV_B = true) and
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
-- ALU operation, function select --
else
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.func operation (re-coding)
910,7 → 969,10
-- multi cycle alu operation? --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV CP op?
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) or -- MULDIV CP op?
((CPU_EXTENSION_RISCV_B = true) and (
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- BITMANIP CP register operation?
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) ) then -- BITMANIP CP immediate operation?
execute_engine.state_nxt <= ALU_WAIT;
else -- single cycle ALU operation
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1012,7 → 1074,7
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
csr.we_nxt <= (not decode_aux.rs1_is_r0) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
when others => -- invalid
csr.we_nxt <= '0';
end case;
1026,7 → 1088,7
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
-- cp access or alu shift? --
-- cp access or alu.shift? --
if (execute_engine.is_cp_op = '1') then
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
else
1077,7 → 1139,7
 
when LOADSTORE_0 => -- trigger memory request
-- ------------------------------------------------------------
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') then -- normal load or atomic load-reservate
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
else -- store
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
1100,7 → 1162,7
end if;
-- register file write-back --
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM
if (is_atomic_sc_v = '1') then
if (decode_aux.is_atomic_sc = '1') then
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res (only relevant for atomic.SC)
else
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
1110,10 → 1172,10
-- wait for memory response --
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
atomic_ctrl.env_abort <= '1'; -- LOCKED (atomic) memory access environment failed (forces SC result to be non-zero => failure)
ctrl_nxt(ctrl_rf_wb_en_c) <= is_atomic_sc_v; -- SC failes: allow write back of non-zero result
ctrl_nxt(ctrl_rf_wb_en_c) <= decode_aux.is_atomic_sc; -- SC failes: allow write back of non-zero result
execute_engine.state_nxt <= DISPATCH;
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') or (is_atomic_sc_v = '1') then -- load / load-reservate / store conditional
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') or (decode_aux.is_atomic_sc = '1') then -- load / load-reservate / store conditional
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
end if;
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment
1138,8 → 1200,8
-- -------------------------------------------------------------------------------------------
invalid_csr_access_check: process(execute_engine.i_reg, csr)
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
variable csr_mcounteren_hpm_v : std_ulogic_vector(28 downto 0); -- max 29 HPM counters
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
begin
-- is this CSR instruction really going to write/read to/from a CSR? --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1218,16 → 1280,16
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
--
when csr_hpmcounter3_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter3_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(00)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(01)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(02)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(03)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(04)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(05)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(06)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(07)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(08)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(09)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter13_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter14_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter15_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
1252,16 → 1314,16
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
--
when csr_hpmcounter3h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter3h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(00)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(01)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(02)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(03)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(04)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(05)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(06)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(07)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(08)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(09)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter13h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter14h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter15h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
1296,7 → 1358,7
 
-- Illegal Instruction Check --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
illegal_instruction_check: process(execute_engine, csr_acc_valid)
illegal_instruction_check: process(execute_engine, decode_aux, csr_acc_valid)
variable opcode_v : std_ulogic_vector(6 downto 0);
begin
-- illegal instructions are checked in the EXECUTE stage
1317,7 → 1379,7
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
case opcode_v is
 
-- OPCODE check sufficient: LUI, UIPC, JAL --
-- check sufficient LUI, UIPC, JAL (only check actual OPCODE) --
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
illegal_instruction <= '0';
-- illegal E-CPU register? --
1325,8 → 1387,35
illegal_register <= '1';
end if;
 
when opcode_alui_c => -- check ALUI funct7
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif (decode_aux.is_bitmanip_reg = '1') then -- bit manipulation
if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
illegal_instruction <= '1';
else
illegal_instruction <= '0';
end if;
-- illegal E-CPU register? --
if (CPU_EXTENSION_RISCV_E = true) and
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
illegal_register <= '1';
end if;
 
when opcode_alui_c => -- check ALUI.funct7
if (decode_aux.is_bitmanip_imm = '1') then -- bit manipulation
if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
1340,7 → 1429,7
illegal_register <= '1';
end if;
 
when opcode_load_c => -- check LOAD funct3
when opcode_load_c => -- check LOAD.funct3
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
1355,7 → 1444,7
illegal_register <= '1';
end if;
 
when opcode_store_c => -- check STORE funct3
when opcode_store_c => -- check STORE.funct3
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
1368,7 → 1457,7
illegal_register <= '1';
end if;
 
when opcode_branch_c => -- check BRANCH funct3
when opcode_branch_c => -- check BRANCH.funct3
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
1384,7 → 1473,7
illegal_register <= '1';
end if;
 
when opcode_jalr_c => -- check JALR funct3
when opcode_jalr_c => -- check JALR.funct3
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
illegal_instruction <= '0';
else
1395,25 → 1484,6
illegal_register <= '1';
end if;
 
when opcode_alu_c => -- check ALU funct3 & funct7
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
illegal_instruction <= '1';
else
illegal_instruction <= '0';
end if;
-- illegal E-CPU register? --
if (CPU_EXTENSION_RISCV_E = true) and
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
illegal_register <= '1';
end if;
 
when opcode_fence_c => -- fence instructions --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
illegal_instruction <= '0';
2050,7 → 2120,7
cnt_event <= cnt_event_nxt;
hpmcnt_trigger <= (others => '0'); -- default
for i in 0 to HPM_NUM_CNTS-1 loop
-- enabled selected triggers by ANDing events and configuration bits --
-- enable selected triggers by ANDing events and configuration bits --
-- OR everything to see if counter should increment --
-- AND with inverted sleep flag to increment only when CPU is awake --
hpmcnt_trigger(i) <= (or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0))) and (not execute_engine.sleep);
2101,6 → 2171,7
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode)
when csr_misa_c => -- R/-: misa - ISA and extensions
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
2353,9 → 2424,10
csr.rdata <= HW_THREAD_ID;
 
-- custom machine read-only CSRs --
when csr_mzext_c => -- R/-: mzext - available Z* extensions
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
when csr_mzext_c => -- R/-: mzext - available RISC-V Z* extensions
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei
csr.rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zbb
 
-- undefined/unavailable --
when others =>
/neorv32_cpu_cp_bitmanip.vhd
0,0 → 1,335
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: Bit manipulation unit (RISC-V "B" Extension) >> #
-- # ********************************************************************************************* #
-- # The bit manipulation unit is implemted as co-processor that has a processing latency of at #
-- # least 3 cycles. Only the "base" bit manipulation subset ('Zbb') is supported yet. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_bitmanip is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
start_i : in std_ulogic; -- trigger operation
-- data input --
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
-- result and status --
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
valid_o : out std_ulogic -- data output valid
);
end neorv32_cpu_cp_bitmanip;
 
architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is
 
-- commands --
constant op_clz_c : natural := 0;
constant op_ctz_c : natural := 1;
constant op_cpop_c : natural := 2;
constant op_min_c : natural := 3;
constant op_max_c : natural := 4;
constant op_sextb_c : natural := 5;
constant op_sexth_c : natural := 6;
constant op_andn_c : natural := 7;
constant op_orn_c : natural := 8;
constant op_xnor_c : natural := 9;
constant op_pack_c : natural := 10;
constant op_ror_c : natural := 11;
constant op_rol_c : natural := 12;
constant op_rev8_c : natural := 13;
constant op_orcb_c : natural := 14;
--
constant op_width_c : natural := 15;
 
-- controller --
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT, S_BUSY_LOGIC);
signal ctrl_state : ctrl_state_t;
signal cmd, cmd_buf : std_ulogic_vector(op_width_c-1 downto 0);
 
-- operand buffers --
signal rs1_reg, rs2_reg : std_ulogic_vector(data_width_c-1 downto 0);
 
-- shift amount (immediate or register) --
signal shamt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
 
-- shifter --
type shifter_t is record
start : std_ulogic;
run : std_ulogic;
bcnt : std_ulogic_vector(index_size_f(data_width_c) downto 0); -- bit counter
cnt : std_ulogic_vector(index_size_f(data_width_c) downto 0); -- iteration counter
cnt_max : std_ulogic_vector(index_size_f(data_width_c) downto 0);
sreg : std_ulogic_vector(data_width_c-1 downto 0);
end record;
signal shifter : shifter_t;
 
-- operation results --
type res_t is array (0 to op_width_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
signal res_int, res_out : res_t;
 
begin
 
-- Instruction Decoding (One-Hot) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- a minimal decoding logic is used here -> just to distinguish between B.zbb instructions
-- a more specific decoding and instruction check is done by the CPU control unit
 
-- Zbb - Base Instructions --
cmd(op_clz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0';
cmd(op_ctz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0';
cmd(op_cpop_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0';
cmd(op_sextb_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0';
cmd(op_sexth_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0';
--
cmd(op_ror_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
cmd(op_rol_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '1') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") else '0';
--
cmd(op_rev8_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1101") else '0';
--
cmd(op_orcb_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") else '0';
--
cmd(op_min_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_7_c downto ctrl_ir_funct12_5_c) = "101") and (ctrl_i(ctrl_ir_funct3_1_c) = '0') else '0';
cmd(op_max_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_7_c downto ctrl_ir_funct12_5_c) = "101") and (ctrl_i(ctrl_ir_funct3_1_c) = '1') else '0';
--
cmd(op_andn_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0';
cmd(op_orn_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0';
cmd(op_xnor_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0';
--
cmd(op_pack_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_5_c) = "000100") else '0';
 
 
-- Co-Processor Controller ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
coprocessor_ctrl: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_state <= S_IDLE;
cmd_buf <= (others => '0');
rs1_reg <= (others => '0');
rs2_reg <= (others => '0');
shifter.start <= '0';
valid_o <= '0';
elsif rising_edge(clk_i) then
-- defaults --
shifter.start <= '0';
valid_o <= '0';
 
-- fsm --
case ctrl_state is
 
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
if (start_i = '1') then
cmd_buf <= cmd;
rs1_reg <= rs1_i;
rs2_reg <= rs2_i;
if ((cmd(op_clz_c) or cmd(op_ctz_c) or cmd(op_cpop_c) or cmd(op_ror_c) or cmd(op_rol_c)) = '1') then -- multi-cycle shift operation
shifter.start <= '1';
ctrl_state <= S_START_SHIFT;
else
ctrl_state <= S_BUSY_LOGIC;
end if;
end if;
 
when S_START_SHIFT => -- one cycle delay to start shift operation
-- ------------------------------------------------------------
ctrl_state <= S_BUSY_SHIFT;
 
when S_BUSY_SHIFT => -- wait for multi-cycle shift operation to finish
-- ------------------------------------------------------------
if (shifter.run = '0') then
ctrl_state <= S_BUSY_LOGIC;
end if;
 
when S_BUSY_LOGIC => -- single-cycle logic operation (and output)
-- ------------------------------------------------------------
valid_o <= '1';
ctrl_state <= S_IDLE;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl_state <= S_IDLE;
 
end case;
end if;
end process coprocessor_ctrl;
 
 
-- Shift Amount ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- we could also use ALU's internal operand B - but we are having a local version here in order to allow
-- better logic combination inside the ALU (since that is the critical path of the CPU)
shamt <= ctrl_i(shamt'left+ctrl_ir_funct12_0_c downto ctrl_ir_funct12_0_c) when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') else rs2_reg(shamt'left downto 0);
 
 
-- Shifter Function Core ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shifter_unit: process(clk_i)
variable new_bit_v : std_ulogic;
begin
if rising_edge(clk_i) then
if (shifter.start = '1') then -- trigger new shift
shifter.cnt <= (others => '0');
-- shift operand --
if (cmd_buf(op_clz_c) = '1') or (cmd_buf(op_rol_c) = '1') then -- count LEADING zeros / rotate LEFT
shifter.sreg <= bit_rev_f(rs1_reg); -- reverse - we can only do right shifts here
else -- ctz, cpop, ror
shifter.sreg <= rs1_reg;
end if;
-- max shift amount --
if (cmd_buf(op_cpop_c) = '1') then -- population count
shifter.cnt_max <= (others => '0');
shifter.cnt_max(shifter.cnt_max'left) <= '1';
else
shifter.cnt_max <= '0' & shamt;
end if;
shifter.bcnt <= (others => '0');
elsif (shifter.run = '1') then -- right shifts only
new_bit_v := ((cmd_buf(op_ror_c) or cmd_buf(op_rol_c)) and shifter.sreg(0)) or (cmd_buf(op_clz_c) or cmd_buf(op_ctz_c));
shifter.sreg <= new_bit_v & shifter.sreg(shifter.sreg'left downto 1); -- ro[r/l]/lsr(for counting)
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) + 1); -- iteration counter
if (shifter.sreg(0) = '1') then
shifter.bcnt <= std_ulogic_vector(unsigned(shifter.bcnt) + 1); -- bit counter
end if;
end if;
end if;
end process shifter_unit;
 
shifter_unit_ctrl: process(cmd_buf, shifter)
begin
-- keep shifting until ... --
if (cmd_buf(op_clz_c) = '1') or (cmd_buf(op_ctz_c) = '1') then -- count leading/trailing zeros
shifter.run <= not shifter.sreg(0);
else -- population count / rotate
if (shifter.cnt = shifter.cnt_max) then
shifter.run <= '0';
else
shifter.run <= '1';
end if;
end if;
end process shifter_unit_ctrl;
 
 
-- Base ('Zbb') Logic Function Core -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- count leading/trailing zeros --
res_int(op_clz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0');
res_int(op_clz_c)(shifter.cnt'left downto 0) <= shifter.cnt;
res_int(op_ctz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0');
res_int(op_ctz_c)(shifter.cnt'left downto 0) <= shifter.cnt;
 
-- count set bits --
res_int(op_cpop_c)(data_width_c-1 downto shifter.bcnt'left+1) <= (others => '0');
res_int(op_cpop_c)(shifter.bcnt'left downto 0) <= shifter.bcnt;
 
-- min/max select --
res_int(op_min_c) <= rs1_reg when (cmp_i(alu_cmp_less_c) = '1') else rs2_reg;
res_int(op_max_c) <= rs2_reg when (cmp_i(alu_cmp_less_c) = '1') else rs1_reg;
 
-- sign-extension --
res_int(op_sextb_c)(data_width_c-1 downto 8) <= (others => rs1_reg(7));
res_int(op_sextb_c)(7 downto 0) <= rs1_reg(7 downto 0); -- sign-extend byte
res_int(op_sexth_c)(data_width_c-1 downto 16) <= (others => rs1_reg(15));
res_int(op_sexth_c)(15 downto 0) <= rs1_reg(15 downto 0); -- sign-extend half-word
 
-- logic with negate --
res_int(op_andn_c) <= rs1_reg and (not rs2_reg); -- logical and-not
res_int(op_orn_c) <= rs1_reg or (not rs2_reg); -- logical or-not
res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg); -- logical xor-not
 
-- pack two words in one register --
res_int(op_pack_c) <= rs2_reg((data_width_c/2)-1 downto 0) & rs1_reg((data_width_c/2)-1 downto 0); -- pack lower halves
 
-- rotate right/left --
res_int(op_ror_c) <= shifter.sreg;
res_int(op_rol_c) <= bit_rev_f(shifter.sreg);
 
-- reversal.8 (byte swap) --
res_int(op_rev8_c) <= bswap32_f(rs1_reg);
 
-- or-combine.byte --
or_combine_byte_gen:
for i in 0 to (data_width_c/8)-1 generate
res_int(op_orcb_c)(i*8+7 downto i*8) <= (others => or_all_f(rs1_reg(i*8+7 downto i*8)));
end generate; -- i
 
 
-- Output Selector ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
res_out(op_clz_c) <= res_int(op_clz_c) when (cmd_buf(op_clz_c) = '1') else (others => '0');
res_out(op_ctz_c) <= res_int(op_ctz_c) when (cmd_buf(op_ctz_c) = '1') else (others => '0');
res_out(op_cpop_c) <= res_int(op_cpop_c) when (cmd_buf(op_cpop_c) = '1') else (others => '0');
res_out(op_min_c) <= res_int(op_min_c) when (cmd_buf(op_min_c) = '1') else (others => '0');
res_out(op_max_c) <= res_int(op_max_c) when (cmd_buf(op_max_c) = '1') else (others => '0');
res_out(op_sextb_c) <= res_int(op_sextb_c) when (cmd_buf(op_sextb_c) = '1') else (others => '0');
res_out(op_sexth_c) <= res_int(op_sexth_c) when (cmd_buf(op_sexth_c) = '1') else (others => '0');
res_out(op_andn_c) <= res_int(op_andn_c) when (cmd_buf(op_andn_c) = '1') else (others => '0');
res_out(op_orn_c) <= res_int(op_orn_c) when (cmd_buf(op_orn_c) = '1') else (others => '0');
res_out(op_xnor_c) <= res_int(op_xnor_c) when (cmd_buf(op_xnor_c) = '1') else (others => '0');
res_out(op_pack_c) <= res_int(op_pack_c) when (cmd_buf(op_pack_c) = '1') else (others => '0');
res_out(op_ror_c) <= res_int(op_ror_c) when (cmd_buf(op_ror_c) = '1') else (others => '0');
res_out(op_rol_c) <= res_int(op_rol_c) when (cmd_buf(op_rol_c) = '1') else (others => '0');
res_out(op_rev8_c) <= res_int(op_rev8_c) when (cmd_buf(op_rev8_c) = '1') else (others => '0');
res_out(op_orcb_c) <= res_int(op_orcb_c) when (cmd_buf(op_orcb_c) = '1') else (others => '0');
 
 
-- Output Gate ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
output_gate: process(clk_i)
begin
if rising_edge(clk_i) then
res_o <= (others => '0');
if (ctrl_state = S_BUSY_LOGIC) then
res_o <= res_out(op_clz_c) or res_out(op_ctz_c) or res_out(op_cpop_c) or
res_out(op_min_c) or res_out(op_max_c) or
res_out(op_sextb_c) or res_out(op_sexth_c) or
res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or
res_out(op_pack_c) or
res_out(op_ror_c) or res_out(op_rol_c) or
res_out(op_rev8_c) or
res_out(op_orcb_c);
end if;
end if;
end process output_gate;
 
 
end neorv32_cpu_cp_bitmanip_rtl;
/neorv32_cpu_cp_muldiv.vhd
1,5 → 1,5
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
-- # << NEORV32 - CPU Co-Processor: MULDIV unit (RISC-V "M" Extension)>> #
-- # ********************************************************************************************* #
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
8,7 → 8,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
68,6 → 68,16
-- advanced configuration --
constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
 
-- operations --
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
 
-- controller --
type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
signal state : state_t;
/neorv32_dmem.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
/neorv32_imem.vhd
8,7 → 8,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
47,10 → 47,10
 
entity neorv32_imem is
generic (
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLOADER_USE : boolean := true -- implement and use bootloader?
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLOADER_EN : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
165,7 → 165,7
rdata(23 downto 16) <= imem_file_rom_hl(to_integer(unsigned(addr)));
rdata(31 downto 24) <= imem_file_rom_hh(to_integer(unsigned(addr)));
 
elsif (BOOTLOADER_USE = true) then -- implement IMEM as non-initialized RAM
elsif (BOOTLOADER_EN = true) then -- implement IMEM as non-initialized RAM
if (wren_i = '1') then
if (ben_i(0) = '1') then
imem_file_ram_ll(to_integer(unsigned(addr))) <= data_i(07 downto 00);
/neorv32_package.vhd
55,7 → 55,7
-- Architecture Constants (do not modify!)= -----------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040908"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050000"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
220,7 → 220,7
-- current privilege level --
constant ctrl_priv_lvl_lsb_c : natural := 45; -- privilege level lsb
constant ctrl_priv_lvl_msb_c : natural := 46; -- privilege level msb
-- instruction's control blocks --
-- instruction's control blocks (used by cpu co-processors) --
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
236,8 → 236,15
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0
constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
-- control bus size --
constant ctrl_width_c : natural := 62; -- control bus size
constant ctrl_width_c : natural := 69; -- control bus size
 
-- ALU Comparator Bus ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
615,22 → 622,12
-- custom read-only CSRs --
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
 
-- Co-Processor Operations ----------------------------------------------------------------
-- Co-Processor IDs -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- cp ids --
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV
constant cp_sel_atomic_c : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations success/failure evaluation
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved
-- muldiv cp --
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- multiplication/division operations ('M' extension)
constant cp_sel_atomic_c : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations; success/failure evaluation ('A' extension)
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extension)
--constant cp_sel_float32_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved -- single-precision floating point operations ('F' extension)
 
-- ALU Function Codes ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
739,11 → 736,12
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
759,29 → 757,29
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE : boolean := false; -- implement instruction cache
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)?
);
port (
-- Global control --
799,7 → 797,7
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO --
818,10 → 816,10
twi_scl_io : inout std_logic; -- twi serial clock line
-- PWM --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- system time input from external MTIME (available if IO_MTIME_USE = false) --
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
837,6 → 835,7
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
902,6 → 901,7
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
996,7 → 996,6
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B
-- co-processor interface --
cp0_start_o : out std_ulogic; -- trigger co-processor 0
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
1015,7 → 1014,7
);
end component;
 
-- Component: CPU Co-Processor MULDIV -----------------------------------------------------
-- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_cp_muldiv
generic (
1036,6 → 1035,25
);
end component;
 
-- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_cp_bitmanip
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
start_i : in std_ulogic; -- trigger operation
-- data input --
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
-- result and status --
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
valid_o : out std_ulogic -- data output valid
);
end component;
 
-- Component: CPU Bus Interface -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_bus
1204,7 → 1222,7
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLOADER_USE : boolean := true -- implement and use bootloader?
BOOTLOADER_EN : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
1427,10 → 1445,10
generic (
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
-- Internal instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
-- Internal data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
);
port (
1513,33 → 1531,33
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE : boolean := true; -- implement instruction cache
ICACHE_EN : boolean := true; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)?
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU0_EN : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_EN : boolean := true -- implement custom functions unit 1 (CFU1)?
);
port (
-- host access --
/neorv32_sysinfo.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
46,33 → 46,33
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE : boolean := true; -- implement instruction cache
ICACHE_EN : boolean := true; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)?
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFU0_EN : boolean := true; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_EN : boolean := true -- implement custom functions unit 1 (CFU1)?
);
port (
-- host access --
121,33 → 121,33
 
-- SYSINFO(2): Implemented processor devices/features --
-- Memory --
sysinfo_mem(2)(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- processor-internal bootloader implemented?
sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- external memory bus interface implemented?
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- processor-internal instruction memory implemented?
sysinfo_mem(2)(00) <= bool_to_ulogic_f(BOOTLOADER_EN); -- processor-internal bootloader implemented?
sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_EN); -- external memory bus interface implemented?
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_EN); -- processor-internal instruction memory implemented?
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- processor-internal instruction memory implemented as ROM?
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- processor-internal data memory implemented?
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_EN); -- processor-internal data memory implemented?
sysinfo_mem(2)(05) <= bool_to_ulogic_f(xbus_big_endian_c); -- is external memory bus interface using BIG-endian byte-order?
sysinfo_mem(2)(06) <= bool_to_ulogic_f(ICACHE_USE); -- processor-internal instruction cache implemented?
sysinfo_mem(2)(06) <= bool_to_ulogic_f(ICACHE_EN); -- processor-internal instruction cache implemented?
--
sysinfo_mem(2)(15 downto 07) <= (others => '0'); -- reserved
-- IO --
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- general purpose input/output port unit (GPIO) implemented?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- machine system timer (MTIME) implemented?
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_USE); -- universal asynchronous receiver/transmitter (UART) implemented?
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_USE); -- serial peripheral interface (SPI) implemented?
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- watch dog timer (WDT) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFU0_USE); -- custom functions unit 0 (CFU0) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- true random number generator (TRNG) implemented?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_USE); -- custom functions unit 1 (CFU1) implemented?
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented?
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_EN); -- universal asynchronous receiver/transmitter (UART) implemented?
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented?
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFU0_EN); -- custom functions unit 0 (CFU0) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_EN); -- custom functions unit 1 (CFU1) implemented?
--
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
 
-- SYSINFO(3): Cache configuration --
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(number_of_block)
sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(associativity)
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
sysinfo_mem(3)(15 downto 12) <= (others => '0'); -- replacement strategy (irrelevant since i-cache is read-only)
--
sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved (for d-cache.block_size)
162,10 → 162,10
sysinfo_mem(5) <= dspace_base_c; -- defined in neorv32_package.vhd file
 
-- SYSINFO(6): Size of IMEM in bytes --
sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_USE = true) else (others => '0');
sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_EN = true) else (others => '0');
 
-- SYSINFO(7): Size of DMEM in bytes --
sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_USE = true) else (others => '0');
sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_EN = true) else (others => '0');
 
 
-- Read Access ----------------------------------------------------------------------------
/neorv32_top.vhd
49,11 → 49,12
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
69,35 → 70,35
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE : boolean := false; -- implement instruction cache
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)?
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)?
);
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
109,29 → 110,29
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO (available if IO_GPIO_USE = true) --
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
-- UART (available if IO_UART_USE = true) --
-- UART (available if IO_UART_EN = true) --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
-- SPI (available if IO_SPI_USE = true) --
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_USE = true) --
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- PWM (available if IO_PWM_USE = true) --
-- PWM (available if IO_PWM_EN = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- system time input from external MTIME (available if IO_MTIME_USE = false) --
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
);
140,11 → 141,11
architecture neorv32_top_rtl of neorv32_top is
 
-- CPU boot address --
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_USE, boot_rom_base_c, ispace_base_c);
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
 
-- Bus timeout --
constant bus_timeout_temp_c : natural := 2**index_size_f(bus_timeout_c); -- round to next power-of-two
constant bus_timeout_proc_c : natural := cond_sel_natural_f(ICACHE_USE, ((ICACHE_BLOCK_SIZE/4)*bus_timeout_temp_c)-1, bus_timeout_c);
constant bus_timeout_proc_c : natural := cond_sel_natural_f(ICACHE_EN, ((ICACHE_BLOCK_SIZE/4)*bus_timeout_temp_c)-1, bus_timeout_c);
 
-- alignment check for internal memories --
constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
246,26 → 247,26
-- clock --
assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
-- internal bootloader ROM --
assert not ((BOOTLOADER_USE = true) and (boot_rom_size_c > boot_rom_max_size_c)) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;
assert not ((BOOTLOADER_USE = true) and (MEM_INT_IMEM_ROM = true)) report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning;
assert not ((BOOTLOADER_EN = true) and (boot_rom_size_c > boot_rom_max_size_c)) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;
assert not ((BOOTLOADER_EN = true) and (MEM_INT_IMEM_ROM = true)) report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning;
-- memory system - data/instruction fetch --
assert not ((MEM_EXT_USE = false) and (MEM_INT_DMEM_USE = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
assert not ((MEM_EXT_USE = false) and (MEM_INT_IMEM_USE = false) and (BOOTLOADER_USE = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
-- memory system - size --
assert not ((MEM_INT_DMEM_USE = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
assert not ((MEM_INT_IMEM_USE = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
-- memory system - alignment --
assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;
assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_USE = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_USE = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
-- memory system - layout warning --
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
assert not ((ICACHE_USE = true) and (MEM_EXT_USE = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
-- memory system - cached instruction fetch latency check --
assert not (ICACHE_USE = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing i-cache. Increasing bus access timeout from " & integer'image(bus_timeout_c) & " cycles to " & integer'image(bus_timeout_proc_c) & " cycles." severity warning;
assert not (ICACHE_EN = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing i-cache. Increasing bus access timeout from " & integer'image(bus_timeout_c) & " cycles to " & integer'image(bus_timeout_proc_c) & " cycles." severity warning;
 
 
-- Reset Generator ------------------------------------------------------------------------
336,6 → 337,7
BUS_TIMEOUT => bus_timeout_proc_c, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
409,7 → 411,7
-- CPU Instruction Cache ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_icache_inst_true:
if (ICACHE_USE = true) generate
if (ICACHE_EN = true) generate
neorv32_icache_inst: neorv32_cache
generic map (
CACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2
446,7 → 448,7
end generate;
 
neorv32_icache_inst_false:
if (ICACHE_USE = false) generate
if (ICACHE_EN = false) generate
i_cache.addr <= cpu_i.addr;
cpu_i.rdata <= i_cache.rdata;
i_cache.wdata <= cpu_i.wdata;
525,13 → 527,13
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_int_imem_inst_true:
if (MEM_INT_IMEM_USE = true) generate
if (MEM_INT_IMEM_EN = true) generate
neorv32_int_imem_inst: neorv32_imem
generic map (
IMEM_BASE => imem_base_c, -- memory base address
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
BOOTLOADER_EN => BOOTLOADER_EN -- implement and use bootloader?
)
port map (
clk_i => clk_i, -- global clock line
546,7 → 548,7
end generate;
 
neorv32_int_imem_inst_false:
if (MEM_INT_IMEM_USE = false) generate
if (MEM_INT_IMEM_EN = false) generate
imem_rdata <= (others => '0');
imem_ack <= '0';
end generate;
555,7 → 557,7
-- Processor-Internal Data Memory (DMEM) --------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_int_dmem_inst_true:
if (MEM_INT_DMEM_USE = true) generate
if (MEM_INT_DMEM_EN = true) generate
neorv32_int_dmem_inst: neorv32_dmem
generic map (
DMEM_BASE => dmem_base_c, -- memory base address
574,7 → 576,7
end generate;
 
neorv32_int_dmem_inst_false:
if (MEM_INT_DMEM_USE = false) generate
if (MEM_INT_DMEM_EN = false) generate
dmem_rdata <= (others => '0');
dmem_ack <= '0';
end generate;
583,7 → 585,7
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_boot_rom_inst_true:
if (BOOTLOADER_USE = true) generate
if (BOOTLOADER_EN = true) generate
neorv32_boot_rom_inst: neorv32_boot_rom
generic map (
BOOTROM_BASE => boot_rom_base_c, -- boot ROM base address
599,7 → 601,7
end generate;
 
neorv32_boot_rom_inst_false:
if (BOOTLOADER_USE = false) generate
if (BOOTLOADER_EN = false) generate
bootrom_rdata <= (others => '0');
bootrom_ack <= '0';
end generate;
608,15 → 610,15
-- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_wishbone_inst_true:
if (MEM_EXT_USE = true) generate
if (MEM_EXT_EN = true) generate
neorv32_wishbone_inst: neorv32_wishbone
generic map (
WB_PIPELINED_MODE => wb_pipe_mode_c, -- false: classic/standard wishbone mode, true: pipelined wishbone mode
-- Internal instruction memory --
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
-- Internal data memory --
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
)
port map (
652,7 → 654,7
end generate;
 
neorv32_wishbone_inst_false:
if (MEM_EXT_USE = false) generate
if (MEM_EXT_EN = false) generate
wishbone_rdata <= (others => '0');
wishbone_ack <= '0';
wishbone_err <= '0';
679,7 → 681,7
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_gpio_inst_true:
if (IO_GPIO_USE = true) generate
if (IO_GPIO_EN = true) generate
neorv32_gpio_inst: neorv32_gpio
port map (
-- host access --
699,7 → 701,7
end generate;
 
neorv32_gpio_inst_false:
if (IO_GPIO_USE = false) generate
if (IO_GPIO_EN = false) generate
gpio_rdata <= (others => '0');
gpio_ack <= '0';
gpio_o <= (others => '0');
710,7 → 712,7
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_wdt_inst_true:
if (IO_WDT_USE = true) generate
if (IO_WDT_EN = true) generate
neorv32_wdt_inst: neorv32_wdt
port map (
-- host access --
732,7 → 734,7
end generate;
 
neorv32_wdt_inst_false:
if (IO_WDT_USE = false) generate
if (IO_WDT_EN = false) generate
wdt_rdata <= (others => '0');
wdt_ack <= '0';
wdt_irq <= '0';
744,7 → 746,7
-- Machine System Timer (MTIME) -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_mtime_inst_true:
if (IO_MTIME_USE = true) generate
if (IO_MTIME_EN = true) generate
neorv32_mtime_inst: neorv32_mtime
port map (
-- host access --
764,7 → 766,7
end generate;
 
neorv32_mtime_inst_false:
if (IO_MTIME_USE = false) generate
if (IO_MTIME_EN = false) generate
mtime_rdata <= (others => '0');
mtime_time <= mtime_i; -- use external machine timer time signal
mtime_ack <= '0';
775,7 → 777,7
-- Universal Asynchronous Receiver/Transmitter (UART) -------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart_inst_true:
if (IO_UART_USE = true) generate
if (IO_UART_EN = true) generate
neorv32_uart_inst: neorv32_uart
port map (
-- host access --
798,7 → 800,7
end generate;
 
neorv32_uart_inst_false:
if (IO_UART_USE = false) generate
if (IO_UART_EN = false) generate
uart_rdata <= (others => '0');
uart_ack <= '0';
uart_txd_o <= '0';
810,7 → 812,7
-- Serial Peripheral Interface (SPI) ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_spi_inst_true:
if (IO_SPI_USE = true) generate
if (IO_SPI_EN = true) generate
neorv32_spi_inst: neorv32_spi
port map (
-- host access --
835,7 → 837,7
end generate;
 
neorv32_spi_inst_false:
if (IO_SPI_USE = false) generate
if (IO_SPI_EN = false) generate
spi_rdata <= (others => '0');
spi_ack <= '0';
spi_sck_o <= '0';
849,7 → 851,7
-- Two-Wire Interface (TWI) ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_twi_inst_true:
if (IO_TWI_USE = true) generate
if (IO_TWI_EN = true) generate
neorv32_twi_inst: neorv32_twi
port map (
-- host access --
872,7 → 874,7
end generate;
 
neorv32_twi_inst_false:
if (IO_TWI_USE = false) generate
if (IO_TWI_EN = false) generate
twi_rdata <= (others => '0');
twi_ack <= '0';
-- twi_sda_io <= 'Z';
885,7 → 887,7
-- Pulse-Width Modulation Controller (PWM) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_pwm_inst_true:
if (IO_PWM_USE = true) generate
if (IO_PWM_EN = true) generate
neorv32_pwm_inst: neorv32_pwm
port map (
-- host access --
905,7 → 907,7
end generate;
 
neorv32_pwm_inst_false:
if (IO_PWM_USE = false) generate
if (IO_PWM_EN = false) generate
pwm_rdata <= (others => '0');
pwm_ack <= '0';
pwm_cg_en <= '0';
916,7 → 918,7
-- True Random Number Generator (TRNG) ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_trng_inst_true:
if (IO_TRNG_USE = true) generate
if (IO_TRNG_EN = true) generate
neorv32_trng_inst: neorv32_trng
port map (
-- host access --
931,7 → 933,7
end generate;
 
neorv32_trng_inst_false:
if (IO_TRNG_USE = false) generate
if (IO_TRNG_EN = false) generate
trng_rdata <= (others => '0');
trng_ack <= '0';
end generate;
940,7 → 942,7
-- Custom Functions Unit 0 (CFU0) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cfu0_inst_true:
if (IO_CFU0_USE = true) generate
if (IO_CFU0_EN = true) generate
neorv32_cfu0_inst: neorv32_cfu0
port map (
-- host access --
961,7 → 963,7
end generate;
 
neorv32_cfu0_inst_false:
if (IO_CFU0_USE = false) generate
if (IO_CFU0_EN = false) generate
cfu0_rdata <= (others => '0');
cfu0_ack <= '0';
cfu0_cg_en <= '0';
971,7 → 973,7
-- Custom Functions Unit 1 (CFU1) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cfu1_inst_true:
if (IO_CFU1_USE = true) generate
if (IO_CFU1_EN = true) generate
neorv32_cfu1_inst: neorv32_cfu1
port map (
-- host access --
992,7 → 994,7
end generate;
 
neorv32_cfu1_inst_false:
if (IO_CFU1_USE = false) generate
if (IO_CFU1_EN = false) generate
cfu1_rdata <= (others => '0');
cfu1_ack <= '0';
cfu1_cg_en <= '0';
1005,33 → 1007,33
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
BOOTLOADER_EN => BOOTLOADER_EN, -- implement processor-internal bootloader?
USER_CODE => USER_CODE, -- custom user code
-- internal Instruction memory --
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE => ICACHE_USE, -- implement instruction cache
ICACHE_EN => ICACHE_EN, -- implement instruction cache
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_CFU0_USE => IO_CFU0_USE, -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE => IO_CFU1_USE -- implement custom functions unit 1 (CFU1)?
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
IO_CFU0_EN => IO_CFU0_EN, -- implement custom functions unit 0 (CFU0)?
IO_CFU1_EN => IO_CFU1_EN -- implement custom functions unit 1 (CFU1)?
)
port map (
-- host access --
/neorv32_wishbone.vhd
18,7 → 18,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
58,10 → 58,10
generic (
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
-- Internal instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
-- Internal data memory --
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Bus Timeout --
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
148,8 → 148,8
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- access to processor-internal IMEM or DMEM? --
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_USE = true) else '0';
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_USE = true) else '0';
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0';
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0';
-- access to processor-internal BOOTROM or IO devices? --
int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
-- actual external bus access? --

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