URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/core
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/neorv32_application_image.vhd
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 1043) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 1063) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
60,7 → 60,7
00000049 => x"00158593", |
00000050 => x"ff5ff06f", |
00000051 => x"00001597", |
00000052 => x"f8058593", |
00000052 => x"fd058593", |
00000053 => x"80000617", |
00000054 => x"f2c60613", |
00000055 => x"80000697", |
110,19 → 110,19
00000099 => x"00000593", |
00000100 => x"b0050513", |
00000101 => x"00112623", |
00000102 => x"668000ef", |
00000103 => x"1a1000ef", |
00000102 => x"728000ef", |
00000103 => x"1f1000ef", |
00000104 => x"02050063", |
00000105 => x"4ac000ef", |
00000106 => x"00000513", |
00000107 => x"500000ef", |
00000108 => x"00001537", |
00000109 => x"ce050513", |
00000110 => x"6dc000ef", |
00000109 => x"d3050513", |
00000110 => x"778000ef", |
00000111 => x"020000ef", |
00000112 => x"00001537", |
00000113 => x"cbc50513", |
00000114 => x"6cc000ef", |
00000113 => x"d0c50513", |
00000114 => x"768000ef", |
00000115 => x"00c12083", |
00000116 => x"00000513", |
00000117 => x"01010113", |
132,11 → 132,11
00000121 => x"00812423", |
00000122 => x"00112623", |
00000123 => x"00000413", |
00000124 => x"15d000ef", |
00000124 => x"1ad000ef", |
00000125 => x"0ff47513", |
00000126 => x"155000ef", |
00000126 => x"1a5000ef", |
00000127 => x"0c800513", |
00000128 => x"0cd000ef", |
00000128 => x"11d000ef", |
00000129 => x"00140413", |
00000130 => x"fedff06f", |
00000131 => x"00000000", |
192,7 → 192,7
00000181 => x"30200073", |
00000182 => x"00001737", |
00000183 => x"00279793", |
00000184 => x"cfc70713", |
00000184 => x"d4c70713", |
00000185 => x"00e787b3", |
00000186 => x"0007a783", |
00000187 => x"00078067", |
203,7 → 203,7
00000192 => x"f8f764e3", |
00000193 => x"00001737", |
00000194 => x"00279793", |
00000195 => x"d2c70713", |
00000195 => x"d7c70713", |
00000196 => x"00e787b3", |
00000197 => x"0007a783", |
00000198 => x"00078067", |
276,14 → 276,14
00000265 => x"00050913", |
00000266 => x"00001537", |
00000267 => x"00912a23", |
00000268 => x"da050513", |
00000268 => x"df050513", |
00000269 => x"000014b7", |
00000270 => x"00812c23", |
00000271 => x"01312623", |
00000272 => x"00112e23", |
00000273 => x"01c00413", |
00000274 => x"44c000ef", |
00000275 => x"01c48493", |
00000274 => x"4e8000ef", |
00000275 => x"06c48493", |
00000276 => x"ffc00993", |
00000277 => x"008957b3", |
00000278 => x"00f7f793", |
290,7 → 290,7
00000279 => x"00f487b3", |
00000280 => x"0007c503", |
00000281 => x"ffc40413", |
00000282 => x"41c000ef", |
00000282 => x"46c000ef", |
00000283 => x"ff3414e3", |
00000284 => x"01c12083", |
00000285 => x"01812403", |
301,11 → 301,11
00000290 => x"00008067", |
00000291 => x"00001537", |
00000292 => x"ff010113", |
00000293 => x"da450513", |
00000293 => x"df450513", |
00000294 => x"00112623", |
00000295 => x"00812423", |
00000296 => x"00912223", |
00000297 => x"3f0000ef", |
00000297 => x"48c000ef", |
00000298 => x"34202473", |
00000299 => x"00900713", |
00000300 => x"00f47793", |
316,7 → 316,7
00000305 => x"0087ee63", |
00000306 => x"00001737", |
00000307 => x"00241793", |
00000308 => x"f3070713", |
00000308 => x"f8070713", |
00000309 => x"00e787b3", |
00000310 => x"0007a783", |
00000311 => x"00078067", |
329,8 → 329,8
00000318 => x"00778793", |
00000319 => x"10f40663", |
00000320 => x"00001537", |
00000321 => x"f0450513", |
00000322 => x"38c000ef", |
00000321 => x"f5450513", |
00000322 => x"428000ef", |
00000323 => x"00040513", |
00000324 => x"f0dff0ef", |
00000325 => x"0380006f", |
339,22 → 339,22
00000328 => x"00f00713", |
00000329 => x"fcf76ee3", |
00000330 => x"00001537", |
00000331 => x"ef450513", |
00000332 => x"364000ef", |
00000331 => x"f4450513", |
00000332 => x"400000ef", |
00000333 => x"00048513", |
00000334 => x"34c000ef", |
00000334 => x"39c000ef", |
00000335 => x"0100006f", |
00000336 => x"00001537", |
00000337 => x"dac50513", |
00000338 => x"34c000ef", |
00000337 => x"dfc50513", |
00000338 => x"3e8000ef", |
00000339 => x"00001537", |
00000340 => x"f1c50513", |
00000341 => x"340000ef", |
00000340 => x"f6c50513", |
00000341 => x"3dc000ef", |
00000342 => x"34002573", |
00000343 => x"ec1ff0ef", |
00000344 => x"00001537", |
00000345 => x"f2450513", |
00000346 => x"32c000ef", |
00000345 => x"f7450513", |
00000346 => x"3c8000ef", |
00000347 => x"34302573", |
00000348 => x"eadff0ef", |
00000349 => x"00812403", |
361,44 → 361,44
00000350 => x"00c12083", |
00000351 => x"00412483", |
00000352 => x"00001537", |
00000353 => x"f8c50513", |
00000353 => x"fdc50513", |
00000354 => x"01010113", |
00000355 => x"3080006f", |
00000355 => x"3a40006f", |
00000356 => x"00001537", |
00000357 => x"dcc50513", |
00000357 => x"e1c50513", |
00000358 => x"fb1ff06f", |
00000359 => x"00001537", |
00000360 => x"de850513", |
00000360 => x"e3850513", |
00000361 => x"fa5ff06f", |
00000362 => x"00001537", |
00000363 => x"dfc50513", |
00000363 => x"e4c50513", |
00000364 => x"f99ff06f", |
00000365 => x"00001537", |
00000366 => x"e0850513", |
00000366 => x"e5850513", |
00000367 => x"f8dff06f", |
00000368 => x"00001537", |
00000369 => x"e2050513", |
00000369 => x"e7050513", |
00000370 => x"f81ff06f", |
00000371 => x"00001537", |
00000372 => x"e3450513", |
00000372 => x"e8450513", |
00000373 => x"f75ff06f", |
00000374 => x"00001537", |
00000375 => x"e5050513", |
00000375 => x"ea050513", |
00000376 => x"f69ff06f", |
00000377 => x"00001537", |
00000378 => x"e6450513", |
00000378 => x"eb450513", |
00000379 => x"f5dff06f", |
00000380 => x"00001537", |
00000381 => x"e8450513", |
00000381 => x"ed450513", |
00000382 => x"f51ff06f", |
00000383 => x"00001537", |
00000384 => x"ea450513", |
00000384 => x"ef450513", |
00000385 => x"f45ff06f", |
00000386 => x"00001537", |
00000387 => x"ec050513", |
00000387 => x"f1050513", |
00000388 => x"f39ff06f", |
00000389 => x"00001537", |
00000390 => x"ed850513", |
00000390 => x"f2850513", |
00000391 => x"f2dff06f", |
00000392 => x"01f00793", |
00000393 => x"02a7e263", |
419,8 → 419,8
00000408 => x"301027f3", |
00000409 => x"00079863", |
00000410 => x"00001537", |
00000411 => x"f6050513", |
00000412 => x"224000ef", |
00000411 => x"fb050513", |
00000412 => x"2c0000ef", |
00000413 => x"21000793", |
00000414 => x"30579073", |
00000415 => x"00000413", |
447,8 → 447,8
00000436 => x"00100413", |
00000437 => x"00051863", |
00000438 => x"00001537", |
00000439 => x"f9450513", |
00000440 => x"20c000ef", |
00000439 => x"fe450513", |
00000440 => x"3dc000ef", |
00000441 => x"00c12083", |
00000442 => x"00040513", |
00000443 => x"00812403", |
468,10 → 468,10
00000457 => x"00058523", |
00000458 => x"00000993", |
00000459 => x"00410913", |
00000460 => x"02ca0a13", |
00000460 => x"07ca0a13", |
00000461 => x"00a00593", |
00000462 => x"00048513", |
00000463 => x"51c000ef", |
00000463 => x"56c000ef", |
00000464 => x"00aa0533", |
00000465 => x"00054783", |
00000466 => x"01390ab3", |
478,7 → 478,7
00000467 => x"00048513", |
00000468 => x"00fa8023", |
00000469 => x"00a00593", |
00000470 => x"4b8000ef", |
00000470 => x"508000ef", |
00000471 => x"00198993", |
00000472 => x"00a00793", |
00000473 => x"00050493", |
520,537 → 520,557
00000509 => x"00008067", |
00000510 => x"00070793", |
00000511 => x"fadff06f", |
00000512 => x"fa002023", |
00000513 => x"fe002783", |
00000514 => x"00151513", |
00000515 => x"00000713", |
00000516 => x"02a7fe63", |
00000517 => x"000016b7", |
00000518 => x"00000793", |
00000519 => x"ffe68693", |
00000520 => x"04e6e063", |
00000521 => x"fff70713", |
00000522 => x"0035f593", |
00000523 => x"01879793", |
00000524 => x"00e7e7b3", |
00000525 => x"01659593", |
00000526 => x"00b7e7b3", |
00000527 => x"10000737", |
00000528 => x"00e7e7b3", |
00000529 => x"faf02023", |
00000530 => x"00008067", |
00000531 => x"00170713", |
00000532 => x"01071713", |
00000533 => x"40a787b3", |
00000534 => x"01075713", |
00000535 => x"fb5ff06f", |
00000536 => x"ffe78613", |
00000537 => x"0fd67613", |
00000538 => x"00061a63", |
00000539 => x"00375713", |
00000540 => x"00178793", |
00000541 => x"0ff7f793", |
00000542 => x"fa9ff06f", |
00000543 => x"00175713", |
00000544 => x"ff1ff06f", |
00000545 => x"fa002783", |
00000546 => x"fe07cee3", |
00000547 => x"faa02223", |
00000548 => x"00008067", |
00000549 => x"ff010113", |
00000550 => x"00812423", |
00000551 => x"01212023", |
00000552 => x"00112623", |
00000553 => x"00912223", |
00000554 => x"00050413", |
00000555 => x"00a00913", |
00000556 => x"00044483", |
00000557 => x"00140413", |
00000558 => x"00049e63", |
00000559 => x"00c12083", |
00000560 => x"00812403", |
00000561 => x"00412483", |
00000562 => x"00012903", |
00000563 => x"01010113", |
00000512 => x"00001637", |
00000513 => x"00758693", |
00000514 => x"00000713", |
00000515 => x"08860613", |
00000516 => x"02000813", |
00000517 => x"00e557b3", |
00000518 => x"00f7f793", |
00000519 => x"00f607b3", |
00000520 => x"0007c783", |
00000521 => x"00470713", |
00000522 => x"fff68693", |
00000523 => x"00f680a3", |
00000524 => x"ff0712e3", |
00000525 => x"00058423", |
00000526 => x"00008067", |
00000527 => x"fa002023", |
00000528 => x"fe002783", |
00000529 => x"00151513", |
00000530 => x"00000713", |
00000531 => x"02a7fe63", |
00000532 => x"000016b7", |
00000533 => x"00000793", |
00000534 => x"ffe68693", |
00000535 => x"04e6e063", |
00000536 => x"fff70713", |
00000537 => x"0035f593", |
00000538 => x"01879793", |
00000539 => x"00e7e7b3", |
00000540 => x"01659593", |
00000541 => x"00b7e7b3", |
00000542 => x"10000737", |
00000543 => x"00e7e7b3", |
00000544 => x"faf02023", |
00000545 => x"00008067", |
00000546 => x"00170713", |
00000547 => x"01071713", |
00000548 => x"40a787b3", |
00000549 => x"01075713", |
00000550 => x"fb5ff06f", |
00000551 => x"ffe78613", |
00000552 => x"0fd67613", |
00000553 => x"00061a63", |
00000554 => x"00375713", |
00000555 => x"00178793", |
00000556 => x"0ff7f793", |
00000557 => x"fa9ff06f", |
00000558 => x"00175713", |
00000559 => x"ff1ff06f", |
00000560 => x"f7dff06f", |
00000561 => x"fa002783", |
00000562 => x"fe07cee3", |
00000563 => x"faa02223", |
00000564 => x"00008067", |
00000565 => x"01249663", |
00000566 => x"00d00513", |
00000567 => x"fa9ff0ef", |
00000568 => x"00048513", |
00000569 => x"fa1ff0ef", |
00000570 => x"fc9ff06f", |
00000571 => x"fa010113", |
00000572 => x"02912a23", |
00000573 => x"04f12a23", |
00000574 => x"000014b7", |
00000575 => x"04410793", |
00000576 => x"02812c23", |
00000577 => x"03212823", |
00000578 => x"03412423", |
00000579 => x"03512223", |
00000580 => x"03612023", |
00000581 => x"01712e23", |
00000582 => x"02112e23", |
00000583 => x"03312623", |
00000584 => x"01812c23", |
00000585 => x"00050413", |
00000586 => x"04b12223", |
00000587 => x"04c12423", |
00000588 => x"04d12623", |
00000589 => x"04e12823", |
00000590 => x"05012c23", |
00000591 => x"05112e23", |
00000592 => x"00f12023", |
00000593 => x"02500a13", |
00000594 => x"00a00a93", |
00000595 => x"07300913", |
00000596 => x"07500b13", |
00000597 => x"07800b93", |
00000598 => x"03848493", |
00000599 => x"00044c03", |
00000600 => x"020c0463", |
00000601 => x"134c1263", |
00000602 => x"00144783", |
00000603 => x"00240993", |
00000604 => x"09278c63", |
00000605 => x"04f96263", |
00000606 => x"06300713", |
00000607 => x"0ae78463", |
00000608 => x"06900713", |
00000609 => x"0ae78c63", |
00000610 => x"03c12083", |
00000611 => x"03812403", |
00000612 => x"03412483", |
00000613 => x"03012903", |
00000614 => x"02c12983", |
00000615 => x"02812a03", |
00000616 => x"02412a83", |
00000617 => x"02012b03", |
00000618 => x"01c12b83", |
00000619 => x"01812c03", |
00000620 => x"06010113", |
00000621 => x"00008067", |
00000622 => x"0b678c63", |
00000623 => x"fd7796e3", |
00000624 => x"00012783", |
00000625 => x"00410693", |
00000626 => x"00068513", |
00000627 => x"0007a583", |
00000628 => x"00478713", |
00000629 => x"00e12023", |
00000630 => x"02000613", |
00000631 => x"00000713", |
00000632 => x"00e5d7b3", |
00000633 => x"00f7f793", |
00000634 => x"00f487b3", |
00000635 => x"0007c783", |
00000636 => x"00470713", |
00000637 => x"fff68693", |
00000638 => x"00f68423", |
00000639 => x"fec712e3", |
00000640 => x"00010623", |
00000641 => x"0140006f", |
00000565 => x"ff1ff06f", |
00000566 => x"ff010113", |
00000567 => x"00812423", |
00000568 => x"01212023", |
00000569 => x"00112623", |
00000570 => x"00912223", |
00000571 => x"00050413", |
00000572 => x"00a00913", |
00000573 => x"00044483", |
00000574 => x"00140413", |
00000575 => x"00049e63", |
00000576 => x"00c12083", |
00000577 => x"00812403", |
00000578 => x"00412483", |
00000579 => x"00012903", |
00000580 => x"01010113", |
00000581 => x"00008067", |
00000582 => x"01249663", |
00000583 => x"00d00513", |
00000584 => x"fa5ff0ef", |
00000585 => x"00048513", |
00000586 => x"f9dff0ef", |
00000587 => x"fc9ff06f", |
00000588 => x"fa9ff06f", |
00000589 => x"fa010113", |
00000590 => x"04f12a23", |
00000591 => x"04410793", |
00000592 => x"02812c23", |
00000593 => x"03212823", |
00000594 => x"03412423", |
00000595 => x"03512223", |
00000596 => x"03612023", |
00000597 => x"01712e23", |
00000598 => x"01812c23", |
00000599 => x"01912a23", |
00000600 => x"02112e23", |
00000601 => x"02912a23", |
00000602 => x"03312623", |
00000603 => x"00050413", |
00000604 => x"04b12223", |
00000605 => x"04c12423", |
00000606 => x"04d12623", |
00000607 => x"04e12823", |
00000608 => x"05012c23", |
00000609 => x"05112e23", |
00000610 => x"00f12023", |
00000611 => x"02500a13", |
00000612 => x"00a00a93", |
00000613 => x"07300913", |
00000614 => x"07500b13", |
00000615 => x"07800b93", |
00000616 => x"06300c13", |
00000617 => x"06900c93", |
00000618 => x"00044483", |
00000619 => x"02048063", |
00000620 => x"0f449a63", |
00000621 => x"00144783", |
00000622 => x"00240993", |
00000623 => x"07278463", |
00000624 => x"04f96063", |
00000625 => x"07878e63", |
00000626 => x"09978863", |
00000627 => x"03c12083", |
00000628 => x"03812403", |
00000629 => x"03412483", |
00000630 => x"03012903", |
00000631 => x"02c12983", |
00000632 => x"02812a03", |
00000633 => x"02412a83", |
00000634 => x"02012b03", |
00000635 => x"01c12b83", |
00000636 => x"01812c03", |
00000637 => x"01412c83", |
00000638 => x"06010113", |
00000639 => x"00008067", |
00000640 => x"09678663", |
00000641 => x"fd7794e3", |
00000642 => x"00012783", |
00000643 => x"0007a503", |
00000644 => x"00478713", |
00000645 => x"00e12023", |
00000646 => x"e7dff0ef", |
00000647 => x"00098413", |
00000648 => x"f3dff06f", |
00000643 => x"00410593", |
00000644 => x"0007a503", |
00000645 => x"00478713", |
00000646 => x"00e12023", |
00000647 => x"de5ff0ef", |
00000648 => x"0640006f", |
00000649 => x"00012783", |
00000650 => x"0007c503", |
00000650 => x"0007a503", |
00000651 => x"00478713", |
00000652 => x"00e12023", |
00000653 => x"e51ff0ef", |
00000654 => x"fe5ff06f", |
00000655 => x"00012783", |
00000656 => x"0007a403", |
00000657 => x"00478713", |
00000658 => x"00e12023", |
00000659 => x"00045863", |
00000660 => x"02d00513", |
00000661 => x"40800433", |
00000662 => x"e2dff0ef", |
00000663 => x"00410593", |
00000664 => x"00040513", |
00000665 => x"c95ff0ef", |
00000666 => x"00410513", |
00000667 => x"fadff06f", |
00000668 => x"00012783", |
00000669 => x"00410593", |
00000670 => x"00478713", |
00000671 => x"0007a503", |
00000672 => x"00e12023", |
00000673 => x"fe1ff06f", |
00000674 => x"015c1663", |
00000675 => x"00d00513", |
00000676 => x"df5ff0ef", |
00000677 => x"00140993", |
00000678 => x"000c0513", |
00000679 => x"f99ff06f", |
00000680 => x"ff010113", |
00000681 => x"c80026f3", |
00000682 => x"c0002773", |
00000683 => x"c80027f3", |
00000684 => x"fed79ae3", |
00000685 => x"00e12023", |
00000686 => x"00f12223", |
00000687 => x"00012503", |
00000688 => x"00412583", |
00000689 => x"01010113", |
00000690 => x"00008067", |
00000691 => x"fe010113", |
00000692 => x"00112e23", |
00000693 => x"00812c23", |
00000694 => x"00912a23", |
00000695 => x"00a12623", |
00000696 => x"fc1ff0ef", |
00000697 => x"00050493", |
00000698 => x"fe002503", |
00000699 => x"00058413", |
00000700 => x"3e800593", |
00000701 => x"11c000ef", |
00000702 => x"00c12603", |
00000703 => x"00000693", |
00000704 => x"00000593", |
00000705 => x"074000ef", |
00000706 => x"009504b3", |
00000707 => x"00a4b533", |
00000708 => x"00858433", |
00000709 => x"00850433", |
00000710 => x"f89ff0ef", |
00000711 => x"fe85eee3", |
00000712 => x"00b41463", |
00000713 => x"fe956ae3", |
00000714 => x"01c12083", |
00000715 => x"01812403", |
00000716 => x"01412483", |
00000717 => x"02010113", |
00000718 => x"00008067", |
00000719 => x"fe802503", |
00000720 => x"01055513", |
00000721 => x"00157513", |
00000722 => x"00008067", |
00000723 => x"f8a02223", |
00000724 => x"00008067", |
00000725 => x"00050613", |
00000726 => x"00000513", |
00000727 => x"0015f693", |
00000728 => x"00068463", |
00000729 => x"00c50533", |
00000730 => x"0015d593", |
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00000970 => x"6863614d", |
00000971 => x"20656e69", |
00000972 => x"65747865", |
00000973 => x"6c616e72", |
00000974 => x"746e6920", |
00000975 => x"75727265", |
00000976 => x"00007470", |
00000977 => x"74736146", |
00000978 => x"746e6920", |
00000979 => x"75727265", |
00000980 => x"00207470", |
00000981 => x"6e6b6e55", |
00000982 => x"206e776f", |
00000983 => x"70617274", |
00000984 => x"75616320", |
00000985 => x"203a6573", |
00000986 => x"00000000", |
00000987 => x"50204020", |
00000988 => x"00003d43", |
00000989 => x"544d202c", |
00000990 => x"3d4c4156", |
00000991 => x"00000000", |
00000992 => x"00000540", |
00000993 => x"00000590", |
00000994 => x"0000059c", |
00000995 => x"000005a8", |
00000996 => x"000005b4", |
00000997 => x"000005c0", |
00000998 => x"000005cc", |
00000999 => x"000005d8", |
00001000 => x"000005e4", |
00001001 => x"00000500", |
00001002 => x"00000500", |
00001003 => x"000005f0", |
00001004 => x"4554523c", |
00001005 => x"4157203e", |
00001006 => x"4e494e52", |
00001007 => x"43202147", |
00001008 => x"43205550", |
00001009 => x"73205253", |
00001010 => x"65747379", |
00001011 => x"6f6e206d", |
00001012 => x"76612074", |
00001013 => x"616c6961", |
00001014 => x"21656c62", |
00001015 => x"522f3c20", |
00001016 => x"003e4554", |
00001017 => x"5241570a", |
00001018 => x"474e494e", |
00001019 => x"57532021", |
00001020 => x"4153495f", |
00001021 => x"65662820", |
00001022 => x"72757461", |
00001023 => x"72207365", |
00001024 => x"69757165", |
00001025 => x"29646572", |
00001026 => x"20737620", |
00001027 => x"495f5748", |
00001028 => x"28204153", |
00001029 => x"74616566", |
00001030 => x"73657275", |
00001031 => x"61766120", |
00001032 => x"62616c69", |
00001033 => x"2029656c", |
00001034 => x"6d73696d", |
00001035 => x"68637461", |
00001036 => x"57530a21", |
00001037 => x"4153495f", |
00001038 => x"30203d20", |
00001039 => x"20782578", |
00001040 => x"6d6f6328", |
00001041 => x"656c6970", |
00001042 => x"6c662072", |
00001043 => x"29736761", |
00001044 => x"5f57480a", |
00001045 => x"20415349", |
00001046 => x"7830203d", |
00001047 => x"28207825", |
00001048 => x"6173696d", |
00001049 => x"72736320", |
00001050 => x"000a0a29", |
00001051 => x"33323130", |
00001052 => x"37363534", |
00001053 => x"42413938", |
00001054 => x"46454443", |
00001055 => x"33323130", |
00001056 => x"37363534", |
00001057 => x"00003938", |
00001058 => x"33323130", |
00001059 => x"37363534", |
00001060 => x"62613938", |
00001061 => x"66656463", |
00001062 => x"00000000", |
others => x"00000000" |
); |
|
/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 987) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 999) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
44,7 → 44,7
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"ee058593", |
00000036 => x"f1058593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
111,13 → 111,13
00000100 => x"00200513", |
00000101 => x"0087f463", |
00000102 => x"00400513", |
00000103 => x"319000ef", |
00000103 => x"349000ef", |
00000104 => x"00100513", |
00000105 => x"3b9000ef", |
00000105 => x"3e9000ef", |
00000106 => x"00005537", |
00000107 => x"00000593", |
00000108 => x"b0050513", |
00000109 => x"1f9000ef", |
00000109 => x"289000ef", |
00000110 => x"1b1000ef", |
00000111 => x"00245793", |
00000112 => x"00a78533", |
133,63 → 133,63
00000122 => x"00000013", |
00000123 => x"00000013", |
00000124 => x"ffff1537", |
00000125 => x"e8850513", |
00000126 => x"265000ef", |
00000125 => x"eb850513", |
00000126 => x"2e9000ef", |
00000127 => x"f1302573", |
00000128 => x"24c000ef", |
00000129 => x"ffff1537", |
00000130 => x"ec050513", |
00000131 => x"251000ef", |
00000130 => x"ef050513", |
00000131 => x"2d5000ef", |
00000132 => x"fe002503", |
00000133 => x"238000ef", |
00000134 => x"ffff1537", |
00000135 => x"ec850513", |
00000136 => x"23d000ef", |
00000135 => x"ef850513", |
00000136 => x"2c1000ef", |
00000137 => x"fe402503", |
00000138 => x"224000ef", |
00000139 => x"ffff1537", |
00000140 => x"ed450513", |
00000141 => x"229000ef", |
00000140 => x"f0450513", |
00000141 => x"2ad000ef", |
00000142 => x"30102573", |
00000143 => x"210000ef", |
00000144 => x"ffff1537", |
00000145 => x"edc50513", |
00000146 => x"215000ef", |
00000145 => x"f0c50513", |
00000146 => x"299000ef", |
00000147 => x"fe802503", |
00000148 => x"ffff14b7", |
00000149 => x"00341413", |
00000150 => x"1f4000ef", |
00000151 => x"ffff1537", |
00000152 => x"ee450513", |
00000153 => x"1f9000ef", |
00000152 => x"f1450513", |
00000153 => x"27d000ef", |
00000154 => x"ff802503", |
00000155 => x"1e0000ef", |
00000156 => x"eec48513", |
00000157 => x"1e9000ef", |
00000156 => x"f1c48513", |
00000157 => x"26d000ef", |
00000158 => x"ff002503", |
00000159 => x"1d0000ef", |
00000160 => x"ffff1537", |
00000161 => x"ef850513", |
00000162 => x"1d5000ef", |
00000161 => x"f2850513", |
00000162 => x"259000ef", |
00000163 => x"ffc02503", |
00000164 => x"1bc000ef", |
00000165 => x"eec48513", |
00000166 => x"1c5000ef", |
00000165 => x"f1c48513", |
00000166 => x"249000ef", |
00000167 => x"ff402503", |
00000168 => x"1ac000ef", |
00000169 => x"ffff1537", |
00000170 => x"f0050513", |
00000171 => x"1b1000ef", |
00000170 => x"f3050513", |
00000171 => x"235000ef", |
00000172 => x"0b9000ef", |
00000173 => x"00a404b3", |
00000174 => x"0084b433", |
00000175 => x"00b40433", |
00000176 => x"fa402783", |
00000177 => x"0207d263", |
00000176 => x"1c5000ef", |
00000177 => x"02050263", |
00000178 => x"ffff1537", |
00000179 => x"f2850513", |
00000180 => x"18d000ef", |
00000181 => x"17d000ef", |
00000179 => x"f5850513", |
00000180 => x"211000ef", |
00000181 => x"0d9000ef", |
00000182 => x"02300793", |
00000183 => x"02f51263", |
00000184 => x"00000513", |
209,13 → 209,13
00000198 => x"07500b93", |
00000199 => x"ffff14b7", |
00000200 => x"ffff1c37", |
00000201 => x"f3490513", |
00000202 => x"135000ef", |
00000203 => x"115000ef", |
00000201 => x"f6490513", |
00000202 => x"1b9000ef", |
00000203 => x"149000ef", |
00000204 => x"00050413", |
00000205 => x"0fd000ef", |
00000206 => x"e4098513", |
00000207 => x"121000ef", |
00000205 => x"11d000ef", |
00000206 => x"e7098513", |
00000207 => x"1a5000ef", |
00000208 => x"fb4400e3", |
00000209 => x"01541863", |
00000210 => x"ffff02b7", |
240,20 → 240,20
00000229 => x"02c000ef", |
00000230 => x"f8dff06f", |
00000231 => x"03f00793", |
00000232 => x"f3cc0513", |
00000232 => x"f6cc0513", |
00000233 => x"00f40463", |
00000234 => x"f5048513", |
00000235 => x"0b1000ef", |
00000234 => x"f8048513", |
00000235 => x"135000ef", |
00000236 => x"f75ff06f", |
00000237 => x"ffff1537", |
00000238 => x"d6450513", |
00000239 => x"0a10006f", |
00000238 => x"d9450513", |
00000239 => x"1250006f", |
00000240 => x"800007b7", |
00000241 => x"0007a783", |
00000242 => x"00079863", |
00000243 => x"ffff1537", |
00000244 => x"dc850513", |
00000245 => x"0890006f", |
00000244 => x"df850513", |
00000245 => x"10d0006f", |
00000246 => x"ff010113", |
00000247 => x"00112623", |
00000248 => x"30047073", |
260,10 → 260,10
00000249 => x"00000013", |
00000250 => x"00000013", |
00000251 => x"ffff1537", |
00000252 => x"de450513", |
00000253 => x"069000ef", |
00000254 => x"fa002783", |
00000255 => x"fe07cee3", |
00000252 => x"e1450513", |
00000253 => x"0ed000ef", |
00000254 => x"069000ef", |
00000255 => x"fe051ee3", |
00000256 => x"ff002783", |
00000257 => x"00078067", |
00000258 => x"0000006f", |
271,17 → 271,17
00000260 => x"00812423", |
00000261 => x"00050413", |
00000262 => x"ffff1537", |
00000263 => x"df450513", |
00000263 => x"e2450513", |
00000264 => x"00112623", |
00000265 => x"039000ef", |
00000265 => x"0bd000ef", |
00000266 => x"03040513", |
00000267 => x"0ff57513", |
00000268 => x"001000ef", |
00000268 => x"021000ef", |
00000269 => x"30047073", |
00000270 => x"00000013", |
00000271 => x"00000013", |
00000272 => x"00100513", |
00000273 => x"119000ef", |
00000273 => x"149000ef", |
00000274 => x"0000006f", |
00000275 => x"fe010113", |
00000276 => x"01212823", |
288,14 → 288,14
00000277 => x"00050913", |
00000278 => x"ffff1537", |
00000279 => x"00912a23", |
00000280 => x"e0c50513", |
00000280 => x"e3c50513", |
00000281 => x"ffff14b7", |
00000282 => x"00812c23", |
00000283 => x"01312623", |
00000284 => x"00112e23", |
00000285 => x"01c00413", |
00000286 => x"7e4000ef", |
00000287 => x"f5c48493", |
00000286 => x"069000ef", |
00000287 => x"f8c48493", |
00000288 => x"ffc00993", |
00000289 => x"008957b3", |
00000290 => x"00f7f793", |
302,7 → 302,7
00000291 => x"00f487b3", |
00000292 => x"0007c503", |
00000293 => x"ffc40413", |
00000294 => x"798000ef", |
00000294 => x"7b8000ef", |
00000295 => x"ff3414e3", |
00000296 => x"01c12083", |
00000297 => x"01812403", |
334,7 → 334,7
00000323 => x"00778793", |
00000324 => x"06f41a63", |
00000325 => x"00000513", |
00000326 => x"029000ef", |
00000326 => x"059000ef", |
00000327 => x"64c000ef", |
00000328 => x"fe002783", |
00000329 => x"0027d793", |
367,13 → 367,13
00000356 => x"00100513", |
00000357 => x"02079863", |
00000358 => x"ffff1537", |
00000359 => x"e0050513", |
00000360 => x"6bc000ef", |
00000359 => x"e3050513", |
00000360 => x"740000ef", |
00000361 => x"00040513", |
00000362 => x"ea5ff0ef", |
00000363 => x"ffff1537", |
00000364 => x"e0850513", |
00000365 => x"6a8000ef", |
00000364 => x"e3850513", |
00000365 => x"72c000ef", |
00000366 => x"34102573", |
00000367 => x"e91ff0ef", |
00000368 => x"00500513", |
382,14 → 382,14
00000371 => x"00000513", |
00000372 => x"00112623", |
00000373 => x"00812423", |
00000374 => x"710000ef", |
00000374 => x"740000ef", |
00000375 => x"09e00513", |
00000376 => x"74c000ef", |
00000376 => x"77c000ef", |
00000377 => x"00000513", |
00000378 => x"744000ef", |
00000378 => x"774000ef", |
00000379 => x"00050413", |
00000380 => x"00000513", |
00000381 => x"714000ef", |
00000381 => x"744000ef", |
00000382 => x"00c12083", |
00000383 => x"0ff47513", |
00000384 => x"00812403", |
399,15 → 399,15
00000388 => x"00112623", |
00000389 => x"00812423", |
00000390 => x"00000513", |
00000391 => x"6cc000ef", |
00000391 => x"6fc000ef", |
00000392 => x"00500513", |
00000393 => x"708000ef", |
00000393 => x"738000ef", |
00000394 => x"00000513", |
00000395 => x"700000ef", |
00000395 => x"730000ef", |
00000396 => x"00050413", |
00000397 => x"00147413", |
00000398 => x"00000513", |
00000399 => x"6cc000ef", |
00000399 => x"6fc000ef", |
00000400 => x"fc041ce3", |
00000401 => x"00c12083", |
00000402 => x"00812403", |
416,13 → 416,13
00000405 => x"ff010113", |
00000406 => x"00000513", |
00000407 => x"00112623", |
00000408 => x"688000ef", |
00000408 => x"6b8000ef", |
00000409 => x"00600513", |
00000410 => x"6c4000ef", |
00000410 => x"6f4000ef", |
00000411 => x"00c12083", |
00000412 => x"00000513", |
00000413 => x"01010113", |
00000414 => x"6900006f", |
00000414 => x"6c00006f", |
00000415 => x"ff010113", |
00000416 => x"00812423", |
00000417 => x"00050413", |
429,30 → 429,30
00000418 => x"01055513", |
00000419 => x"0ff57513", |
00000420 => x"00112623", |
00000421 => x"698000ef", |
00000421 => x"6c8000ef", |
00000422 => x"00845513", |
00000423 => x"0ff57513", |
00000424 => x"68c000ef", |
00000424 => x"6bc000ef", |
00000425 => x"0ff47513", |
00000426 => x"00812403", |
00000427 => x"00c12083", |
00000428 => x"01010113", |
00000429 => x"6780006f", |
00000429 => x"6a80006f", |
00000430 => x"ff010113", |
00000431 => x"00812423", |
00000432 => x"00050413", |
00000433 => x"00000513", |
00000434 => x"00112623", |
00000435 => x"61c000ef", |
00000435 => x"64c000ef", |
00000436 => x"00300513", |
00000437 => x"658000ef", |
00000437 => x"688000ef", |
00000438 => x"00040513", |
00000439 => x"fa1ff0ef", |
00000440 => x"00000513", |
00000441 => x"648000ef", |
00000441 => x"678000ef", |
00000442 => x"00050413", |
00000443 => x"00000513", |
00000444 => x"618000ef", |
00000444 => x"648000ef", |
00000445 => x"00c12083", |
00000446 => x"0ff47513", |
00000447 => x"00812403", |
471,7 → 471,7
00000460 => x"00000413", |
00000461 => x"00400a13", |
00000462 => x"02091e63", |
00000463 => x"504000ef", |
00000463 => x"538000ef", |
00000464 => x"00a481a3", |
00000465 => x"00140413", |
00000466 => x"fff48493", |
513,8 → 513,8
00000502 => x"04079663", |
00000503 => x"02041863", |
00000504 => x"ffff1537", |
00000505 => x"e1050513", |
00000506 => x"474000ef", |
00000505 => x"e4050513", |
00000506 => x"4f8000ef", |
00000507 => x"008005b7", |
00000508 => x"00040513", |
00000509 => x"f15ff0ef", |
524,8 → 524,8
00000513 => x"00000513", |
00000514 => x"01c0006f", |
00000515 => x"ffff1537", |
00000516 => x"e3050513", |
00000517 => x"448000ef", |
00000516 => x"e6050513", |
00000517 => x"4cc000ef", |
00000518 => x"db1ff0ef", |
00000519 => x"fc0518e3", |
00000520 => x"00300513", |
550,8 → 550,8
00000539 => x"00200513", |
00000540 => x"fa049ae3", |
00000541 => x"ffff1537", |
00000542 => x"e3c50513", |
00000543 => x"3e0000ef", |
00000542 => x"e6c50513", |
00000543 => x"464000ef", |
00000544 => x"02c12083", |
00000545 => x"02812403", |
00000546 => x"800007b7", |
578,8 → 578,8
00000567 => x"00112623", |
00000568 => x"ea1ff0ef", |
00000569 => x"ffff1537", |
00000570 => x"e4050513", |
00000571 => x"370000ef", |
00000570 => x"e7050513", |
00000571 => x"3f4000ef", |
00000572 => x"ad1ff0ef", |
00000573 => x"0000006f", |
00000574 => x"ff010113", |
590,15 → 590,15
00000579 => x"00050493", |
00000580 => x"d45ff0ef", |
00000581 => x"00000513", |
00000582 => x"3d0000ef", |
00000582 => x"400000ef", |
00000583 => x"00200513", |
00000584 => x"40c000ef", |
00000584 => x"43c000ef", |
00000585 => x"00048513", |
00000586 => x"d55ff0ef", |
00000587 => x"00040513", |
00000588 => x"3fc000ef", |
00000588 => x"42c000ef", |
00000589 => x"00000513", |
00000590 => x"3d0000ef", |
00000590 => x"400000ef", |
00000591 => x"00812403", |
00000592 => x"00c12083", |
00000593 => x"00412483", |
632,13 → 632,13
00000621 => x"00050413", |
00000622 => x"c9dff0ef", |
00000623 => x"00000513", |
00000624 => x"328000ef", |
00000624 => x"358000ef", |
00000625 => x"0d800513", |
00000626 => x"364000ef", |
00000626 => x"394000ef", |
00000627 => x"00040513", |
00000628 => x"cadff0ef", |
00000629 => x"00000513", |
00000630 => x"330000ef", |
00000630 => x"360000ef", |
00000631 => x"00812403", |
00000632 => x"00c12083", |
00000633 => x"01010113", |
655,7 → 655,7
00000644 => x"01512223", |
00000645 => x"02041863", |
00000646 => x"ffff1537", |
00000647 => x"dc850513", |
00000647 => x"df850513", |
00000648 => x"01812403", |
00000649 => x"01c12083", |
00000650 => x"01412483", |
664,23 → 664,23
00000653 => x"00812a03", |
00000654 => x"00412a83", |
00000655 => x"02010113", |
00000656 => x"21c0006f", |
00000656 => x"2a00006f", |
00000657 => x"ffff1537", |
00000658 => x"e4450513", |
00000659 => x"210000ef", |
00000658 => x"e7450513", |
00000659 => x"294000ef", |
00000660 => x"00040513", |
00000661 => x"9f9ff0ef", |
00000662 => x"ffff1537", |
00000663 => x"e5050513", |
00000664 => x"1fc000ef", |
00000663 => x"e8050513", |
00000664 => x"280000ef", |
00000665 => x"00800537", |
00000666 => x"9e5ff0ef", |
00000667 => x"ffff1537", |
00000668 => x"e6c50513", |
00000669 => x"1e8000ef", |
00000670 => x"1c8000ef", |
00000668 => x"e9c50513", |
00000669 => x"26c000ef", |
00000670 => x"1fc000ef", |
00000671 => x"00050493", |
00000672 => x"1b0000ef", |
00000672 => x"1d0000ef", |
00000673 => x"07900793", |
00000674 => x"0af49e63", |
00000675 => x"b3dff0ef", |
688,9 → 688,9
00000677 => x"00300513", |
00000678 => x"975ff0ef", |
00000679 => x"ffff1537", |
00000680 => x"e7850513", |
00000680 => x"ea850513", |
00000681 => x"01045493", |
00000682 => x"1b4000ef", |
00000682 => x"238000ef", |
00000683 => x"00148493", |
00000684 => x"00800937", |
00000685 => x"fff00993", |
718,7 → 718,7
00000707 => x"412005b3", |
00000708 => x"e41ff0ef", |
00000709 => x"ffff1537", |
00000710 => x"e3c50513", |
00000710 => x"e6c50513", |
00000711 => x"f05ff06f", |
00000712 => x"00090513", |
00000713 => x"e85ff0ef", |
755,246 → 755,258
00000744 => x"00a6a023", |
00000745 => x"00b6a223", |
00000746 => x"00008067", |
00000747 => x"fa002023", |
00000748 => x"fe002783", |
00000749 => x"00151513", |
00000750 => x"00000713", |
00000751 => x"02a7fe63", |
00000752 => x"000016b7", |
00000753 => x"00000793", |
00000754 => x"ffe68693", |
00000755 => x"04e6e063", |
00000756 => x"fff70713", |
00000757 => x"0035f593", |
00000758 => x"01879793", |
00000759 => x"00e7e7b3", |
00000760 => x"01659593", |
00000761 => x"00b7e7b3", |
00000762 => x"10000737", |
00000763 => x"00e7e7b3", |
00000764 => x"faf02023", |
00000765 => x"00008067", |
00000766 => x"00170713", |
00000767 => x"01071713", |
00000768 => x"40a787b3", |
00000769 => x"01075713", |
00000770 => x"fb5ff06f", |
00000771 => x"ffe78613", |
00000772 => x"0fd67613", |
00000773 => x"00061a63", |
00000774 => x"00375713", |
00000775 => x"00178793", |
00000776 => x"0ff7f793", |
00000777 => x"fa9ff06f", |
00000778 => x"00175713", |
00000779 => x"ff1ff06f", |
00000780 => x"fa002783", |
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00000781 => x"00175713", |
00000782 => x"ff1ff06f", |
00000783 => x"f7dff06f", |
00000784 => x"fa002783", |
00000785 => x"fe07cee3", |
00000786 => x"faa02223", |
00000787 => x"00008067", |
00000788 => x"fa402503", |
00000789 => x"0ff57513", |
00000790 => x"00008067", |
00000791 => x"ff010113", |
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00000807 => x"00050413", |
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00000812 => x"00c12083", |
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00000818 => x"01249663", |
00000819 => x"00d00513", |
00000820 => x"f71ff0ef", |
00000821 => x"00048513", |
00000822 => x"f69ff0ef", |
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00000830 => x"00c56533", |
00000831 => x"00959593", |
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00000833 => x"00b56533", |
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00000838 => x"fa800713", |
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00000840 => x"00757793", |
00000841 => x"00100513", |
00000842 => x"00f51533", |
00000843 => x"00d56533", |
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00000845 => x"00008067", |
00000846 => x"fa800713", |
00000847 => x"00072683", |
00000848 => x"00757513", |
00000849 => x"00100793", |
00000850 => x"00a797b3", |
00000851 => x"fff7c793", |
00000852 => x"00d7f7b3", |
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00000854 => x"00008067", |
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00000856 => x"00008067", |
00000857 => x"69617641", |
00000858 => x"6c62616c", |
00000859 => x"4d432065", |
00000860 => x"0a3a7344", |
00000861 => x"203a6820", |
00000862 => x"706c6548", |
00000863 => x"3a72200a", |
00000864 => x"73655220", |
00000865 => x"74726174", |
00000866 => x"3a75200a", |
00000867 => x"6c705520", |
00000868 => x"0a64616f", |
00000869 => x"203a7320", |
00000870 => x"726f7453", |
00000871 => x"6f742065", |
00000872 => x"616c6620", |
00000873 => x"200a6873", |
00000874 => x"4c203a6c", |
00000875 => x"2064616f", |
00000876 => x"6d6f7266", |
00000877 => x"616c6620", |
00000878 => x"200a6873", |
00000879 => x"45203a65", |
00000880 => x"75636578", |
00000881 => x"00006574", |
00000882 => x"65206f4e", |
00000883 => x"75636578", |
00000884 => x"6c626174", |
00000885 => x"76612065", |
00000886 => x"616c6961", |
00000887 => x"2e656c62", |
00000888 => x"00000000", |
00000889 => x"746f6f42", |
00000890 => x"2e676e69", |
00000891 => x"0a0a2e2e", |
00000892 => x"00000000", |
00000893 => x"52450a07", |
00000894 => x"5f524f52", |
00000895 => x"00000000", |
00000896 => x"58450a0a", |
00000897 => x"00282043", |
00000898 => x"20402029", |
00000899 => x"00007830", |
00000900 => x"69617741", |
00000901 => x"676e6974", |
00000902 => x"6f656e20", |
00000903 => x"32337672", |
00000904 => x"6578655f", |
00000905 => x"6e69622e", |
00000906 => x"202e2e2e", |
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00000856 => x"fa802783", |
00000857 => x"fe07cee3", |
00000858 => x"fac02503", |
00000859 => x"00008067", |
00000860 => x"f8400713", |
00000861 => x"00072683", |
00000862 => x"00100793", |
00000863 => x"00a797b3", |
00000864 => x"00d7c7b3", |
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00000866 => x"00008067", |
00000867 => x"f8a02223", |
00000868 => x"00008067", |
00000869 => x"69617641", |
00000870 => x"6c62616c", |
00000871 => x"4d432065", |
00000872 => x"0a3a7344", |
00000873 => x"203a6820", |
00000874 => x"706c6548", |
00000875 => x"3a72200a", |
00000876 => x"73655220", |
00000877 => x"74726174", |
00000878 => x"3a75200a", |
00000879 => x"6c705520", |
00000880 => x"0a64616f", |
00000881 => x"203a7320", |
00000882 => x"726f7453", |
00000883 => x"6f742065", |
00000884 => x"616c6620", |
00000885 => x"200a6873", |
00000886 => x"4c203a6c", |
00000887 => x"2064616f", |
00000888 => x"6d6f7266", |
00000889 => x"616c6620", |
00000890 => x"200a6873", |
00000891 => x"45203a65", |
00000892 => x"75636578", |
00000893 => x"00006574", |
00000894 => x"65206f4e", |
00000895 => x"75636578", |
00000896 => x"6c626174", |
00000897 => x"76612065", |
00000898 => x"616c6961", |
00000899 => x"2e656c62", |
00000900 => x"00000000", |
00000901 => x"746f6f42", |
00000902 => x"2e676e69", |
00000903 => x"0a0a2e2e", |
00000904 => x"00000000", |
00000905 => x"52450a07", |
00000906 => x"5f524f52", |
00000907 => x"00000000", |
00000908 => x"64616f4c", |
00000909 => x"2e676e69", |
00000910 => x"00202e2e", |
00000911 => x"00004b4f", |
00000912 => x"0000000a", |
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00000914 => x"78302065", |
00000915 => x"00000000", |
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00000917 => x"74207365", |
00000918 => x"5053206f", |
00000919 => x"6c662049", |
00000920 => x"20687361", |
00000921 => x"78302040", |
00000922 => x"00000000", |
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00000924 => x"20296e2f", |
00000925 => x"00000000", |
00000926 => x"616c460a", |
00000927 => x"6e696873", |
00000928 => x"2e2e2e67", |
00000929 => x"00000020", |
00000930 => x"0a0a0a0a", |
00000931 => x"4e203c3c", |
00000932 => x"56524f45", |
00000933 => x"42203233", |
00000934 => x"6c746f6f", |
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00000937 => x"4c420a0a", |
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00000943 => x"00002020", |
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00000945 => x"0020203a", |
00000946 => x"0a7a4820", |
00000947 => x"52455355", |
00000948 => x"0000203a", |
00000949 => x"53494d0a", |
00000950 => x"00203a41", |
00000951 => x"4f52500a", |
00000952 => x"00203a43", |
00000953 => x"454d490a", |
00000954 => x"00203a4d", |
00000955 => x"74796220", |
00000956 => x"40207365", |
00000957 => x"00000020", |
00000958 => x"454d440a", |
00000959 => x"00203a4d", |
00000960 => x"75410a0a", |
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00000962 => x"6920746f", |
00000963 => x"7338206e", |
00000964 => x"7250202e", |
00000965 => x"20737365", |
00000966 => x"2079656b", |
00000967 => x"61206f74", |
00000968 => x"74726f62", |
00000969 => x"00000a2e", |
00000970 => x"726f6241", |
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00000972 => x"00000a0a", |
00000973 => x"444d430a", |
00000974 => x"00203e3a", |
00000975 => x"53207962", |
00000976 => x"68706574", |
00000977 => x"4e206e61", |
00000978 => x"69746c6f", |
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00000980 => x"61766e49", |
00000981 => x"2064696c", |
00000982 => x"00444d43", |
00000983 => x"33323130", |
00000984 => x"37363534", |
00000985 => x"42413938", |
00000986 => x"46454443", |
00000908 => x"58450a0a", |
00000909 => x"00282043", |
00000910 => x"20402029", |
00000911 => x"00007830", |
00000912 => x"69617741", |
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00000914 => x"6f656e20", |
00000915 => x"32337672", |
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00000917 => x"6e69622e", |
00000918 => x"202e2e2e", |
00000919 => x"00000000", |
00000920 => x"64616f4c", |
00000921 => x"2e676e69", |
00000922 => x"00202e2e", |
00000923 => x"00004b4f", |
00000924 => x"0000000a", |
00000925 => x"74697257", |
00000926 => x"78302065", |
00000927 => x"00000000", |
00000928 => x"74796220", |
00000929 => x"74207365", |
00000930 => x"5053206f", |
00000931 => x"6c662049", |
00000932 => x"20687361", |
00000933 => x"78302040", |
00000934 => x"00000000", |
00000935 => x"7928203f", |
00000936 => x"20296e2f", |
00000937 => x"00000000", |
00000938 => x"616c460a", |
00000939 => x"6e696873", |
00000940 => x"2e2e2e67", |
00000941 => x"00000020", |
00000942 => x"0a0a0a0a", |
00000943 => x"4e203c3c", |
00000944 => x"56524f45", |
00000945 => x"42203233", |
00000946 => x"6c746f6f", |
00000947 => x"6564616f", |
00000948 => x"3e3e2072", |
00000949 => x"4c420a0a", |
00000950 => x"203a5644", |
00000951 => x"20626546", |
00000952 => x"32203731", |
00000953 => x"0a313230", |
00000954 => x"3a565748", |
00000955 => x"00002020", |
00000956 => x"4b4c430a", |
00000957 => x"0020203a", |
00000958 => x"0a7a4820", |
00000959 => x"52455355", |
00000960 => x"0000203a", |
00000961 => x"53494d0a", |
00000962 => x"00203a41", |
00000963 => x"4f52500a", |
00000964 => x"00203a43", |
00000965 => x"454d490a", |
00000966 => x"00203a4d", |
00000967 => x"74796220", |
00000968 => x"40207365", |
00000969 => x"00000020", |
00000970 => x"454d440a", |
00000971 => x"00203a4d", |
00000972 => x"75410a0a", |
00000973 => x"6f626f74", |
00000974 => x"6920746f", |
00000975 => x"7338206e", |
00000976 => x"7250202e", |
00000977 => x"20737365", |
00000978 => x"2079656b", |
00000979 => x"61206f74", |
00000980 => x"74726f62", |
00000981 => x"00000a2e", |
00000982 => x"726f6241", |
00000983 => x"2e646574", |
00000984 => x"00000a0a", |
00000985 => x"444d430a", |
00000986 => x"00203e3a", |
00000987 => x"53207962", |
00000988 => x"68706574", |
00000989 => x"4e206e61", |
00000990 => x"69746c6f", |
00000991 => x"0000676e", |
00000992 => x"61766e49", |
00000993 => x"2064696c", |
00000994 => x"00444d43", |
00000995 => x"33323130", |
00000996 => x"37363534", |
00000997 => x"42413938", |
00000998 => x"46454443", |
others => x"00000000" |
); |
|
/neorv32_cfs.vhd
57,7 → 57,6
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs |
189,12 → 188,10
-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register> |
-- for issueing commands and a <status register> for status information. |
-- |
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal. |
-- If no ACK is generated, the bus access will time out and cause a store bus access fault exception. This exception can also be immediatly |
-- triggered by setting err_o high for one cycle (only during a valid bus access). |
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later |
-- if the module needs additional time; the maximumx latency until an unacknwoledged access will trigger a bus exception is defined via the package's |
-- gloabl "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception. |
|
err_o <= '0'; -- not used for this minimal example |
|
-- Host access: Read and write access to the interface registers + bus transfer acknowledge. |
-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not |
-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged. |
/neorv32_package.vhd
60,7 → 60,7
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050104"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW |
70,6 → 70,7
function index_size_f(input : natural) return natural; |
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural; |
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector; |
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string; |
function bool_to_ulogic_f(cond : boolean) return std_ulogic; |
function or_all_f(a : std_ulogic_vector) return std_ulogic; |
function and_all_f(a : std_ulogic_vector) return std_ulogic; |
164,11 → 165,11
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98"; |
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C"; |
|
-- Universal Asynchronous Receiver/Transmitter (UART) -- |
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address |
constant uart_size_c : natural := 2*4; -- module's address space in bytes |
constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; |
constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4"; |
-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART -- |
constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address |
constant uart0_size_c : natural := 2*4; -- module's address space in bytes |
constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; |
constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4"; |
|
-- Serial Peripheral Interface (SPI) -- |
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address |
196,9 → 197,15
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; |
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; |
|
-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART -- |
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address |
constant uart1_size_c : natural := 2*4; -- module's address space in bytes |
constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; |
constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4"; |
|
-- reserved -- |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address |
--constant reserved_size_c : natural := 4*4; -- module's address space in bytes |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address |
--constant reserved_size_c : natural := 2*4; -- module's address space in bytes |
|
-- System Information Memory (SYSINFO) -- |
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address |
842,7 → 849,8
-- Processor peripherals -- |
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
874,9 → 882,12
-- GPIO (available if IO_GPIO_EN = true) -- |
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input |
-- UART (available if IO_UART_EN = true) -- |
uart_txd_o : out std_ulogic; -- UART send data |
uart_rxd_i : in std_ulogic := '0'; -- UART receive data |
-- primary UART0 (available if IO_UART0_EN = true) -- |
uart0_txd_o : out std_ulogic; -- UART0 send data |
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data |
-- secondary UART1 (available if IO_UART1_EN = true) -- |
uart1_txd_o : out std_ulogic; -- UART1 send data |
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data |
-- SPI (available if IO_SPI_EN = true) -- |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
895,7 → 906,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
1407,6 → 1418,9
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ---------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_uart |
generic ( |
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1) |
); |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
1571,7 → 1585,6
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs |
1631,7 → 1644,8
-- Processor peripherals -- |
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
1688,8 → 1702,19
end if; |
end function cond_sel_stdulogicvector_f; |
|
-- Function: Convert BOOL to STD_ULOGIC --------------------------------------------------- |
-- Function: Conditional select string ---------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is |
begin |
if (cond = true) then |
return val_t; |
else |
return val_f; |
end if; |
end function cond_sel_string_f; |
|
-- Function: Convert bool to std_ulogic --------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function bool_to_ulogic_f(cond : boolean) return std_ulogic is |
begin |
if (cond = true) then |
/neorv32_spi.vhd
2,7 → 2,7
-- # << NEORV32 - Serial Peripheral Interface Controller (SPI) >> # |
-- # ********************************************************************************************* # |
-- # Frame format: 8/16/24/32-bit receive/transmit data, always MSB first, 2 clock modes, # |
-- # 8 clock speeds (derived from system clock), 8 dedicated chip-select lines (low-active). # |
-- # 8 pre-scaled clocks (derived from system clock), 8 dedicated chip-select lines (low-active). # |
-- # Interrupt: SPI_transfer_done # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
/neorv32_sysinfo.vhd
65,7 → 65,8
-- Processor peripherals -- |
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
133,7 → 134,7
-- IO -- |
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented? |
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented? |
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_EN); -- universal asynchronous receiver/transmitter (UART) implemented? |
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented? |
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented? |
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented? |
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN); -- pulse-width modulation unit (PWM) implemented? |
141,8 → 142,9
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented? |
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented? |
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_NCO_EN); -- numerically-controlled oscillator (NCO) implemented? |
sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented? |
-- |
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved |
sysinfo_mem(2)(31 downto 27) <= (others => '0'); -- reserved |
|
-- SYSINFO(3): Cache configuration -- |
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) |
/neorv32_top.vhd
52,6 → 52,7
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) |
|
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions? |
61,32 → 62,41
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
|
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
|
-- Physical Memory Protection (PMP) -- |
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
|
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) |
|
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
|
-- Internal Data memory -- |
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
|
-- Internal Cache memory -- |
ICACHE_EN : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 |
|
-- External memory interface -- |
MEM_EXT_EN : boolean := false; -- implement external memory bus interface? |
|
-- Processor peripherals -- |
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
100,6 → 110,7
-- Global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) -- |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
112,34 → 123,48
wb_lock_o : out std_ulogic; -- locked/exclusive bus access |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
|
-- GPIO (available if IO_GPIO_EN = true) -- |
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input |
-- UART (available if IO_UART_EN = true) -- |
uart_txd_o : out std_ulogic; -- UART send data |
uart_rxd_i : in std_ulogic := '0'; -- UART receive data |
|
-- primary UART0 (available if IO_UART0_EN = true) -- |
uart0_txd_o : out std_ulogic; -- UART0 send data |
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data |
|
-- secondary UART1 (available if IO_UART1_EN = true) -- |
uart1_txd_o : out std_ulogic; -- UART1 send data |
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data |
|
-- SPI (available if IO_SPI_EN = true) -- |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select |
|
-- TWI (available if IO_TWI_EN = true) -- |
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
|
-- PWM (available if IO_PWM_EN = true) -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CFS inputs conduit |
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CFS outputs conduit |
|
-- NCO output (available if IO_NCO_EN = true) -- |
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels |
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
|
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels |
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
172,14 → 197,16
signal clk_div : std_ulogic_vector(11 downto 0); |
signal clk_div_ff : std_ulogic_vector(11 downto 0); |
signal clk_gen : std_ulogic_vector(07 downto 0); |
signal clk_gen_en : std_ulogic_vector(07 downto 0); |
-- |
signal wdt_cg_en : std_ulogic; |
signal uart_cg_en : std_ulogic; |
signal spi_cg_en : std_ulogic; |
signal twi_cg_en : std_ulogic; |
signal pwm_cg_en : std_ulogic; |
signal cfs_cg_en : std_ulogic; |
signal nco_cg_en : std_ulogic; |
signal wdt_cg_en : std_ulogic; |
signal uart0_cg_en : std_ulogic; |
signal uart1_cg_en : std_ulogic; |
signal spi_cg_en : std_ulogic; |
signal twi_cg_en : std_ulogic; |
signal pwm_cg_en : std_ulogic; |
signal cfs_cg_en : std_ulogic; |
signal nco_cg_en : std_ulogic; |
|
-- bus interface -- |
type bus_interface_t is record |
218,8 → 245,10
signal gpio_ack : std_ulogic; |
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal mtime_ack : std_ulogic; |
signal uart_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal uart_ack : std_ulogic; |
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal uart0_ack : std_ulogic; |
signal uart1_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal uart1_ack : std_ulogic; |
signal spi_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal spi_ack : std_ulogic; |
signal twi_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
231,7 → 260,6
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal trng_ack : std_ulogic; |
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal cfs_err : std_ulogic; |
signal cfs_ack : std_ulogic; |
signal nco_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal nco_ack : std_ulogic; |
244,14 → 272,16
signal fast_irq : std_ulogic_vector(15 downto 0); |
signal fast_irq_ack : std_ulogic_vector(15 downto 0); |
-- |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart_rxd_irq : std_ulogic; |
signal uart_txd_irq : std_ulogic; |
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
signal cfs_irq : std_ulogic; |
signal cfs_irq_ack : std_ulogic; |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart0_rxd_irq : std_ulogic; |
signal uart0_txd_irq : std_ulogic; |
signal uart1_rxd_irq : std_ulogic; |
signal uart1_txd_irq : std_ulogic; |
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
signal cfs_irq : std_ulogic; |
signal cfs_irq_ack : std_ulogic; |
|
-- misc -- |
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME |
319,9 → 349,18
if (sys_rstn = '0') then |
clk_div <= (others => '0'); |
clk_div_ff <= (others => '0'); |
clk_gen_en <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- fresh clocks anyone? -- |
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfs_cg_en or nco_cg_en) = '1') then |
clk_gen_en(0) <= wdt_cg_en; |
clk_gen_en(1) <= uart0_cg_en; |
clk_gen_en(2) <= uart1_cg_en; |
clk_gen_en(3) <= spi_cg_en; |
clk_gen_en(4) <= twi_cg_en; |
clk_gen_en(5) <= pwm_cg_en; |
clk_gen_en(6) <= cfs_cg_en; |
clk_gen_en(7) <= nco_cg_en; |
if (or_all_f(clk_gen_en) = '1') then |
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1); |
end if; |
clk_div_ff <= clk_div; |
421,24 → 460,24
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- fast interrupts - processor-internal -- |
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout |
fast_irq(01) <= '0'; -- reserved |
fast_irq(02) <= cfs_irq; -- custom functions subsystem |
fast_irq(03) <= uart_rxd_irq; -- UART data received |
fast_irq(04) <= uart_txd_irq; -- UART transmission done |
fast_irq(05) <= spi_irq; -- SPI transmission done |
fast_irq(06) <= twi_irq; -- TWI transmission done |
fast_irq(07) <= gpio_irq; -- GPIO pin-change |
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout |
fast_irq(01) <= cfs_irq; -- custom functions subsystem |
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received |
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done |
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received |
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done |
fast_irq(06) <= spi_irq; -- SPI transmission done |
fast_irq(07) <= twi_irq; -- TWI transmission done |
fast_irq(08) <= gpio_irq; -- GPIO pin-change |
fast_irq(09) <= '0'; -- reserved |
|
-- fast interrupts - platform level (for custom use) -- |
fast_irq(08) <= soc_firq_i(0); |
fast_irq(09) <= soc_firq_i(1); |
fast_irq(10) <= soc_firq_i(2); |
fast_irq(11) <= soc_firq_i(3); |
fast_irq(12) <= soc_firq_i(4); |
fast_irq(13) <= soc_firq_i(5); |
fast_irq(14) <= soc_firq_i(6); |
fast_irq(15) <= soc_firq_i(7); |
fast_irq(10) <= soc_firq_i(0); |
fast_irq(11) <= soc_firq_i(1); |
fast_irq(12) <= soc_firq_i(2); |
fast_irq(13) <= soc_firq_i(3); |
fast_irq(14) <= soc_firq_i(4); |
fast_irq(15) <= soc_firq_i(5); |
|
-- IRQ acknowledge -- |
cfs_irq_ack <= fast_irq_ack(2); |
547,15 → 586,15
); |
|
-- processor bus: CPU transfer data input -- |
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or |
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or sysinfo_rdata); |
|
-- processor bus: CPU transfer ACK input -- |
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or |
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or |
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or sysinfo_ack); |
|
-- processor bus: CPU transfer data bus error input -- |
p_bus.err <= wishbone_err or cfs_err; |
p_bus.err <= wishbone_err; |
|
-- current CPU privilege level -- |
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv |
733,7 → 772,6
data_i => p_bus.wdata, -- data in |
data_o => cfs_rdata, -- data out |
ack_o => cfs_ack, -- transfer acknowledge |
err_o => cfs_err, -- transfer error |
-- clock generator -- |
clkgen_en_o => cfs_cg_en, -- enable clock generator |
clkgen_i => clk_gen, -- "clock" inputs |
752,7 → 790,6
if (IO_CFS_EN = false) generate |
cfs_rdata <= (others => '0'); |
cfs_ack <= '0'; |
cfs_err <= '0'; |
cfs_cg_en <= '0'; |
cfs_irq <= '0'; |
cfs_out_o <= (others => '0'); |
855,11 → 892,14
end generate; |
|
|
-- Universal Asynchronous Receiver/Transmitter (UART) ------------------------------------- |
-- Universal Asynchronous Receiver/Transmitter 0, Primary UART (UART0) -------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_uart_inst_true: |
if (IO_UART_EN = true) generate |
neorv32_uart_inst: neorv32_uart |
neorv32_uart0_inst_true: |
if (IO_UART0_EN = true) generate |
neorv32_uart0_inst: neorv32_uart |
generic map ( |
UART_PRIMARY => true -- true = primary UART (UART0), false = secondary UART (UART1) |
) |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
867,31 → 907,71
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
data_o => uart0_rdata, -- data out |
ack_o => uart0_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => uart_cg_en, -- enable clock generator |
clkgen_en_o => uart0_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
uart_txd_o => uart_txd_o, |
uart_rxd_i => uart_rxd_i, |
uart_txd_o => uart0_txd_o, |
uart_rxd_i => uart0_rxd_i, |
-- interrupts -- |
irq_rxd_o => uart_rxd_irq, -- uart data received interrupt |
irq_txd_o => uart_txd_irq -- uart transmission done interrupt |
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt |
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt |
); |
end generate; |
|
neorv32_uart_inst_false: |
if (IO_UART_EN = false) generate |
uart_rdata <= (others => '0'); |
uart_ack <= '0'; |
uart_txd_o <= '0'; |
uart_cg_en <= '0'; |
uart_rxd_irq <= '0'; |
uart_txd_irq <= '0'; |
neorv32_uart0_inst_false: |
if (IO_UART0_EN = false) generate |
uart0_rdata <= (others => '0'); |
uart0_ack <= '0'; |
uart0_txd_o <= '0'; |
uart0_cg_en <= '0'; |
uart0_rxd_irq <= '0'; |
uart0_txd_irq <= '0'; |
end generate; |
|
|
-- Universal Asynchronous Receiver/Transmitter 1, Secondary UART (UART1) ------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_uart1_inst_true: |
if (IO_UART1_EN = true) generate |
neorv32_uart1_inst: neorv32_uart |
generic map ( |
UART_PRIMARY => false -- true = primary UART (UART0), false = secondary UART (UART1) |
) |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => uart1_rdata, -- data out |
ack_o => uart1_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => uart1_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
uart_txd_o => uart1_txd_o, |
uart_rxd_i => uart1_rxd_i, |
-- interrupts -- |
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt |
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt |
); |
end generate; |
|
neorv32_uart1_inst_false: |
if (IO_UART1_EN = false) generate |
uart1_rdata <= (others => '0'); |
uart1_ack <= '0'; |
uart1_txd_o <= '0'; |
uart1_cg_en <= '0'; |
uart1_rxd_irq <= '0'; |
uart1_txd_irq <= '0'; |
end generate; |
|
|
-- Serial Peripheral Interface (SPI) ------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_spi_inst_true: |
1078,7 → 1158,8
-- Processor peripherals -- |
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? |
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? |
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? |
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)? |
/neorv32_uart.vhd
1,17 → 1,23
-- ################################################################################################# |
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> # |
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> # |
-- # ********************************************************************************************* # |
-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, # |
-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. # |
-- # Interrupt: UART_RX_available or UART_TX_done # |
-- # # |
-- # UART0 / UART1: # |
-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the # |
-- # interface register addresses and simulation output setting for UART0 (UART_PRIMARY = true) # |
-- # or UART1 (UART_PRIMARY = false). # |
-- # # |
-- # SIMULATION: # |
-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write # |
-- # access to the TX register will not trigger any UART activity. Instead, the written data is # |
-- # output to the simulation environment. The lowest 8 bits of the written data are printed as # |
-- # ASCII char to the simulator console. This char is also stored to a text file # |
-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char # |
-- # encoded value to text file "neorv32.uart.sim_mode.data.out". # |
-- # ASCII char to the simulator console. # |
-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 # |
-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value # |
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
53,6 → 59,9
use std.textio.all; -- obviously only for simulation |
|
entity neorv32_uart is |
generic ( |
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1) |
); |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
76,14 → 85,24
|
architecture neorv32_uart_rtl of neorv32_uart is |
|
-- interface configuration for UART0 / UART1 -- |
constant uart_id_base_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c); |
constant uart_id_size_c : natural := cond_sel_natural_f( UART_PRIMARY, uart0_size_c, uart1_size_c); |
constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c); |
constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c); |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(uart_id_size_c); -- low address boundary bit |
|
-- simulation output configuration -- |
constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled |
constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled |
constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit |
-- simulation output file configuration -- |
constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out"); |
constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out"); |
|
-- accessible regs -- |
signal ctrl : std_ulogic_vector(31 downto 0); |
97,7 → 116,6
constant ctrl_uart_baud05_c : natural := 5; -- r/w: UART baud config bit 5 |
constant ctrl_uart_baud06_c : natural := 6; -- r/w: UART baud config bit 6 |
constant ctrl_uart_baud07_c : natural := 7; -- r/w: UART baud config bit 7 |
-- |
constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8 |
constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9 |
constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10 |
161,8 → 179,8
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= uart_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_id_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= uart_id_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
wr_en <= acc_en and wren_i; |
rd_en <= acc_en and rden_i; |
|
175,7 → 193,7
ack_o <= acc_en and (rden_i or wren_i); |
-- write access -- |
if (wr_en = '1') then |
if (addr = uart_ctrl_addr_c) then |
if (addr = uart_id_ctrl_addr_c) then |
ctrl <= (others => '0'); |
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c); |
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c); |
187,7 → 205,7
-- read access -- |
data_o <= (others => '0'); |
if (rd_en = '1') then |
if (addr = uart_ctrl_addr_c) then |
if (addr = uart_id_ctrl_addr_c) then |
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c); |
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c); |
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c); |
194,7 → 212,7
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c); |
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c); |
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy; |
else -- uart_rtx_addr_c |
else -- uart_id_rtx_addr_c |
data_o(data_rx_avail_c) <= uart_rx.avail(0); |
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1); |
data_o(data_rx_ferr_c) <= uart_rx.ferr; |
232,7 → 250,7
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c); |
uart_tx.bitcnt <= num_bits; |
uart_tx.sreg(0) <= '1'; |
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode |
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode |
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag |
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit |
else |
301,7 → 319,7
|
-- RX available flag -- |
uart_rx.busy_ff <= uart_rx.busy; |
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then -- off/RX read access |
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_id_rtx_addr_c)) then -- off/RX read access |
uart_rx.avail <= "00"; |
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done |
uart_rx.avail <= uart_rx.avail(0) & '1'; |
321,16 → 339,16
-- SIMULATION Output ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
sim_output: process(clk_i) -- for SIMULATION ONLY! |
file file_devnull_text_out : text open write_mode is "neorv32.uart.sim_mode.text.out"; |
file file_devnull_data_out : text open write_mode is "neorv32.uart.sim_mode.data.out"; |
variable char_v : integer; |
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable |
variable line_text_v : line; |
variable line_data_v : line; |
file file_uart_text_out : text open write_mode is sim_uart_text_file_c; |
file file_uart_data_out : text open write_mode is sim_uart_data_file_c; |
variable char_v : integer; |
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable |
variable line_text_v : line; |
variable line_data_v : line; |
begin |
if rising_edge(clk_i) then |
if (ctrl(ctrl_uart_en_c) = '1') and (ctrl(ctrl_uart_sim_en_c) = '1') then -- UART enabled and simulation output selected? |
if (wr_en = '1') and (addr = uart_rtx_addr_c) then -- write access to tx register |
if (wr_en = '1') and (addr = uart_id_rtx_addr_c) then -- write access to tx register |
|
-- print lowest byte to ASCII char -- |
char_v := to_integer(unsigned(data_i(7 downto 0))); |
352,7 → 370,7
writeline(output, line_screen_v); |
end if; |
if (sim_text_output_en_c = true) then |
writeline(file_devnull_text_out, line_text_v); |
writeline(file_uart_text_out, line_text_v); |
end if; |
end if; |
|
361,7 → 379,7
for x in 7 downto 0 loop |
write(line_data_v, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form |
end loop; -- x |
writeline(file_devnull_data_out, line_data_v); |
writeline(file_uart_data_out, line_data_v); |
end if; |
|
end if; |