OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 50 to Rev 51
    ↔ Reverse comparison
  •

Rev 50 → Rev 51

/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1063) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1066) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"fd058593",
00000052 => x"fdc58593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
107,39 → 107,39
00000096 => x"30200073",
00000097 => x"00005537",
00000098 => x"ff010113",
00000099 => x"00000593",
00000100 => x"b0050513",
00000101 => x"00112623",
00000102 => x"728000ef",
00000103 => x"1f1000ef",
00000104 => x"02050063",
00000105 => x"4ac000ef",
00000106 => x"00000513",
00000107 => x"500000ef",
00000108 => x"00001537",
00000109 => x"d3050513",
00000110 => x"778000ef",
00000111 => x"020000ef",
00000112 => x"00001537",
00000113 => x"d0c50513",
00000114 => x"768000ef",
00000115 => x"00c12083",
00000116 => x"00000513",
00000117 => x"01010113",
00000118 => x"00008067",
00000119 => x"ff010113",
00000120 => x"00000513",
00000121 => x"00812423",
00000122 => x"00112623",
00000123 => x"00000413",
00000124 => x"1ad000ef",
00000125 => x"0ff47513",
00000126 => x"1a5000ef",
00000127 => x"0c800513",
00000128 => x"11d000ef",
00000129 => x"00140413",
00000130 => x"fedff06f",
00000131 => x"00000000",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"730000ef",
00000104 => x"1f9000ef",
00000105 => x"02050063",
00000106 => x"4a8000ef",
00000107 => x"00000513",
00000108 => x"4fc000ef",
00000109 => x"00001537",
00000110 => x"d3c50513",
00000111 => x"780000ef",
00000112 => x"020000ef",
00000113 => x"00001537",
00000114 => x"d1850513",
00000115 => x"770000ef",
00000116 => x"00c12083",
00000117 => x"00000513",
00000118 => x"01010113",
00000119 => x"00008067",
00000120 => x"ff010113",
00000121 => x"00000513",
00000122 => x"00812423",
00000123 => x"00112623",
00000124 => x"00000413",
00000125 => x"1b5000ef",
00000126 => x"0ff47513",
00000127 => x"1ad000ef",
00000128 => x"0c800513",
00000129 => x"125000ef",
00000130 => x"00140413",
00000131 => x"fedff06f",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
192,7 → 192,7
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"d4c70713",
00000184 => x"d5870713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
203,7 → 203,7
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d7c70713",
00000195 => x"d8870713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
276,14 → 276,14
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"df050513",
00000268 => x"dfc50513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"4e8000ef",
00000275 => x"06c48493",
00000274 => x"4f4000ef",
00000275 => x"07848493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
290,7 → 290,7
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"46c000ef",
00000282 => x"478000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
301,11 → 301,11
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"df450513",
00000293 => x"e0050513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"48c000ef",
00000297 => x"498000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
316,7 → 316,7
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"f8070713",
00000308 => x"f8c70713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
329,8 → 329,8
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f5450513",
00000322 => x"428000ef",
00000321 => x"f6050513",
00000322 => x"434000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
339,22 → 339,22
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"f4450513",
00000332 => x"400000ef",
00000331 => x"f5050513",
00000332 => x"40c000ef",
00000333 => x"00048513",
00000334 => x"39c000ef",
00000334 => x"3a8000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"dfc50513",
00000338 => x"3e8000ef",
00000337 => x"e0850513",
00000338 => x"3f4000ef",
00000339 => x"00001537",
00000340 => x"f6c50513",
00000341 => x"3dc000ef",
00000340 => x"f7850513",
00000341 => x"3e8000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f7450513",
00000346 => x"3c8000ef",
00000345 => x"f8050513",
00000346 => x"3d4000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
361,44 → 361,44
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"fdc50513",
00000353 => x"fe850513",
00000354 => x"01010113",
00000355 => x"3a40006f",
00000355 => x"3b00006f",
00000356 => x"00001537",
00000357 => x"e1c50513",
00000357 => x"e2850513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"e3850513",
00000360 => x"e4450513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"e4c50513",
00000363 => x"e5850513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e5850513",
00000366 => x"e6450513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e7050513",
00000369 => x"e7c50513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"e8450513",
00000372 => x"e9050513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"ea050513",
00000375 => x"eac50513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"eb450513",
00000378 => x"ec050513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"ed450513",
00000381 => x"ee050513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"ef450513",
00000384 => x"f0050513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"f1050513",
00000387 => x"f1c50513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"f2850513",
00000390 => x"f3450513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
419,8 → 419,8
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"fb050513",
00000412 => x"2c0000ef",
00000411 => x"fbc50513",
00000412 => x"2cc000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
447,8 → 447,8
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"fe450513",
00000440 => x"3dc000ef",
00000439 => x"ff050513",
00000440 => x"3e8000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
468,10 → 468,10
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"07ca0a13",
00000460 => x"088a0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"56c000ef",
00000463 => x"578000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
478,7 → 478,7
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"508000ef",
00000470 => x"514000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
523,7 → 523,7
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"08860613",
00000515 => x"09460613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
536,541 → 536,544
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002783",
00000528 => x"fe002703",
00000529 => x"00151513",
00000530 => x"00000713",
00000531 => x"02a7fe63",
00000530 => x"00000793",
00000531 => x"04a77463",
00000532 => x"000016b7",
00000533 => x"00000793",
00000533 => x"00000713",
00000534 => x"ffe68693",
00000535 => x"04e6e063",
00000536 => x"fff70713",
00000535 => x"04f6e663",
00000536 => x"00367613",
00000537 => x"0035f593",
00000538 => x"01879793",
00000539 => x"00e7e7b3",
00000540 => x"01659593",
00000541 => x"00b7e7b3",
00000542 => x"10000737",
00000543 => x"00e7e7b3",
00000544 => x"faf02023",
00000545 => x"00008067",
00000546 => x"00170713",
00000547 => x"01071713",
00000548 => x"40a787b3",
00000549 => x"01075713",
00000550 => x"fb5ff06f",
00000551 => x"ffe78613",
00000552 => x"0fd67613",
00000553 => x"00061a63",
00000554 => x"00375713",
00000555 => x"00178793",
00000556 => x"0ff7f793",
00000557 => x"fa9ff06f",
00000558 => x"00175713",
00000559 => x"ff1ff06f",
00000560 => x"f7dff06f",
00000561 => x"fa002783",
00000562 => x"fe07cee3",
00000563 => x"faa02223",
00000564 => x"00008067",
00000565 => x"ff1ff06f",
00000566 => x"ff010113",
00000567 => x"00812423",
00000568 => x"01212023",
00000569 => x"00112623",
00000570 => x"00912223",
00000571 => x"00050413",
00000572 => x"00a00913",
00000573 => x"00044483",
00000574 => x"00140413",
00000575 => x"00049e63",
00000576 => x"00c12083",
00000577 => x"00812403",
00000578 => x"00412483",
00000579 => x"00012903",
00000580 => x"01010113",
00000581 => x"00008067",
00000582 => x"01249663",
00000583 => x"00d00513",
00000584 => x"fa5ff0ef",
00000585 => x"00048513",
00000586 => x"f9dff0ef",
00000587 => x"fc9ff06f",
00000588 => x"fa9ff06f",
00000589 => x"fa010113",
00000590 => x"04f12a23",
00000591 => x"04410793",
00000592 => x"02812c23",
00000593 => x"03212823",
00000594 => x"03412423",
00000595 => x"03512223",
00000596 => x"03612023",
00000597 => x"01712e23",
00000598 => x"01812c23",
00000599 => x"01912a23",
00000600 => x"02112e23",
00000601 => x"02912a23",
00000602 => x"03312623",
00000603 => x"00050413",
00000604 => x"04b12223",
00000605 => x"04c12423",
00000606 => x"04d12623",
00000607 => x"04e12823",
00000608 => x"05012c23",
00000609 => x"05112e23",
00000610 => x"00f12023",
00000611 => x"02500a13",
00000612 => x"00a00a93",
00000613 => x"07300913",
00000614 => x"07500b13",
00000615 => x"07800b93",
00000616 => x"06300c13",
00000617 => x"06900c93",
00000618 => x"00044483",
00000619 => x"02048063",
00000620 => x"0f449a63",
00000621 => x"00144783",
00000622 => x"00240993",
00000623 => x"07278463",
00000624 => x"04f96063",
00000625 => x"07878e63",
00000626 => x"09978863",
00000627 => x"03c12083",
00000628 => x"03812403",
00000629 => x"03412483",
00000630 => x"03012903",
00000631 => x"02c12983",
00000632 => x"02812a03",
00000633 => x"02412a83",
00000634 => x"02012b03",
00000635 => x"01c12b83",
00000636 => x"01812c03",
00000637 => x"01412c83",
00000638 => x"06010113",
00000639 => x"00008067",
00000640 => x"09678663",
00000641 => x"fd7794e3",
00000642 => x"00012783",
00000643 => x"00410593",
00000644 => x"0007a503",
00000645 => x"00478713",
00000646 => x"00e12023",
00000647 => x"de5ff0ef",
00000648 => x"0640006f",
00000649 => x"00012783",
00000650 => x"0007a503",
00000651 => x"00478713",
00000652 => x"00e12023",
00000653 => x"ea5ff0ef",
00000654 => x"00098413",
00000655 => x"f6dff06f",
00000656 => x"00012783",
00000657 => x"0007c503",
00000658 => x"00478713",
00000659 => x"00e12023",
00000660 => x"e75ff0ef",
00000661 => x"fe5ff06f",
00000662 => x"00012783",
00000663 => x"0007a403",
00000664 => x"00478713",
00000665 => x"00e12023",
00000666 => x"00045863",
00000667 => x"02d00513",
00000668 => x"40800433",
00000669 => x"e51ff0ef",
00000670 => x"00410593",
00000671 => x"00040513",
00000672 => x"c79ff0ef",
00000673 => x"00410513",
00000674 => x"fadff06f",
00000675 => x"00012783",
00000676 => x"00410593",
00000677 => x"00478713",
00000678 => x"0007a503",
00000679 => x"00e12023",
00000680 => x"fe1ff06f",
00000681 => x"01549663",
00000682 => x"00d00513",
00000683 => x"e19ff0ef",
00000684 => x"00140993",
00000685 => x"00048513",
00000686 => x"f99ff06f",
00000687 => x"fd010113",
00000688 => x"00112623",
00000689 => x"00b12a23",
00000690 => x"00c12c23",
00000691 => x"00d12e23",
00000692 => x"02e12023",
00000693 => x"02f12223",
00000694 => x"03012423",
00000695 => x"03112623",
00000696 => x"e55ff0ef",
00000697 => x"00c12083",
00000698 => x"03010113",
00000699 => x"00008067",
00000700 => x"ff010113",
00000701 => x"c80026f3",
00000702 => x"c0002773",
00000703 => x"c80027f3",
00000704 => x"fed79ae3",
00000705 => x"00e12023",
00000706 => x"00f12223",
00000707 => x"00012503",
00000708 => x"00412583",
00000709 => x"01010113",
00000710 => x"00008067",
00000711 => x"fe010113",
00000712 => x"00112e23",
00000713 => x"00812c23",
00000714 => x"00912a23",
00000715 => x"00a12623",
00000716 => x"fc1ff0ef",
00000717 => x"00050493",
00000718 => x"fe002503",
00000719 => x"00058413",
00000720 => x"3e800593",
00000721 => x"11c000ef",
00000722 => x"00c12603",
00000723 => x"00000693",
00000724 => x"00000593",
00000725 => x"074000ef",
00000726 => x"009504b3",
00000727 => x"00a4b533",
00000728 => x"00858433",
00000729 => x"00850433",
00000730 => x"f89ff0ef",
00000731 => x"fe85eee3",
00000732 => x"00b41463",
00000733 => x"fe956ae3",
00000734 => x"01c12083",
00000735 => x"01812403",
00000736 => x"01412483",
00000737 => x"02010113",
00000738 => x"00008067",
00000739 => x"fe802503",
00000740 => x"01055513",
00000741 => x"00157513",
00000742 => x"00008067",
00000743 => x"f8a02223",
00000744 => x"00008067",
00000745 => x"00050613",
00000746 => x"00000513",
00000747 => x"0015f693",
00000748 => x"00068463",
00000749 => x"00c50533",
00000750 => x"0015d593",
00000751 => x"00161613",
00000752 => x"fe0596e3",
00000753 => x"00008067",
00000754 => x"00050313",
00000755 => x"ff010113",
00000756 => x"00060513",
00000757 => x"00068893",
00000758 => x"00112623",
00000759 => x"00030613",
00000760 => x"00050693",
00000761 => x"00000713",
00000762 => x"00000793",
00000763 => x"00000813",
00000764 => x"0016fe13",
00000765 => x"00171e93",
00000766 => x"000e0c63",
00000767 => x"01060e33",
00000768 => x"010e3833",
00000769 => x"00e787b3",
00000770 => x"00f807b3",
00000771 => x"000e0813",
00000772 => x"01f65713",
00000773 => x"0016d693",
00000774 => x"00eee733",
00000775 => x"00161613",
00000776 => x"fc0698e3",
00000777 => x"00058663",
00000778 => x"f7dff0ef",
00000779 => x"00a787b3",
00000780 => x"00088a63",
00000781 => x"00030513",
00000782 => x"00088593",
00000783 => x"f69ff0ef",
00000784 => x"00f507b3",
00000785 => x"00c12083",
00000786 => x"00080513",
00000787 => x"00078593",
00000788 => x"01010113",
00000789 => x"00008067",
00000790 => x"06054063",
00000791 => x"0605c663",
00000792 => x"00058613",
00000793 => x"00050593",
00000794 => x"fff00513",
00000795 => x"02060c63",
00000796 => x"00100693",
00000797 => x"00b67a63",
00000798 => x"00c05863",
00000799 => x"00161613",
00000800 => x"00169693",
00000801 => x"feb66ae3",
00000802 => x"00000513",
00000803 => x"00c5e663",
00000804 => x"40c585b3",
00000805 => x"00d56533",
00000806 => x"0016d693",
00000807 => x"00165613",
00000808 => x"fe0696e3",
00000809 => x"00008067",
00000810 => x"00008293",
00000811 => x"fb5ff0ef",
00000812 => x"00058513",
00000813 => x"00028067",
00000814 => x"40a00533",
00000815 => x"00b04863",
00000816 => x"40b005b3",
00000817 => x"f9dff06f",
00000818 => x"40b005b3",
00000819 => x"00008293",
00000820 => x"f91ff0ef",
00000821 => x"40a00533",
00000822 => x"00028067",
00000823 => x"00008293",
00000824 => x"0005ca63",
00000825 => x"00054c63",
00000826 => x"f79ff0ef",
00000827 => x"00058513",
00000828 => x"00028067",
00000829 => x"40b005b3",
00000830 => x"fe0558e3",
00000831 => x"40a00533",
00000832 => x"f61ff0ef",
00000833 => x"40b00533",
00000834 => x"00028067",
00000835 => x"6f727245",
00000836 => x"4e202172",
00000837 => x"5047206f",
00000838 => x"75204f49",
00000839 => x"2074696e",
00000840 => x"746e7973",
00000841 => x"69736568",
00000842 => x"2164657a",
00000843 => x"0000000a",
00000844 => x"6e696c42",
00000845 => x"676e696b",
00000846 => x"44454c20",
00000847 => x"6d656420",
00000848 => x"7270206f",
00000849 => x"6172676f",
00000850 => x"00000a6d",
00000851 => x"0000031c",
00000852 => x"00000328",
00000853 => x"00000334",
00000854 => x"00000340",
00000855 => x"0000034c",
00000856 => x"00000354",
00000857 => x"0000035c",
00000858 => x"00000364",
00000859 => x"0000036c",
00000860 => x"00000288",
00000861 => x"00000288",
00000862 => x"00000374",
00000863 => x"0000037c",
00000538 => x"fff78793",
00000539 => x"01461613",
00000540 => x"00c7e7b3",
00000541 => x"01659593",
00000542 => x"01871713",
00000543 => x"00b7e7b3",
00000544 => x"00e7e7b3",
00000545 => x"10000737",
00000546 => x"00e7e7b3",
00000547 => x"faf02023",
00000548 => x"00008067",
00000549 => x"00178793",
00000550 => x"01079793",
00000551 => x"40a70733",
00000552 => x"0107d793",
00000553 => x"fa9ff06f",
00000554 => x"ffe70513",
00000555 => x"0fd57513",
00000556 => x"00051a63",
00000557 => x"0037d793",
00000558 => x"00170713",
00000559 => x"0ff77713",
00000560 => x"f9dff06f",
00000561 => x"0017d793",
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00001050 => x"28207825",
00001051 => x"6173696d",
00001052 => x"72736320",
00001053 => x"000a0a29",
00001054 => x"33323130",
00001055 => x"37363534",
00001056 => x"42413938",
00001057 => x"46454443",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"62613938",
00001061 => x"66656463",
00001062 => x"00000000",
00001060 => x"00003938",
00001061 => x"33323130",
00001062 => x"37363534",
00001063 => x"62613938",
00001064 => x"66656463",
00001065 => x"00000000",
others => x"00000000"
);
 
/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 999) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1003) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"f1058593",
00000036 => x"f2058593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
111,902 → 111,906
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"349000ef",
00000103 => x"359000ef",
00000104 => x"00100513",
00000105 => x"3e9000ef",
00000105 => x"3f9000ef",
00000106 => x"00005537",
00000107 => x"00000593",
00000108 => x"b0050513",
00000109 => x"289000ef",
00000110 => x"1b1000ef",
00000111 => x"00245793",
00000112 => x"00a78533",
00000113 => x"00f537b3",
00000114 => x"00b785b3",
00000115 => x"1c9000ef",
00000116 => x"ffff07b7",
00000117 => x"4bc78793",
00000118 => x"30579073",
00000119 => x"08000793",
00000120 => x"30479073",
00000121 => x"30046073",
00000122 => x"00000013",
00000107 => x"00000613",
00000108 => x"00000593",
00000109 => x"b0050513",
00000110 => x"295000ef",
00000111 => x"1b1000ef",
00000112 => x"00245793",
00000113 => x"00a78533",
00000114 => x"00f537b3",
00000115 => x"00b785b3",
00000116 => x"1c9000ef",
00000117 => x"ffff07b7",
00000118 => x"4c078793",
00000119 => x"30579073",
00000120 => x"08000793",
00000121 => x"30479073",
00000122 => x"30046073",
00000123 => x"00000013",
00000124 => x"ffff1537",
00000125 => x"eb850513",
00000126 => x"2e9000ef",
00000127 => x"f1302573",
00000128 => x"24c000ef",
00000129 => x"ffff1537",
00000130 => x"ef050513",
00000131 => x"2d5000ef",
00000132 => x"fe002503",
00000133 => x"238000ef",
00000134 => x"ffff1537",
00000135 => x"ef850513",
00000136 => x"2c1000ef",
00000137 => x"fe402503",
00000138 => x"224000ef",
00000139 => x"ffff1537",
00000140 => x"f0450513",
00000141 => x"2ad000ef",
00000142 => x"30102573",
00000143 => x"210000ef",
00000144 => x"ffff1537",
00000145 => x"f0c50513",
00000146 => x"299000ef",
00000147 => x"fe802503",
00000148 => x"ffff14b7",
00000149 => x"00341413",
00000150 => x"1f4000ef",
00000151 => x"ffff1537",
00000152 => x"f1450513",
00000153 => x"27d000ef",
00000154 => x"ff802503",
00000155 => x"1e0000ef",
00000156 => x"f1c48513",
00000157 => x"26d000ef",
00000158 => x"ff002503",
00000159 => x"1d0000ef",
00000160 => x"ffff1537",
00000161 => x"f2850513",
00000162 => x"259000ef",
00000163 => x"ffc02503",
00000164 => x"1bc000ef",
00000165 => x"f1c48513",
00000166 => x"249000ef",
00000167 => x"ff402503",
00000168 => x"1ac000ef",
00000169 => x"ffff1537",
00000170 => x"f3050513",
00000171 => x"235000ef",
00000172 => x"0b9000ef",
00000173 => x"00a404b3",
00000174 => x"0084b433",
00000175 => x"00b40433",
00000176 => x"1c5000ef",
00000177 => x"02050263",
00000178 => x"ffff1537",
00000179 => x"f5850513",
00000180 => x"211000ef",
00000181 => x"0d9000ef",
00000182 => x"02300793",
00000183 => x"02f51263",
00000184 => x"00000513",
00000185 => x"0180006f",
00000186 => x"081000ef",
00000187 => x"fc85eae3",
00000188 => x"00b41463",
00000189 => x"fc9566e3",
00000190 => x"00100513",
00000191 => x"5dc000ef",
00000192 => x"0b4000ef",
00000193 => x"ffff1937",
00000194 => x"ffff19b7",
00000195 => x"02300a13",
00000196 => x"07200a93",
00000197 => x"06800b13",
00000198 => x"07500b93",
00000199 => x"ffff14b7",
00000200 => x"ffff1c37",
00000201 => x"f6490513",
00000202 => x"1b9000ef",
00000203 => x"149000ef",
00000204 => x"00050413",
00000205 => x"11d000ef",
00000206 => x"e7098513",
00000207 => x"1a5000ef",
00000208 => x"fb4400e3",
00000209 => x"01541863",
00000210 => x"ffff02b7",
00000211 => x"00028067",
00000212 => x"fd5ff06f",
00000213 => x"01641663",
00000214 => x"05c000ef",
00000215 => x"fc9ff06f",
00000216 => x"00000513",
00000217 => x"03740063",
00000218 => x"07300793",
00000219 => x"00f41663",
00000220 => x"67c000ef",
00000221 => x"fb1ff06f",
00000222 => x"06c00793",
00000223 => x"00f41863",
00000224 => x"00100513",
00000225 => x"3fc000ef",
00000226 => x"f9dff06f",
00000227 => x"06500793",
00000228 => x"00f41663",
00000229 => x"02c000ef",
00000230 => x"f8dff06f",
00000231 => x"03f00793",
00000232 => x"f6cc0513",
00000233 => x"00f40463",
00000234 => x"f8048513",
00000235 => x"135000ef",
00000236 => x"f75ff06f",
00000237 => x"ffff1537",
00000238 => x"d9450513",
00000239 => x"1250006f",
00000240 => x"800007b7",
00000241 => x"0007a783",
00000242 => x"00079863",
00000243 => x"ffff1537",
00000244 => x"df850513",
00000245 => x"10d0006f",
00000246 => x"ff010113",
00000247 => x"00112623",
00000248 => x"30047073",
00000249 => x"00000013",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"ec850513",
00000127 => x"2f5000ef",
00000128 => x"f1302573",
00000129 => x"24c000ef",
00000130 => x"ffff1537",
00000131 => x"f0050513",
00000132 => x"2e1000ef",
00000133 => x"fe002503",
00000134 => x"238000ef",
00000135 => x"ffff1537",
00000136 => x"f0850513",
00000137 => x"2cd000ef",
00000138 => x"fe402503",
00000139 => x"224000ef",
00000140 => x"ffff1537",
00000141 => x"f1450513",
00000142 => x"2b9000ef",
00000143 => x"30102573",
00000144 => x"210000ef",
00000145 => x"ffff1537",
00000146 => x"f1c50513",
00000147 => x"2a5000ef",
00000148 => x"fe802503",
00000149 => x"ffff14b7",
00000150 => x"00341413",
00000151 => x"1f4000ef",
00000152 => x"ffff1537",
00000153 => x"f2450513",
00000154 => x"289000ef",
00000155 => x"ff802503",
00000156 => x"1e0000ef",
00000157 => x"f2c48513",
00000158 => x"279000ef",
00000159 => x"ff002503",
00000160 => x"1d0000ef",
00000161 => x"ffff1537",
00000162 => x"f3850513",
00000163 => x"265000ef",
00000164 => x"ffc02503",
00000165 => x"1bc000ef",
00000166 => x"f2c48513",
00000167 => x"255000ef",
00000168 => x"ff402503",
00000169 => x"1ac000ef",
00000170 => x"ffff1537",
00000171 => x"f4050513",
00000172 => x"241000ef",
00000173 => x"0b9000ef",
00000174 => x"00a404b3",
00000175 => x"0084b433",
00000176 => x"00b40433",
00000177 => x"1d1000ef",
00000178 => x"02050263",
00000179 => x"ffff1537",
00000180 => x"f6850513",
00000181 => x"21d000ef",
00000182 => x"0d9000ef",
00000183 => x"02300793",
00000184 => x"02f51263",
00000185 => x"00000513",
00000186 => x"0180006f",
00000187 => x"081000ef",
00000188 => x"fc85eae3",
00000189 => x"00b41463",
00000190 => x"fc9566e3",
00000191 => x"00100513",
00000192 => x"5dc000ef",
00000193 => x"0b4000ef",
00000194 => x"ffff1937",
00000195 => x"ffff19b7",
00000196 => x"02300a13",
00000197 => x"07200a93",
00000198 => x"06800b13",
00000199 => x"07500b93",
00000200 => x"ffff14b7",
00000201 => x"ffff1c37",
00000202 => x"f7490513",
00000203 => x"1c5000ef",
00000204 => x"155000ef",
00000205 => x"00050413",
00000206 => x"129000ef",
00000207 => x"e8098513",
00000208 => x"1b1000ef",
00000209 => x"fb4400e3",
00000210 => x"01541863",
00000211 => x"ffff02b7",
00000212 => x"00028067",
00000213 => x"fd5ff06f",
00000214 => x"01641663",
00000215 => x"05c000ef",
00000216 => x"fc9ff06f",
00000217 => x"00000513",
00000218 => x"03740063",
00000219 => x"07300793",
00000220 => x"00f41663",
00000221 => x"67c000ef",
00000222 => x"fb1ff06f",
00000223 => x"06c00793",
00000224 => x"00f41863",
00000225 => x"00100513",
00000226 => x"3fc000ef",
00000227 => x"f9dff06f",
00000228 => x"06500793",
00000229 => x"00f41663",
00000230 => x"02c000ef",
00000231 => x"f8dff06f",
00000232 => x"03f00793",
00000233 => x"f7cc0513",
00000234 => x"00f40463",
00000235 => x"f9048513",
00000236 => x"141000ef",
00000237 => x"f75ff06f",
00000238 => x"ffff1537",
00000239 => x"da450513",
00000240 => x"1310006f",
00000241 => x"800007b7",
00000242 => x"0007a783",
00000243 => x"00079863",
00000244 => x"ffff1537",
00000245 => x"e0850513",
00000246 => x"1190006f",
00000247 => x"ff010113",
00000248 => x"00112623",
00000249 => x"30047073",
00000250 => x"00000013",
00000251 => x"ffff1537",
00000252 => x"e1450513",
00000253 => x"0ed000ef",
00000254 => x"069000ef",
00000255 => x"fe051ee3",
00000256 => x"ff002783",
00000257 => x"00078067",
00000258 => x"0000006f",
00000259 => x"ff010113",
00000260 => x"00812423",
00000261 => x"00050413",
00000262 => x"ffff1537",
00000263 => x"e2450513",
00000264 => x"00112623",
00000265 => x"0bd000ef",
00000266 => x"03040513",
00000267 => x"0ff57513",
00000268 => x"021000ef",
00000269 => x"30047073",
00000270 => x"00000013",
00000251 => x"00000013",
00000252 => x"ffff1537",
00000253 => x"e2450513",
00000254 => x"0f9000ef",
00000255 => x"075000ef",
00000256 => x"fe051ee3",
00000257 => x"ff002783",
00000258 => x"00078067",
00000259 => x"0000006f",
00000260 => x"ff010113",
00000261 => x"00812423",
00000262 => x"00050413",
00000263 => x"ffff1537",
00000264 => x"e3450513",
00000265 => x"00112623",
00000266 => x"0c9000ef",
00000267 => x"03040513",
00000268 => x"0ff57513",
00000269 => x"02d000ef",
00000270 => x"30047073",
00000271 => x"00000013",
00000272 => x"00100513",
00000273 => x"149000ef",
00000274 => x"0000006f",
00000275 => x"fe010113",
00000276 => x"01212823",
00000277 => x"00050913",
00000278 => x"ffff1537",
00000279 => x"00912a23",
00000280 => x"e3c50513",
00000281 => x"ffff14b7",
00000282 => x"00812c23",
00000283 => x"01312623",
00000284 => x"00112e23",
00000285 => x"01c00413",
00000286 => x"069000ef",
00000287 => x"f8c48493",
00000288 => x"ffc00993",
00000289 => x"008957b3",
00000290 => x"00f7f793",
00000291 => x"00f487b3",
00000292 => x"0007c503",
00000293 => x"ffc40413",
00000294 => x"7b8000ef",
00000295 => x"ff3414e3",
00000296 => x"01c12083",
00000297 => x"01812403",
00000298 => x"01412483",
00000299 => x"01012903",
00000300 => x"00c12983",
00000301 => x"02010113",
00000302 => x"00008067",
00000303 => x"fb010113",
00000304 => x"04112623",
00000305 => x"04512423",
00000306 => x"04612223",
00000307 => x"04712023",
00000308 => x"02812e23",
00000309 => x"02a12c23",
00000310 => x"02b12a23",
00000311 => x"02c12823",
00000312 => x"02d12623",
00000313 => x"02e12423",
00000314 => x"02f12223",
00000315 => x"03012023",
00000316 => x"01112e23",
00000317 => x"01c12c23",
00000318 => x"01d12a23",
00000319 => x"01e12823",
00000320 => x"01f12623",
00000321 => x"34202473",
00000322 => x"800007b7",
00000323 => x"00778793",
00000324 => x"06f41a63",
00000325 => x"00000513",
00000326 => x"059000ef",
00000327 => x"64c000ef",
00000328 => x"fe002783",
00000329 => x"0027d793",
00000330 => x"00a78533",
00000331 => x"00f537b3",
00000332 => x"00b785b3",
00000333 => x"660000ef",
00000334 => x"03c12403",
00000335 => x"04c12083",
00000336 => x"04812283",
00000337 => x"04412303",
00000338 => x"04012383",
00000339 => x"03812503",
00000340 => x"03412583",
00000341 => x"03012603",
00000342 => x"02c12683",
00000343 => x"02812703",
00000344 => x"02412783",
00000345 => x"02012803",
00000346 => x"01c12883",
00000347 => x"01812e03",
00000348 => x"01412e83",
00000349 => x"01012f03",
00000350 => x"00c12f83",
00000351 => x"05010113",
00000352 => x"30200073",
00000353 => x"00700793",
00000354 => x"00f41863",
00000355 => x"8041a783",
00000356 => x"00100513",
00000357 => x"02079863",
00000358 => x"ffff1537",
00000359 => x"e3050513",
00000360 => x"740000ef",
00000361 => x"00040513",
00000362 => x"ea5ff0ef",
00000363 => x"ffff1537",
00000364 => x"e3850513",
00000365 => x"72c000ef",
00000366 => x"34102573",
00000367 => x"e91ff0ef",
00000368 => x"00500513",
00000369 => x"e49ff0ef",
00000370 => x"ff010113",
00000371 => x"00000513",
00000372 => x"00112623",
00000373 => x"00812423",
00000374 => x"740000ef",
00000375 => x"09e00513",
00000376 => x"77c000ef",
00000377 => x"00000513",
00000378 => x"774000ef",
00000379 => x"00050413",
00000380 => x"00000513",
00000381 => x"744000ef",
00000382 => x"00c12083",
00000383 => x"0ff47513",
00000384 => x"00812403",
00000385 => x"01010113",
00000386 => x"00008067",
00000387 => x"ff010113",
00000388 => x"00112623",
00000389 => x"00812423",
00000390 => x"00000513",
00000391 => x"6fc000ef",
00000392 => x"00500513",
00000393 => x"738000ef",
00000394 => x"00000513",
00000395 => x"730000ef",
00000396 => x"00050413",
00000397 => x"00147413",
00000398 => x"00000513",
00000399 => x"6fc000ef",
00000400 => x"fc041ce3",
00000401 => x"00c12083",
00000402 => x"00812403",
00000403 => x"01010113",
00000404 => x"00008067",
00000405 => x"ff010113",
00000406 => x"00000513",
00000407 => x"00112623",
00000408 => x"6b8000ef",
00000409 => x"00600513",
00000410 => x"6f4000ef",
00000411 => x"00c12083",
00000412 => x"00000513",
00000413 => x"01010113",
00000414 => x"6c00006f",
00000415 => x"ff010113",
00000416 => x"00812423",
00000417 => x"00050413",
00000418 => x"01055513",
00000419 => x"0ff57513",
00000420 => x"00112623",
00000421 => x"6c8000ef",
00000422 => x"00845513",
00000423 => x"0ff57513",
00000424 => x"6bc000ef",
00000425 => x"0ff47513",
00000426 => x"00812403",
00000427 => x"00c12083",
00000428 => x"01010113",
00000429 => x"6a80006f",
00000430 => x"ff010113",
00000431 => x"00812423",
00000432 => x"00050413",
00000433 => x"00000513",
00000434 => x"00112623",
00000435 => x"64c000ef",
00000436 => x"00300513",
00000437 => x"688000ef",
00000438 => x"00040513",
00000439 => x"fa1ff0ef",
00000440 => x"00000513",
00000441 => x"678000ef",
00000442 => x"00050413",
00000443 => x"00000513",
00000444 => x"648000ef",
00000445 => x"00c12083",
00000446 => x"0ff47513",
00000447 => x"00812403",
00000448 => x"01010113",
00000449 => x"00008067",
00000450 => x"fd010113",
00000451 => x"02812423",
00000452 => x"02912223",
00000453 => x"03212023",
00000454 => x"01312e23",
00000455 => x"01412c23",
00000456 => x"02112623",
00000457 => x"00050913",
00000458 => x"00058993",
00000459 => x"00c10493",
00000460 => x"00000413",
00000461 => x"00400a13",
00000462 => x"02091e63",
00000463 => x"538000ef",
00000464 => x"00a481a3",
00000465 => x"00140413",
00000466 => x"fff48493",
00000467 => x"ff4416e3",
00000468 => x"02c12083",
00000469 => x"02812403",
00000470 => x"00c12503",
00000471 => x"02412483",
00000472 => x"02012903",
00000473 => x"01c12983",
00000474 => x"01812a03",
00000475 => x"03010113",
00000476 => x"00008067",
00000477 => x"00898533",
00000478 => x"f41ff0ef",
00000479 => x"fc5ff06f",
00000480 => x"fd010113",
00000481 => x"01412c23",
00000482 => x"80418793",
00000483 => x"02812423",
00000484 => x"02112623",
00000485 => x"02912223",
00000486 => x"03212023",
00000487 => x"01312e23",
00000488 => x"01512a23",
00000489 => x"01612823",
00000490 => x"01712623",
00000491 => x"01812423",
00000492 => x"00100713",
00000493 => x"00e7a023",
00000494 => x"fe802783",
00000495 => x"00050413",
00000496 => x"80418a13",
00000497 => x"0087f793",
00000498 => x"00078a63",
00000499 => x"fe802783",
00000500 => x"00400513",
00000501 => x"0047f793",
00000502 => x"04079663",
00000503 => x"02041863",
00000504 => x"ffff1537",
00000505 => x"e4050513",
00000506 => x"4f8000ef",
00000507 => x"008005b7",
00000508 => x"00040513",
00000509 => x"f15ff0ef",
00000510 => x"4788d7b7",
00000511 => x"afe78793",
00000512 => x"02f50463",
00000513 => x"00000513",
00000514 => x"01c0006f",
00000515 => x"ffff1537",
00000516 => x"e6050513",
00000517 => x"4cc000ef",
00000518 => x"db1ff0ef",
00000519 => x"fc0518e3",
00000520 => x"00300513",
00000521 => x"be9ff0ef",
00000522 => x"008009b7",
00000523 => x"00498593",
00000524 => x"00040513",
00000525 => x"ed5ff0ef",
00000526 => x"00050a93",
00000527 => x"00898593",
00000528 => x"00040513",
00000529 => x"ec5ff0ef",
00000530 => x"ff002c03",
00000531 => x"00050b13",
00000532 => x"ffcafb93",
00000533 => x"00000913",
00000534 => x"00000493",
00000535 => x"00c98993",
00000536 => x"013905b3",
00000537 => x"052b9c63",
00000538 => x"016484b3",
00000539 => x"00200513",
00000540 => x"fa049ae3",
00000541 => x"ffff1537",
00000542 => x"e6c50513",
00000543 => x"464000ef",
00000544 => x"02c12083",
00000545 => x"02812403",
00000546 => x"800007b7",
00000547 => x"0157a023",
00000548 => x"000a2023",
00000549 => x"02412483",
00000550 => x"02012903",
00000551 => x"01c12983",
00000552 => x"01812a03",
00000553 => x"01412a83",
00000554 => x"01012b03",
00000555 => x"00c12b83",
00000556 => x"00812c03",
00000557 => x"03010113",
00000558 => x"00008067",
00000559 => x"00040513",
00000560 => x"e49ff0ef",
00000561 => x"012c07b3",
00000562 => x"00a484b3",
00000563 => x"00a7a023",
00000564 => x"00490913",
00000565 => x"f8dff06f",
00000566 => x"ff010113",
00000567 => x"00112623",
00000568 => x"ea1ff0ef",
00000569 => x"ffff1537",
00000570 => x"e7050513",
00000571 => x"3f4000ef",
00000572 => x"ad1ff0ef",
00000573 => x"0000006f",
00000574 => x"ff010113",
00000575 => x"00112623",
00000576 => x"00812423",
00000577 => x"00912223",
00000578 => x"00058413",
00000579 => x"00050493",
00000580 => x"d45ff0ef",
00000581 => x"00000513",
00000582 => x"400000ef",
00000583 => x"00200513",
00000584 => x"43c000ef",
00000585 => x"00048513",
00000586 => x"d55ff0ef",
00000587 => x"00040513",
00000588 => x"42c000ef",
00000589 => x"00000513",
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00000767 => x"00b7e7b3",
00000768 => x"00e7e7b3",
00000769 => x"10000737",
00000770 => x"00e7e7b3",
00000771 => x"faf02023",
00000772 => x"00008067",
00000773 => x"00178793",
00000774 => x"01079793",
00000775 => x"40a70733",
00000776 => x"0107d793",
00000777 => x"fa9ff06f",
00000778 => x"ffe70513",
00000779 => x"0fd57513",
00000780 => x"00051a63",
00000781 => x"0037d793",
00000782 => x"00170713",
00000783 => x"0ff77713",
00000784 => x"f9dff06f",
00000785 => x"0017d793",
00000786 => x"ff1ff06f",
00000787 => x"f71ff06f",
00000788 => x"fa002783",
00000789 => x"fe07cee3",
00000790 => x"faa02223",
00000791 => x"00008067",
00000792 => x"ff5ff06f",
00000793 => x"fa402503",
00000794 => x"fe055ee3",
00000795 => x"0ff57513",
00000796 => x"00008067",
00000797 => x"ff1ff06f",
00000798 => x"fa402503",
00000799 => x"01f55513",
00000792 => x"ff1ff06f",
00000793 => x"fa002503",
00000794 => x"01f55513",
00000795 => x"00008067",
00000796 => x"ff5ff06f",
00000797 => x"fa402503",
00000798 => x"fe055ee3",
00000799 => x"0ff57513",
00000800 => x"00008067",
00000801 => x"ff5ff06f",
00000802 => x"ff010113",
00000803 => x"00812423",
00000804 => x"01212023",
00000805 => x"00112623",
00000806 => x"00912223",
00000807 => x"00050413",
00000808 => x"00a00913",
00000809 => x"00044483",
00000810 => x"00140413",
00000811 => x"00049e63",
00000812 => x"00c12083",
00000813 => x"00812403",
00000814 => x"00412483",
00000815 => x"00012903",
00000816 => x"01010113",
00000817 => x"00008067",
00000818 => x"01249663",
00000819 => x"00d00513",
00000820 => x"f71ff0ef",
00000821 => x"00048513",
00000822 => x"f69ff0ef",
00000823 => x"fc9ff06f",
00000824 => x"fa9ff06f",
00000825 => x"00757513",
00000826 => x"00367613",
00000827 => x"0015f593",
00000828 => x"00a51513",
00000829 => x"00d61613",
00000830 => x"00c56533",
00000831 => x"00959593",
00000832 => x"fa800793",
00000833 => x"00b56533",
00000834 => x"0007a023",
00000835 => x"10056513",
00000836 => x"00a7a023",
00000837 => x"00008067",
00000838 => x"fa800713",
00000839 => x"00072683",
00000840 => x"00757793",
00000841 => x"00100513",
00000842 => x"00f51533",
00000843 => x"00d56533",
00000844 => x"00a72023",
00000845 => x"00008067",
00000846 => x"fa800713",
00000847 => x"00072683",
00000848 => x"00757513",
00000849 => x"00100793",
00000850 => x"00a797b3",
00000851 => x"fff7c793",
00000852 => x"00d7f7b3",
00000853 => x"00f72023",
00000854 => x"00008067",
00000855 => x"faa02623",
00000856 => x"fa802783",
00000857 => x"fe07cee3",
00000858 => x"fac02503",
00000859 => x"00008067",
00000860 => x"f8400713",
00000861 => x"00072683",
00000862 => x"00100793",
00000863 => x"00a797b3",
00000864 => x"00d7c7b3",
00000865 => x"00f72023",
00000866 => x"00008067",
00000867 => x"f8a02223",
00000868 => x"00008067",
00000869 => x"69617641",
00000870 => x"6c62616c",
00000871 => x"4d432065",
00000872 => x"0a3a7344",
00000873 => x"203a6820",
00000874 => x"706c6548",
00000875 => x"3a72200a",
00000876 => x"73655220",
00000877 => x"74726174",
00000878 => x"3a75200a",
00000879 => x"6c705520",
00000880 => x"0a64616f",
00000881 => x"203a7320",
00000882 => x"726f7453",
00000883 => x"6f742065",
00000884 => x"616c6620",
00000885 => x"200a6873",
00000886 => x"4c203a6c",
00000887 => x"2064616f",
00000888 => x"6d6f7266",
00000889 => x"616c6620",
00000890 => x"200a6873",
00000891 => x"45203a65",
00000892 => x"75636578",
00000893 => x"00006574",
00000894 => x"65206f4e",
00000895 => x"75636578",
00000896 => x"6c626174",
00000897 => x"76612065",
00000898 => x"616c6961",
00000899 => x"2e656c62",
00000900 => x"00000000",
00000901 => x"746f6f42",
00000902 => x"2e676e69",
00000903 => x"0a0a2e2e",
00000801 => x"ff1ff06f",
00000802 => x"fa402503",
00000803 => x"01f55513",
00000804 => x"00008067",
00000805 => x"ff5ff06f",
00000806 => x"ff010113",
00000807 => x"00812423",
00000808 => x"01212023",
00000809 => x"00112623",
00000810 => x"00912223",
00000811 => x"00050413",
00000812 => x"00a00913",
00000813 => x"00044483",
00000814 => x"00140413",
00000815 => x"00049e63",
00000816 => x"00c12083",
00000817 => x"00812403",
00000818 => x"00412483",
00000819 => x"00012903",
00000820 => x"01010113",
00000821 => x"00008067",
00000822 => x"01249663",
00000823 => x"00d00513",
00000824 => x"f71ff0ef",
00000825 => x"00048513",
00000826 => x"f69ff0ef",
00000827 => x"fc9ff06f",
00000828 => x"fa9ff06f",
00000829 => x"00757513",
00000830 => x"00367613",
00000831 => x"0015f593",
00000832 => x"00a51513",
00000833 => x"00d61613",
00000834 => x"00c56533",
00000835 => x"00959593",
00000836 => x"fa800793",
00000837 => x"00b56533",
00000838 => x"0007a023",
00000839 => x"10056513",
00000840 => x"00a7a023",
00000841 => x"00008067",
00000842 => x"fa800713",
00000843 => x"00072683",
00000844 => x"00757793",
00000845 => x"00100513",
00000846 => x"00f51533",
00000847 => x"00d56533",
00000848 => x"00a72023",
00000849 => x"00008067",
00000850 => x"fa800713",
00000851 => x"00072683",
00000852 => x"00757513",
00000853 => x"00100793",
00000854 => x"00a797b3",
00000855 => x"fff7c793",
00000856 => x"00d7f7b3",
00000857 => x"00f72023",
00000858 => x"00008067",
00000859 => x"faa02623",
00000860 => x"fa802783",
00000861 => x"fe07cee3",
00000862 => x"fac02503",
00000863 => x"00008067",
00000864 => x"f8400713",
00000865 => x"00072683",
00000866 => x"00100793",
00000867 => x"00a797b3",
00000868 => x"00d7c7b3",
00000869 => x"00f72023",
00000870 => x"00008067",
00000871 => x"f8a02223",
00000872 => x"00008067",
00000873 => x"69617641",
00000874 => x"6c62616c",
00000875 => x"4d432065",
00000876 => x"0a3a7344",
00000877 => x"203a6820",
00000878 => x"706c6548",
00000879 => x"3a72200a",
00000880 => x"73655220",
00000881 => x"74726174",
00000882 => x"3a75200a",
00000883 => x"6c705520",
00000884 => x"0a64616f",
00000885 => x"203a7320",
00000886 => x"726f7453",
00000887 => x"6f742065",
00000888 => x"616c6620",
00000889 => x"200a6873",
00000890 => x"4c203a6c",
00000891 => x"2064616f",
00000892 => x"6d6f7266",
00000893 => x"616c6620",
00000894 => x"200a6873",
00000895 => x"45203a65",
00000896 => x"75636578",
00000897 => x"00006574",
00000898 => x"65206f4e",
00000899 => x"75636578",
00000900 => x"6c626174",
00000901 => x"76612065",
00000902 => x"616c6961",
00000903 => x"2e656c62",
00000904 => x"00000000",
00000905 => x"52450a07",
00000906 => x"5f524f52",
00000907 => x"00000000",
00000908 => x"58450a0a",
00000909 => x"00282043",
00000910 => x"20402029",
00000911 => x"00007830",
00000912 => x"69617741",
00000913 => x"676e6974",
00000914 => x"6f656e20",
00000915 => x"32337672",
00000916 => x"6578655f",
00000917 => x"6e69622e",
00000918 => x"202e2e2e",
00000919 => x"00000000",
00000920 => x"64616f4c",
00000921 => x"2e676e69",
00000922 => x"00202e2e",
00000923 => x"00004b4f",
00000924 => x"0000000a",
00000925 => x"74697257",
00000926 => x"78302065",
00000927 => x"00000000",
00000928 => x"74796220",
00000929 => x"74207365",
00000930 => x"5053206f",
00000931 => x"6c662049",
00000932 => x"20687361",
00000933 => x"78302040",
00000934 => x"00000000",
00000935 => x"7928203f",
00000936 => x"20296e2f",
00000937 => x"00000000",
00000938 => x"616c460a",
00000939 => x"6e696873",
00000940 => x"2e2e2e67",
00000941 => x"00000020",
00000942 => x"0a0a0a0a",
00000943 => x"4e203c3c",
00000944 => x"56524f45",
00000945 => x"42203233",
00000946 => x"6c746f6f",
00000947 => x"6564616f",
00000948 => x"3e3e2072",
00000949 => x"4c420a0a",
00000950 => x"203a5644",
00000951 => x"20626546",
00000952 => x"32203731",
00000953 => x"0a313230",
00000954 => x"3a565748",
00000955 => x"00002020",
00000956 => x"4b4c430a",
00000957 => x"0020203a",
00000958 => x"0a7a4820",
00000959 => x"52455355",
00000960 => x"0000203a",
00000961 => x"53494d0a",
00000962 => x"00203a41",
00000963 => x"4f52500a",
00000964 => x"00203a43",
00000965 => x"454d490a",
00000966 => x"00203a4d",
00000967 => x"74796220",
00000968 => x"40207365",
00000969 => x"00000020",
00000970 => x"454d440a",
00000971 => x"00203a4d",
00000972 => x"75410a0a",
00000973 => x"6f626f74",
00000974 => x"6920746f",
00000975 => x"7338206e",
00000976 => x"7250202e",
00000977 => x"20737365",
00000978 => x"2079656b",
00000979 => x"61206f74",
00000980 => x"74726f62",
00000981 => x"00000a2e",
00000982 => x"726f6241",
00000983 => x"2e646574",
00000984 => x"00000a0a",
00000985 => x"444d430a",
00000986 => x"00203e3a",
00000987 => x"53207962",
00000988 => x"68706574",
00000989 => x"4e206e61",
00000990 => x"69746c6f",
00000991 => x"0000676e",
00000992 => x"61766e49",
00000993 => x"2064696c",
00000994 => x"00444d43",
00000995 => x"33323130",
00000996 => x"37363534",
00000997 => x"42413938",
00000998 => x"46454443",
00000905 => x"746f6f42",
00000906 => x"2e676e69",
00000907 => x"0a0a2e2e",
00000908 => x"00000000",
00000909 => x"52450a07",
00000910 => x"5f524f52",
00000911 => x"00000000",
00000912 => x"58450a0a",
00000913 => x"00282043",
00000914 => x"20402029",
00000915 => x"00007830",
00000916 => x"69617741",
00000917 => x"676e6974",
00000918 => x"6f656e20",
00000919 => x"32337672",
00000920 => x"6578655f",
00000921 => x"6e69622e",
00000922 => x"202e2e2e",
00000923 => x"00000000",
00000924 => x"64616f4c",
00000925 => x"2e676e69",
00000926 => x"00202e2e",
00000927 => x"00004b4f",
00000928 => x"0000000a",
00000929 => x"74697257",
00000930 => x"78302065",
00000931 => x"00000000",
00000932 => x"74796220",
00000933 => x"74207365",
00000934 => x"5053206f",
00000935 => x"6c662049",
00000936 => x"20687361",
00000937 => x"78302040",
00000938 => x"00000000",
00000939 => x"7928203f",
00000940 => x"20296e2f",
00000941 => x"00000000",
00000942 => x"616c460a",
00000943 => x"6e696873",
00000944 => x"2e2e2e67",
00000945 => x"00000020",
00000946 => x"0a0a0a0a",
00000947 => x"4e203c3c",
00000948 => x"56524f45",
00000949 => x"42203233",
00000950 => x"6c746f6f",
00000951 => x"6564616f",
00000952 => x"3e3e2072",
00000953 => x"4c420a0a",
00000954 => x"203a5644",
00000955 => x"20626546",
00000956 => x"32203232",
00000957 => x"0a313230",
00000958 => x"3a565748",
00000959 => x"00002020",
00000960 => x"4b4c430a",
00000961 => x"0020203a",
00000962 => x"0a7a4820",
00000963 => x"52455355",
00000964 => x"0000203a",
00000965 => x"53494d0a",
00000966 => x"00203a41",
00000967 => x"4f52500a",
00000968 => x"00203a43",
00000969 => x"454d490a",
00000970 => x"00203a4d",
00000971 => x"74796220",
00000972 => x"40207365",
00000973 => x"00000020",
00000974 => x"454d440a",
00000975 => x"00203a4d",
00000976 => x"75410a0a",
00000977 => x"6f626f74",
00000978 => x"6920746f",
00000979 => x"7338206e",
00000980 => x"7250202e",
00000981 => x"20737365",
00000982 => x"2079656b",
00000983 => x"61206f74",
00000984 => x"74726f62",
00000985 => x"00000a2e",
00000986 => x"726f6241",
00000987 => x"2e646574",
00000988 => x"00000a0a",
00000989 => x"444d430a",
00000990 => x"00203e3a",
00000991 => x"53207962",
00000992 => x"68706574",
00000993 => x"4e206e61",
00000994 => x"69746c6f",
00000995 => x"0000676e",
00000996 => x"61766e49",
00000997 => x"2064696c",
00000998 => x"00444d43",
00000999 => x"33323130",
00001000 => x"37363534",
00001001 => x"42413938",
00001002 => x"46454443",
others => x"00000000"
);
 
/neorv32_cpu.vhd
175,7 → 175,7
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
 
-- Bit manipulation notifier --
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) only supports 'base' instruction sub-set (Zbb) yet and is still 'unofficial' (not-ratified)." severity warning;
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still highly experimental (not ratified yet)." severity warning;
 
-- PMP regions check --
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
/neorv32_cpu_control.vhd
781,7 → 781,7
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
end if;
 
-- is BITMANIP.Zbb instruction? --
-- is BITMANIP instruction? --
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
-- immediate operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
793,10 → 793,15
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
)
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLRI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSETI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINVI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- SBEXTI
--
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0000111")) or -- GORCI.b 7 (orc.b)
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0011000")) then -- GREVI.-8 (rev8)
decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);
decode_aux.is_bitmanip_imm <= '1';
end if;
-- register operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
808,8 → 813,12
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
)
) then
decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLR
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSET
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINV
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) then -- SBSEXT
decode_aux.is_bitmanip_reg <= '1';
end if;
-- system/environment instructions --
sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c; -- sum-up set bits
1234,7 → 1243,9
 
-- low privilege level access to hpm counters? --
csr_mcounteren_hpm_v := (others => '0');
csr_mcounteren_hpm_v(HPM_NUM_CNTS-1 downto 0) := csr.mcounteren_hpm(HPM_NUM_CNTS-1 downto 0);
if (CPU_EXTENSION_RISCV_U = true) then -- 'mcounteren' CSR is hardwired to zero if user mode is not implemented
csr_mcounteren_hpm_v(HPM_NUM_CNTS-1 downto 0) := csr.mcounteren_hpm(HPM_NUM_CNTS-1 downto 0);
end if;
 
-- check CSR access --
case csr.addr is
1932,10 → 1943,14
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when csr_mcounteren_c => -- R/W: machine counter enable register
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
csr.mcounteren_hpm <= csr.wdata(csr.mcounteren_hpm'left+3 downto 3); -- enable user-level access to hpmcounterx[h]
if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
csr.mcounteren_hpm <= csr.wdata(csr.mcounteren_hpm'left+3 downto 3); -- enable user-level access to hpmcounterx[h]
else
NULL;
end if;
 
-- machine trap handling --
-- --------------------------------------------------------------------
2095,8 → 2110,8
end process csr_write_access;
 
-- decode privilege mode --
csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) or (CPU_EXTENSION_RISCV_U = false) else '0';
csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0';
csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) else '0';
csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) else '0';
 
-- PMP configuration output to bus unit --
pmp_output: process(csr)
2279,10 → 2294,14
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when csr_mcounteren_c => -- R/W: machine counter enable register
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
csr.rdata(csr.mcounteren_hpm'left+3 downto 3) <= csr.mcounteren_hpm; -- enable user-level access to hpmcounterx[h]
if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
csr.rdata(csr.mcounteren_hpm'left+3 downto 3) <= csr.mcounteren_hpm; -- enable user-level access to hpmcounterx[h]
else
csr.rdata <= (others => '0');
end if;
 
-- machine trap handling --
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
2514,6 → 2533,7
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei
csr.rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zbb
csr.rdata(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zbs
 
-- undefined/unavailable --
when others =>
/neorv32_cpu_cp_bitmanip.vhd
7,6 → 7,7
-- # #
-- # Supported sub-extensions (Zb*): #
-- # - Zbb: Base instructions (mandatory) #
-- # - Zbs: Single-bit instructions (optional) #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
65,6 → 66,9
 
architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is
 
-- extension configuration --
constant zbs_enable_c : boolean := true; -- enable single-bit instructions
 
-- commands --
constant op_clz_c : natural := 0;
constant op_ctz_c : natural := 1;
82,7 → 86,12
constant op_rev8_c : natural := 13;
constant op_orcb_c : natural := 14;
--
constant op_width_c : natural := 15;
constant op_bset_c : natural := 15;
constant op_bclr_c : natural := 16;
constant op_binv_c : natural := 17;
constant op_bext_c : natural := 18;
--
constant op_width_c : natural := 19;
 
-- controller --
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT);
96,7 → 105,8
signal less_ff : std_ulogic;
 
-- shift amount (immediate or register) --
signal shamt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
signal shamt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
signal bit_mask : std_ulogic_vector(data_width_c-1 downto 0); -- one-hot mask
 
-- shifter --
type shifter_t is record
121,18 → 131,18
-- a more specific decoding and instruction check is done by the CPU control unit
 
-- Zbb - Base Instructions --
cmd(op_clz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0';
cmd(op_ctz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0';
cmd(op_cpop_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0';
cmd(op_sextb_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0';
cmd(op_sexth_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0';
cmd(op_clz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0';
cmd(op_ctz_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0';
cmd(op_cpop_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0';
cmd(op_sextb_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0';
cmd(op_sexth_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0';
--
cmd(op_ror_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
cmd(op_rol_c) <= '1' when (ctrl_i(ctrl_ir_opcode7_5_c) = '1') and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1100") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") else '0';
--
cmd(op_rev8_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1101") else '0';
cmd(op_rev8_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1101") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
--
cmd(op_orcb_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") else '0';
cmd(op_orcb_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "0101") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
--
cmd(op_min_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_7_c downto ctrl_ir_funct12_5_c) = "101") and (ctrl_i(ctrl_ir_funct3_1_c) = '0') else '0';
cmd(op_max_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_7_c downto ctrl_ir_funct12_5_c) = "101") and (ctrl_i(ctrl_ir_funct3_1_c) = '1') else '0';
143,7 → 153,13
--
cmd(op_pack_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_5_c) = "000100") else '0';
 
-- Zbs - Single-Bit Instructions --
cmd(op_bset_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "0101") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (zbs_enable_c = true) else '0';
cmd(op_bclr_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1001") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (zbs_enable_c = true) else '0';
cmd(op_binv_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1101") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (zbs_enable_c = true) else '0';
cmd(op_bext_c) <= '1' when (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_7_c) = "1001") and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") and (zbs_enable_c = true) else '0';
 
 
-- Co-Processor Controller ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
coprocessor_ctrl: process(rstn_i, clk_i)
204,9 → 220,16
-- -------------------------------------------------------------------------------------------
-- we could also use ALU's internal operand B - but we are having a local version here in order to allow
-- better logic combination inside the ALU (since that is the critical path of the CPU)
shamt <= ctrl_i(shamt'left+ctrl_ir_funct12_0_c downto ctrl_ir_funct12_0_c) when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') else rs2_reg(shamt'left downto 0);
shamt <= ctrl_i(ctrl_ir_funct12_0_c+shamt'left downto ctrl_ir_funct12_0_c) when (ctrl_i(ctrl_ir_opcode7_5_c) = '0') else rs2_reg(shamt'left downto 0);
 
-- one-hot bit mask --
bit_mask_generator: process(shamt)
begin
bit_mask <= (others => '0');
bit_mask(to_integer(unsigned(shamt))) <= '1';
end process bit_mask_generator;
 
 
-- Shifter Function Core ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shifter_unit: process(clk_i)
298,8 → 321,18
end generate; -- i
 
 
-- Single-Bit ('Zbs') Function Core -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
res_int(op_bset_c) <= rs1_reg or bit_mask;
res_int(op_bclr_c) <= rs1_reg and (not bit_mask);
res_int(op_binv_c) <= rs1_reg xor bit_mask;
res_int(op_bext_c)(data_width_c-1 downto 1) <= (others => '0');
res_int(op_bext_c)(0) <= or_all_f(rs1_reg and bit_mask);
 
 
-- Output Selector ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Zbb --
res_out(op_clz_c) <= res_int(op_clz_c) when ((cmd_buf(op_clz_c) or cmd_buf(op_ctz_c)) = '1') else (others => '0');
res_out(op_ctz_c) <= (others => '0'); -- unused/redundant
res_out(op_cpop_c) <= res_int(op_cpop_c) when (cmd_buf(op_cpop_c) = '1') else (others => '0');
315,6 → 348,11
res_out(op_rol_c) <= res_int(op_rol_c) when (cmd_buf(op_rol_c) = '1') else (others => '0');
res_out(op_rev8_c) <= res_int(op_rev8_c) when (cmd_buf(op_rev8_c) = '1') else (others => '0');
res_out(op_orcb_c) <= res_int(op_orcb_c) when (cmd_buf(op_orcb_c) = '1') else (others => '0');
-- Zbs --
res_out(op_bset_c) <= res_int(op_bset_c) when (cmd_buf(op_bset_c) = '1') else (others => '0');
res_out(op_bclr_c) <= res_int(op_bclr_c) when (cmd_buf(op_bclr_c) = '1') else (others => '0');
res_out(op_binv_c) <= res_int(op_binv_c) when (cmd_buf(op_binv_c) = '1') else (others => '0');
res_out(op_bext_c) <= res_int(op_bext_c) when (cmd_buf(op_bext_c) = '1') else (others => '0');
 
 
-- Output Gate ----------------------------------------------------------------------------
324,7 → 362,7
if rising_edge(clk_i) then
res_o <= (others => '0');
if (valid = '1') then
res_o <= res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here
res_o <= res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here
res_out(op_min_c) or -- res_out(op_max_c) is unused here
res_out(op_sextb_c) or res_out(op_sexth_c) or
res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or
331,7 → 369,8
res_out(op_pack_c) or
res_out(op_ror_c) or res_out(op_rol_c) or
res_out(op_rev8_c) or
res_out(op_orcb_c);
res_out(op_orcb_c) or
res_out(op_bset_c) or res_out(op_bclr_c) or res_out(op_binv_c) or res_out(op_bext_c);
end if;
end if;
end process output_gate;
/neorv32_package.vhd
60,7 → 60,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050200"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
885,9 → 885,13
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
1436,6 → 1440,9
-- com lines --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- hardware flow control --
uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o : out std_ulogic; -- uart data received interrupt
irq_txd_o : out std_ulogic -- uart transmission done interrupt
/neorv32_top.vhd
135,10 → 135,14
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
 
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
 
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
479,8 → 483,8
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
 
-- IRQ acknowledge --
cfs_irq_ack <= fast_irq_ack(2);
-- CFS IRQ acknowledge --
cfs_irq_ack <= fast_irq_ack(1);
 
 
-- CPU Instruction Cache ------------------------------------------------------------------
892,7 → 896,7
end generate;
 
 
-- Universal Asynchronous Receiver/Transmitter 0, Primary UART (UART0) --------------------
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart0_inst_true:
if (IO_UART0_EN = true) generate
902,19 → 906,22
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart0_rdata, -- data out
ack_o => uart0_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart0_rdata, -- data out
ack_o => uart0_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart0_cg_en, -- enable clock generator
clkgen_en_o => uart0_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart0_txd_o,
uart_rxd_i => uart0_rxd_i,
-- hardware flow control --
uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
926,6 → 933,7
uart0_rdata <= (others => '0');
uart0_ack <= '0';
uart0_txd_o <= '0';
uart0_rts_o <= '0';
uart0_cg_en <= '0';
uart0_rxd_irq <= '0';
uart0_txd_irq <= '0';
932,7 → 940,7
end generate;
 
 
-- Universal Asynchronous Receiver/Transmitter 1, Secondary UART (UART1) ------------------
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --------------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart1_inst_true:
if (IO_UART1_EN = true) generate
942,19 → 950,22
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart1_rdata, -- data out
ack_o => uart1_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart1_rdata, -- data out
ack_o => uart1_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart1_cg_en, -- enable clock generator
clkgen_en_o => uart1_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart1_txd_o,
uart_rxd_i => uart1_rxd_i,
-- hardware flow control --
uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
966,6 → 977,7
uart1_rdata <= (others => '0');
uart1_ack <= '0';
uart1_txd_o <= '0';
uart1_rts_o <= '0';
uart1_cg_en <= '0';
uart1_rxd_irq <= '0';
uart1_txd_irq <= '0';
1040,8 → 1052,8
if (IO_TWI_EN = false) generate
twi_rdata <= (others => '0');
twi_ack <= '0';
-- twi_sda_io <= 'Z';
-- twi_scl_io <= 'Z';
-- twi_sda_io <= 'Z'; -- FIXME?
-- twi_scl_io <= 'Z'; -- FIXME?
twi_cg_en <= '0';
twi_irq <= '0';
end generate;
/neorv32_uart.vhd
1,16 → 1,21
-- #################################################################################################
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> #
-- # ********************************************************************************************* #
-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, #
-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. #
-- # Interrupt: UART_RX_available or UART_TX_done #
-- # Frame configuration: 1 start bit, 8 bit data, parity bit (none/even/odd), 1 stop bit, #
-- # programmable BAUD rate via clock pre-scaler and 12-bit BAUD value config register. RX engine #
-- # a simple 2-entry data buffer (for double-buffering). #
-- # Interrupts: UART_RX_available, UART_TX_done #
-- # #
-- # Support for RTS("RTR")/CTS hardware flow control: #
-- # * uart_rts_o = 0: RX is ready to receive a new char, enabled via CTRL.ctrl_uart_rts_en_c #
-- # * uart_cts_i = 0: TX is allowed to send a new char, enabled via CTRL.ctrl_uart_cts_en_c #
-- # #
-- # UART0 / UART1: #
-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the #
-- # interface register addresses and simulation output setting for UART0 (UART_PRIMARY = true) #
-- # or UART1 (UART_PRIMARY = false). #
-- # #
-- # SIMULATION: #
-- # SIMULATION MODE: #
-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write #
-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
18,6 → 23,7
-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 #
-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value #
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
-- # No interrupts are triggered when in SIMULATION MODE. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
77,6 → 83,9
-- com lines --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- hardware flow control --
uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o : out std_ulogic; -- uart data received interrupt
irq_txd_o : out std_ulogic -- uart transmission done interrupt
104,10 → 113,10
constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out");
constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out");
 
-- accessible regs --
-- control register --
signal ctrl : std_ulogic_vector(31 downto 0);
 
-- control reg bits --
-- control register bits --
constant ctrl_uart_baud00_c : natural := 0; -- r/w: UART baud config bit 0
constant ctrl_uart_baud01_c : natural := 1; -- r/w: UART baud config bit 1
constant ctrl_uart_baud02_c : natural := 2; -- r/w: UART baud config bit 2
120,23 → 129,25
constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
constant ctrl_uart_baud11_c : natural := 11; -- r/w: UART baud config bit 11
--
constant ctrl_uart_sim_en_c : natural := 12; -- r/w: UART SIMULATION OUTPUT enable
--
constant ctrl_uart_sim_en_c : natural := 12; -- r/w: UART <<SIMULATION MODE>> enable
-- ...
constant ctrl_uart_rts_en_c : natural := 20; -- r/w: enable hardware flow control: assert rts_o if ready to receive
constant ctrl_uart_cts_en_c : natural := 21; -- r/w: enable hardware flow control: send only if cts_i is asserted
constant ctrl_uart_pmode0_c : natural := 22; -- r/w: Parity config (0=even; 1=odd)
constant ctrl_uart_pmode1_c : natural := 23; -- r/w: Enable parity bit
constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
--
constant ctrl_uart_cts_c : natural := 27; -- r/-: current state of CTS input
constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
-- ...
constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
 
-- data register flags --
constant data_rx_perr_c : natural := 28; -- r/-: Rx parity error
constant data_rx_ferr_c : natural := 29; -- r/-: Rx frame error
constant data_rx_overr_c : natural := 30; -- r/-: Rx data overrun
constant data_rx_avail_c : natural := 31; -- r/-: Rx data available
constant data_rx_overr_c : natural := 30; -- r/-: Rx data overrun
constant data_rx_ferr_c : natural := 29; -- r/-: Rx frame error
constant data_rx_perr_c : natural := 28; -- r/-: Rx parity error
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
150,28 → 161,40
-- numbers of bits in transmission frame --
signal num_bits : std_ulogic_vector(03 downto 0);
 
-- hardware flow-control IO buffer --
signal uart_cts_ff : std_ulogic_vector(1 downto 0);
signal uart_rts : std_ulogic;
 
-- uart tx unit --
type uart_tx_t is record
busy : std_ulogic;
done : std_ulogic;
bitcnt : std_ulogic_vector(03 downto 0);
sreg : std_ulogic_vector(10 downto 0);
baud_cnt : std_ulogic_vector(11 downto 0);
busy : std_ulogic;
done : std_ulogic;
bitcnt : std_ulogic_vector(03 downto 0);
sreg : std_ulogic_vector(10 downto 0);
baud_cnt : std_ulogic_vector(11 downto 0);
tx_granted : std_ulogic; -- allowed to start sending when 1
cts : std_ulogic; -- allow new transmission when 1
end record;
signal uart_tx : uart_tx_t;
 
-- uart rx unit --
type ry_data_buf_t is array (0 to 1) of std_ulogic_vector(07 downto 0);
type uart_rx_t is record
sync : std_ulogic_vector(04 downto 0);
avail : std_ulogic_vector(01 downto 0);
busy : std_ulogic;
busy_ff : std_ulogic;
bitcnt : std_ulogic_vector(03 downto 0);
sreg : std_ulogic_vector(09 downto 0);
data : std_ulogic_vector(07 downto 0);
baud_cnt : std_ulogic_vector(11 downto 0);
ferr : std_ulogic; -- frame error (stop bit not set)
perr : std_ulogic; -- parity error
rtr : std_ulogic; -- ready to receive when 1
--
avail : std_ulogic_vector(02 downto 0);
data : ry_data_buf_t;
data_rd : std_ulogic_vector(07 downto 0);
ferr : std_ulogic_vector(01 downto 0); -- frame error (stop bit not set)
ferr_rd : std_ulogic;
perr : std_ulogic_vector(01 downto 0); -- parity error
perr_rd : std_ulogic;
end record;
signal uart_rx : uart_rx_t;
 
199,6 → 222,8
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
ctrl(ctrl_uart_rts_en_c) <= data_i(ctrl_uart_rts_en_c);
ctrl(ctrl_uart_cts_en_c) <= data_i(ctrl_uart_cts_en_c);
ctrl(ctrl_uart_en_c) <= data_i(ctrl_uart_en_c);
end if;
end if;
210,14 → 235,17
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
data_o(ctrl_uart_rts_en_c) <= ctrl(ctrl_uart_rts_en_c);
data_o(ctrl_uart_cts_en_c) <= ctrl(ctrl_uart_cts_en_c);
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
data_o(ctrl_uart_cts_c) <= uart_cts_ff(1);
else -- uart_id_rtx_addr_c
data_o(data_rx_avail_c) <= uart_rx.avail(0);
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
data_o(data_rx_ferr_c) <= uart_rx.ferr;
data_o(data_rx_perr_c) <= uart_rx.perr;
data_o(07 downto 0) <= uart_rx.data;
data_o(data_rx_avail_c) <= or_all_f(uart_rx.avail);
data_o(data_rx_overr_c) <= and_all_f(uart_rx.avail);
data_o(data_rx_ferr_c) <= uart_rx.ferr_rd;
data_o(data_rx_perr_c) <= uart_rx.perr_rd;
data_o(7 downto 0) <= uart_rx.data_rd;
end if;
end if;
end if;
224,8 → 252,8
end process rw_access;
 
-- number of bits to be sampled --
-- if parity flag is ENABLED: 11 bit (1 start bit + 8 data bits + 1 parity bit + 1 stop bit)
-- if parity flag is DISABLED: 10 bit (1 start bit + 8 data bits + 1 stop bit)
-- if parity flag is ENABLED: 11 bit -> "1011" (1 start bit + 8 data bits + 1 parity bit + 1 stop bit)
-- if parity flag is DISABLED: 10 bit -> "1010" (1 start bit + 8 data bits + 1 stop bit)
num_bits <= "1011" when (ctrl(ctrl_uart_pmode1_c) = '1') else "1010";
 
 
258,7 → 286,7
end if;
uart_tx.busy <= '1';
end if;
elsif (uart_clk = '1') then
elsif (uart_clk = '1') and (uart_tx.tx_granted = '1') then
if (uart_tx.baud_cnt = x"000") then
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx.bitcnt <= std_ulogic_vector(unsigned(uart_tx.bitcnt) - 1);
271,8 → 299,16
uart_tx.done <= '1';
end if;
end if;
-- transmission granted --
if (ctrl(ctrl_uart_en_c) = '0') then -- disabled
uart_tx.tx_granted <= '0';
elsif (uart_tx.done = '1') then
uart_tx.tx_granted <= '0';
elsif (uart_tx.cts = '1') then
uart_tx.tx_granted <= '1';
end if;
-- transmitter output --
uart_txd_o <= uart_tx.sreg(0);
uart_txd_o <= uart_tx.sreg(0) or (not uart_tx.tx_granted); -- keep TX line idle (=high) if waiting for permission to start sending (->CTS)
end if;
end process uart_tx_unit;
 
286,14 → 322,14
uart_rx.sync <= uart_rxd_i & uart_rx.sync(4 downto 1);
 
-- serial engine --
if (uart_rx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
if (uart_rx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
uart_rx.busy <= '0';
uart_rx.baud_cnt <= '0' & ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud01_c); -- half baud delay at the beginning to sample in the middle of each bit
uart_rx.bitcnt <= num_bits;
if (ctrl(ctrl_uart_en_c) = '0') then -- to ensure defined state when reading
uart_rx.perr <= '0';
uart_rx.ferr <= '0';
uart_rx.data <= (others => '0');
uart_rx.perr <= (others => '0');
uart_rx.ferr <= (others => '0');
uart_rx.data <= (others => (others => '0'));
elsif (uart_rx.sync(2 downto 0) = "001") then -- start bit? (falling edge)
uart_rx.busy <= '1';
end if;
307,32 → 343,61
end if;
if (uart_rx.bitcnt = "0000") then
uart_rx.busy <= '0'; -- done
uart_rx.perr <= ctrl(ctrl_uart_pmode1_c) and (xor_all_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
uart_rx.ferr <= not uart_rx.sreg(9); -- check stop bit (error if not set)
-- data buffer (double buffering) --
uart_rx.perr(0) <= ctrl(ctrl_uart_pmode1_c) and (xor_all_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
uart_rx.ferr(0) <= not uart_rx.sreg(9); -- check stop bit (error if not set)
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_rx.data <= uart_rx.sreg(7 downto 0);
uart_rx.data(0) <= uart_rx.sreg(7 downto 0);
else
uart_rx.data <= uart_rx.sreg(8 downto 1);
uart_rx.data(0) <= uart_rx.sreg(8 downto 1);
end if;
uart_rx.perr(1) <= uart_rx.perr(0);
uart_rx.ferr(1) <= uart_rx.ferr(0);
uart_rx.data(1) <= uart_rx.data(0);
end if;
end if;
 
-- RX available flag --
uart_rx.busy_ff <= uart_rx.busy;
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_id_rtx_addr_c)) then -- off/RX read access
uart_rx.avail <= "00";
if (ctrl(ctrl_uart_en_c) = '0') then -- disabled
uart_rx.avail <= "000";
elsif ((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_id_rtx_addr_c) then -- RX read access
uart_rx.avail <= '0' & '0' & uart_rx.avail(1);
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done
uart_rx.avail <= uart_rx.avail(0) & '1';
uart_rx.avail <= uart_rx.avail(1 downto 0) & '1';
end if;
end if;
end process uart_rx_unit;
 
-- Receiver double-buffering - buffer read --
uart_rx.perr_rd <= uart_rx.perr(1) when (uart_rx.avail(1) = '1') else uart_rx.perr(0);
uart_rx.ferr_rd <= uart_rx.ferr(1) when (uart_rx.avail(1) = '1') else uart_rx.ferr(0);
uart_rx.data_rd <= uart_rx.data(1) when (uart_rx.avail(1) = '1') else uart_rx.data(0);
 
-- Interrupt ------------------------------------------------------------------------------
-- RX engine ready for a new char? --
uart_rx.rtr <= '1' when (uart_rx.avail(2 downto 0) = "000") and (uart_rx.busy = '0') and (uart_rx.busy_ff = '0') and (ctrl(ctrl_uart_en_c) = '1') else '0';
 
 
-- Hardware Flow Control ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- UART Rx data available
uart_tx.cts <= (not uart_cts_ff(1)) when (ctrl(ctrl_uart_cts_en_c) = '1') else '1'; -- input is low-active, internal signal is high-active
uart_rts <= (not uart_rx.rtr) when (ctrl(ctrl_uart_rts_en_c) = '1') else '0'; -- output is low-active
 
-- flow-control input/output synchronizer --
flow_control_buffer: process(clk_i)
begin
if rising_edge(clk_i) then -- should be mapped to IOBs
uart_cts_ff <= uart_cts_ff(0) & uart_cts_i;
uart_rts_o <= uart_rts;
end if;
end process flow_control_buffer;
 
 
-- Interrupts -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- UART RX data available
irq_rxd_o <= uart_rx.busy_ff and (not uart_rx.busy);
-- UART Tx complete
-- UART TX complete
irq_txd_o <= uart_tx.done;
 
 

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