OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 54 to Rev 55
    ↔ Reverse comparison
  •

Rev 54 → Rev 55

/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1066) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1068) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"fdc58593",
00000052 => x"fe458593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
111,19 → 111,19
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"730000ef",
00000104 => x"15d000ef",
00000103 => x"248000ef",
00000104 => x"201000ef",
00000105 => x"02050063",
00000106 => x"4a8000ef",
00000106 => x"151000ef",
00000107 => x"00000513",
00000108 => x"4fc000ef",
00000108 => x"1a5000ef",
00000109 => x"00001537",
00000110 => x"d3c50513",
00000111 => x"780000ef",
00000110 => x"d4450513",
00000111 => x"298000ef",
00000112 => x"020000ef",
00000113 => x"00001537",
00000114 => x"d1850513",
00000115 => x"770000ef",
00000114 => x"d2050513",
00000115 => x"288000ef",
00000116 => x"00c12083",
00000117 => x"00000513",
00000118 => x"01010113",
133,947 → 133,949
00000122 => x"00812423",
00000123 => x"00112623",
00000124 => x"00000413",
00000125 => x"119000ef",
00000125 => x"1bd000ef",
00000126 => x"0ff47513",
00000127 => x"111000ef",
00000127 => x"1b5000ef",
00000128 => x"0c800513",
00000129 => x"13d000ef",
00000129 => x"43c000ef",
00000130 => x"00140413",
00000131 => x"fedff06f",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
00000135 => x"02612a23",
00000136 => x"02712823",
00000137 => x"02a12623",
00000138 => x"02b12423",
00000139 => x"02c12223",
00000140 => x"02d12023",
00000141 => x"00e12e23",
00000142 => x"00f12c23",
00000143 => x"01012a23",
00000144 => x"01112823",
00000145 => x"01c12623",
00000146 => x"01d12423",
00000147 => x"01e12223",
00000148 => x"01f12023",
00000149 => x"34102773",
00000150 => x"34071073",
00000151 => x"342027f3",
00000152 => x"0807c863",
00000153 => x"00071683",
00000154 => x"00300593",
00000155 => x"0036f693",
00000156 => x"00270613",
00000157 => x"00b69463",
00000158 => x"00470613",
00000159 => x"34161073",
00000160 => x"00b00713",
00000161 => x"04f77a63",
00000162 => x"48c00793",
00000163 => x"000780e7",
00000164 => x"03c12083",
00000165 => x"03812283",
00000166 => x"03412303",
00000167 => x"03012383",
00000168 => x"02c12503",
00000169 => x"02812583",
00000170 => x"02412603",
00000171 => x"02012683",
00000172 => x"01c12703",
00000173 => x"01812783",
00000174 => x"01412803",
00000175 => x"01012883",
00000176 => x"00c12e03",
00000177 => x"00812e83",
00000178 => x"00412f03",
00000179 => x"00012f83",
00000180 => x"04010113",
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"d5870713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
00000188 => x"80000737",
00000189 => x"ffd74713",
00000190 => x"00e787b3",
00000191 => x"01c00713",
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d8870713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
00000199 => x"800007b7",
00000200 => x"0007a783",
00000201 => x"f69ff06f",
00000202 => x"800007b7",
00000203 => x"0047a783",
00000204 => x"f5dff06f",
00000205 => x"800007b7",
00000206 => x"0087a783",
00000207 => x"f51ff06f",
00000208 => x"800007b7",
00000209 => x"00c7a783",
00000210 => x"f45ff06f",
00000211 => x"8101a783",
00000212 => x"f3dff06f",
00000213 => x"8141a783",
00000214 => x"f35ff06f",
00000215 => x"8181a783",
00000216 => x"f2dff06f",
00000217 => x"81c1a783",
00000218 => x"f25ff06f",
00000219 => x"8201a783",
00000220 => x"f1dff06f",
00000221 => x"8241a783",
00000222 => x"f15ff06f",
00000223 => x"8281a783",
00000224 => x"f0dff06f",
00000225 => x"82c1a783",
00000226 => x"f05ff06f",
00000227 => x"8301a783",
00000228 => x"efdff06f",
00000229 => x"8341a783",
00000230 => x"ef5ff06f",
00000231 => x"8381a783",
00000232 => x"eedff06f",
00000233 => x"83c1a783",
00000234 => x"ee5ff06f",
00000235 => x"8401a783",
00000236 => x"eddff06f",
00000237 => x"8441a783",
00000238 => x"ed5ff06f",
00000239 => x"8481a783",
00000240 => x"ecdff06f",
00000241 => x"84c1a783",
00000242 => x"ec5ff06f",
00000243 => x"8501a783",
00000244 => x"ebdff06f",
00000245 => x"8541a783",
00000246 => x"eb5ff06f",
00000247 => x"8581a783",
00000248 => x"eadff06f",
00000249 => x"85c1a783",
00000250 => x"ea5ff06f",
00000251 => x"8601a783",
00000252 => x"e9dff06f",
00000253 => x"8641a783",
00000254 => x"e95ff06f",
00000255 => x"8681a783",
00000256 => x"e8dff06f",
00000257 => x"86c1a783",
00000258 => x"e85ff06f",
00000259 => x"8701a783",
00000260 => x"e7dff06f",
00000261 => x"00000000",
00000262 => x"00000000",
00000263 => x"fe010113",
00000264 => x"01212823",
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"dfc50513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"4f4000ef",
00000275 => x"07848493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"478000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
00000286 => x"01412483",
00000287 => x"01012903",
00000288 => x"00c12983",
00000289 => x"02010113",
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"e0050513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"498000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
00000301 => x"05778493",
00000302 => x"00f76463",
00000303 => x"03078493",
00000304 => x"00b00793",
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"f8c70713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
00000312 => x"800007b7",
00000313 => x"00b78713",
00000314 => x"12e40663",
00000315 => x"02876663",
00000316 => x"00378713",
00000317 => x"10e40463",
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f6050513",
00000322 => x"434000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
00000326 => x"ff07c793",
00000327 => x"00f407b3",
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"f5050513",
00000332 => x"40c000ef",
00000333 => x"00048513",
00000334 => x"3a8000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"e0850513",
00000338 => x"3f4000ef",
00000339 => x"00001537",
00000340 => x"f7850513",
00000341 => x"3e8000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f8050513",
00000346 => x"3d4000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"fe850513",
00000354 => x"01010113",
00000355 => x"3b00006f",
00000356 => x"00001537",
00000357 => x"e2850513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"e4450513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"e5850513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e6450513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e7c50513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"e9050513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"eac50513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"ec050513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"ee050513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"f0050513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"f1c50513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"f3450513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
00000394 => x"800007b7",
00000395 => x"00078793",
00000396 => x"00251513",
00000397 => x"00a78533",
00000398 => x"48c00793",
00000399 => x"00f52023",
00000400 => x"00000513",
00000401 => x"00008067",
00000402 => x"00100513",
00000403 => x"00008067",
00000404 => x"ff010113",
00000405 => x"00112623",
00000406 => x"00812423",
00000407 => x"00912223",
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"fbc50513",
00000412 => x"2cc000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
00000416 => x"01d00493",
00000417 => x"00040513",
00000418 => x"00140413",
00000419 => x"0ff47413",
00000420 => x"f91ff0ef",
00000421 => x"fe9418e3",
00000422 => x"00c12083",
00000423 => x"00812403",
00000424 => x"00412483",
00000425 => x"01010113",
00000426 => x"00008067",
00000427 => x"ff010113",
00000428 => x"00112623",
00000429 => x"00812423",
00000430 => x"30102673",
00000431 => x"400005b7",
00000432 => x"10058593",
00000433 => x"00b677b3",
00000434 => x"00000413",
00000435 => x"00b78c63",
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"ff050513",
00000440 => x"3e8000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
00000444 => x"01010113",
00000445 => x"00008067",
00000446 => x"fd010113",
00000447 => x"02812423",
00000448 => x"02912223",
00000449 => x"03212023",
00000450 => x"01312e23",
00000451 => x"01412c23",
00000452 => x"02112623",
00000453 => x"01512a23",
00000454 => x"00001a37",
00000455 => x"00050493",
00000456 => x"00058413",
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"088a0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"578000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"514000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
00000474 => x"fcf996e3",
00000475 => x"00090693",
00000476 => x"00900713",
00000477 => x"03000613",
00000478 => x"0096c583",
00000479 => x"00070793",
00000480 => x"fff70713",
00000481 => x"01071713",
00000482 => x"01075713",
00000483 => x"00c59a63",
00000484 => x"000684a3",
00000485 => x"fff68693",
00000486 => x"fe0710e3",
00000487 => x"00000793",
00000488 => x"00f907b3",
00000489 => x"00000593",
00000490 => x"0007c703",
00000491 => x"00070c63",
00000492 => x"00158693",
00000493 => x"00b405b3",
00000494 => x"00e58023",
00000495 => x"01069593",
00000496 => x"0105d593",
00000497 => x"fff78713",
00000498 => x"02f91863",
00000499 => x"00b40433",
00000500 => x"00040023",
00000501 => x"02c12083",
00000502 => x"02812403",
00000503 => x"02412483",
00000504 => x"02012903",
00000505 => x"01c12983",
00000506 => x"01812a03",
00000507 => x"01412a83",
00000508 => x"03010113",
00000509 => x"00008067",
00000510 => x"00070793",
00000511 => x"fadff06f",
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"09460613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
00000519 => x"00f607b3",
00000520 => x"0007c783",
00000521 => x"00470713",
00000522 => x"fff68693",
00000523 => x"00f680a3",
00000524 => x"ff0712e3",
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002703",
00000529 => x"00151513",
00000530 => x"00000793",
00000531 => x"04a77463",
00000532 => x"000016b7",
00000533 => x"00000713",
00000534 => x"ffe68693",
00000535 => x"04f6e663",
00000536 => x"00367613",
00000537 => x"0035f593",
00000538 => x"fff78793",
00000539 => x"01461613",
00000540 => x"00c7e7b3",
00000541 => x"01659593",
00000542 => x"01871713",
00000543 => x"00b7e7b3",
00000544 => x"00e7e7b3",
00000545 => x"10000737",
00000546 => x"00e7e7b3",
00000547 => x"faf02023",
00000548 => x"00008067",
00000549 => x"00178793",
00000550 => x"01079793",
00000551 => x"40a70733",
00000552 => x"0107d793",
00000553 => x"fa9ff06f",
00000554 => x"ffe70513",
00000555 => x"0fd57513",
00000556 => x"00051a63",
00000557 => x"0037d793",
00000558 => x"00170713",
00000559 => x"0ff77713",
00000560 => x"f9dff06f",
00000561 => x"0017d793",
00000562 => x"ff1ff06f",
00000563 => x"f71ff06f",
00000564 => x"fa002783",
00000565 => x"fe07cee3",
00000566 => x"faa02223",
00000567 => x"00008067",
00000568 => x"ff1ff06f",
00000569 => x"ff010113",
00000570 => x"00812423",
00000571 => x"01212023",
00000572 => x"00112623",
00000573 => x"00912223",
00000574 => x"00050413",
00000575 => x"00a00913",
00000576 => x"00044483",
00000577 => x"00140413",
00000578 => x"00049e63",
00000579 => x"00c12083",
00000580 => x"00812403",
00000581 => x"00412483",
00000582 => x"00012903",
00000583 => x"01010113",
00000584 => x"00008067",
00000585 => x"01249663",
00000586 => x"00d00513",
00000587 => x"fa5ff0ef",
00000588 => x"00048513",
00000589 => x"f9dff0ef",
00000590 => x"fc9ff06f",
00000591 => x"fa9ff06f",
00000592 => x"fa010113",
00000593 => x"04f12a23",
00000594 => x"04410793",
00000595 => x"02812c23",
00000596 => x"03212823",
00000597 => x"03412423",
00000598 => x"03512223",
00000599 => x"03612023",
00000600 => x"01712e23",
00000601 => x"01812c23",
00000602 => x"01912a23",
00000603 => x"02112e23",
00000604 => x"02912a23",
00000605 => x"03312623",
00000606 => x"00050413",
00000607 => x"04b12223",
00000608 => x"04c12423",
00000609 => x"04d12623",
00000610 => x"04e12823",
00000611 => x"05012c23",
00000612 => x"05112e23",
00000613 => x"00f12023",
00000614 => x"02500a13",
00000615 => x"00a00a93",
00000616 => x"07300913",
00000617 => x"07500b13",
00000618 => x"07800b93",
00000619 => x"06300c13",
00000620 => x"06900c93",
00000621 => x"00044483",
00000622 => x"02048063",
00000623 => x"0f449a63",
00000624 => x"00144783",
00000625 => x"00240993",
00000626 => x"07278463",
00000627 => x"04f96063",
00000628 => x"07878e63",
00000629 => x"09978863",
00000630 => x"03c12083",
00000631 => x"03812403",
00000632 => x"03412483",
00000633 => x"03012903",
00000634 => x"02c12983",
00000635 => x"02812a03",
00000636 => x"02412a83",
00000637 => x"02012b03",
00000638 => x"01c12b83",
00000639 => x"01812c03",
00000640 => x"01412c83",
00000641 => x"06010113",
00000642 => x"00008067",
00000643 => x"09678663",
00000644 => x"fd7794e3",
00000645 => x"00012783",
00000646 => x"00410593",
00000647 => x"0007a503",
00000648 => x"00478713",
00000649 => x"00e12023",
00000650 => x"dd9ff0ef",
00000651 => x"0640006f",
00000652 => x"00012783",
00000653 => x"0007a503",
00000654 => x"00478713",
00000655 => x"00e12023",
00000656 => x"ea5ff0ef",
00000657 => x"00098413",
00000658 => x"f6dff06f",
00000659 => x"00012783",
00000660 => x"0007c503",
00000661 => x"00478713",
00000662 => x"00e12023",
00000663 => x"e75ff0ef",
00000664 => x"fe5ff06f",
00000665 => x"00012783",
00000666 => x"0007a403",
00000667 => x"00478713",
00000668 => x"00e12023",
00000669 => x"00045863",
00000670 => x"02d00513",
00000671 => x"40800433",
00000672 => x"e51ff0ef",
00000673 => x"00410593",
00000674 => x"00040513",
00000675 => x"c6dff0ef",
00000676 => x"00410513",
00000677 => x"fadff06f",
00000678 => x"00012783",
00000679 => x"00410593",
00000680 => x"00478713",
00000681 => x"0007a503",
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00000683 => x"fe1ff06f",
00000684 => x"01549663",
00000685 => x"00d00513",
00000686 => x"e19ff0ef",
00000687 => x"00140993",
00000688 => x"00048513",
00000689 => x"f99ff06f",
00000690 => x"fd010113",
00000691 => x"00112623",
00000692 => x"00b12a23",
00000693 => x"00c12c23",
00000694 => x"00d12e23",
00000695 => x"02e12023",
00000696 => x"02f12223",
00000697 => x"03012423",
00000698 => x"03112623",
00000699 => x"e55ff0ef",
00000700 => x"00c12083",
00000701 => x"03010113",
00000702 => x"00008067",
00000703 => x"fe802503",
00000704 => x"01055513",
00000705 => x"00157513",
00000706 => x"00008067",
00000707 => x"f8a02223",
00000708 => x"00008067",
00000709 => x"ff010113",
00000710 => x"c80026f3",
00000711 => x"c0002773",
00000712 => x"c80027f3",
00000713 => x"fed79ae3",
00000714 => x"00e12023",
00000715 => x"00f12223",
00000716 => x"00012503",
00000717 => x"00412583",
00000718 => x"01010113",
00000719 => x"00008067",
00000720 => x"fe010113",
00000721 => x"00112e23",
00000722 => x"00812c23",
00000723 => x"00912a23",
00000724 => x"00a12623",
00000725 => x"fc1ff0ef",
00000726 => x"00050493",
00000727 => x"fe002503",
00000728 => x"00058413",
00000729 => x"3e800593",
00000730 => x"104000ef",
00000731 => x"00c12603",
00000732 => x"00000693",
00000733 => x"00000593",
00000734 => x"05c000ef",
00000735 => x"009504b3",
00000736 => x"00a4b533",
00000737 => x"00858433",
00000738 => x"00850433",
00000739 => x"f89ff0ef",
00000740 => x"fe85eee3",
00000741 => x"00b41463",
00000742 => x"fe956ae3",
00000743 => x"01c12083",
00000744 => x"01812403",
00000745 => x"01412483",
00000746 => x"02010113",
00000132 => x"fd010113",
00000133 => x"02812423",
00000134 => x"02912223",
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00000749 => x"00008067",
00000750 => x"00050613",
00000751 => x"00000513",
00000752 => x"0015f693",
00000753 => x"00068463",
00000754 => x"00c50533",
00000755 => x"0015d593",
00000756 => x"00161613",
00000757 => x"fe0596e3",
00000758 => x"00008067",
00000759 => x"00050313",
00000760 => x"ff010113",
00000761 => x"00060513",
00000762 => x"00068893",
00000763 => x"00112623",
00000764 => x"00030613",
00000765 => x"00050693",
00000766 => x"00000713",
00000767 => x"00000793",
00000768 => x"00000813",
00000769 => x"0016fe13",
00000770 => x"00171e93",
00000771 => x"000e0c63",
00000772 => x"01060e33",
00000773 => x"010e3833",
00000774 => x"00e787b3",
00000775 => x"00f807b3",
00000776 => x"000e0813",
00000777 => x"01f65713",
00000778 => x"0016d693",
00000779 => x"00eee733",
00000780 => x"00161613",
00000781 => x"fc0698e3",
00000782 => x"00058663",
00000783 => x"f7dff0ef",
00000784 => x"00a787b3",
00000785 => x"00088a63",
00000786 => x"00030513",
00000787 => x"00088593",
00000788 => x"f69ff0ef",
00000789 => x"00f507b3",
00000790 => x"00c12083",
00000791 => x"00080513",
00000792 => x"00078593",
00000793 => x"01010113",
00000794 => x"00008067",
00000795 => x"06054063",
00000796 => x"0605c663",
00000797 => x"00058613",
00000798 => x"00050593",
00000799 => x"fff00513",
00000800 => x"02060c63",
00000801 => x"00100693",
00000802 => x"00b67a63",
00000803 => x"00c05863",
00000804 => x"00161613",
00000805 => x"00169693",
00000806 => x"feb66ae3",
00000807 => x"00000513",
00000808 => x"00c5e663",
00000809 => x"40c585b3",
00000810 => x"00d56533",
00000811 => x"0016d693",
00000812 => x"00165613",
00000813 => x"fe0696e3",
00000814 => x"00008067",
00000815 => x"00008293",
00000816 => x"fb5ff0ef",
00000817 => x"00058513",
00000818 => x"00028067",
00000819 => x"40a00533",
00000820 => x"00b04863",
00000821 => x"40b005b3",
00000822 => x"00008293",
00000823 => x"f91ff0ef",
00000824 => x"40a00533",
00000825 => x"00028067",
00000826 => x"00008293",
00000827 => x"0005ca63",
00000828 => x"00054c63",
00000829 => x"f79ff0ef",
00000830 => x"00058513",
00000831 => x"00028067",
00000832 => x"40b005b3",
00000833 => x"fe0558e3",
00000834 => x"40a00533",
00000835 => x"f61ff0ef",
00000836 => x"40b00533",
00000837 => x"00028067",
00000838 => x"6f727245",
00000839 => x"4e202172",
00000840 => x"5047206f",
00000841 => x"75204f49",
00000842 => x"2074696e",
00000843 => x"746e7973",
00000844 => x"69736568",
00000845 => x"2164657a",
00000846 => x"0000000a",
00000847 => x"6e696c42",
00000848 => x"676e696b",
00000849 => x"44454c20",
00000850 => x"6d656420",
00000851 => x"7270206f",
00000852 => x"6172676f",
00000853 => x"00000a6d",
00000854 => x"0000031c",
00000855 => x"00000328",
00000856 => x"00000334",
00000857 => x"00000340",
00000858 => x"0000034c",
00000859 => x"00000354",
00000860 => x"0000035c",
00000861 => x"00000364",
00000862 => x"0000036c",
00000863 => x"00000288",
00000864 => x"00000288",
00000865 => x"00000374",
00000866 => x"0000037c",
00000867 => x"00000288",
00000868 => x"00000288",
00000869 => x"00000288",
00000870 => x"00000384",
00000871 => x"00000288",
00000872 => x"00000288",
00000873 => x"00000288",
00000874 => x"0000038c",
00000875 => x"00000288",
00000876 => x"00000288",
00000877 => x"00000288",
00000878 => x"00000288",
00000879 => x"00000394",
00000880 => x"0000039c",
00000881 => x"000003a4",
00000882 => x"000003ac",
00000883 => x"000003b4",
00000884 => x"000003bc",
00000885 => x"000003c4",
00000886 => x"000003cc",
00000887 => x"000003d4",
00000888 => x"000003dc",
00000889 => x"000003e4",
00000890 => x"000003ec",
00000891 => x"000003f4",
00000892 => x"000003fc",
00000893 => x"00000404",
00000894 => x"0000040c",
00000895 => x"00007830",
00000896 => x"4554523c",
00000897 => x"0000203e",
00000898 => x"74736e49",
00000899 => x"74637572",
00000900 => x"206e6f69",
00000901 => x"72646461",
00000902 => x"20737365",
00000903 => x"6173696d",
00000904 => x"6e67696c",
00000905 => x"00006465",
00000906 => x"74736e49",
00000907 => x"74637572",
00000908 => x"206e6f69",
00000909 => x"65636361",
00000910 => x"66207373",
00000911 => x"746c7561",
00000912 => x"00000000",
00000913 => x"656c6c49",
00000914 => x"206c6167",
00000915 => x"74736e69",
00000916 => x"74637572",
00000917 => x"006e6f69",
00000918 => x"61657242",
00000919 => x"696f706b",
00000920 => x"0000746e",
00000921 => x"64616f4c",
00000922 => x"64646120",
00000923 => x"73736572",
00000924 => x"73696d20",
00000925 => x"67696c61",
00000926 => x"0064656e",
00000927 => x"64616f4c",
00000928 => x"63636120",
00000929 => x"20737365",
00000930 => x"6c756166",
00000931 => x"00000074",
00000932 => x"726f7453",
00000933 => x"64612065",
00000934 => x"73657264",
00000935 => x"696d2073",
00000936 => x"696c6173",
00000937 => x"64656e67",
00000938 => x"00000000",
00000939 => x"726f7453",
00000940 => x"63612065",
00000941 => x"73736563",
00000942 => x"75616620",
00000943 => x"0000746c",
00000944 => x"69766e45",
00000945 => x"6d6e6f72",
00000946 => x"20746e65",
00000947 => x"6c6c6163",
00000948 => x"6f726620",
00000949 => x"2d55206d",
00000950 => x"65646f6d",
00000951 => x"00000000",
00000952 => x"69766e45",
00000953 => x"6d6e6f72",
00000954 => x"20746e65",
00000955 => x"6c6c6163",
00000956 => x"6f726620",
00000957 => x"2d4d206d",
00000958 => x"65646f6d",
00000959 => x"00000000",
00000960 => x"6863614d",
00000961 => x"20656e69",
00000962 => x"74666f73",
00000963 => x"65726177",
00000964 => x"746e6920",
00000965 => x"75727265",
00000966 => x"00007470",
00000967 => x"6863614d",
00000968 => x"20656e69",
00000969 => x"656d6974",
00000970 => x"6e692072",
00000971 => x"72726574",
00000972 => x"00747075",
00000973 => x"6863614d",
00000974 => x"20656e69",
00000975 => x"65747865",
00000976 => x"6c616e72",
00000977 => x"746e6920",
00000978 => x"75727265",
00000979 => x"00007470",
00000980 => x"74736146",
00000981 => x"746e6920",
00000982 => x"75727265",
00000983 => x"00207470",
00000984 => x"6e6b6e55",
00000985 => x"206e776f",
00000986 => x"70617274",
00000987 => x"75616320",
00000988 => x"203a6573",
00000989 => x"00000000",
00000990 => x"50204020",
00000991 => x"00003d43",
00000992 => x"544d202c",
00000993 => x"3d4c4156",
00000994 => x"00000000",
00000995 => x"00000540",
00000996 => x"00000590",
00000997 => x"0000059c",
00000998 => x"000005a8",
00000999 => x"000005b4",
00001000 => x"000005c0",
00001001 => x"000005cc",
00001002 => x"000005d8",
00001003 => x"000005e4",
00001004 => x"00000500",
00001005 => x"00000500",
00001006 => x"000005f0",
00001007 => x"4554523c",
00001008 => x"4157203e",
00001009 => x"4e494e52",
00001010 => x"43202147",
00001011 => x"43205550",
00001012 => x"73205253",
00001013 => x"65747379",
00001014 => x"6f6e206d",
00001015 => x"76612074",
00001016 => x"616c6961",
00001017 => x"21656c62",
00001018 => x"522f3c20",
00001019 => x"003e4554",
00001020 => x"5241570a",
00001021 => x"474e494e",
00001022 => x"57532021",
00001023 => x"4153495f",
00001024 => x"65662820",
00001025 => x"72757461",
00001026 => x"72207365",
00001027 => x"69757165",
00001028 => x"29646572",
00001029 => x"20737620",
00001030 => x"495f5748",
00001031 => x"28204153",
00001032 => x"74616566",
00001033 => x"73657275",
00001034 => x"61766120",
00001035 => x"62616c69",
00001036 => x"2029656c",
00001037 => x"6d73696d",
00001038 => x"68637461",
00001039 => x"57530a21",
00001040 => x"4153495f",
00001041 => x"30203d20",
00001042 => x"20782578",
00001043 => x"6d6f6328",
00001044 => x"656c6970",
00001045 => x"6c662072",
00001046 => x"29736761",
00001047 => x"5f57480a",
00001048 => x"20415349",
00001049 => x"7830203d",
00001050 => x"28207825",
00001051 => x"6173696d",
00001052 => x"72736320",
00001053 => x"000a0a29",
00001054 => x"33323130",
00001055 => x"37363534",
00001056 => x"42413938",
00001057 => x"46454443",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"00003938",
00001061 => x"33323130",
00001062 => x"37363534",
00001063 => x"62613938",
00001064 => x"66656463",
00001065 => x"00000000",
00000822 => x"f9dff06f",
00000823 => x"40b005b3",
00000824 => x"00008293",
00000825 => x"f91ff0ef",
00000826 => x"40a00533",
00000827 => x"00028067",
00000828 => x"00008293",
00000829 => x"0005ca63",
00000830 => x"00054c63",
00000831 => x"f79ff0ef",
00000832 => x"00058513",
00000833 => x"00028067",
00000834 => x"40b005b3",
00000835 => x"fe0558e3",
00000836 => x"40a00533",
00000837 => x"f61ff0ef",
00000838 => x"40b00533",
00000839 => x"00028067",
00000840 => x"6f727245",
00000841 => x"4e202172",
00000842 => x"5047206f",
00000843 => x"75204f49",
00000844 => x"2074696e",
00000845 => x"746e7973",
00000846 => x"69736568",
00000847 => x"2164657a",
00000848 => x"0000000a",
00000849 => x"6e696c42",
00000850 => x"676e696b",
00000851 => x"44454c20",
00000852 => x"6d656420",
00000853 => x"7270206f",
00000854 => x"6172676f",
00000855 => x"00000a6d",
00000856 => x"33323130",
00000857 => x"37363534",
00000858 => x"00003938",
00000859 => x"33323130",
00000860 => x"37363534",
00000861 => x"62613938",
00000862 => x"66656463",
00000863 => x"00000000",
00000864 => x"000007c0",
00000865 => x"000007cc",
00000866 => x"000007d8",
00000867 => x"000007e4",
00000868 => x"000007f0",
00000869 => x"000007f8",
00000870 => x"00000800",
00000871 => x"00000808",
00000872 => x"00000810",
00000873 => x"00000728",
00000874 => x"00000728",
00000875 => x"00000818",
00000876 => x"00000820",
00000877 => x"00000728",
00000878 => x"00000728",
00000879 => x"00000728",
00000880 => x"00000828",
00000881 => x"00000728",
00000882 => x"00000728",
00000883 => x"00000728",
00000884 => x"00000830",
00000885 => x"00000728",
00000886 => x"00000728",
00000887 => x"00000728",
00000888 => x"00000728",
00000889 => x"00000838",
00000890 => x"00000840",
00000891 => x"00000848",
00000892 => x"00000850",
00000893 => x"00000858",
00000894 => x"00000860",
00000895 => x"00000868",
00000896 => x"00000870",
00000897 => x"00000878",
00000898 => x"00000880",
00000899 => x"00000888",
00000900 => x"00000890",
00000901 => x"00000898",
00000902 => x"000008a0",
00000903 => x"000008a8",
00000904 => x"000008b0",
00000905 => x"00007830",
00000906 => x"4554523c",
00000907 => x"0000203e",
00000908 => x"74736e49",
00000909 => x"74637572",
00000910 => x"206e6f69",
00000911 => x"72646461",
00000912 => x"20737365",
00000913 => x"6173696d",
00000914 => x"6e67696c",
00000915 => x"00006465",
00000916 => x"74736e49",
00000917 => x"74637572",
00000918 => x"206e6f69",
00000919 => x"65636361",
00000920 => x"66207373",
00000921 => x"746c7561",
00000922 => x"00000000",
00000923 => x"656c6c49",
00000924 => x"206c6167",
00000925 => x"74736e69",
00000926 => x"74637572",
00000927 => x"006e6f69",
00000928 => x"61657242",
00000929 => x"696f706b",
00000930 => x"0000746e",
00000931 => x"64616f4c",
00000932 => x"64646120",
00000933 => x"73736572",
00000934 => x"73696d20",
00000935 => x"67696c61",
00000936 => x"0064656e",
00000937 => x"64616f4c",
00000938 => x"63636120",
00000939 => x"20737365",
00000940 => x"6c756166",
00000941 => x"00000074",
00000942 => x"726f7453",
00000943 => x"64612065",
00000944 => x"73657264",
00000945 => x"696d2073",
00000946 => x"696c6173",
00000947 => x"64656e67",
00000948 => x"00000000",
00000949 => x"726f7453",
00000950 => x"63612065",
00000951 => x"73736563",
00000952 => x"75616620",
00000953 => x"0000746c",
00000954 => x"69766e45",
00000955 => x"6d6e6f72",
00000956 => x"20746e65",
00000957 => x"6c6c6163",
00000958 => x"6f726620",
00000959 => x"2d55206d",
00000960 => x"65646f6d",
00000961 => x"00000000",
00000962 => x"69766e45",
00000963 => x"6d6e6f72",
00000964 => x"20746e65",
00000965 => x"6c6c6163",
00000966 => x"6f726620",
00000967 => x"2d4d206d",
00000968 => x"65646f6d",
00000969 => x"00000000",
00000970 => x"6863614d",
00000971 => x"20656e69",
00000972 => x"74666f73",
00000973 => x"65726177",
00000974 => x"746e6920",
00000975 => x"75727265",
00000976 => x"00007470",
00000977 => x"6863614d",
00000978 => x"20656e69",
00000979 => x"656d6974",
00000980 => x"6e692072",
00000981 => x"72726574",
00000982 => x"00747075",
00000983 => x"6863614d",
00000984 => x"20656e69",
00000985 => x"65747865",
00000986 => x"6c616e72",
00000987 => x"746e6920",
00000988 => x"75727265",
00000989 => x"00007470",
00000990 => x"74736146",
00000991 => x"746e6920",
00000992 => x"75727265",
00000993 => x"00207470",
00000994 => x"6e6b6e55",
00000995 => x"206e776f",
00000996 => x"70617274",
00000997 => x"75616320",
00000998 => x"203a6573",
00000999 => x"00000000",
00001000 => x"50204020",
00001001 => x"00003d43",
00001002 => x"544d202c",
00001003 => x"3d4c4156",
00001004 => x"00000000",
00001005 => x"000009e4",
00001006 => x"00000a34",
00001007 => x"00000a40",
00001008 => x"00000a4c",
00001009 => x"00000a58",
00001010 => x"00000a64",
00001011 => x"00000a70",
00001012 => x"00000a7c",
00001013 => x"00000a88",
00001014 => x"000009a4",
00001015 => x"000009a4",
00001016 => x"00000a94",
00001017 => x"4554523c",
00001018 => x"4157203e",
00001019 => x"4e494e52",
00001020 => x"43202147",
00001021 => x"43205550",
00001022 => x"73205253",
00001023 => x"65747379",
00001024 => x"6f6e206d",
00001025 => x"76612074",
00001026 => x"616c6961",
00001027 => x"21656c62",
00001028 => x"522f3c20",
00001029 => x"003e4554",
00001030 => x"5241570a",
00001031 => x"474e494e",
00001032 => x"57532021",
00001033 => x"4153495f",
00001034 => x"65662820",
00001035 => x"72757461",
00001036 => x"72207365",
00001037 => x"69757165",
00001038 => x"29646572",
00001039 => x"20737620",
00001040 => x"495f5748",
00001041 => x"28204153",
00001042 => x"74616566",
00001043 => x"73657275",
00001044 => x"61766120",
00001045 => x"62616c69",
00001046 => x"2029656c",
00001047 => x"6d73696d",
00001048 => x"68637461",
00001049 => x"57530a21",
00001050 => x"4153495f",
00001051 => x"30203d20",
00001052 => x"20782578",
00001053 => x"6d6f6328",
00001054 => x"656c6970",
00001055 => x"6c662072",
00001056 => x"29736761",
00001057 => x"5f57480a",
00001058 => x"20415349",
00001059 => x"7830203d",
00001060 => x"28207825",
00001061 => x"6173696d",
00001062 => x"72736320",
00001063 => x"000a0a29",
00001064 => x"33323130",
00001065 => x"37363534",
00001066 => x"42413938",
00001067 => x"46454443",
others => x"00000000"
);
 
/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1003) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1009) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"f2058593",
00000036 => x"f3858593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
111,22 → 111,22
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"359000ef",
00000103 => x"36d000ef",
00000104 => x"00100513",
00000105 => x"3f9000ef",
00000105 => x"40d000ef",
00000106 => x"00005537",
00000107 => x"00000613",
00000108 => x"00000593",
00000109 => x"b0050513",
00000110 => x"295000ef",
00000111 => x"1b1000ef",
00000110 => x"2a9000ef",
00000111 => x"1c5000ef",
00000112 => x"00245793",
00000113 => x"00a78533",
00000114 => x"00f537b3",
00000115 => x"00b785b3",
00000116 => x"1c9000ef",
00000116 => x"1dd000ef",
00000117 => x"ffff07b7",
00000118 => x"4c078793",
00000118 => x"4d478793",
00000119 => x"30579073",
00000120 => x"08000793",
00000121 => x"30479073",
134,883 → 134,889
00000123 => x"00000013",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"ec850513",
00000127 => x"2f5000ef",
00000126 => x"edc50513",
00000127 => x"309000ef",
00000128 => x"f1302573",
00000129 => x"24c000ef",
00000129 => x"260000ef",
00000130 => x"ffff1537",
00000131 => x"f0050513",
00000132 => x"2e1000ef",
00000131 => x"f1450513",
00000132 => x"2f5000ef",
00000133 => x"fe002503",
00000134 => x"238000ef",
00000134 => x"24c000ef",
00000135 => x"ffff1537",
00000136 => x"f0850513",
00000137 => x"2cd000ef",
00000136 => x"f1c50513",
00000137 => x"2e1000ef",
00000138 => x"fe402503",
00000139 => x"224000ef",
00000139 => x"238000ef",
00000140 => x"ffff1537",
00000141 => x"f1450513",
00000142 => x"2b9000ef",
00000141 => x"f2450513",
00000142 => x"2cd000ef",
00000143 => x"30102573",
00000144 => x"210000ef",
00000144 => x"224000ef",
00000145 => x"ffff1537",
00000146 => x"f1c50513",
00000147 => x"2a5000ef",
00000148 => x"fe802503",
00000149 => x"ffff14b7",
00000150 => x"00341413",
00000151 => x"1f4000ef",
00000152 => x"ffff1537",
00000153 => x"f2450513",
00000154 => x"289000ef",
00000155 => x"ff802503",
00000156 => x"1e0000ef",
00000157 => x"f2c48513",
00000158 => x"279000ef",
00000159 => x"ff002503",
00000160 => x"1d0000ef",
00000161 => x"ffff1537",
00000162 => x"f3850513",
00000163 => x"265000ef",
00000164 => x"ffc02503",
00000165 => x"1bc000ef",
00000166 => x"f2c48513",
00000167 => x"255000ef",
00000168 => x"ff402503",
00000169 => x"1ac000ef",
00000170 => x"ffff1537",
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00000852 => x"00d56533",
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00000984 => x"74726f62",
00000985 => x"00000a2e",
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00000896 => x"2064616f",
00000897 => x"6d6f7266",
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00000945 => x"20296e2f",
00000946 => x"00000000",
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00000977 => x"74796220",
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00000982 => x"75410a0a",
00000983 => x"6f626f74",
00000984 => x"6920746f",
00000985 => x"7338206e",
00000986 => x"7250202e",
00000987 => x"20737365",
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00000989 => x"61206f74",
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00000991 => x"00000a2e",
00000992 => x"726f6241",
00000993 => x"2e646574",
00000994 => x"00000a0a",
00000995 => x"444d430a",
00000996 => x"00203e3a",
00000997 => x"53207962",
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00000999 => x"4e206e61",
00001000 => x"69746c6f",
00001001 => x"0000676e",
00001002 => x"61766e49",
00001003 => x"2064696c",
00001004 => x"00444d43",
00001005 => x"33323130",
00001006 => x"37363534",
00001007 => x"42413938",
00001008 => x"46454443",
others => x"00000000"
);
 
/neorv32_cpu.vhd
73,7 → 73,7
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29)
185,8 → 185,8
-- FIXME: Bit manipulation warning --
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still HIGHLY EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
 
-- FIXME: Floating-point extension (Zfinx) warning --
assert not (CPU_EXTENSION_RISCV_Zfinx = true) report "NEORV32 CPU CONFIG WARNING! 32-bit floating-point extension (F/Zfinx) is WORK-IN-PROGRESS and NOT OPERATIONAL yet." severity warning;
-- Co-processor timeout counter (for debugging only) --
assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
 
-- PMP regions check --
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
/neorv32_cpu_alu.vhd
97,11 → 97,12
 
-- co-processor arbiter and interface --
type cp_ctrl_t is record
cmd : std_ulogic;
cmd_ff : std_ulogic;
busy : std_ulogic;
start : std_ulogic;
halt : std_ulogic;
cmd : std_ulogic;
cmd_ff : std_ulogic;
busy : std_ulogic;
start : std_ulogic;
halt : std_ulogic;
timeout : std_ulogic_vector(9 downto 0);
end record;
signal cp_ctrl : cp_ctrl_t;
 
275,15 → 276,25
cp_arbiter: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.timeout <= (others => '0');
elsif rising_edge(clk_i) then
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
if (or_all_f(cp_valid_i) = '1') then -- cp computation done?
cp_ctrl.busy <= '0';
elsif (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
cp_ctrl.busy <= '0';
elsif (cp_ctrl.start = '1') then
cp_ctrl.busy <= '1';
end if;
-- timeout counter --
if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
else
cp_ctrl.timeout <= (others => '0');
end if;
end if;
end process cp_arbiter;
 
/neorv32_cpu_control.vhd
1090,7 → 1090,7
 
when opcode_fop_c => -- floating-point operations
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) then
if (CPU_EXTENSION_RISCV_Zfinx = true) and (decode_aux.is_float_op = '1') then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- use FPU CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
2110,7 → 2110,7
 
-- floating-point (FPU) exception flags --
-- --------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) and (execute_engine.state = ALU_WAIT) then
if (CPU_EXTENSION_RISCV_Zfinx = true) then
csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
end if;
 
/neorv32_cpu_cp_fpu.vhd
1,19 → 1,22
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >> #
-- # ********************************************************************************************* #
-- # #
-- # !!! WORK-IN-PROGRESS !!! #
-- # !!! THIS UNIT IS NOT FUNCTIONAL YET !!! #
-- # #
-- # ********************************************************************************************* #
-- # The Zfinx floating-point extension uses the integer register file (x) for all FP operations. #
-- # See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information. #
-- # #
-- # Design Notes: #
-- # * This FPU is based on a multi-cycle architecture and is NOT suited for pipelined operations. #
-- # * The hardware design goal was SIZE (performance comes second). All shift operations are done #
-- # using an iterative approach (one bit per clock cycle, no barrel shifters!). #
-- # * Multiplication (FMUL instruction) will infer DSP blocks (if available). #
-- # * Subnormal numbers are not supported yet - they are "flushed to zero" before entering the #
-- # actual FPU core. #
-- # * Division and sqare root operations (FDIV, FSQRT) and fused multiply-accumulate operations #
-- # (F[N]MADD) are not supported yet - they will raise an illegal instruction exception. #
-- # * Rounding mode <100> ("round to nearest, ties to max magnitude") is not supported yet. #
-- # * Signaling NaNs (sNaN) will not be generated by the hardware at all. However, if inserted by #
-- # the programmer they are handled correctly. #
-- # ********************************************************************************************* #
-- # !! Enabling the Zfinx extension does not has an effect on the CPU. If F is enabled, there !! #
-- # !! will be no traps when trying to execute floating-point instructions, since the main !! #
-- # !! CPU control unit allready provides all necessary Zfinx-extension infrastructure. !! #
-- # !! However, all Zfinx instructions will always return zero. !! #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
72,13 → 75,1727
 
architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is
 
-- FPU core functions --
constant op_class_c : std_ulogic_vector(2 downto 0) := "000";
constant op_comp_c : std_ulogic_vector(2 downto 0) := "001";
constant op_i2f_c : std_ulogic_vector(2 downto 0) := "010";
constant op_f2i_c : std_ulogic_vector(2 downto 0) := "011";
constant op_sgnj_c : std_ulogic_vector(2 downto 0) := "100";
constant op_minmax_c : std_ulogic_vector(2 downto 0) := "101";
constant op_addsub_c : std_ulogic_vector(2 downto 0) := "110";
constant op_mul_c : std_ulogic_vector(2 downto 0) := "111";
 
-- float-to-integer unit --
component neorv32_cpu_cp_fpu_f2i
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- 0=signed, 1=unsigned
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(07 downto 0); -- exponent
mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa
class_i : in std_ulogic_vector(09 downto 0); -- operand class
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- integer result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end component;
 
-- normalizer + rounding unit --
component neorv32_cpu_cp_fpu_normalizer
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float)
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent
mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa
integer_i : in std_ulogic_vector(31 downto 0); -- integer input
class_i : in std_ulogic_vector(09 downto 0); -- input number class
flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- result (float or int)
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end component;
 
-- commands (one-hot) --
type cmd_t is record
instr_class : std_ulogic;
instr_sgnj : std_ulogic;
instr_comp : std_ulogic;
instr_i2f : std_ulogic;
instr_f2i : std_ulogic;
instr_minmax : std_ulogic;
instr_addsub : std_ulogic;
instr_mul : std_ulogic;
funct : std_ulogic_vector(2 downto 0);
end record;
signal cmd : cmd_t;
signal funct_ff : std_ulogic_vector(2 downto 0);
 
-- co-processor control engine --
type ctrl_state_t is (S_IDLE, S_BUSY);
type ctrl_engine_t is record
state : ctrl_state_t;
start : std_ulogic;
valid : std_ulogic;
end record;
signal ctrl_engine : ctrl_engine_t;
 
-- floating-point operands --
type op_data_t is array (0 to 1) of std_ulogic_vector(31 downto 0);
type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0);
type fpu_operands_t is record
rs1 : std_ulogic_vector(31 downto 0); -- operand 1
rs1_class : std_ulogic_vector(09 downto 0); -- operand 1 number class
rs2 : std_ulogic_vector(31 downto 0); -- operand 2
rs2_class : std_ulogic_vector(09 downto 0); -- operand 2 number class
frm : std_ulogic_vector(02 downto 0); -- rounding mode
end record;
signal op_data : op_data_t;
signal op_class : op_class_t;
signal fpu_operands : fpu_operands_t;
 
-- floating-point comparator --
signal comp_equal_ff : std_ulogic;
signal comp_less_ff : std_ulogic;
signal comp_less : std_ulogic;
 
-- functional units interface --
type fu_interface_t is record
result : std_ulogic_vector(31 downto 0);
flags : std_ulogic_vector(04 downto 0);
start : std_ulogic;
done : std_ulogic;
end record;
signal fu_classify : fu_interface_t;
signal fu_compare : fu_interface_t;
signal fu_sign_inject : fu_interface_t;
signal fu_min_max : fu_interface_t;
signal fu_conv_f2i : fu_interface_t;
signal fu_addsub : fu_interface_t;
signal fu_mul : fu_interface_t;
signal fu_core_done : std_ulogic; -- FU operation completed
 
-- integer-to-float --
type fu_i2f_interface_t is record
result : std_ulogic_vector(31 downto 0);
sign : std_ulogic;
start : std_ulogic;
done : std_ulogic;
end record;
signal fu_conv_i2f : fu_i2f_interface_t; -- float result
 
-- multiplier unit --
type multiplier_t is record
opa : unsigned(23 downto 0); -- mantissa A plus hidden one
opb : unsigned(23 downto 0); -- mantissa B plus hidden one
buf_ff : unsigned(47 downto 0); -- product buffer
sign : std_ulogic; -- resulting sign
product : std_ulogic_vector(47 downto 0); -- product
exp_sum : std_ulogic_vector(08 downto 0); -- incl 1x overflow/underflow bit
exp_res : std_ulogic_vector(09 downto 0); -- resulting exponent incl 2x overflow/underflow bit
--
res_class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0); -- exception flags
--
start : std_ulogic;
latency : std_ulogic_vector(02 downto 0); -- unit latency
done : std_ulogic;
end record;
signal multiplier : multiplier_t;
 
-- adder/subtractor unit --
type addsub_t is record
-- input comparison --
exp_comp : std_ulogic_vector(01 downto 0); -- equal & less
small_exp : std_ulogic_vector(07 downto 0);
small_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one
large_exp : std_ulogic_vector(07 downto 0);
large_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one
-- smaller mantissa alginment --
man_sreg : std_ulogic_vector(23 downto 0); -- mantissa + hidden one
man_g_ext : std_ulogic;
man_r_ext : std_ulogic;
man_s_ext : std_ulogic;
exp_cnt : std_ulogic_vector(08 downto 0);
-- adder/subtractor stage --
man_comp : std_ulogic;
man_s : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS
man_l : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS
add_stage : std_ulogic_vector(27 downto 0); -- adder result incl. overflow
-- result --
res_sign : std_ulogic;
res_sum : std_ulogic_vector(27 downto 0); -- mantissa sum (+1 bit) + GRS bits (for rounding)
res_class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0); -- exception flags
-- arbitration --
start : std_ulogic;
latency : std_ulogic_vector(04 downto 0); -- unit latency
done : std_ulogic;
end record;
signal addsub : addsub_t;
 
-- normalizer interface (normalization & rounding and int-to-float) --
type normalizer_t is record
start : std_ulogic;
mode : std_ulogic;
sign : std_ulogic;
xexp : std_ulogic_vector(08 downto 0);
xmantissa : std_ulogic_vector(47 downto 0);
result : std_ulogic_vector(31 downto 0);
class : std_ulogic_vector(09 downto 0);
flags_in : std_ulogic_vector(04 downto 0);
flags_out : std_ulogic_vector(04 downto 0);
done : std_ulogic;
end record;
signal normalizer : normalizer_t;
 
begin
 
-- There is nothing to see here yet -------------------------------------------------------
-- ****************************************************************************************************************************
-- Control
-- ****************************************************************************************************************************
 
-- Instruction Decoding -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
res_o <= (others => '0');
fflags_o <= (others => '0');
valid_o <= start_i;
-- one-hot re-encoding --
cmd.instr_class <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11100") else '0';
cmd.instr_comp <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "10100") else '0';
cmd.instr_i2f <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11010") else '0';
cmd.instr_f2i <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11000") else '0';
cmd.instr_sgnj <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00100") else '0';
cmd.instr_minmax <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00101") else '0';
cmd.instr_addsub <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_8_c) = "0000") else '0';
cmd.instr_mul <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00010") else '0';
 
-- binary re-encoding --
cmd.funct <= op_mul_c when (cmd.instr_mul = '1') else
op_addsub_c when (cmd.instr_addsub = '1') else
op_minmax_c when (cmd.instr_minmax = '1') else
op_sgnj_c when (cmd.instr_sgnj = '1') else
op_f2i_c when (cmd.instr_f2i = '1') else
op_i2f_c when (cmd.instr_i2f = '1') else
op_comp_c when (cmd.instr_comp = '1') else
op_class_c;--when (cmd.instr_class = '1') else (others => '-');
 
 
-- Input Operands: Check for subnormal numbers (flush to zero) ----------------------------
-- -------------------------------------------------------------------------------------------
-- Subnormal numbers are not supported and are "flushed to zero"! FIXME / TODO
-- rs1 --
op_data(0)(31) <= rs1_i(31);
op_data(0)(30 downto 23) <= rs1_i(30 downto 23);
op_data(0)(22 downto 00) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal
-- rs2 --
op_data(1)(31) <= rs2_i(31);
op_data(1)(30 downto 23) <= rs2_i(30 downto 23);
op_data(1)(22 downto 00) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal
 
 
-- Number Classifier ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
number_classifier: process(op_data)
variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v : std_ulogic;
variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic;
begin
for i in 0 to 1 loop -- for rs1 and rs2 inputs
-- check for all-zero/all-one --
op_m_all_zero_v := not or_all_f(op_data(i)(22 downto 00));
op_e_all_zero_v := not or_all_f(op_data(i)(30 downto 23));
op_e_all_one_v := and_all_f(op_data(i)(30 downto 23));
 
-- check special cases --
op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero
op_is_inf_v := op_e_all_one_v and op_m_all_zero_v; -- infinity
op_is_denorm_v := '0'; -- FIXME / TODO op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal
op_is_nan_v := op_e_all_one_v and (not op_m_all_zero_v); -- NaN
 
-- actual attributes --
op_class(i)(fp_class_neg_inf_c) <= op_data(i)(31) and op_is_inf_v; -- negative infinity
op_class(i)(fp_class_neg_norm_c) <= op_data(i)(31) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- negative normal number
op_class(i)(fp_class_neg_denorm_c) <= op_data(i)(31) and op_is_denorm_v; -- negative subnormal number
op_class(i)(fp_class_neg_zero_c) <= op_data(i)(31) and op_is_zero_v; -- negative zero
op_class(i)(fp_class_pos_zero_c) <= (not op_data(i)(31)) and op_is_zero_v; -- positive zero
op_class(i)(fp_class_pos_denorm_c) <= (not op_data(i)(31)) and op_is_denorm_v; -- positive subnormal number
op_class(i)(fp_class_pos_norm_c) <= (not op_data(i)(31)) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- positive normal number
op_class(i)(fp_class_pos_inf_c) <= (not op_data(i)(31)) and op_is_inf_v; -- positive infinity
op_class(i)(fp_class_snan_c) <= op_is_nan_v and (not op_data(i)(22)); -- signaling NaN
op_class(i)(fp_class_qnan_c) <= op_is_nan_v and ( op_data(i)(22)); -- quiet NaN
end loop; -- i
end process number_classifier;
 
 
-- Co-Processor Control Engine ------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
control_engine_fsm: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_engine.state <= S_IDLE;
ctrl_engine.start <= '0';
fpu_operands.frm <= (others => '0');
fpu_operands.rs1 <= (others => '0');
fpu_operands.rs1_class <= (others => '0');
fpu_operands.rs2 <= (others => '0');
fpu_operands.rs2_class <= (others => '0');
funct_ff <= (others => '0');
elsif rising_edge(clk_i) then
-- arbiter defaults --
ctrl_engine.valid <= '0';
ctrl_engine.start <= '0';
 
-- state machine --
case ctrl_engine.state is
 
when S_IDLE => -- waiting for operation trigger
-- ------------------------------------------------------------
funct_ff <= cmd.funct; -- actual operation to execute
-- rounding mode --
-- TODO / FIXME "round to nearest, ties to max magnitude" (0b100) is not supported yet
if (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "111") then
fpu_operands.frm <= '0' & frm_i(1 downto 0);
else
fpu_operands.frm <= '0' & ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c);
end if;
--
if (start_i = '1') then
-- operand data --
fpu_operands.rs1 <= op_data(0);
fpu_operands.rs1_class <= op_class(0);
fpu_operands.rs2 <= op_data(1);
fpu_operands.rs2_class <= op_class(1);
-- execute! --
ctrl_engine.start <= '1';
ctrl_engine.state <= S_BUSY;
end if;
 
when S_BUSY => -- operation in progress (multi-cycle)
-- -----------------------------------------------------------
if (fu_core_done = '1') then -- processing done?
ctrl_engine.valid <= '1';
ctrl_engine.state <= S_IDLE;
end if;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl_engine.state <= S_IDLE;
 
end case;
end if;
end process control_engine_fsm;
 
-- operation done / valid output --
valid_o <= ctrl_engine.valid;
 
 
-- Functional Unit Interface (operation-start trigger) ------------------------------------
-- -------------------------------------------------------------------------------------------
fu_classify.start <= ctrl_engine.start and cmd.instr_class;
fu_compare.start <= ctrl_engine.start and cmd.instr_comp;
fu_sign_inject.start <= ctrl_engine.start and cmd.instr_sgnj;
fu_min_max.start <= ctrl_engine.start and cmd.instr_minmax;
fu_conv_i2f.start <= ctrl_engine.start and cmd.instr_i2f;
fu_conv_f2i.start <= ctrl_engine.start and cmd.instr_f2i;
fu_addsub.start <= ctrl_engine.start and cmd.instr_addsub;
fu_mul.start <= ctrl_engine.start and cmd.instr_mul;
 
 
-- ****************************************************************************************************************************
-- FPU Core - Functional Units
-- ****************************************************************************************************************************
 
-- Number Classifier (FCLASS) -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
fu_classify.flags <= (others => '0'); -- does not generate flags at all
fu_classify.result(31 downto 10) <= (others => '0');
fu_classify.result(09 downto 00) <= fpu_operands.rs1_class;
fu_classify.done <= fu_classify.start;
 
 
-- Floating-Point Comparator --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
float_comparator: process(clk_i)
variable cond_v : std_ulogic_vector(1 downto 0);
begin
if rising_edge(clk_i) then
-- equal --
if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf == +inf
((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf == -inf
(((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and
((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) or -- +/-zero == +/-zero
(fpu_operands.rs1 = fpu_operands.rs2) then -- identical in every way
comp_equal_ff <= '1';
else
comp_equal_ff <= '0';
end if;
 
-- less than --
if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf !< +inf
((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf !< -inf
(((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and
((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) then -- +/-zero !< +/-zero
comp_less_ff <= '0';
else
cond_v := fpu_operands.rs1(31) & fpu_operands.rs2(31);
case cond_v is
when "10" => comp_less_ff <= '1'; -- rs1 negative, rs2 positive
when "01" => comp_less_ff <= '0'; -- rs1 positive, rs2 negative
when "00" => comp_less_ff <= comp_less; -- both positive
when "11" => comp_less_ff <= not comp_less; -- both negative
when others => comp_less_ff <= '0'; -- undefined
end case;
end if;
 
-- comparator latency --
fu_compare.done <= fu_compare.start; -- for actual comparison operation
fu_min_max.done <= fu_min_max.start; -- for min/max operations
end if;
end process float_comparator;
 
-- less than - only compare the "magnitude" part - sign bit has to be handled separately --
comp_less <= '1' when (unsigned(fpu_operands.rs1(30 downto 0)) < unsigned(fpu_operands.rs2(30 downto 0))) else '0';
 
 
-- Comparison (FEQ/FLT/FLE) ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
float_comparison: process(fpu_operands, ctrl_i, comp_equal_ff, comp_less_ff)
variable snan_v : std_ulogic; -- at least one input is sNaN
variable qnan_v : std_ulogic; -- at least one input is qNaN
begin
-- check for NaN --
snan_v := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_snan_c);
qnan_v := fpu_operands.rs1_class(fp_class_qnan_c) or fpu_operands.rs2_class(fp_class_qnan_c);
 
-- condition evaluation --
fu_compare.result <= (others => '0');
case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is
when "00" => -- FLE: less than or equal
fu_compare.result(0) <= (comp_less_ff or comp_equal_ff) and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when "01" => -- FLT: less than
fu_compare.result(0) <= comp_less_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when "10" => -- FEQ: equal
fu_compare.result(0) <= comp_equal_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when others => -- undefined
fu_compare.result(0) <= '0';
end case;
end process float_comparison;
 
-- latency --
-- -> done in "float_comparator"
 
-- exceptions --
fu_compare.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions
 
 
-- Min/Max Select (FMIN/FMAX) -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
min_max_select: process(fpu_operands, comp_less_ff, fpu_operands, fu_compare, ctrl_i)
variable cond_v : std_ulogic_vector(2 downto 0);
begin
-- comparison restul - check for special cases: -0 is less than +0
if ((fpu_operands.rs1_class(fp_class_neg_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_zero_c) = '1')) then
cond_v(0) := ctrl_i(ctrl_ir_funct3_0_c);
elsif ((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1')) then
cond_v(0) := not ctrl_i(ctrl_ir_funct3_0_c);
else -- "normal= comparison
cond_v(0) := comp_less_ff xnor ctrl_i(ctrl_ir_funct3_0_c); -- min/max select
end if;
 
-- nmumber NaN check --
cond_v(2) := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs1_class(fp_class_qnan_c);
cond_v(1) := fpu_operands.rs2_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_qnan_c);
 
-- data output --
case cond_v is
when "000" => fu_min_max.result <= fpu_operands.rs1;
when "001" => fu_min_max.result <= fpu_operands.rs2;
when "010" | "011" => fu_min_max.result <= fpu_operands.rs1; -- if one input is NaN output the non-NaN one
when "100" | "101" => fu_min_max.result <= fpu_operands.rs2; -- if one input is NaN output the non-NaN one
when others => fu_min_max.result <= fp_single_qnan_c; -- output quiet NaN if both inputs are NaN
end case;
end process min_max_select;
 
-- latency --
-- -> done in "float_comparator"
 
-- exceptions --
fu_min_max.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions
 
 
-- Convert: Float to [unsigned] Integer (FCVT.S.W) ----------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_fpu_f2i_inst: neorv32_cpu_cp_fpu_f2i
port map (
-- control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
start_i => fu_conv_f2i.start, -- trigger operation
rmode_i => fpu_operands.frm, -- rounding mode
funct_i => ctrl_i(ctrl_ir_funct12_0_c), -- 0=signed, 1=unsigned
-- input --
sign_i => fpu_operands.rs1(31), -- sign
exponent_i => fpu_operands.rs1(30 downto 23), -- exponent
mantissa_i => fpu_operands.rs1(22 downto 00), -- mantissa
class_i => fpu_operands.rs1_class, -- operand class
-- output --
result_o => fu_conv_f2i.result, -- integer result
flags_o => fu_conv_f2i.flags, -- exception flags
done_o => fu_conv_f2i.done -- operation done
);
 
 
-- Sign-Injection (FSGNJ) -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
sign_injector: process(ctrl_i, fpu_operands)
begin
case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is
when "00" => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- FSGNJ
when "01" => fu_sign_inject.result(31) <= not fpu_operands.rs2(31); -- FSGNJN
when "10" => fu_sign_inject.result(31) <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- FSGNJX
when others => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- undefined
end case;
fu_sign_inject.result(30 downto 0) <= fpu_operands.rs1(30 downto 0);
fu_sign_inject.flags <= (others => '0'); -- does not generate flags
end process sign_injector;
 
-- latency --
fu_sign_inject.done <= fu_sign_inject.start;
 
 
-- Convert: [unsigned] Integer to Float (FCVT.W.S) ----------------------------------------
-- -------------------------------------------------------------------------------------------
convert_i2f: process(clk_i)
begin
-- this process only computes the absolute input value
-- the actual conversion is done by the normalizer
if rising_edge(clk_i) then
if (ctrl_i(ctrl_ir_funct12_0_c) = '0') and (rs1_i(31) = '1') then -- convert signed integer
fu_conv_i2f.result <= std_ulogic_vector(0 - unsigned(rs1_i));
fu_conv_i2f.sign <= rs1_i(31); -- original sign
else -- convert unsigned integer
fu_conv_i2f.result <= rs1_i;
fu_conv_i2f.sign <= '0';
end if;
fu_conv_i2f.done <= fu_conv_i2f.start; -- actual conversion is done by the normalizer unit
end if;
end process convert_i2f;
 
 
-- Multiplier Core (FMUL) -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
multiplier_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- multiplier core --
if (multiplier.start = '1') then -- FIXME / TODO remove buffer?
multiplier.opa <= unsigned('1' & fpu_operands.rs1(22 downto 0)); -- append hidden one
multiplier.opb <= unsigned('1' & fpu_operands.rs2(22 downto 0));
end if;
multiplier.buf_ff <= multiplier.opa * multiplier.opb;
multiplier.product <= std_ulogic_vector(multiplier.buf_ff(47 downto 0)); -- let the register balancing do the magic here
multiplier.sign <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- resulting sign
 
-- exponent computation --
multiplier.exp_res <= std_ulogic_vector(unsigned('0' & multiplier.exp_sum) - 127);
if (multiplier.exp_res(multiplier.exp_res'left) = '1') then -- underflow (exp_res is "negative")
multiplier.flags(fp_exc_of_c) <= '0';
multiplier.flags(fp_exc_uf_c) <= '1';
elsif (multiplier.exp_res(multiplier.exp_res'left-1) = '1') then -- overflow
multiplier.flags(fp_exc_of_c) <= '1';
multiplier.flags(fp_exc_uf_c) <= '0';
else
multiplier.flags(fp_exc_of_c) <= '0';
multiplier.flags(fp_exc_uf_c) <= '0';
end if;
 
-- invalid operation --
multiplier.flags(fp_exc_nv_c) <=
((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs1_class(fp_class_neg_zero_c)) and
(fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))) or -- mul(+/-zero, +/-inf)
((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and
(fpu_operands.rs2_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c))); -- mul(+/-inf, +/-zero)
 
-- latency shift register --
multiplier.latency <= multiplier.latency(multiplier.latency'left-1 downto 0) & multiplier.start;
end if;
end process multiplier_core;
 
-- exponent sum --
multiplier.exp_sum <= std_ulogic_vector(unsigned('0' & fpu_operands.rs1(30 downto 23)) + unsigned('0' & fpu_operands.rs2(30 downto 23)));
 
-- latency --
multiplier.start <= fu_mul.start;
multiplier.done <= multiplier.latency(multiplier.latency'left);
fu_mul.done <= multiplier.done;
 
-- unused exception flags --
multiplier.flags(fp_exc_dz_c) <= '0'; -- division by zero: not possible here
multiplier.flags(fp_exc_nx_c) <= '0'; -- inexcat: not possible here
 
 
-- result class --
multiplier_class_core: process(clk_i)
variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic;
variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic;
variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic;
variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic;
variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic;
begin
if rising_edge(clk_i) then
-- minions --
a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c);
a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c);
a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c);
a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c);
a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c);
a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c);
a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c);
a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c);
a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c);
a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c);
 
-- +normal --
multiplier.res_class(fp_class_pos_norm_c) <=
(a_pos_norm_v and b_pos_norm_v) or -- +norm * +norm
(a_neg_norm_v and b_neg_norm_v); -- -norm * -norm
-- -normal --
multiplier.res_class(fp_class_neg_norm_c) <=
(a_pos_norm_v and b_neg_norm_v) or -- +norm * -norm
(a_neg_norm_v and b_pos_norm_v); -- -norm * +norm
 
-- +infinity --
multiplier.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_pos_inf_v) or -- +inf * +inf
(a_neg_inf_v and b_neg_inf_v) or -- -inf * -inf
(a_pos_norm_v and b_pos_inf_v) or -- +norm * +inf
(a_pos_inf_v and b_pos_norm_v) or -- +inf * +norm
(a_neg_norm_v and b_neg_inf_v) or -- -norm * -inf
(a_neg_inf_v and b_neg_norm_v) or -- -inf * -norm
(a_neg_subn_v and b_neg_inf_v) or -- -denorm * -inf
(a_neg_inf_v and b_neg_subn_v); -- -inf * -denorm
-- -infinity --
multiplier.res_class(fp_class_neg_inf_c) <=
(a_pos_inf_v and b_neg_inf_v) or -- +inf * -inf
(a_neg_inf_v and b_pos_inf_v) or -- -inf * +inf
(a_pos_norm_v and b_neg_inf_v) or -- +norm * -inf
(a_neg_inf_v and b_pos_norm_v) or -- -inf * +norm
(a_neg_norm_v and b_pos_inf_v) or -- -norm * +inf
(a_pos_inf_v and b_neg_norm_v) or -- +inf * -norm
(a_pos_subn_v and b_neg_inf_v) or -- +denorm * -inf
(a_neg_inf_v and b_pos_subn_v) or -- -inf * +de-norm
(a_neg_subn_v and b_pos_inf_v) or -- -denorm * +inf
(a_pos_inf_v and b_neg_subn_v); -- +inf * -de-norm
 
-- +zero --
multiplier.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero * +zero
(a_pos_zero_v and b_pos_norm_v) or -- +zero * +norm
(a_pos_zero_v and b_pos_subn_v) or -- +zero * +denorm
(a_neg_zero_v and b_neg_zero_v) or -- -zero * -zero
(a_neg_zero_v and b_neg_norm_v) or -- -zero * -norm
(a_neg_zero_v and b_neg_subn_v) or -- -zero * -denorm
(a_pos_norm_v and b_pos_zero_v) or -- +norm * +zero
(a_pos_subn_v and b_pos_zero_v) or -- +denorm * +zero
(a_neg_norm_v and b_neg_zero_v) or -- -norm * -zero
(a_neg_subn_v and b_neg_zero_v); -- -denorm * -zero
-- -zero --
multiplier.res_class(fp_class_neg_zero_c) <=
(a_pos_zero_v and b_neg_zero_v) or -- +zero * -zero
(a_pos_zero_v and b_neg_norm_v) or -- +zero * -norm
(a_pos_zero_v and b_neg_subn_v) or -- +zero * -denorm
(a_neg_zero_v and b_pos_zero_v) or -- -zero * +zero
(a_neg_zero_v and b_pos_norm_v) or -- -zero * +norm
(a_neg_zero_v and b_pos_subn_v) or -- -zero * +denorm
(a_neg_norm_v and b_pos_zero_v) or -- -norm * +zero
(a_neg_subn_v and b_pos_zero_v) or -- -denorm * +zero
(a_pos_norm_v and b_neg_zero_v) or -- +norm * -zero
(a_pos_subn_v and b_neg_zero_v); -- +denorm * -zero
 
-- sNaN --
multiplier.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN
-- qNaN --
multiplier.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- nay input is qNaN
((a_pos_inf_v or a_neg_inf_v) and (b_pos_zero_v or b_neg_zero_v)) or -- +/-inf * +/-zero
((a_pos_zero_v or a_neg_zero_v) and (b_pos_inf_v or b_neg_inf_v)); -- +/-zero * +/-inf
end if;
end process multiplier_class_core;
 
-- subnormal result --
multiplier.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer
multiplier.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer
 
-- unused --
fu_mul.result <= (others => '0');
fu_mul.flags <= (others => '0');
 
 
-- Adder/Subtractor Core (FADD, FSUB) -----------------------------------------------------
-- -------------------------------------------------------------------------------------------
adder_subtractor_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- arbitration / latency --
if (ctrl_engine.state = S_IDLE) then -- hacky "reset"
addsub.latency <= (others => '0');
else
addsub.latency(0) <= addsub.start; -- input comparator delay
if (addsub.latency(0) = '1') then
addsub.latency(1) <= '1';
addsub.latency(2) <= '0';
elsif (addsub.exp_cnt(7 downto 0) = addsub.large_exp) then -- radix point not yet aligned
addsub.latency(1) <= '0';
addsub.latency(2) <= addsub.latency(1) and (not addsub.latency(0)); -- "shift done"
end if;
addsub.latency(3) <= addsub.latency(2); -- adder stage
addsub.latency(4) <= addsub.latency(3); -- final stage
end if;
 
-- exponent check: find smaller number (radix-offset-only) --
if (unsigned(fpu_operands.rs1(30 downto 23)) < unsigned(fpu_operands.rs2(30 downto 23))) then
addsub.exp_comp(0) <= '1'; -- rs1 < rs2
else
addsub.exp_comp(0) <= '0'; -- rs1 >= rs2
end if;
if (unsigned(fpu_operands.rs1(30 downto 23)) = unsigned(fpu_operands.rs2(30 downto 23))) then
addsub.exp_comp(1) <= '1'; -- rs1 == rs2
else -- rs1 != rs2
addsub.exp_comp(1) <= '0';
end if;
 
-- shift right small mantissa to align radix point --
if (addsub.latency(0) = '1') then
if ((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_pos_zero_c) or
fpu_operands.rs1_class(fp_class_neg_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c)) = '0') then -- no input is zero
addsub.man_sreg <= addsub.small_man;
else
addsub.man_sreg <= (others => '0');
end if;
addsub.exp_cnt <= '0' & addsub.small_exp;
addsub.man_g_ext <= '0';
addsub.man_r_ext <= '0';
addsub.man_s_ext <= '0';
elsif (addsub.exp_cnt(7 downto 0) /= addsub.large_exp) then -- shift right until same magnitude
addsub.man_sreg <= '0' & addsub.man_sreg(addsub.man_sreg'left downto 1);
addsub.man_g_ext <= addsub.man_sreg(0);
addsub.man_r_ext <= addsub.man_g_ext;
addsub.man_s_ext <= addsub.man_s_ext or addsub.man_r_ext; -- sticky bit
addsub.exp_cnt <= std_ulogic_vector(unsigned(addsub.exp_cnt) + 1);
end if;
 
-- mantissa check: find smaller number (magnitude-only) --
if (unsigned(addsub.man_sreg) <= unsigned(addsub.large_man)) then
addsub.man_comp <= '1';
else
addsub.man_comp <= '0';
end if;
 
-- actual addition/subtraction (incl. overflow) --
if ((ctrl_i(ctrl_ir_funct12_7_c) xor (fpu_operands.rs1(31) xor fpu_operands.rs2(31))) = '0') then -- add
addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) + unsigned('0' & addsub.man_s));
else -- sub
addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) - unsigned('0' & addsub.man_s));
end if;
 
-- result sign --
if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- add
if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs
addsub.res_sign <= fpu_operands.rs1(31);
else -- different signs
if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas)
addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp);
else
addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
end if;
end if;
else -- sub
if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs
if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas)
addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp);
else
addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
end if;
else -- different signs
addsub.res_sign <= fpu_operands.rs1(31);
end if;
end if;
 
-- exception flags --
addsub.flags(fp_exc_nv_c) <= ((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and
(fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))); -- +/-inf +/- +/-inf
end if;
end process adder_subtractor_core;
 
-- exceptions - unused --
addsub.flags(fp_exc_dz_c) <= '0'; -- division by zero -> not possible
addsub.flags(fp_exc_of_c) <= '0'; -- not possible here (but may occur in normalizer)
addsub.flags(fp_exc_uf_c) <= '0'; -- not possible here (but may occur in normalizer)
addsub.flags(fp_exc_nx_c) <= '0'; -- not possible here (but may occur in normalizer)
 
-- exponent check: find smaller number (magnitude-only) --
addsub.small_exp <= fpu_operands.rs1(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs2(30 downto 23);
addsub.large_exp <= fpu_operands.rs2(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs1(30 downto 23);
addsub.small_man <= ('1' & fpu_operands.rs1(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs2(22 downto 00));
addsub.large_man <= ('1' & fpu_operands.rs2(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs1(22 downto 00));
 
-- mantissa check: find smaller number (magnitude-only) --
addsub.man_s <= (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext) when (addsub.man_comp = '1') else (addsub.large_man & "000");
addsub.man_l <= (addsub.large_man & "000") when (addsub.man_comp = '1') else (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext);
 
-- latency --
addsub.start <= fu_addsub.start;
addsub.done <= addsub.latency(addsub.latency'left);
fu_addsub.done <= addsub.done;
 
-- mantissa result --
addsub.res_sum <= addsub.add_stage(27 downto 0);
 
 
-- result class --
adder_subtractor_class_core: process(clk_i)
variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic;
variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic;
variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic;
variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic;
variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic;
begin
if rising_edge(clk_i) then
-- minions --
a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c);
a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c);
a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c);
a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c);
a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c);
a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c);
a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c);
a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c);
a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c);
a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c);
 
if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- addition
-- +infinity --
addsub.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_pos_inf_v) or -- +inf + +inf
(a_pos_inf_v and b_pos_zero_v) or -- +inf + +zero
(a_pos_zero_v and b_pos_inf_v) or -- +zero + +inf
(a_pos_inf_v and b_neg_zero_v) or -- +inf + -zero
(a_neg_zero_v and b_pos_inf_v) or -- -zero + +inf
--
(a_pos_inf_v and b_pos_norm_v) or -- +inf + +norm
(a_pos_norm_v and b_pos_inf_v) or -- +norm + +inf
(a_pos_inf_v and b_pos_subn_v) or -- +inf + +denorm
(a_pos_subn_v and b_pos_inf_v) or -- +denorm + +inf
--
(a_pos_inf_v and b_neg_norm_v) or -- +inf + -norm
(a_neg_norm_v and b_pos_inf_v) or -- -norm + +inf
(a_pos_inf_v and b_neg_subn_v) or -- +inf + -denorm
(a_neg_subn_v and b_pos_inf_v); -- -denorm + +inf
-- -infinity --
addsub.res_class(fp_class_neg_inf_c) <=
(a_neg_inf_v and b_neg_inf_v) or -- -inf + -inf
(a_neg_inf_v and b_pos_zero_v) or -- -inf + +zero
(a_pos_zero_v and b_neg_inf_v) or -- +zero + -inf
(a_neg_inf_v and b_neg_zero_v) or -- -inf + -zero
(a_neg_zero_v and b_neg_inf_v) or -- -zero + -inf
--
(a_neg_inf_v and b_pos_norm_v) or -- -inf + +norm
(a_pos_norm_v and b_neg_inf_v) or -- +norm + -inf
(a_neg_inf_v and b_neg_norm_v) or -- -inf + -norm
(a_neg_norm_v and b_neg_inf_v) or -- -norm + -inf
--
(a_neg_inf_v and b_pos_subn_v) or -- -inf + +denorm
(a_pos_subn_v and b_neg_inf_v) or -- +denorm + -inf
(a_neg_inf_v and b_neg_subn_v) or -- -inf + -denorm
(a_neg_subn_v and b_neg_inf_v); -- -denorm + -inf
 
-- +zero --
addsub.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero + +zero
(a_pos_zero_v and b_neg_zero_v) or -- +zero + -zero
(a_neg_zero_v and b_pos_zero_v); -- -zero + +zero
-- -zero --
addsub.res_class(fp_class_neg_zero_c) <=
(a_neg_zero_v and b_neg_zero_v); -- -zero + -zero
 
-- qNaN --
addsub.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- any input is qNaN
(a_pos_inf_v and b_neg_inf_v) or -- +inf + -inf
(a_neg_inf_v and b_pos_inf_v); -- -inf + +inf
 
else -- subtraction
-- +infinity --
addsub.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_neg_inf_v) or -- +inf - -inf
(a_pos_inf_v and b_pos_zero_v) or -- +inf - +zero
(a_pos_inf_v and b_neg_zero_v) or -- +inf - -zero
(a_pos_inf_v and b_pos_norm_v) or -- +inf - +norm
(a_pos_inf_v and b_pos_subn_v) or -- +inf - +denorm
(a_pos_inf_v and b_neg_norm_v) or -- +inf - -norm
(a_pos_inf_v and b_neg_subn_v) or -- +inf - -denorm
--
(a_pos_zero_v and b_neg_inf_v) or -- +zero - -inf
(a_neg_zero_v and b_neg_inf_v) or -- -zero - -inf
--
(a_pos_norm_v and b_neg_inf_v) or -- +norm - -inf
(a_pos_subn_v and b_neg_inf_v) or -- +denorm - -inf
(a_neg_norm_v and b_neg_inf_v) or -- -norm - -inf
(a_neg_subn_v and b_neg_inf_v); -- -denorm - -inf
-- -infinity --
addsub.res_class(fp_class_neg_inf_c) <=
(a_neg_inf_v and b_pos_inf_v) or -- -inf - +inf
(a_neg_inf_v and b_pos_zero_v) or -- -inf - +zero
(a_neg_inf_v and b_neg_zero_v) or -- -inf - -zero
(a_neg_inf_v and b_pos_norm_v) or -- -inf - +norm
(a_neg_inf_v and b_pos_subn_v) or -- -inf - +denorm
(a_neg_inf_v and b_neg_norm_v) or -- -inf - -norm
(a_neg_inf_v and b_neg_subn_v) or -- -inf - -denorm
--
(a_pos_zero_v and b_pos_inf_v) or -- +zero - +inf
(a_neg_zero_v and b_pos_inf_v) or -- -zero - +inf
--
(a_pos_norm_v and b_pos_inf_v) or -- +norm - +inf
(a_pos_subn_v and b_pos_inf_v) or -- +denorm - +inf
(a_neg_norm_v and b_pos_inf_v) or -- -norm - +inf
(a_neg_subn_v and b_pos_inf_v); -- -denorm - +inf
 
-- +zero --
addsub.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero - +zero
(a_pos_zero_v and b_neg_zero_v) or -- +zero - -zero
(a_neg_zero_v and b_neg_zero_v); -- -zero - -zero
-- -zero --
addsub.res_class(fp_class_neg_zero_c) <=
(a_neg_zero_v and b_pos_zero_v); -- -zero - +zero
 
-- qNaN --
addsub.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- any input is qNaN
(a_pos_inf_v and b_pos_inf_v) or -- +inf - +inf
(a_neg_inf_v and b_neg_inf_v); -- -inf - -inf
end if;
 
-- normal --
addsub.res_class(fp_class_pos_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here]
addsub.res_class(fp_class_neg_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here]
 
-- sNaN --
addsub.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN
end if;
end process adder_subtractor_class_core;
 
-- subnormal result --
addsub.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer
addsub.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer
 
-- unused --
fu_addsub.result <= (others => '0');
fu_addsub.flags <= (others => '0');
 
 
-- ****************************************************************************************************************************
-- FPU Core - Normalize & Round
-- ****************************************************************************************************************************
 
-- Normalizer Input -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
normalizer_input_select: process(funct_ff, addsub, multiplier, fu_conv_i2f)
begin
case funct_ff is
when op_addsub_c => -- addition/subtraction
normalizer.mode <= '0'; -- normalization
normalizer.sign <= addsub.res_sign;
normalizer.xexp <= addsub.exp_cnt;
normalizer.xmantissa(47 downto 23) <= addsub.res_sum(27 downto 3);
normalizer.xmantissa(22) <= addsub.res_sum(2);
normalizer.xmantissa(21) <= addsub.res_sum(1);
normalizer.xmantissa(20 downto 01) <= (others => '0');
normalizer.xmantissa(00) <= addsub.res_sum(0);
normalizer.class <= addsub.res_class;
normalizer.flags_in <= addsub.flags;
normalizer.start <= addsub.done;
when op_mul_c => -- multiplication
normalizer.mode <= '0'; -- normalization
normalizer.sign <= multiplier.sign;
normalizer.xexp <= '0' & multiplier.exp_res(7 downto 0);
normalizer.xmantissa <= multiplier.product;
normalizer.class <= multiplier.res_class;
normalizer.flags_in <= multiplier.flags;
normalizer.start <= multiplier.done;
when others => -- op_i2f_c
normalizer.mode <= '1'; -- int_to_float
normalizer.sign <= fu_conv_i2f.sign;
normalizer.xexp <= "001111111"; -- bias = 127
normalizer.xmantissa <= (others => '0'); -- don't care
normalizer.class <= (others => '0'); -- don't care
normalizer.flags_in <= (others => '0'); -- no flags yet
normalizer.start <= fu_conv_i2f.done;
end case;
end process normalizer_input_select;
 
 
-- Normalizer & Rounding Unit -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_fpu_normalizer_inst: neorv32_cpu_cp_fpu_normalizer
port map (
-- control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
start_i => normalizer.start, -- trigger operation
rmode_i => fpu_operands.frm, -- rounding mode
funct_i => normalizer.mode, -- operation mode
-- input --
sign_i => normalizer.sign, -- sign
exponent_i => normalizer.xexp, -- extended exponent
mantissa_i => normalizer.xmantissa, -- extended mantissa
integer_i => fu_conv_i2f.result, -- integer input
class_i => normalizer.class, -- input number class
flags_i => normalizer.flags_in, -- exception flags input
-- output --
result_o => normalizer.result, -- result (float or int)
flags_o => normalizer.flags_out, -- exception flags
done_o => normalizer.done -- operation done
);
 
 
-- ****************************************************************************************************************************
-- FPU Core - Result
-- ****************************************************************************************************************************
 
-- Result Output to CPU Pipeline ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
output_gate: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_engine.valid = '1') then
case funct_ff is
when op_class_c =>
res_o <= fu_classify.result;
fflags_o <= fu_classify.flags;
when op_comp_c =>
res_o <= fu_compare.result;
fflags_o <= fu_compare.flags;
when op_f2i_c =>
res_o <= fu_conv_f2i.result;
fflags_o <= fu_conv_f2i.flags;
when op_sgnj_c =>
res_o <= fu_sign_inject.result;
fflags_o <= fu_sign_inject.flags;
when op_minmax_c =>
res_o <= fu_min_max.result;
fflags_o <= fu_min_max.flags;
when others => -- op_mul_c, op_addsub_c, op_i2f_c, ...
res_o <= normalizer.result;
fflags_o <= normalizer.flags_out;
end case;
else
res_o <= (others => '0');
fflags_o <= (others => '0');
end if;
end if;
end process output_gate;
 
-- operation done --
fu_core_done <= fu_compare.done or fu_classify.done or fu_sign_inject.done or fu_min_max.done or normalizer.done or fu_conv_f2i.done;
 
 
end neorv32_cpu_cp_fpu_rtl;
 
-- ###########################################################################################################################################
-- ###########################################################################################################################################
 
-- #################################################################################################
-- # << NEORV32 - Single-Precision Floating-Point Unit: Normalizer and Rounding Unit >> #
-- # ********************************************************************************************* #
-- # This unit also performs integer-to-float conversions. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_fpu_normalizer is
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float)
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent
mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa
integer_i : in std_ulogic_vector(31 downto 0); -- integer input
class_i : in std_ulogic_vector(09 downto 0); -- input number class
flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- float result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags output
done_o : out std_ulogic -- operation done
);
end neorv32_cpu_cp_fpu_normalizer;
 
architecture neorv32_cpu_cp_fpu_normalizer_rtl of neorv32_cpu_cp_fpu_normalizer is
 
-- controller --
type ctrl_engine_state_t is (S_IDLE, S_PREPARE_I2F, S_CHECK_I2F, S_PREPARE_NORM, S_PREPARE_SHIFT, S_NORMALIZE_BUSY, S_ROUND, S_CHECK, S_FINALIZE);
type ctrl_t is record
state : ctrl_engine_state_t; -- current state
norm_r : std_ulogic; -- normalization round 0 or 1
cnt : std_ulogic_vector(08 downto 0); -- interation counter/exponent (incl. overflow)
cnt_pre : std_ulogic_vector(08 downto 0);
cnt_of : std_ulogic; -- counter overflow
cnt_uf : std_ulogic; -- counter underflow
rounded : std_ulogic; -- output is rounded
res_sgn : std_ulogic;
res_exp : std_ulogic_vector(07 downto 0);
res_man : std_ulogic_vector(22 downto 0);
class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0);
end record;
signal ctrl : ctrl_t;
 
-- normalization shift register --
type sreg_t is record
done : std_ulogic;
dir : std_ulogic; -- shift direction: 0=right, 1=left
zero : std_ulogic;
upper : std_ulogic_vector(31 downto 0);
lower : std_ulogic_vector(22 downto 0);
ext_g : std_ulogic; -- guard bit
ext_r : std_ulogic; -- round bit
ext_s : std_ulogic; -- sticky bit
end record;
signal sreg : sreg_t;
 
-- rounding unit --
type round_t is record
en : std_ulogic; -- enable rounding
sub : std_ulogic; -- 0=decrement, 1=increment
output : std_ulogic_vector(24 downto 0); -- mantissa size + hidden one + 1
end record;
signal round : round_t;
 
begin
 
-- Control Engine -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_engine: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl.state <= S_IDLE;
ctrl.norm_r <= '0';
ctrl.cnt <= (others => '0');
ctrl.cnt_pre <= (others => '0');
ctrl.cnt_of <= '0';
ctrl.cnt_uf <= '0';
ctrl.rounded <= '0';
ctrl.res_exp <= (others => '0');
ctrl.res_man <= (others => '0');
ctrl.res_sgn <= '0';
ctrl.class <= (others => '0');
ctrl.flags <= (others => '0');
--
sreg.upper <= (others => '0');
sreg.lower <= (others => '0');
sreg.dir <= '0';
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
--
done_o <= '0';
elsif rising_edge(clk_i) then
-- defaults --
ctrl.cnt_pre <= ctrl.cnt;
done_o <= '0';
 
-- exponent counter underflow/overflow --
if ((ctrl.cnt_pre(8 downto 7) = "01") and (ctrl.cnt(8 downto 7) = "10")) then -- overflow
ctrl.cnt_of <= '1';
elsif (ctrl.cnt_pre(8 downto 7) = "00") and (ctrl.cnt(8 downto 7) = "11") then -- underflow
ctrl.cnt_uf <= '1';
end if;
 
-- fsm --
case ctrl.state is
 
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
ctrl.norm_r <= '0'; -- start with first normalization
ctrl.rounded <= '0'; -- not rounded yet
ctrl.cnt_of <= '0';
ctrl.cnt_uf <= '0';
--
if (start_i = '1') then
ctrl.cnt <= exponent_i;
ctrl.res_sgn <= sign_i;
ctrl.class <= class_i;
ctrl.flags <= flags_i;
if (funct_i = '0') then -- float -> float
ctrl.state <= S_PREPARE_NORM;
else -- integer -> float
ctrl.state <= S_PREPARE_I2F;
end if;
end if;
 
when S_PREPARE_I2F => -- prepare integer-to-float conversion
-- ------------------------------------------------------------
sreg.upper <= integer_i;
sreg.lower <= (others => '0');
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
sreg.dir <= '0'; -- shift right
ctrl.state <= S_CHECK_I2F;
 
when S_CHECK_I2F => -- check if converting zero
-- ------------------------------------------------------------
if (sreg.zero = '1') then -- all zero
ctrl.class(fp_class_pos_zero_c) <= '1';
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_NORMALIZE_BUSY;
end if;
 
when S_PREPARE_NORM => -- prepare "normal" normalization & rounding
-- ------------------------------------------------------------
sreg.upper(31 downto 02) <= (others => '0');
sreg.upper(01 downto 00) <= mantissa_i(47 downto 46);
sreg.lower <= mantissa_i(45 downto 23);
sreg.ext_g <= mantissa_i(22);
sreg.ext_r <= mantissa_i(21);
sreg.ext_s <= or_all_f(mantissa_i(20 downto 0));
-- check for special cases --
if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN
ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero
ctrl.class(fp_class_neg_denorm_c) or ctrl.class(fp_class_pos_denorm_c) or -- subnormal
ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or -- infinity
ctrl.flags(fp_exc_uf_c) or -- underflow
ctrl.flags(fp_exc_of_c) or -- overflow
ctrl.flags(fp_exc_nv_c)) = '1') then -- invalid
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_PREPARE_SHIFT;
end if;
 
when S_PREPARE_SHIFT => -- prepare shift direction (for "normal" normalization only)
-- ------------------------------------------------------------
if (sreg.zero = '0') then -- number < 1.0
sreg.dir <= '0'; -- shift right
else -- number >= 1.0
sreg.dir <= '1'; -- shift left
end if;
ctrl.state <= S_NORMALIZE_BUSY;
 
when S_NORMALIZE_BUSY => -- running normalization cycle
-- ------------------------------------------------------------
-- shift until normalized or exception --
if (sreg.done = '1') or (ctrl.cnt_uf = '1') or (ctrl.cnt_of = '1') then
-- normalization control --
ctrl.norm_r <= '1';
if (ctrl.norm_r = '0') then -- first normalization cycle done
ctrl.state <= S_ROUND;
else -- second normalization cycle done
ctrl.state <= S_CHECK;
end if;
else
if (sreg.dir = '0') then -- shift right
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) + 1);
sreg.upper <= '0' & sreg.upper(sreg.upper'left downto 1);
sreg.lower <= sreg.upper(0) & sreg.lower(sreg.lower'left downto 1);
sreg.ext_g <= sreg.lower(0);
sreg.ext_r <= sreg.ext_g;
sreg.ext_s <= sreg.ext_r or sreg.ext_s; -- sticky bit
else -- shift left
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1);
sreg.upper <= sreg.upper(sreg.upper'left-1 downto 0) & sreg.lower(sreg.lower'left);
sreg.lower <= sreg.lower(sreg.lower'left-1 downto 0) & sreg.ext_g;
sreg.ext_g <= sreg.ext_r;
sreg.ext_r <= sreg.ext_s;
sreg.ext_s <= sreg.ext_s; -- sticky bit
end if;
end if;
 
when S_ROUND => -- rounding cycle (after first normalization)
-- ------------------------------------------------------------
ctrl.rounded <= ctrl.rounded or round.en;
sreg.upper(31 downto 02) <= (others => '0');
sreg.upper(01 downto 00) <= round.output(24 downto 23);
sreg.lower <= round.output(22 downto 00);
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
ctrl.state <= S_PREPARE_SHIFT;
 
when S_CHECK => -- check for overflow/underflow
-- ------------------------------------------------------------
if (ctrl.cnt_uf = '1') then -- underflow
ctrl.flags(fp_exc_uf_c) <= '1';
elsif (ctrl.cnt_of = '1') then -- overflow
ctrl.flags(fp_exc_of_c) <= '1';
elsif (ctrl.cnt(7 downto 0) = x"00") then -- subnormal
ctrl.flags(fp_exc_uf_c) <= '1';
elsif (ctrl.cnt(7 downto 0) = x"FF") then -- infinity
ctrl.flags(fp_exc_of_c) <= '1';
end if;
ctrl.state <= S_FINALIZE;
 
when S_FINALIZE => -- result finalization
-- ------------------------------------------------------------
-- generate result word (the ORDER of checks is imporatant here!) --
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') then -- sNaN / qNaN
ctrl.res_sgn <= fp_single_qnan_c(31);
ctrl.res_exp <= fp_single_qnan_c(30 downto 23);
ctrl.res_man <= fp_single_qnan_c(22 downto 00);
elsif (ctrl.class(fp_class_neg_inf_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- infinity
(ctrl.flags(fp_exc_of_c) = '1') then -- overflow
ctrl.res_exp <= fp_single_pos_inf_c(30 downto 23); -- keep original sign
ctrl.res_man <= fp_single_pos_inf_c(22 downto 00);
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') then -- zero
ctrl.res_sgn <= ctrl.class(fp_class_neg_zero_c);
ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23);
ctrl.res_man <= fp_single_pos_zero_c(22 downto 00);
elsif (ctrl.flags(fp_exc_uf_c) = '1') or -- underflow
(sreg.zero = '1') or (ctrl.class(fp_class_neg_denorm_c) = '1') or (ctrl.class(fp_class_pos_denorm_c) = '1') then -- denormalized (flush-to-zero)
ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); -- keep original sign
ctrl.res_man <= fp_single_pos_zero_c(22 downto 00);
else -- result is ok
ctrl.res_exp <= ctrl.cnt(7 downto 0);
ctrl.res_man <= sreg.lower;
end if;
-- generate exception flags --
ctrl.flags(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c) or ctrl.class(fp_class_snan_c); -- invalid if input is SIGNALING NaN
ctrl.flags(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c) or ctrl.rounded; -- inexcat if result is rounded
--
done_o <= '1';
ctrl.state <= S_IDLE;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl.state <= S_IDLE;
 
end case;
end if;
end process ctrl_engine;
 
-- stop shifting when normalized --
sreg.done <= (not or_all_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
 
-- all-zero including hidden bit --
sreg.zero <= not or_all_f(sreg.upper);
 
-- result --
result_o(31) <= ctrl.res_sgn;
result_o(30 downto 23) <= ctrl.res_exp;
result_o(22 downto 0) <= ctrl.res_man;
 
-- exception flags --
flags_o(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c); -- invalid operation
flags_o(fp_exc_dz_c) <= ctrl.flags(fp_exc_dz_c); -- divide by zero
flags_o(fp_exc_of_c) <= ctrl.flags(fp_exc_of_c); -- overflow
flags_o(fp_exc_uf_c) <= ctrl.flags(fp_exc_uf_c); -- underflow
flags_o(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c); -- inexact
 
 
-- Rounding -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rounding_unit_ctrl: process(rmode_i, sreg)
begin
-- defaults --
round.en <= '0';
round.sub <= '0';
-- rounding mode --
case rmode_i(2 downto 0) is
when "000" => -- round to nearest, ties to even
if (sreg.ext_g = '0') then
round.en <= '0'; -- round down (do nothing)
else
if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie!
round.en <= sreg.lower(0); -- round up if LSB of mantissa is set
else
round.en <= '1'; -- round up
end if;
end if;
round.sub <= '0'; -- increment
when "001" => -- round towards zero
round.en <= '0'; -- no rounding -> just truncate
when "010" => -- round down (towards -infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '1'; -- decrement
when "011" => -- round up (towards +infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '0'; -- increment
when "100" => -- round to nearest, ties to max magnitude
round.en <= '0'; -- FIXME / TODO
when others => -- undefined
round.en <= '0';
end case;
end process rounding_unit_ctrl;
 
 
-- incrementer/decrementer --
rounding_unit_add: process(round, sreg)
variable tmp_v : std_ulogic_vector(24 downto 0);
begin
tmp_v := '0' & sreg.upper(0) & sreg.lower;
if (round.en = '1') then
if (round.sub = '0') then -- increment
round.output <= std_ulogic_vector(unsigned(tmp_v) + 1);
else -- decrement
round.output <= std_ulogic_vector(unsigned(tmp_v) - 1);
end if;
else -- do nothing
round.output <= tmp_v;
end if;
end process rounding_unit_add;
 
 
end neorv32_cpu_cp_fpu_normalizer_rtl;
 
-- ###########################################################################################################################################
-- ###########################################################################################################################################
 
-- #################################################################################################
-- # << NEORV32 - Single-Precision Floating-Point Unit: Float-To-Int Converter >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_fpu_f2i is
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- 0=signed, 1=unsigned
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(07 downto 0); -- exponent
mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa
class_i : in std_ulogic_vector(09 downto 0); -- operand class
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- integer result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end neorv32_cpu_cp_fpu_f2i;
 
architecture neorv32_cpu_cp_fpu_f2i_rtl of neorv32_cpu_cp_fpu_f2i is
 
-- controller --
type ctrl_engine_state_t is (S_IDLE, S_PREPARE_F2I, S_NORMALIZE_BUSY, S_ROUND, S_FINALIZE);
type ctrl_t is record
state : ctrl_engine_state_t; -- current state
unsign : std_ulogic;
cnt : std_ulogic_vector(07 downto 0); -- interation counter/exponent
sign : std_ulogic;
class : std_ulogic_vector(09 downto 0);
rounded : std_ulogic; -- output is rounded
over : std_ulogic; -- output is overflowing
under : std_ulogic; -- output in underflowing
result_tmp : std_ulogic_vector(31 downto 0);
result : std_ulogic_vector(31 downto 0);
end record;
signal ctrl : ctrl_t;
 
-- conversion shift register --
type sreg_t is record
int : std_ulogic_vector(31 downto 0); -- including hidden-zero
mant : std_ulogic_vector(22 downto 0);
ext_g : std_ulogic; -- guard bit
ext_r : std_ulogic; -- round bit
ext_s : std_ulogic; -- sticky bit
end record;
signal sreg : sreg_t;
 
-- rounding unit --
type round_t is record
en : std_ulogic; -- enable rounding
sub : std_ulogic; -- 0=decrement, 1=increment
output : std_ulogic_vector(32 downto 0); -- result + overflow
end record;
signal round : round_t;
 
begin
 
-- Control Engine -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_engine: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl.state <= S_IDLE;
ctrl.cnt <= (others => '0');
ctrl.sign <= '0';
ctrl.class <= (others => '0');
ctrl.rounded <= '0';
ctrl.over <= '0';
ctrl.under <= '0';
ctrl.unsign <= '0';
ctrl.result <= (others => '0');
ctrl.result_tmp <= (others => '0');
sreg.int <= (others => '0');
sreg.mant <= (others => '0');
sreg.ext_s <= '0';
done_o <= '0';
elsif rising_edge(clk_i) then
-- defaults --
done_o <= '0';
 
-- fsm --
case ctrl.state is
 
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
ctrl.rounded <= '0'; -- not rounded yet
ctrl.over <= '0'; -- not overflowing yet
ctrl.under <= '0'; -- not underflowing yet
ctrl.unsign <= funct_i;
sreg.ext_s <= '0'; -- init
if (start_i = '1') then
ctrl.cnt <= exponent_i;
ctrl.sign <= sign_i;
ctrl.class <= class_i;
sreg.mant <= mantissa_i;
ctrl.state <= S_PREPARE_F2I;
end if;
 
when S_PREPARE_F2I => -- prepare float-to-integer conversion
-- ------------------------------------------------------------
if (unsigned(ctrl.cnt) < 126) then -- less than 0.5
sreg.int <= (others => '0');
ctrl.under <= '1'; -- this is an underflow!
ctrl.cnt <= (others => '0');
elsif (unsigned(ctrl.cnt) = 126) then -- num < 1.0 but num >= 0.5
sreg.int <= (others => '0');
sreg.mant <= '1' & sreg.mant(sreg.mant'left downto 1);
ctrl.cnt <= (others => '0');
else
sreg.int <= (others => '0');
sreg.int(0) <= '1'; -- hidden one
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 127); -- remove bias to get raw number of left shifts
end if;
-- check terminal cases --
if ((ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or
ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or
ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c)) = '1') then
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_NORMALIZE_BUSY;
end if;
 
when S_NORMALIZE_BUSY => -- running normalization cycle
-- ------------------------------------------------------------
sreg.ext_s <= sreg.ext_s or or_all_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
if (or_all_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
if (ctrl.unsign = '0') then -- signed conversion
ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit
end if;
ctrl.state <= S_ROUND;
else -- shift left
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1);
sreg.int <= sreg.int(sreg.int'left-1 downto 0) & sreg.mant(sreg.mant'left);
sreg.mant <= sreg.mant(sreg.mant'left-1 downto 0) & '0';
ctrl.over <= ctrl.over or sreg.int(sreg.int'left);
end if;
 
when S_ROUND => -- rounding cycle
-- ------------------------------------------------------------
ctrl.rounded <= ctrl.rounded or round.en;
ctrl.over <= ctrl.over or round.output(round.output'left); -- overflow after rounding
ctrl.result_tmp <= round.output(round.output'left-1 downto 0);
ctrl.state <= S_FINALIZE;
 
when S_FINALIZE => -- check for corner cases and finalize result
-- ------------------------------------------------------------
if (ctrl.unsign = '1') then -- unsigned conversion
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf
((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range
ctrl.result <= x"ffffffff";
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.class(fp_class_neg_inf_c) = '1') or -- subnormal zero or -inf
(ctrl.sign = '1') or (ctrl.under = '1') then -- negative out-of-range or underflow
ctrl.result <= x"00000000";
else
ctrl.result <= ctrl.result_tmp;
end if;
 
else -- signed conversion
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf
((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range
ctrl.result <= x"7fffffff";
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.under = '1') then -- subnormal zero or underflow
ctrl.result <= x"00000000";
elsif (ctrl.class(fp_class_neg_inf_c) = '1') or ((ctrl.sign = '1') and (ctrl.over = '1')) then -- -inf or negative out-of-range
ctrl.result <= x"80000000";
else -- result is ok, make sign adaption
if (ctrl.sign = '1') then
ctrl.result <= std_ulogic_vector(0 - unsigned(ctrl.result_tmp)); -- abs()
else
ctrl.result <= ctrl.result_tmp;
end if;
end if;
end if;
done_o <= '1';
ctrl.state <= S_IDLE;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl.state <= S_IDLE;
 
end case;
end if;
end process ctrl_engine;
 
-- result --
result_o <= ctrl.result;
 
-- exception flags --
flags_o(fp_exc_nv_c) <= ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c); -- invalid operation
flags_o(fp_exc_dz_c) <= '0'; -- divide by zero - not possible here
flags_o(fp_exc_of_c) <= ctrl.over or ctrl.class(fp_class_pos_inf_c) or ctrl.class(fp_class_neg_inf_c); -- overflow
flags_o(fp_exc_uf_c) <= ctrl.under; -- underflow
flags_o(fp_exc_nx_c) <= ctrl.rounded; -- inexact if result was rounded
 
 
-- Rounding -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rounding_unit_ctrl: process(rmode_i, sreg)
begin
-- defaults --
round.en <= '0';
round.sub <= '0';
-- rounding mode --
case rmode_i(2 downto 0) is
when "000" => -- round to nearest, ties to even
if (sreg.ext_g = '0') then
round.en <= '0'; -- round down (do nothing)
else
if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie!
round.en <= sreg.int(0); -- round up if LSB of integer is set
else
round.en <= '1'; -- round up
end if;
end if;
round.sub <= '0'; -- increment
when "001" => -- round towards zero
round.en <= '0'; -- no rounding -> just truncate
when "010" => -- round down (towards -infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '1'; -- decrement
when "011" => -- round up (towards +infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '0'; -- increment
when "100" => -- round to nearest, ties to max magnitude
round.en <= '0'; -- FIXME / TODO
when others => -- undefined
round.en <= '0';
end case;
end process rounding_unit_ctrl;
 
-- rounding: guard and round bits --
sreg.ext_g <= sreg.mant(sreg.mant'left);
sreg.ext_r <= sreg.mant(sreg.mant'left-1);
 
 
-- incrementer/decrementer --
rounding_unit_add: process(round, sreg)
variable tmp_v : std_ulogic_vector(32 downto 0); -- including overflow
begin
tmp_v := '0' & sreg.int;
if (round.en = '1') then
if (round.sub = '0') then -- increment
round.output <= std_ulogic_vector(unsigned(tmp_v) + 1);
else -- decrement
round.output <= std_ulogic_vector(unsigned(tmp_v) - 1);
end if;
else -- do nothing
round.output <= tmp_v;
end if;
end process rounding_unit_add;
 
 
end neorv32_cpu_cp_fpu_f2i_rtl;
/neorv32_package.vhd
50,7 → 50,8
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
 
-- CPU core --
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
 
-- "critical" number of implemented PMP regions --
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
60,7 → 61,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050208"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050302"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
870,6 → 871,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
-- Extension Options --
/neorv32_top.vhd
5,7 → 5,7
-- # and define all the configuration generics according to your needs. Alternatively, you can use #
-- # one of the alternative top entities provided in the "rtl/top_templates" folder. #
-- # #
-- # Check the processor's data sheet for more information: docs/NEORV32.pdf #
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
60,6 → 60,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
415,7 → 416,7
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --

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