OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 57 to Rev 58
    ↔ Reverse comparison
  •

Rev 57 → Rev 58

/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1071) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1062) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
15,1070 → 15,1061
00000004 => x"00000293",
00000005 => x"00000313",
00000006 => x"00000393",
00000007 => x"00000413",
00000008 => x"00000493",
00000009 => x"00000713",
00000010 => x"00000793",
00000011 => x"00000517",
00000012 => x"10c50513",
00000013 => x"30551073",
00000014 => x"34151073",
00000015 => x"34301073",
00000016 => x"34201073",
00000017 => x"30001073",
00000018 => x"30401073",
00000019 => x"30601073",
00000020 => x"ffa00593",
00000021 => x"32059073",
00000022 => x"b0001073",
00000023 => x"b8001073",
00000024 => x"b0201073",
00000025 => x"b8201073",
00000026 => x"00000813",
00000027 => x"00000893",
00000028 => x"00000913",
00000029 => x"00000993",
00000030 => x"00000a13",
00000031 => x"00000a93",
00000032 => x"00000b13",
00000033 => x"00000b93",
00000034 => x"00000c13",
00000035 => x"00000c93",
00000036 => x"00000d13",
00000037 => x"00000d93",
00000038 => x"00000e13",
00000039 => x"00000e93",
00000040 => x"00000f13",
00000041 => x"00000f93",
00000042 => x"80002117",
00000043 => x"f5410113",
00000044 => x"ffc17113",
00000045 => x"00010413",
00000046 => x"80000197",
00000047 => x"74818193",
00000048 => x"f0000593",
00000049 => x"0005a023",
00000050 => x"00458593",
00000051 => x"feb01ce3",
00000052 => x"80000597",
00000053 => x"f3058593",
00000054 => x"87418613",
00000055 => x"00c5d863",
00000056 => x"00058023",
00000057 => x"00158593",
00000058 => x"ff5ff06f",
00000059 => x"00001597",
00000060 => x"fd058593",
00000061 => x"80000617",
00000062 => x"f0c60613",
00000063 => x"80000697",
00000064 => x"f0468693",
00000065 => x"00d65c63",
00000066 => x"00058703",
00000067 => x"00e60023",
00000068 => x"00158593",
00000069 => x"00160613",
00000070 => x"fedff06f",
00000071 => x"00000513",
00000072 => x"00000593",
00000073 => x"060000ef",
00000074 => x"30047073",
00000075 => x"00000013",
00000076 => x"10500073",
00000077 => x"0000006f",
00000078 => x"ff810113",
00000079 => x"00812023",
00000080 => x"00912223",
00000081 => x"34202473",
00000082 => x"02044663",
00000083 => x"34102473",
00000084 => x"00041483",
00000085 => x"0034f493",
00000086 => x"00240413",
00000087 => x"34141073",
00000088 => x"00300413",
00000089 => x"00941863",
00000090 => x"34102473",
00000091 => x"00240413",
00000092 => x"34141073",
00000093 => x"00012403",
00000094 => x"00412483",
00000095 => x"00810113",
00000096 => x"30200073",
00000097 => x"00005537",
00000098 => x"ff010113",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"730000ef",
00000104 => x"16d000ef",
00000105 => x"02050063",
00000106 => x"4a8000ef",
00000107 => x"00000513",
00000108 => x"4fc000ef",
00000109 => x"00001537",
00000110 => x"d5050513",
00000111 => x"780000ef",
00000112 => x"020000ef",
00000113 => x"00001537",
00000114 => x"d2c50513",
00000115 => x"770000ef",
00000116 => x"00c12083",
00000117 => x"00000513",
00000118 => x"01010113",
00000119 => x"00008067",
00000120 => x"ff010113",
00000121 => x"00000513",
00000122 => x"00812423",
00000123 => x"00112623",
00000124 => x"00000413",
00000125 => x"129000ef",
00000126 => x"0ff47513",
00000127 => x"121000ef",
00000128 => x"0c800513",
00000129 => x"14d000ef",
00000130 => x"00140413",
00000131 => x"fedff06f",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
00000135 => x"02612a23",
00000136 => x"02712823",
00000137 => x"02a12623",
00000138 => x"02b12423",
00000139 => x"02c12223",
00000140 => x"02d12023",
00000141 => x"00e12e23",
00000142 => x"00f12c23",
00000143 => x"01012a23",
00000144 => x"01112823",
00000145 => x"01c12623",
00000146 => x"01d12423",
00000147 => x"01e12223",
00000148 => x"01f12023",
00000149 => x"34102773",
00000150 => x"34071073",
00000151 => x"342027f3",
00000152 => x"0807c863",
00000153 => x"00071683",
00000154 => x"00300593",
00000155 => x"0036f693",
00000156 => x"00270613",
00000157 => x"00b69463",
00000158 => x"00470613",
00000159 => x"34161073",
00000160 => x"00b00713",
00000161 => x"04f77a63",
00000162 => x"48c00793",
00000163 => x"000780e7",
00000164 => x"03c12083",
00000165 => x"03812283",
00000166 => x"03412303",
00000167 => x"03012383",
00000168 => x"02c12503",
00000169 => x"02812583",
00000170 => x"02412603",
00000171 => x"02012683",
00000172 => x"01c12703",
00000173 => x"01812783",
00000174 => x"01412803",
00000175 => x"01012883",
00000176 => x"00c12e03",
00000177 => x"00812e83",
00000178 => x"00412f03",
00000179 => x"00012f83",
00000180 => x"04010113",
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"d6c70713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
00000188 => x"80000737",
00000189 => x"ffd74713",
00000190 => x"00e787b3",
00000191 => x"01c00713",
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d9c70713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
00000199 => x"800007b7",
00000200 => x"0007a783",
00000201 => x"f69ff06f",
00000202 => x"800007b7",
00000203 => x"0047a783",
00000204 => x"f5dff06f",
00000205 => x"800007b7",
00000206 => x"0087a783",
00000207 => x"f51ff06f",
00000208 => x"800007b7",
00000209 => x"00c7a783",
00000210 => x"f45ff06f",
00000211 => x"8101a783",
00000212 => x"f3dff06f",
00000213 => x"8141a783",
00000214 => x"f35ff06f",
00000215 => x"8181a783",
00000216 => x"f2dff06f",
00000217 => x"81c1a783",
00000218 => x"f25ff06f",
00000219 => x"8201a783",
00000220 => x"f1dff06f",
00000221 => x"8241a783",
00000222 => x"f15ff06f",
00000223 => x"8281a783",
00000224 => x"f0dff06f",
00000225 => x"82c1a783",
00000226 => x"f05ff06f",
00000227 => x"8301a783",
00000228 => x"efdff06f",
00000229 => x"8341a783",
00000230 => x"ef5ff06f",
00000231 => x"8381a783",
00000232 => x"eedff06f",
00000233 => x"83c1a783",
00000234 => x"ee5ff06f",
00000235 => x"8401a783",
00000236 => x"eddff06f",
00000237 => x"8441a783",
00000238 => x"ed5ff06f",
00000239 => x"8481a783",
00000240 => x"ecdff06f",
00000241 => x"84c1a783",
00000242 => x"ec5ff06f",
00000243 => x"8501a783",
00000244 => x"ebdff06f",
00000245 => x"8541a783",
00000246 => x"eb5ff06f",
00000247 => x"8581a783",
00000248 => x"eadff06f",
00000249 => x"85c1a783",
00000250 => x"ea5ff06f",
00000251 => x"8601a783",
00000252 => x"e9dff06f",
00000253 => x"8641a783",
00000254 => x"e95ff06f",
00000255 => x"8681a783",
00000256 => x"e8dff06f",
00000257 => x"86c1a783",
00000258 => x"e85ff06f",
00000259 => x"8701a783",
00000260 => x"e7dff06f",
00000261 => x"00000000",
00000262 => x"00000000",
00000263 => x"fe010113",
00000264 => x"01212823",
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"e1050513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"4f4000ef",
00000275 => x"08c48493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"478000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
00000286 => x"01412483",
00000287 => x"01012903",
00000288 => x"00c12983",
00000289 => x"02010113",
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"e1450513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"498000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
00000301 => x"05778493",
00000302 => x"00f76463",
00000303 => x"03078493",
00000304 => x"00b00793",
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"fa070713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
00000312 => x"800007b7",
00000313 => x"00b78713",
00000314 => x"12e40663",
00000315 => x"02876663",
00000316 => x"00378713",
00000317 => x"10e40463",
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f7450513",
00000322 => x"434000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
00000326 => x"ff07c793",
00000327 => x"00f407b3",
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"f6450513",
00000332 => x"40c000ef",
00000333 => x"00048513",
00000334 => x"3a8000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"e1c50513",
00000338 => x"3f4000ef",
00000339 => x"00001537",
00000340 => x"f8c50513",
00000341 => x"3e8000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f9450513",
00000346 => x"3d4000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"ffc50513",
00000354 => x"01010113",
00000355 => x"3b00006f",
00000356 => x"00001537",
00000357 => x"e3c50513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"e5850513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"e6c50513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e7850513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e9050513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"ea450513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"ec050513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"ed450513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"ef450513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"f1450513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"f3050513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"f4850513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
00000394 => x"800007b7",
00000395 => x"00078793",
00000396 => x"00251513",
00000397 => x"00a78533",
00000398 => x"48c00793",
00000399 => x"00f52023",
00000400 => x"00000513",
00000401 => x"00008067",
00000402 => x"00100513",
00000403 => x"00008067",
00000404 => x"ff010113",
00000405 => x"00112623",
00000406 => x"00812423",
00000407 => x"00912223",
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"fd050513",
00000412 => x"2cc000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
00000416 => x"01d00493",
00000417 => x"00040513",
00000418 => x"00140413",
00000419 => x"0ff47413",
00000420 => x"f91ff0ef",
00000421 => x"fe9418e3",
00000422 => x"00c12083",
00000423 => x"00812403",
00000424 => x"00412483",
00000425 => x"01010113",
00000426 => x"00008067",
00000427 => x"ff010113",
00000428 => x"00112623",
00000429 => x"00812423",
00000430 => x"30102673",
00000431 => x"400005b7",
00000432 => x"10058593",
00000433 => x"00b677b3",
00000434 => x"00000413",
00000435 => x"00b78c63",
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"00450513",
00000440 => x"3f8000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
00000444 => x"01010113",
00000445 => x"00008067",
00000446 => x"fd010113",
00000447 => x"02812423",
00000448 => x"02912223",
00000449 => x"03212023",
00000450 => x"01312e23",
00000451 => x"01412c23",
00000452 => x"02112623",
00000453 => x"01512a23",
00000454 => x"00001a37",
00000455 => x"00050493",
00000456 => x"00058413",
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"09ca0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"58c000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"528000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
00000474 => x"fcf996e3",
00000475 => x"00090693",
00000476 => x"00900713",
00000477 => x"03000613",
00000478 => x"0096c583",
00000479 => x"00070793",
00000480 => x"fff70713",
00000481 => x"01071713",
00000482 => x"01075713",
00000483 => x"00c59a63",
00000484 => x"000684a3",
00000485 => x"fff68693",
00000486 => x"fe0710e3",
00000487 => x"00000793",
00000488 => x"00f907b3",
00000489 => x"00000593",
00000490 => x"0007c703",
00000491 => x"00070c63",
00000492 => x"00158693",
00000493 => x"00b405b3",
00000494 => x"00e58023",
00000495 => x"01069593",
00000496 => x"0105d593",
00000497 => x"fff78713",
00000498 => x"02f91863",
00000499 => x"00b40433",
00000500 => x"00040023",
00000501 => x"02c12083",
00000502 => x"02812403",
00000503 => x"02412483",
00000504 => x"02012903",
00000505 => x"01c12983",
00000506 => x"01812a03",
00000507 => x"01412a83",
00000508 => x"03010113",
00000509 => x"00008067",
00000510 => x"00070793",
00000511 => x"fadff06f",
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"0a860613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
00000519 => x"00f607b3",
00000520 => x"0007c783",
00000521 => x"00470713",
00000522 => x"fff68693",
00000523 => x"00f680a3",
00000524 => x"ff0712e3",
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002703",
00000529 => x"00151513",
00000530 => x"00000793",
00000531 => x"04a77463",
00000532 => x"000016b7",
00000533 => x"00000713",
00000534 => x"ffe68693",
00000535 => x"04f6e663",
00000536 => x"00367613",
00000537 => x"0035f593",
00000538 => x"fff78793",
00000539 => x"01461613",
00000540 => x"00c7e7b3",
00000541 => x"01659593",
00000542 => x"01871713",
00000543 => x"00b7e7b3",
00000544 => x"00e7e7b3",
00000545 => x"10000737",
00000546 => x"00e7e7b3",
00000547 => x"faf02023",
00000548 => x"00008067",
00000549 => x"00178793",
00000550 => x"01079793",
00000551 => x"40a70733",
00000552 => x"0107d793",
00000553 => x"fa9ff06f",
00000554 => x"ffe70513",
00000555 => x"0fd57513",
00000556 => x"00051a63",
00000557 => x"0037d793",
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00000571 => x"01212023",
00000572 => x"00112623",
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00000574 => x"00050413",
00000575 => x"00a00913",
00000576 => x"00044483",
00000577 => x"00140413",
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00000581 => x"00412483",
00000582 => x"00012903",
00000583 => x"01010113",
00000584 => x"00008067",
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00000591 => x"fa9ff06f",
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00000595 => x"02812c23",
00000596 => x"03212823",
00000597 => x"03412423",
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00000599 => x"03612023",
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00000602 => x"01912a23",
00000603 => x"02112e23",
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00000635 => x"00008067",
00000636 => x"0d449863",
00000637 => x"00240993",
00000638 => x"00144403",
00000639 => x"05240263",
00000640 => x"00896e63",
00000641 => x"05840c63",
00000642 => x"07940663",
00000643 => x"02500513",
00000644 => x"ec1ff0ef",
00000645 => x"00040513",
00000646 => x"0540006f",
00000647 => x"09640663",
00000648 => x"ff7416e3",
00000649 => x"00012783",
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00000661 => x"00098413",
00000662 => x"f5dff06f",
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00000666 => x"00e12023",
00000667 => x"e65ff0ef",
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00000669 => x"00012783",
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00000675 => x"40800433",
00000676 => x"e41ff0ef",
00000677 => x"00410593",
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00000987 => x"00207470",
00000988 => x"6e6b6e55",
00000989 => x"206e776f",
00000990 => x"70617274",
00000991 => x"75616320",
00000992 => x"203a6573",
00000993 => x"00000000",
00000994 => x"50204020",
00000995 => x"00003d43",
00000996 => x"544d202c",
00000997 => x"3d4c4156",
00000998 => x"00000000",
00000999 => x"000009c0",
00001000 => x"00000a10",
00001001 => x"00000a1c",
00001002 => x"00000a28",
00001003 => x"00000a34",
00001004 => x"00000a40",
00001005 => x"00000a4c",
00001006 => x"00000a58",
00001007 => x"00000a64",
00001008 => x"00000980",
00001009 => x"00000980",
00001010 => x"00000a70",
00001011 => x"4554523c",
00001012 => x"4157203e",
00001013 => x"4e494e52",
00001014 => x"43202147",
00001015 => x"43205550",
00001016 => x"73205253",
00001017 => x"65747379",
00001018 => x"6f6e206d",
00001019 => x"76612074",
00001020 => x"616c6961",
00001021 => x"21656c62",
00001022 => x"522f3c20",
00001023 => x"003e4554",
00001024 => x"5241570a",
00001025 => x"474e494e",
00001026 => x"57532021",
00001027 => x"4153495f",
00001028 => x"65662820",
00001029 => x"72757461",
00001030 => x"72207365",
00001031 => x"69757165",
00001032 => x"29646572",
00001033 => x"20737620",
00001034 => x"495f5748",
00001035 => x"28204153",
00001036 => x"74616566",
00001037 => x"73657275",
00001038 => x"61766120",
00001039 => x"62616c69",
00001040 => x"2029656c",
00001041 => x"6d73696d",
00001042 => x"68637461",
00001043 => x"57530a21",
00001044 => x"4153495f",
00001045 => x"30203d20",
00001046 => x"20782578",
00001047 => x"6d6f6328",
00001048 => x"656c6970",
00001049 => x"6c662072",
00001050 => x"29736761",
00001051 => x"5f57480a",
00001052 => x"20415349",
00001053 => x"7830203d",
00001054 => x"28207825",
00001055 => x"6173696d",
00001056 => x"72736320",
00001057 => x"000a0a29",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"42413938",
00001061 => x"46454443",
others => x"00000000"
);
 
/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1021) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1022) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
15,1020 → 15,1021
00000004 => x"00000293",
00000005 => x"00000313",
00000006 => x"00000393",
00000007 => x"00000413",
00000008 => x"00000493",
00000009 => x"00000713",
00000010 => x"00000793",
00000011 => x"80012117",
00000012 => x"fd010113",
00000013 => x"ffc17113",
00000014 => x"00010413",
00000015 => x"80010197",
00000016 => x"7c418193",
00000017 => x"00000517",
00000018 => x"0b450513",
00000019 => x"30551073",
00000020 => x"34151073",
00000021 => x"34301073",
00000022 => x"34201073",
00000023 => x"30001073",
00000024 => x"30401073",
00000025 => x"30601073",
00000026 => x"ffa00593",
00000027 => x"32059073",
00000028 => x"b0001073",
00000029 => x"b8001073",
00000030 => x"b0201073",
00000031 => x"b8201073",
00000032 => x"f0000593",
00000033 => x"0005a023",
00000034 => x"00458593",
00000035 => x"feb01ce3",
00000036 => x"80010597",
00000037 => x"f7058593",
00000038 => x"80818613",
00000039 => x"00c5d863",
00000040 => x"00058023",
00000041 => x"00158593",
00000042 => x"ff5ff06f",
00000043 => x"00001597",
00000044 => x"f4858593",
00000045 => x"80010617",
00000046 => x"f4c60613",
00000047 => x"80010697",
00000048 => x"f4468693",
00000049 => x"00d65c63",
00000050 => x"00058703",
00000051 => x"00e60023",
00000052 => x"00158593",
00000053 => x"00160613",
00000054 => x"fedff06f",
00000055 => x"00000513",
00000056 => x"00000593",
00000057 => x"060000ef",
00000058 => x"30047073",
00000059 => x"00000013",
00000060 => x"10500073",
00000061 => x"0000006f",
00000062 => x"ff810113",
00000063 => x"00812023",
00000064 => x"00912223",
00000065 => x"34202473",
00000066 => x"02044663",
00000067 => x"34102473",
00000068 => x"00041483",
00000069 => x"0034f493",
00000070 => x"00240413",
00000071 => x"34141073",
00000072 => x"00300413",
00000073 => x"00941863",
00000074 => x"34102473",
00000075 => x"00240413",
00000076 => x"34141073",
00000077 => x"00012403",
00000078 => x"00412483",
00000079 => x"00810113",
00000080 => x"30200073",
00000081 => x"800007b7",
00000082 => x"0007a023",
00000083 => x"fd010113",
00000084 => x"8001a223",
00000085 => x"02812423",
00000086 => x"fe002403",
00000087 => x"026267b7",
00000088 => x"02112623",
00000089 => x"02912223",
00000090 => x"03212023",
00000091 => x"01312e23",
00000092 => x"01412c23",
00000093 => x"01512a23",
00000094 => x"01612823",
00000095 => x"01712623",
00000096 => x"01812423",
00000097 => x"9ff78793",
00000098 => x"00000613",
00000099 => x"00000593",
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"389000ef",
00000104 => x"00100513",
00000105 => x"429000ef",
00000106 => x"00005537",
00000107 => x"00000613",
00000108 => x"00000593",
00000109 => x"b0050513",
00000110 => x"2b5000ef",
00000111 => x"1d1000ef",
00000112 => x"00245793",
00000113 => x"00a78533",
00000114 => x"00f537b3",
00000115 => x"00b785b3",
00000116 => x"1e9000ef",
00000117 => x"ffff07b7",
00000118 => x"4d478793",
00000119 => x"30579073",
00000120 => x"08000793",
00000121 => x"30479073",
00000122 => x"30046073",
00000123 => x"00000013",
00000007 => x"00000713",
00000008 => x"00000793",
00000009 => x"80012117",
00000010 => x"fd810113",
00000011 => x"ffc17113",
00000012 => x"00010413",
00000013 => x"80010197",
00000014 => x"7cc18193",
00000015 => x"00000517",
00000016 => x"0c050513",
00000017 => x"30551073",
00000018 => x"34151073",
00000019 => x"34301073",
00000020 => x"34201073",
00000021 => x"30001073",
00000022 => x"30401073",
00000023 => x"30601073",
00000024 => x"ffa00593",
00000025 => x"32059073",
00000026 => x"b0001073",
00000027 => x"b8001073",
00000028 => x"b0201073",
00000029 => x"b8201073",
00000030 => x"00010417",
00000031 => x"e8840413",
00000032 => x"00010497",
00000033 => x"f8048493",
00000034 => x"00042023",
00000035 => x"00440413",
00000036 => x"fe941ce3",
00000037 => x"80010597",
00000038 => x"f6c58593",
00000039 => x"80818613",
00000040 => x"00c5d863",
00000041 => x"00058023",
00000042 => x"00158593",
00000043 => x"ff5ff06f",
00000044 => x"00001597",
00000045 => x"f4858593",
00000046 => x"80010617",
00000047 => x"f4860613",
00000048 => x"80010697",
00000049 => x"f4068693",
00000050 => x"00d65c63",
00000051 => x"00058703",
00000052 => x"00e60023",
00000053 => x"00158593",
00000054 => x"00160613",
00000055 => x"fedff06f",
00000056 => x"00000513",
00000057 => x"00000593",
00000058 => x"060000ef",
00000059 => x"30047073",
00000060 => x"00000013",
00000061 => x"10500073",
00000062 => x"0000006f",
00000063 => x"ff810113",
00000064 => x"00812023",
00000065 => x"00912223",
00000066 => x"34202473",
00000067 => x"02044663",
00000068 => x"34102473",
00000069 => x"00041483",
00000070 => x"0034f493",
00000071 => x"00240413",
00000072 => x"34141073",
00000073 => x"00300413",
00000074 => x"00941863",
00000075 => x"34102473",
00000076 => x"00240413",
00000077 => x"34141073",
00000078 => x"00012403",
00000079 => x"00412483",
00000080 => x"00810113",
00000081 => x"30200073",
00000082 => x"800007b7",
00000083 => x"0007a023",
00000084 => x"fd010113",
00000085 => x"8001a223",
00000086 => x"02812423",
00000087 => x"fe002403",
00000088 => x"026267b7",
00000089 => x"02112623",
00000090 => x"02912223",
00000091 => x"03212023",
00000092 => x"01312e23",
00000093 => x"01412c23",
00000094 => x"01512a23",
00000095 => x"01612823",
00000096 => x"01712623",
00000097 => x"01812423",
00000098 => x"9ff78793",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"00200513",
00000102 => x"0087f463",
00000103 => x"00400513",
00000104 => x"389000ef",
00000105 => x"00100513",
00000106 => x"429000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
00000110 => x"b0050513",
00000111 => x"2b5000ef",
00000112 => x"1d1000ef",
00000113 => x"00245793",
00000114 => x"00a78533",
00000115 => x"00f537b3",
00000116 => x"00b785b3",
00000117 => x"1e9000ef",
00000118 => x"ffff07b7",
00000119 => x"4d878793",
00000120 => x"30579073",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"f0850513",
00000127 => x"315000ef",
00000128 => x"f1302573",
00000129 => x"260000ef",
00000130 => x"ffff1537",
00000131 => x"f4050513",
00000132 => x"301000ef",
00000133 => x"fe002503",
00000134 => x"24c000ef",
00000135 => x"ffff1537",
00000136 => x"f4850513",
00000137 => x"2ed000ef",
00000138 => x"fe402503",
00000139 => x"238000ef",
00000140 => x"ffff1537",
00000141 => x"f5050513",
00000142 => x"2d9000ef",
00000143 => x"30102573",
00000144 => x"224000ef",
00000145 => x"ffff1537",
00000146 => x"f5850513",
00000147 => x"2c5000ef",
00000148 => x"fc002573",
00000149 => x"210000ef",
00000150 => x"ffff1537",
00000151 => x"f6050513",
00000152 => x"2b1000ef",
00000153 => x"fe802503",
00000154 => x"ffff14b7",
00000155 => x"00341413",
00000156 => x"1f4000ef",
00000157 => x"ffff1537",
00000158 => x"f6850513",
00000159 => x"295000ef",
00000160 => x"ff802503",
00000161 => x"1e0000ef",
00000162 => x"f7048513",
00000163 => x"285000ef",
00000164 => x"ff002503",
00000165 => x"1d0000ef",
00000166 => x"ffff1537",
00000167 => x"f7c50513",
00000168 => x"271000ef",
00000169 => x"ffc02503",
00000170 => x"1bc000ef",
00000171 => x"f7048513",
00000172 => x"261000ef",
00000173 => x"ff402503",
00000174 => x"1ac000ef",
00000175 => x"ffff1537",
00000176 => x"f8450513",
00000177 => x"24d000ef",
00000178 => x"0c5000ef",
00000179 => x"00a404b3",
00000180 => x"0084b433",
00000181 => x"00b40433",
00000182 => x"1dd000ef",
00000183 => x"02050263",
00000184 => x"ffff1537",
00000185 => x"fb050513",
00000186 => x"229000ef",
00000187 => x"0e5000ef",
00000188 => x"02300793",
00000189 => x"02f51263",
00000190 => x"00000513",
00000191 => x"0180006f",
00000192 => x"08d000ef",
00000193 => x"fc85eae3",
00000194 => x"00b41463",
00000195 => x"fc9566e3",
00000196 => x"00100513",
00000197 => x"5e8000ef",
00000198 => x"0b4000ef",
00000199 => x"ffff1937",
00000200 => x"ffff19b7",
00000201 => x"02300a13",
00000202 => x"07200a93",
00000203 => x"06800b13",
00000204 => x"07500b93",
00000205 => x"ffff14b7",
00000206 => x"ffff1c37",
00000207 => x"fbc90513",
00000208 => x"1d1000ef",
00000209 => x"161000ef",
00000210 => x"00050413",
00000211 => x"135000ef",
00000212 => x"ec098513",
00000213 => x"1bd000ef",
00000214 => x"fb4400e3",
00000215 => x"01541863",
00000216 => x"ffff02b7",
00000217 => x"00028067",
00000218 => x"fd5ff06f",
00000219 => x"01641663",
00000220 => x"05c000ef",
00000221 => x"fc9ff06f",
00000222 => x"00000513",
00000223 => x"03740063",
00000224 => x"07300793",
00000225 => x"00f41663",
00000226 => x"688000ef",
00000227 => x"fb1ff06f",
00000228 => x"06c00793",
00000229 => x"00f41863",
00000230 => x"00100513",
00000231 => x"3fc000ef",
00000232 => x"f9dff06f",
00000233 => x"06500793",
00000234 => x"00f41663",
00000235 => x"02c000ef",
00000236 => x"f8dff06f",
00000237 => x"03f00793",
00000238 => x"fc4c0513",
00000239 => x"00f40463",
00000240 => x"fd848513",
00000241 => x"14d000ef",
00000242 => x"f75ff06f",
00000243 => x"ffff1537",
00000244 => x"dd450513",
00000245 => x"13d0006f",
00000246 => x"800007b7",
00000247 => x"0007a783",
00000248 => x"00079863",
00000249 => x"ffff1537",
00000250 => x"e3850513",
00000251 => x"1250006f",
00000252 => x"ff010113",
00000253 => x"00112623",
00000254 => x"30047073",
00000255 => x"00000013",
00000125 => x"00000013",
00000126 => x"ffff1537",
00000127 => x"f0c50513",
00000128 => x"315000ef",
00000129 => x"f1302573",
00000130 => x"260000ef",
00000131 => x"ffff1537",
00000132 => x"f4450513",
00000133 => x"301000ef",
00000134 => x"fe002503",
00000135 => x"24c000ef",
00000136 => x"ffff1537",
00000137 => x"f4c50513",
00000138 => x"2ed000ef",
00000139 => x"fe402503",
00000140 => x"238000ef",
00000141 => x"ffff1537",
00000142 => x"f5450513",
00000143 => x"2d9000ef",
00000144 => x"30102573",
00000145 => x"224000ef",
00000146 => x"ffff1537",
00000147 => x"f5c50513",
00000148 => x"2c5000ef",
00000149 => x"fc002573",
00000150 => x"210000ef",
00000151 => x"ffff1537",
00000152 => x"f6450513",
00000153 => x"2b1000ef",
00000154 => x"fe802503",
00000155 => x"ffff14b7",
00000156 => x"00341413",
00000157 => x"1f4000ef",
00000158 => x"ffff1537",
00000159 => x"f6c50513",
00000160 => x"295000ef",
00000161 => x"ff802503",
00000162 => x"1e0000ef",
00000163 => x"f7448513",
00000164 => x"285000ef",
00000165 => x"ff002503",
00000166 => x"1d0000ef",
00000167 => x"ffff1537",
00000168 => x"f8050513",
00000169 => x"271000ef",
00000170 => x"ffc02503",
00000171 => x"1bc000ef",
00000172 => x"f7448513",
00000173 => x"261000ef",
00000174 => x"ff402503",
00000175 => x"1ac000ef",
00000176 => x"ffff1537",
00000177 => x"f8850513",
00000178 => x"24d000ef",
00000179 => x"0c5000ef",
00000180 => x"00a404b3",
00000181 => x"0084b433",
00000182 => x"00b40433",
00000183 => x"1dd000ef",
00000184 => x"02050263",
00000185 => x"ffff1537",
00000186 => x"fb450513",
00000187 => x"229000ef",
00000188 => x"0e5000ef",
00000189 => x"02300793",
00000190 => x"02f51263",
00000191 => x"00000513",
00000192 => x"0180006f",
00000193 => x"08d000ef",
00000194 => x"fc85eae3",
00000195 => x"00b41463",
00000196 => x"fc9566e3",
00000197 => x"00100513",
00000198 => x"5e8000ef",
00000199 => x"0b4000ef",
00000200 => x"ffff1937",
00000201 => x"ffff19b7",
00000202 => x"02300a13",
00000203 => x"07200a93",
00000204 => x"06800b13",
00000205 => x"07500b93",
00000206 => x"ffff14b7",
00000207 => x"ffff1c37",
00000208 => x"fc090513",
00000209 => x"1d1000ef",
00000210 => x"161000ef",
00000211 => x"00050413",
00000212 => x"135000ef",
00000213 => x"ec498513",
00000214 => x"1bd000ef",
00000215 => x"fb4400e3",
00000216 => x"01541863",
00000217 => x"ffff02b7",
00000218 => x"00028067",
00000219 => x"fd5ff06f",
00000220 => x"01641663",
00000221 => x"05c000ef",
00000222 => x"fc9ff06f",
00000223 => x"00000513",
00000224 => x"03740063",
00000225 => x"07300793",
00000226 => x"00f41663",
00000227 => x"688000ef",
00000228 => x"fb1ff06f",
00000229 => x"06c00793",
00000230 => x"00f41863",
00000231 => x"00100513",
00000232 => x"3fc000ef",
00000233 => x"f9dff06f",
00000234 => x"06500793",
00000235 => x"00f41663",
00000236 => x"02c000ef",
00000237 => x"f8dff06f",
00000238 => x"03f00793",
00000239 => x"fc8c0513",
00000240 => x"00f40463",
00000241 => x"fdc48513",
00000242 => x"14d000ef",
00000243 => x"f75ff06f",
00000244 => x"ffff1537",
00000245 => x"dd850513",
00000246 => x"13d0006f",
00000247 => x"800007b7",
00000248 => x"0007a783",
00000249 => x"00079863",
00000250 => x"ffff1537",
00000251 => x"e3c50513",
00000252 => x"1250006f",
00000253 => x"ff010113",
00000254 => x"00112623",
00000255 => x"30047073",
00000256 => x"00000013",
00000257 => x"ffff1537",
00000258 => x"e5450513",
00000259 => x"105000ef",
00000260 => x"081000ef",
00000261 => x"fe051ee3",
00000262 => x"ff002783",
00000263 => x"00078067",
00000264 => x"0000006f",
00000265 => x"ff010113",
00000266 => x"00812423",
00000267 => x"00050413",
00000268 => x"ffff1537",
00000269 => x"e6450513",
00000270 => x"00112623",
00000271 => x"0d5000ef",
00000272 => x"03040513",
00000273 => x"0ff57513",
00000274 => x"039000ef",
00000275 => x"30047073",
00000276 => x"00000013",
00000257 => x"00000013",
00000258 => x"ffff1537",
00000259 => x"e5850513",
00000260 => x"105000ef",
00000261 => x"081000ef",
00000262 => x"fe051ee3",
00000263 => x"ff002783",
00000264 => x"00078067",
00000265 => x"0000006f",
00000266 => x"ff010113",
00000267 => x"00812423",
00000268 => x"00050413",
00000269 => x"ffff1537",
00000270 => x"e6850513",
00000271 => x"00112623",
00000272 => x"0d5000ef",
00000273 => x"03040513",
00000274 => x"0ff57513",
00000275 => x"039000ef",
00000276 => x"30047073",
00000277 => x"00000013",
00000278 => x"00100513",
00000279 => x"171000ef",
00000280 => x"0000006f",
00000281 => x"fe010113",
00000282 => x"01212823",
00000283 => x"00050913",
00000284 => x"ffff1537",
00000285 => x"00912a23",
00000286 => x"e7050513",
00000287 => x"ffff14b7",
00000288 => x"00812c23",
00000289 => x"01312623",
00000290 => x"00112e23",
00000291 => x"01c00413",
00000292 => x"081000ef",
00000293 => x"fe448493",
00000294 => x"ffc00993",
00000295 => x"008957b3",
00000296 => x"00f7f793",
00000297 => x"00f487b3",
00000298 => x"0007c503",
00000299 => x"ffc40413",
00000300 => x"7d0000ef",
00000301 => x"ff3414e3",
00000302 => x"01c12083",
00000303 => x"01812403",
00000304 => x"01412483",
00000305 => x"01012903",
00000306 => x"00c12983",
00000307 => x"02010113",
00000308 => x"00008067",
00000309 => x"fb010113",
00000310 => x"04112623",
00000311 => x"04512423",
00000312 => x"04612223",
00000313 => x"04712023",
00000314 => x"02812e23",
00000315 => x"02a12c23",
00000316 => x"02b12a23",
00000317 => x"02c12823",
00000318 => x"02d12623",
00000319 => x"02e12423",
00000320 => x"02f12223",
00000321 => x"03012023",
00000322 => x"01112e23",
00000323 => x"01c12c23",
00000324 => x"01d12a23",
00000325 => x"01e12823",
00000326 => x"01f12623",
00000327 => x"34202473",
00000328 => x"800007b7",
00000329 => x"00778793",
00000330 => x"06f41a63",
00000331 => x"00000513",
00000332 => x"081000ef",
00000333 => x"658000ef",
00000334 => x"fe002783",
00000335 => x"0027d793",
00000336 => x"00a78533",
00000337 => x"00f537b3",
00000338 => x"00b785b3",
00000339 => x"66c000ef",
00000340 => x"03c12403",
00000341 => x"04c12083",
00000342 => x"04812283",
00000343 => x"04412303",
00000344 => x"04012383",
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00000974 => x"0a313230",
00000975 => x"3a565748",
00000976 => x"00002020",
00000977 => x"4b4c430a",
00000978 => x"0020203a",
00000979 => x"4553550a",
00000980 => x"00203a52",
00000981 => x"53494d0a",
00000982 => x"00203a41",
00000983 => x"58455a0a",
00000984 => x"00203a54",
00000985 => x"4f52500a",
00000986 => x"00203a43",
00000987 => x"454d490a",
00000988 => x"00203a4d",
00000989 => x"74796220",
00000990 => x"40207365",
00000991 => x"00000020",
00000992 => x"454d440a",
00000993 => x"00203a4d",
00000994 => x"75410a0a",
00000995 => x"6f626f74",
00000996 => x"6920746f",
00000997 => x"3828206e",
00000998 => x"202e7329",
00000999 => x"73657250",
00001000 => x"656b2073",
00001001 => x"6f742079",
00001002 => x"6f626120",
00001003 => x"0a2e7472",
00001004 => x"00000000",
00001005 => x"726f6241",
00001006 => x"2e646574",
00001007 => x"00000a0a",
00001008 => x"444d430a",
00001009 => x"00203e3a",
00001010 => x"53207962",
00001011 => x"68706574",
00001012 => x"4e206e61",
00001013 => x"69746c6f",
00001014 => x"0000676e",
00001015 => x"61766e49",
00001016 => x"2064696c",
00001017 => x"00444d43",
00001018 => x"33323130",
00001019 => x"37363534",
00001020 => x"62613938",
00001021 => x"66656463",
others => x"00000000"
);
 
/neorv32_cpu.vhd
111,6 → 111,8
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- non-maskable interrupt --
nm_irq_i : in std_ulogic := '0'; -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
259,6 → 261,8
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
-- non-maskable interrupt --
nm_irq_i => nm_irq_i, -- nmi
-- fast interrupts (custom) --
firq_i => firq_i, -- fast interrupt trigger
firq_ack_o => firq_ack_o, -- fast interrupt acknowledge mask
/neorv32_cpu_control.vhd
92,6 → 92,8
-- FPU interface --
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
-- non-maskable interrupt --
nm_irq_i : in std_ulogic;
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
236,7 → 238,6
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
firq_sync : std_ulogic_vector(15 downto 0);
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
exc_ack : std_ulogic; -- acknowledge all exceptions
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
266,11 → 267,9
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_ctrl_rd_t is array (0 to 63) of std_ulogic_vector(7 downto 0);
type pmp_addr_rd_t is array (0 to 63) of std_ulogic_vector(data_width_c-1 downto 0);
type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0); -- 32-bit, plus 1-bit overflow
type mhpmcnth_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0); -- 32-bit
type mhpmevent_rd_t is array (0 to 29) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
type mhpmcnth_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
type csr_t is record
300,9 → 299,6
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
--
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
--
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
priv_m_mode : std_ulogic; -- CPU in M-mode
priv_u_mode : std_ulogic; -- CPU in u-mode
313,7 → 309,6
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)
--
mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
mhpmevent_rd : mhpmevent_rd_t; -- mhpmevent*: actual read data
--
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
--
330,7 → 325,6
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
pmpcfg_rd : pmp_ctrl_rd_t; -- physical memory protection - actual read data
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
pmpaddr_rd : pmp_addr_rd_t; -- physical memory protection - actual read data
--
frm : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode
fflags : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags
708,7 → 702,7
-- PC update --
if (execute_engine.pc_we = '1') then
if (execute_engine.pc_mux_sel = '0') then
execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment OR trap enter/exit
else
execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
end if;
947,7 → 941,7
when DISPATCH => -- Get new command from instruction issue engine
-- ------------------------------------------------------------
-- housekeeping --
execute_engine.is_cp_op_nxt <= '0'; -- no compressed instruction yet
execute_engine.is_cp_op_nxt <= '0'; -- no co-processor operation yet
-- PC update --
execute_engine.pc_mux_sel <= '0'; -- linear next PC
-- IR update --
1289,17 → 1283,14
-- -------------------------------------------------------------------------------------------
csr_access_check: process(execute_engine.i_reg, csr)
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
variable csr_mcounteren_hpm_v : std_ulogic_vector(31 downto 0); -- max 29 HPM counters, plus 3 LSB-aligned dummy bits
begin
-- is this CSR instruction really going to write/read to/from a CSR? --
-- is this CSR instruction really going to write to a CSR? --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
csr_wacc_v := '1'; -- always write CSR
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
else
else -- clear/set
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
-- csr_racc_v := '1'; -- always read CSR
end if;
 
-- low privilege level access to hpm counters? --
1311,11 → 1302,16
end if;
 
-- check CSR access --
csr_acc_valid <= '0'; -- default = invalid access
case csr.addr is
 
-- user floating-point CSRs --
-- floating-point CSRs --
when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- full access for everyone if Zfinx extension is implemented
if (CPU_EXTENSION_RISCV_Zfinx = true) then
csr_acc_valid <= '1'; -- full access for everyone if Zfinx extension is implemented
else
NULL;
end if;
 
-- machine trap setup --
when csr_mstatus_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mstatush_c =>
1322,13 → 1318,19
csr_acc_valid <= csr.priv_m_mode; -- M-mode only, NOTE: MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
 
-- machine trap handling --
when csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mtval_c | csr_mip_c =>
when csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mtval_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mip_c => -- NOTE: MIP is read-only in the NEORV32
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- physical memory protection - address --
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
1339,17 → 1341,17
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- machine counters/timers --
when csr_mcycle_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access if implemented
when csr_mcycleh_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access if implemented
when csr_minstret_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access if implemented
when csr_minstreth_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access if implemented
when csr_mcycle_c | csr_minstret_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_lo_width_c > 0)); -- M-mode only, access valid if really implemented
when csr_mcycleh_c | csr_minstreth_c =>
csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(cpu_cnt_hi_width_c > 0)); -- M-mode only, access valid if really implemented
 
when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c | -- LOW
csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
1361,7 → 1363,11
csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- user counters/timers --
when csr_cycle_c =>
1386,7 → 1392,11
csr_hpmcounter15h_c | csr_hpmcounter16h_c | csr_hpmcounter17h_c | csr_hpmcounter18h_c | csr_hpmcounter19h_c | csr_hpmcounter20h_c |
csr_hpmcounter21h_c | csr_hpmcounter22h_c | csr_hpmcounter23h_c | csr_hpmcounter24h_c | csr_hpmcounter25h_c | csr_hpmcounter26h_c |
csr_hpmcounter27h_c | csr_hpmcounter28h_c | csr_hpmcounter29h_c | csr_hpmcounter30h_c | csr_hpmcounter31h_c =>
csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(to_integer(unsigned(csr.addr(4 downto 0))))); -- M-mode, U-mode if authorized, read-only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(to_integer(unsigned(csr.addr(4 downto 0))))); -- M-mode, U-mode if authorized, read-only
else
NULL;
end if;
 
-- machine counter setup --
when csr_mcountinhibit_c =>
1397,17 → 1407,19
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
if (HPM_NUM_CNTS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- machine information registers --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c =>
-- machine information registers & custom (NEORV32-specific) read-only CSRs --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mzext_c =>
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
-- custom (NEORV32-specific) read-only CSRs --
when csr_mzext_c =>
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- undefined / not implemented --
when others =>
csr_acc_valid <= '0'; -- invalid access
NULL; -- invalid access
end case;
end process csr_access_check;
 
1644,11 → 1656,11
if (rstn_i = '0') then
trap_ctrl.exc_buf <= (others => '0');
trap_ctrl.irq_buf <= (others => def_rst_val_c);
trap_ctrl.irq_buf(interrupt_nm_irq_c) <= '0'; -- NMI
trap_ctrl.exc_ack <= '0';
trap_ctrl.irq_ack <= (others => '0');
trap_ctrl.env_start <= '0';
trap_ctrl.cause <= (others => def_rst_val_c);
trap_ctrl.firq_sync <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- exception buffer: misaligned load/store/instruction address
1664,14 → 1676,15
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
-- interrupt buffer: non-maskable interrupt
trap_ctrl.irq_buf(interrupt_nm_irq_c) <= (trap_ctrl.irq_buf(interrupt_nm_irq_c) or nm_irq_i) and (not trap_ctrl.irq_ack(interrupt_nm_irq_c));
-- interrupt buffer: machine software/external/timer interrupt
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
-- interrupt buffer: NEORV32-specific fast interrupts
trap_ctrl.firq_sync <= firq_i;
for i in 0 to 15 loop
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or trap_ctrl.firq_sync(i)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c+i) or csr.mip_clear(interrupt_firq_0_c+i)));
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or firq_i(i)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c+i));
end loop;
-- trap control --
if (trap_ctrl.env_start = '0') then -- no started trap handler
1678,7 → 1691,7
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- trap triggered!
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
trap_ctrl.exc_ack <= '1'; -- clear execption
trap_ctrl.exc_ack <= '1'; -- clear exception
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- clear interrupt with interrupt ACK mask
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
end if;
1697,9 → 1710,6
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
 
-- current pending interrupts (for CSR.MIP register) --
csr.mip_status <= trap_ctrl.irq_buf;
 
-- acknowledge mask output --
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_15_c downto interrupt_firq_0_c);
 
1709,14 → 1719,22
trap_priority: process(trap_ctrl)
begin
-- defaults --
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.cause_nxt <= (others => '-');
trap_ctrl.irq_ack_nxt <= (others => '0');
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
-- here we do need a specific acknowledge mask since several sources can trigger at once
-- ----------------------------------------------------------------------------------------
 
-- interrupt: 1.0 non-maskable interrupt --
if (trap_ctrl.irq_buf(interrupt_nm_irq_c) = '1') then
trap_ctrl.cause_nxt <= trap_nmi_c;
trap_ctrl.irq_ack_nxt(interrupt_nm_irq_c) <= '1';
 
 
-- interrupt: 1.11 machine external interrupt --
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
trap_ctrl.cause_nxt <= trap_mei_c;
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
 
1812,9 → 1830,11
trap_ctrl.irq_ack_nxt(interrupt_firq_15_c) <= '1';
 
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
-- here we do not need a specific acknowledge mask since only one exception (the one
-- with highest priority) is evaluated at once
-- ----------------------------------------------------------------------------------------
 
-- exception: 0.1 instruction access fault --
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
1857,11 → 1877,6
-- exception: 0.5 load access fault --
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
trap_ctrl.cause_nxt <= trap_lbe_c;
 
-- not implemented --
else
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.irq_ack_nxt <= (others => '0');
end if;
end process trap_priority;
1914,7 → 1929,6
csr.mepc <= (others => def_rst_val_c);
csr.mcause <= (others => def_rst_val_c);
csr.mtval <= (others => def_rst_val_c);
csr.mip_clear <= (others => def_rst_val_c);
--
csr.pmpcfg <= (others => (others => '0'));
csr.pmpaddr <= (others => (others => def_rst_val_c));
1936,8 → 1950,6
elsif rising_edge(clk_i) then
-- write access? --
csr.we <= csr.we_nxt;
-- defaults --
csr.mip_clear <= (others => '0');
 
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- --------------------------------------------------------------------------------
2020,15 → 2032,6
if (csr.addr(3 downto 0) = csr_mtval_c(3 downto 0)) then
csr.mtval <= csr.wdata;
end if;
-- R/W: mip - machine interrupt pending --
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
for i in 0 to 15 loop -- fast interrupt channels 0..15
csr.mip_clear(interrupt_firq_0_c+i) <= not csr.wdata(16+i);
end loop; -- i
end if;
end if;
 
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
2213,18 → 2216,13
end if;
end process pmp_output;
 
-- PMP read dummy --
-- PMP config read dummy --
pmp_rd_dummy: process(csr)
begin
csr.pmpcfg_rd <= (others => (others => '0'));
csr.pmpaddr_rd <= (others => (others => '0'));
if (PMP_NUM_REGIONS /= 0) then
for i in 0 to PMP_NUM_REGIONS-1 loop
csr.pmpcfg_rd(i) <= csr.pmpcfg(i);
csr.pmpaddr_rd(i) <= csr.pmpaddr(i);
if (csr.pmpcfg(i)(4 downto 3) = "00") then -- mode = off
csr.pmpaddr_rd(i)(index_size_f(PMP_MIN_GRANULARITY)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end loop; -- i
end if;
end process pmp_rd_dummy;
2251,7 → 2249,7
elsif rising_edge(clk_i) then
 
-- [m]cycle --
csr.mcycle(csr.mcycle'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mcycle(csr.mcycle'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.mcycle <= (others => '0');
mcycle_msb <= '0';
2264,7 → 2262,7
end if;
 
-- [m]cycleh --
csr.mcycleh(csr.mcycleh'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mcycleh(csr.mcycleh'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_hi_width_c = 0) then
csr.mcycleh <= (others => '0');
elsif (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
2274,7 → 2272,7
end if;
 
-- [m]instret --
csr.minstret(csr.minstret'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.minstret(csr.minstret'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.minstret <= (others => '0');
minstret_msb <= '0';
2298,7 → 2296,7
 
-- [machine] hardware performance monitors (counters) --
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmcounter(i)(csr.mhpmcounter(i)'left downto hpm_cnt_lo_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mhpmcounter(i)(csr.mhpmcounter(i)'left downto hpm_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_lo_width_c = 0) then
csr.mhpmcounter(i) <= (others => '0');
mhpmcounter_msb(i) <= '0';
2314,7 → 2312,7
end if;
 
-- [m]hpmcounter*h --
csr.mhpmcounterh(i)(csr.mhpmcounterh(i)'left downto hpm_cnt_hi_width_c+1) <= (others => '0'); -- set unsued bits to zero
csr.mhpmcounterh(i)(csr.mhpmcounterh(i)'left downto hpm_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_hi_width_c = 0) then
csr.mhpmcounterh(i) <= (others => '0');
else
2329,15 → 2327,13
end if;
end process csr_counters;
 
-- hpm read dummy --
-- hpm counters read dummy --
hpm_rd_dummy: process(csr)
begin
csr.mhpmevent_rd <= (others => (others => '0'));
csr.mhpmcounter_rd <= (others => (others => '0'));
csr.mhpmcounterh_rd <= (others => (others => '0'));
if (HPM_NUM_CNTS /= 0) then
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmevent_rd(i) <= csr.mhpmevent(i);
if (hpm_cnt_lo_width_c > 0) then
csr.mhpmcounter_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0);
end if;
2406,23 → 2402,26
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
case csr.addr is
 
-- user floating-point CSRs --
-- floating-point CSRs --
-- --------------------------------------------------------------------
when csr_fflags_c => -- R/W: fflags - floating-point (FPU) exception flags
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(4 downto 0) <= csr.fflags;
else
NULL;
end if;
when csr_frm_c => -- R/W: frm - floating-point (FPU) rounding mode
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(2 downto 0) <= csr.frm;
else
NULL;
end if;
when csr_fcsr_c => -- R/W: fcsr - floating-point (FPU) control/status (frm + fflags)
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
csr.rdata(7 downto 5) <= csr.frm;
csr.rdata(4 downto 0) <= csr.fflags;
else
NULL;
end if;
 
-- machine trap setup --
2455,8 → 2454,9
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when csr_mcounteren_c => -- R/W: machine counter enable register
csr.rdata <= (others => '0');
if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
if (CPU_EXTENSION_RISCV_U = false) then -- this CSR is hardwired to zero if user mode is not implemented
NULL;
else
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
2473,97 → 2473,97
csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
csr.rdata <= csr.mtval;
when csr_mip_c => -- R/W: mip - machine interrupt pending
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
when csr_mip_c => -- R/-: mip - machine interrupt pending
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
for i in 0 to 15 loop -- fast interrupt channels 0..15 pending
csr.rdata(16+i) <= csr.mip_status(interrupt_firq_0_c+i);
csr.rdata(16+i) <= trap_ctrl.irq_buf(interrupt_firq_0_c+i);
end loop; -- i
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
when csr_pmpcfg3_c => csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); -- R/W: pmpcfg3
when csr_pmpcfg4_c => csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); -- R/W: pmpcfg4
when csr_pmpcfg5_c => csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); -- R/W: pmpcfg5
when csr_pmpcfg6_c => csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); -- R/W: pmpcfg6
when csr_pmpcfg7_c => csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); -- R/W: pmpcfg7
when csr_pmpcfg8_c => csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); -- R/W: pmpcfg8
when csr_pmpcfg9_c => csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); -- R/W: pmpcfg9
when csr_pmpcfg10_c => csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); -- R/W: pmpcfg10
when csr_pmpcfg11_c => csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); -- R/W: pmpcfg11
when csr_pmpcfg12_c => csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); -- R/W: pmpcfg12
when csr_pmpcfg13_c => csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); -- R/W: pmpcfg13
when csr_pmpcfg14_c => csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); -- R/W: pmpcfg14
when csr_pmpcfg15_c => csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); -- R/W: pmpcfg15
when csr_pmpcfg0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); else NULL; end if; -- R/W: pmpcfg0
when csr_pmpcfg1_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); else NULL; end if; -- R/W: pmpcfg1
when csr_pmpcfg2_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); else NULL; end if; -- R/W: pmpcfg2
when csr_pmpcfg3_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); else NULL; end if; -- R/W: pmpcfg3
when csr_pmpcfg4_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); else NULL; end if; -- R/W: pmpcfg4
when csr_pmpcfg5_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); else NULL; end if; -- R/W: pmpcfg5
when csr_pmpcfg6_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); else NULL; end if; -- R/W: pmpcfg6
when csr_pmpcfg7_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); else NULL; end if; -- R/W: pmpcfg7
when csr_pmpcfg8_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); else NULL; end if; -- R/W: pmpcfg8
when csr_pmpcfg9_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); else NULL; end if; -- R/W: pmpcfg9
when csr_pmpcfg10_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); else NULL; end if; -- R/W: pmpcfg10
when csr_pmpcfg11_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); else NULL; end if; -- R/W: pmpcfg11
when csr_pmpcfg12_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); else NULL; end if; -- R/W: pmpcfg12
when csr_pmpcfg13_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); else NULL; end if; -- R/W: pmpcfg13
when csr_pmpcfg14_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); else NULL; end if; -- R/W: pmpcfg14
when csr_pmpcfg15_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); else NULL; end if; -- R/W: pmpcfg15
 
-- physical memory protection - addresses --
when csr_pmpaddr0_c => csr.rdata <= csr.pmpaddr_rd(00); -- R/W: pmpaddr0
when csr_pmpaddr1_c => csr.rdata <= csr.pmpaddr_rd(01); -- R/W: pmpaddr1
when csr_pmpaddr2_c => csr.rdata <= csr.pmpaddr_rd(02); -- R/W: pmpaddr2
when csr_pmpaddr3_c => csr.rdata <= csr.pmpaddr_rd(03); -- R/W: pmpaddr3
when csr_pmpaddr4_c => csr.rdata <= csr.pmpaddr_rd(04); -- R/W: pmpaddr4
when csr_pmpaddr5_c => csr.rdata <= csr.pmpaddr_rd(05); -- R/W: pmpaddr5
when csr_pmpaddr6_c => csr.rdata <= csr.pmpaddr_rd(06); -- R/W: pmpaddr6
when csr_pmpaddr7_c => csr.rdata <= csr.pmpaddr_rd(07); -- R/W: pmpaddr7
when csr_pmpaddr8_c => csr.rdata <= csr.pmpaddr_rd(08); -- R/W: pmpaddr8
when csr_pmpaddr9_c => csr.rdata <= csr.pmpaddr_rd(09); -- R/W: pmpaddr9
when csr_pmpaddr10_c => csr.rdata <= csr.pmpaddr_rd(10); -- R/W: pmpaddr10
when csr_pmpaddr11_c => csr.rdata <= csr.pmpaddr_rd(11); -- R/W: pmpaddr11
when csr_pmpaddr12_c => csr.rdata <= csr.pmpaddr_rd(12); -- R/W: pmpaddr12
when csr_pmpaddr13_c => csr.rdata <= csr.pmpaddr_rd(13); -- R/W: pmpaddr13
when csr_pmpaddr14_c => csr.rdata <= csr.pmpaddr_rd(14); -- R/W: pmpaddr14
when csr_pmpaddr15_c => csr.rdata <= csr.pmpaddr_rd(15); -- R/W: pmpaddr15
when csr_pmpaddr16_c => csr.rdata <= csr.pmpaddr_rd(16); -- R/W: pmpaddr16
when csr_pmpaddr17_c => csr.rdata <= csr.pmpaddr_rd(17); -- R/W: pmpaddr17
when csr_pmpaddr18_c => csr.rdata <= csr.pmpaddr_rd(18); -- R/W: pmpaddr18
when csr_pmpaddr19_c => csr.rdata <= csr.pmpaddr_rd(19); -- R/W: pmpaddr19
when csr_pmpaddr20_c => csr.rdata <= csr.pmpaddr_rd(20); -- R/W: pmpaddr20
when csr_pmpaddr21_c => csr.rdata <= csr.pmpaddr_rd(21); -- R/W: pmpaddr21
when csr_pmpaddr22_c => csr.rdata <= csr.pmpaddr_rd(22); -- R/W: pmpaddr22
when csr_pmpaddr23_c => csr.rdata <= csr.pmpaddr_rd(23); -- R/W: pmpaddr23
when csr_pmpaddr24_c => csr.rdata <= csr.pmpaddr_rd(24); -- R/W: pmpaddr24
when csr_pmpaddr25_c => csr.rdata <= csr.pmpaddr_rd(25); -- R/W: pmpaddr25
when csr_pmpaddr26_c => csr.rdata <= csr.pmpaddr_rd(26); -- R/W: pmpaddr26
when csr_pmpaddr27_c => csr.rdata <= csr.pmpaddr_rd(27); -- R/W: pmpaddr27
when csr_pmpaddr28_c => csr.rdata <= csr.pmpaddr_rd(28); -- R/W: pmpaddr28
when csr_pmpaddr29_c => csr.rdata <= csr.pmpaddr_rd(29); -- R/W: pmpaddr29
when csr_pmpaddr30_c => csr.rdata <= csr.pmpaddr_rd(30); -- R/W: pmpaddr30
when csr_pmpaddr31_c => csr.rdata <= csr.pmpaddr_rd(31); -- R/W: pmpaddr31
when csr_pmpaddr32_c => csr.rdata <= csr.pmpaddr_rd(32); -- R/W: pmpaddr32
when csr_pmpaddr33_c => csr.rdata <= csr.pmpaddr_rd(33); -- R/W: pmpaddr33
when csr_pmpaddr34_c => csr.rdata <= csr.pmpaddr_rd(34); -- R/W: pmpaddr34
when csr_pmpaddr35_c => csr.rdata <= csr.pmpaddr_rd(35); -- R/W: pmpaddr35
when csr_pmpaddr36_c => csr.rdata <= csr.pmpaddr_rd(36); -- R/W: pmpaddr36
when csr_pmpaddr37_c => csr.rdata <= csr.pmpaddr_rd(37); -- R/W: pmpaddr37
when csr_pmpaddr38_c => csr.rdata <= csr.pmpaddr_rd(38); -- R/W: pmpaddr38
when csr_pmpaddr39_c => csr.rdata <= csr.pmpaddr_rd(39); -- R/W: pmpaddr39
when csr_pmpaddr40_c => csr.rdata <= csr.pmpaddr_rd(40); -- R/W: pmpaddr40
when csr_pmpaddr41_c => csr.rdata <= csr.pmpaddr_rd(41); -- R/W: pmpaddr41
when csr_pmpaddr42_c => csr.rdata <= csr.pmpaddr_rd(42); -- R/W: pmpaddr42
when csr_pmpaddr43_c => csr.rdata <= csr.pmpaddr_rd(43); -- R/W: pmpaddr43
when csr_pmpaddr44_c => csr.rdata <= csr.pmpaddr_rd(44); -- R/W: pmpaddr44
when csr_pmpaddr45_c => csr.rdata <= csr.pmpaddr_rd(45); -- R/W: pmpaddr45
when csr_pmpaddr46_c => csr.rdata <= csr.pmpaddr_rd(46); -- R/W: pmpaddr46
when csr_pmpaddr47_c => csr.rdata <= csr.pmpaddr_rd(47); -- R/W: pmpaddr47
when csr_pmpaddr48_c => csr.rdata <= csr.pmpaddr_rd(48); -- R/W: pmpaddr48
when csr_pmpaddr49_c => csr.rdata <= csr.pmpaddr_rd(49); -- R/W: pmpaddr49
when csr_pmpaddr50_c => csr.rdata <= csr.pmpaddr_rd(50); -- R/W: pmpaddr50
when csr_pmpaddr51_c => csr.rdata <= csr.pmpaddr_rd(51); -- R/W: pmpaddr51
when csr_pmpaddr52_c => csr.rdata <= csr.pmpaddr_rd(52); -- R/W: pmpaddr52
when csr_pmpaddr53_c => csr.rdata <= csr.pmpaddr_rd(53); -- R/W: pmpaddr53
when csr_pmpaddr54_c => csr.rdata <= csr.pmpaddr_rd(54); -- R/W: pmpaddr54
when csr_pmpaddr55_c => csr.rdata <= csr.pmpaddr_rd(55); -- R/W: pmpaddr55
when csr_pmpaddr56_c => csr.rdata <= csr.pmpaddr_rd(56); -- R/W: pmpaddr56
when csr_pmpaddr57_c => csr.rdata <= csr.pmpaddr_rd(57); -- R/W: pmpaddr57
when csr_pmpaddr58_c => csr.rdata <= csr.pmpaddr_rd(58); -- R/W: pmpaddr58
when csr_pmpaddr59_c => csr.rdata <= csr.pmpaddr_rd(59); -- R/W: pmpaddr59
when csr_pmpaddr60_c => csr.rdata <= csr.pmpaddr_rd(60); -- R/W: pmpaddr60
when csr_pmpaddr61_c => csr.rdata <= csr.pmpaddr_rd(61); -- R/W: pmpaddr61
when csr_pmpaddr62_c => csr.rdata <= csr.pmpaddr_rd(62); -- R/W: pmpaddr62
when csr_pmpaddr63_c => csr.rdata <= csr.pmpaddr_rd(63); -- R/W: pmpaddr63
when csr_pmpaddr0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpaddr(00); else NULL; end if; -- R/W: pmpaddr0
when csr_pmpaddr1_c => if (PMP_NUM_REGIONS > 01) then csr.rdata <= csr.pmpaddr(01); else NULL; end if; -- R/W: pmpaddr1
when csr_pmpaddr2_c => if (PMP_NUM_REGIONS > 02) then csr.rdata <= csr.pmpaddr(02); else NULL; end if; -- R/W: pmpaddr2
when csr_pmpaddr3_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpaddr(03); else NULL; end if; -- R/W: pmpaddr3
when csr_pmpaddr4_c => if (PMP_NUM_REGIONS > 04) then csr.rdata <= csr.pmpaddr(04); else NULL; end if; -- R/W: pmpaddr4
when csr_pmpaddr5_c => if (PMP_NUM_REGIONS > 05) then csr.rdata <= csr.pmpaddr(05); else NULL; end if; -- R/W: pmpaddr5
when csr_pmpaddr6_c => if (PMP_NUM_REGIONS > 06) then csr.rdata <= csr.pmpaddr(06); else NULL; end if; -- R/W: pmpaddr6
when csr_pmpaddr7_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpaddr(07); else NULL; end if; -- R/W: pmpaddr7
when csr_pmpaddr8_c => if (PMP_NUM_REGIONS > 08) then csr.rdata <= csr.pmpaddr(08); else NULL; end if; -- R/W: pmpaddr8
when csr_pmpaddr9_c => if (PMP_NUM_REGIONS > 09) then csr.rdata <= csr.pmpaddr(09); else NULL; end if; -- R/W: pmpaddr9
when csr_pmpaddr10_c => if (PMP_NUM_REGIONS > 10) then csr.rdata <= csr.pmpaddr(10); else NULL; end if; -- R/W: pmpaddr10
when csr_pmpaddr11_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpaddr(11); else NULL; end if; -- R/W: pmpaddr11
when csr_pmpaddr12_c => if (PMP_NUM_REGIONS > 12) then csr.rdata <= csr.pmpaddr(12); else NULL; end if; -- R/W: pmpaddr12
when csr_pmpaddr13_c => if (PMP_NUM_REGIONS > 13) then csr.rdata <= csr.pmpaddr(13); else NULL; end if; -- R/W: pmpaddr13
when csr_pmpaddr14_c => if (PMP_NUM_REGIONS > 14) then csr.rdata <= csr.pmpaddr(14); else NULL; end if; -- R/W: pmpaddr14
when csr_pmpaddr15_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpaddr(15); else NULL; end if; -- R/W: pmpaddr15
when csr_pmpaddr16_c => if (PMP_NUM_REGIONS > 16) then csr.rdata <= csr.pmpaddr(16); else NULL; end if; -- R/W: pmpaddr16
when csr_pmpaddr17_c => if (PMP_NUM_REGIONS > 17) then csr.rdata <= csr.pmpaddr(17); else NULL; end if; -- R/W: pmpaddr17
when csr_pmpaddr18_c => if (PMP_NUM_REGIONS > 18) then csr.rdata <= csr.pmpaddr(18); else NULL; end if; -- R/W: pmpaddr18
when csr_pmpaddr19_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpaddr(19); else NULL; end if; -- R/W: pmpaddr19
when csr_pmpaddr20_c => if (PMP_NUM_REGIONS > 20) then csr.rdata <= csr.pmpaddr(20); else NULL; end if; -- R/W: pmpaddr20
when csr_pmpaddr21_c => if (PMP_NUM_REGIONS > 21) then csr.rdata <= csr.pmpaddr(21); else NULL; end if; -- R/W: pmpaddr21
when csr_pmpaddr22_c => if (PMP_NUM_REGIONS > 22) then csr.rdata <= csr.pmpaddr(22); else NULL; end if; -- R/W: pmpaddr22
when csr_pmpaddr23_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpaddr(23); else NULL; end if; -- R/W: pmpaddr23
when csr_pmpaddr24_c => if (PMP_NUM_REGIONS > 24) then csr.rdata <= csr.pmpaddr(24); else NULL; end if; -- R/W: pmpaddr24
when csr_pmpaddr25_c => if (PMP_NUM_REGIONS > 25) then csr.rdata <= csr.pmpaddr(25); else NULL; end if; -- R/W: pmpaddr25
when csr_pmpaddr26_c => if (PMP_NUM_REGIONS > 26) then csr.rdata <= csr.pmpaddr(26); else NULL; end if; -- R/W: pmpaddr26
when csr_pmpaddr27_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpaddr(27); else NULL; end if; -- R/W: pmpaddr27
when csr_pmpaddr28_c => if (PMP_NUM_REGIONS > 28) then csr.rdata <= csr.pmpaddr(28); else NULL; end if; -- R/W: pmpaddr28
when csr_pmpaddr29_c => if (PMP_NUM_REGIONS > 29) then csr.rdata <= csr.pmpaddr(29); else NULL; end if; -- R/W: pmpaddr29
when csr_pmpaddr30_c => if (PMP_NUM_REGIONS > 30) then csr.rdata <= csr.pmpaddr(30); else NULL; end if; -- R/W: pmpaddr30
when csr_pmpaddr31_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpaddr(31); else NULL; end if; -- R/W: pmpaddr31
when csr_pmpaddr32_c => if (PMP_NUM_REGIONS > 32) then csr.rdata <= csr.pmpaddr(32); else NULL; end if; -- R/W: pmpaddr32
when csr_pmpaddr33_c => if (PMP_NUM_REGIONS > 33) then csr.rdata <= csr.pmpaddr(33); else NULL; end if; -- R/W: pmpaddr33
when csr_pmpaddr34_c => if (PMP_NUM_REGIONS > 34) then csr.rdata <= csr.pmpaddr(34); else NULL; end if; -- R/W: pmpaddr34
when csr_pmpaddr35_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpaddr(35); else NULL; end if; -- R/W: pmpaddr35
when csr_pmpaddr36_c => if (PMP_NUM_REGIONS > 36) then csr.rdata <= csr.pmpaddr(36); else NULL; end if; -- R/W: pmpaddr36
when csr_pmpaddr37_c => if (PMP_NUM_REGIONS > 37) then csr.rdata <= csr.pmpaddr(37); else NULL; end if; -- R/W: pmpaddr37
when csr_pmpaddr38_c => if (PMP_NUM_REGIONS > 38) then csr.rdata <= csr.pmpaddr(38); else NULL; end if; -- R/W: pmpaddr38
when csr_pmpaddr39_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpaddr(39); else NULL; end if; -- R/W: pmpaddr39
when csr_pmpaddr40_c => if (PMP_NUM_REGIONS > 40) then csr.rdata <= csr.pmpaddr(40); else NULL; end if; -- R/W: pmpaddr40
when csr_pmpaddr41_c => if (PMP_NUM_REGIONS > 41) then csr.rdata <= csr.pmpaddr(41); else NULL; end if; -- R/W: pmpaddr41
when csr_pmpaddr42_c => if (PMP_NUM_REGIONS > 42) then csr.rdata <= csr.pmpaddr(42); else NULL; end if; -- R/W: pmpaddr42
when csr_pmpaddr43_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpaddr(43); else NULL; end if; -- R/W: pmpaddr43
when csr_pmpaddr44_c => if (PMP_NUM_REGIONS > 44) then csr.rdata <= csr.pmpaddr(44); else NULL; end if; -- R/W: pmpaddr44
when csr_pmpaddr45_c => if (PMP_NUM_REGIONS > 45) then csr.rdata <= csr.pmpaddr(45); else NULL; end if; -- R/W: pmpaddr45
when csr_pmpaddr46_c => if (PMP_NUM_REGIONS > 46) then csr.rdata <= csr.pmpaddr(46); else NULL; end if; -- R/W: pmpaddr46
when csr_pmpaddr47_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpaddr(47); else NULL; end if; -- R/W: pmpaddr47
when csr_pmpaddr48_c => if (PMP_NUM_REGIONS > 48) then csr.rdata <= csr.pmpaddr(48); else NULL; end if; -- R/W: pmpaddr48
when csr_pmpaddr49_c => if (PMP_NUM_REGIONS > 49) then csr.rdata <= csr.pmpaddr(49); else NULL; end if; -- R/W: pmpaddr49
when csr_pmpaddr50_c => if (PMP_NUM_REGIONS > 50) then csr.rdata <= csr.pmpaddr(50); else NULL; end if; -- R/W: pmpaddr50
when csr_pmpaddr51_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpaddr(51); else NULL; end if; -- R/W: pmpaddr51
when csr_pmpaddr52_c => if (PMP_NUM_REGIONS > 52) then csr.rdata <= csr.pmpaddr(52); else NULL; end if; -- R/W: pmpaddr52
when csr_pmpaddr53_c => if (PMP_NUM_REGIONS > 53) then csr.rdata <= csr.pmpaddr(53); else NULL; end if; -- R/W: pmpaddr53
when csr_pmpaddr54_c => if (PMP_NUM_REGIONS > 54) then csr.rdata <= csr.pmpaddr(54); else NULL; end if; -- R/W: pmpaddr54
when csr_pmpaddr55_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpaddr(55); else NULL; end if; -- R/W: pmpaddr55
when csr_pmpaddr56_c => if (PMP_NUM_REGIONS > 56) then csr.rdata <= csr.pmpaddr(56); else NULL; end if; -- R/W: pmpaddr56
when csr_pmpaddr57_c => if (PMP_NUM_REGIONS > 57) then csr.rdata <= csr.pmpaddr(57); else NULL; end if; -- R/W: pmpaddr57
when csr_pmpaddr58_c => if (PMP_NUM_REGIONS > 58) then csr.rdata <= csr.pmpaddr(58); else NULL; end if; -- R/W: pmpaddr58
when csr_pmpaddr59_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpaddr(59); else NULL; end if; -- R/W: pmpaddr59
when csr_pmpaddr60_c => if (PMP_NUM_REGIONS > 60) then csr.rdata <= csr.pmpaddr(60); else NULL; end if; -- R/W: pmpaddr60
when csr_pmpaddr61_c => if (PMP_NUM_REGIONS > 61) then csr.rdata <= csr.pmpaddr(61); else NULL; end if; -- R/W: pmpaddr61
when csr_pmpaddr62_c => if (PMP_NUM_REGIONS > 62) then csr.rdata <= csr.pmpaddr(62); else NULL; end if; -- R/W: pmpaddr62
when csr_pmpaddr63_c => if (PMP_NUM_REGIONS > 63) then csr.rdata <= csr.pmpaddr(63); else NULL; end if; -- R/W: pmpaddr63
 
-- machine counter setup --
-- --------------------------------------------------------------------
2573,110 → 2573,112
csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
 
-- machine performance-monitoring event selector --
when csr_mhpmevent3_c => csr.rdata(csr.mhpmevent_rd(00)'left downto 0) <= csr.mhpmevent_rd(00); -- R/W: mhpmevent3
when csr_mhpmevent4_c => csr.rdata(csr.mhpmevent_rd(01)'left downto 0) <= csr.mhpmevent_rd(01); -- R/W: mhpmevent4
when csr_mhpmevent5_c => csr.rdata(csr.mhpmevent_rd(02)'left downto 0) <= csr.mhpmevent_rd(02); -- R/W: mhpmevent5
when csr_mhpmevent6_c => csr.rdata(csr.mhpmevent_rd(03)'left downto 0) <= csr.mhpmevent_rd(03); -- R/W: mhpmevent6
when csr_mhpmevent7_c => csr.rdata(csr.mhpmevent_rd(04)'left downto 0) <= csr.mhpmevent_rd(04); -- R/W: mhpmevent7
when csr_mhpmevent8_c => csr.rdata(csr.mhpmevent_rd(05)'left downto 0) <= csr.mhpmevent_rd(05); -- R/W: mhpmevent8
when csr_mhpmevent9_c => csr.rdata(csr.mhpmevent_rd(06)'left downto 0) <= csr.mhpmevent_rd(06); -- R/W: mhpmevent9
when csr_mhpmevent10_c => csr.rdata(csr.mhpmevent_rd(07)'left downto 0) <= csr.mhpmevent_rd(07); -- R/W: mhpmevent10
when csr_mhpmevent11_c => csr.rdata(csr.mhpmevent_rd(08)'left downto 0) <= csr.mhpmevent_rd(08); -- R/W: mhpmevent11
when csr_mhpmevent12_c => csr.rdata(csr.mhpmevent_rd(09)'left downto 0) <= csr.mhpmevent_rd(09); -- R/W: mhpmevent12
when csr_mhpmevent13_c => csr.rdata(csr.mhpmevent_rd(10)'left downto 0) <= csr.mhpmevent_rd(10); -- R/W: mhpmevent13
when csr_mhpmevent14_c => csr.rdata(csr.mhpmevent_rd(11)'left downto 0) <= csr.mhpmevent_rd(11); -- R/W: mhpmevent14
when csr_mhpmevent15_c => csr.rdata(csr.mhpmevent_rd(12)'left downto 0) <= csr.mhpmevent_rd(12); -- R/W: mhpmevent15
when csr_mhpmevent16_c => csr.rdata(csr.mhpmevent_rd(13)'left downto 0) <= csr.mhpmevent_rd(13); -- R/W: mhpmevent16
when csr_mhpmevent17_c => csr.rdata(csr.mhpmevent_rd(14)'left downto 0) <= csr.mhpmevent_rd(14); -- R/W: mhpmevent17
when csr_mhpmevent18_c => csr.rdata(csr.mhpmevent_rd(15)'left downto 0) <= csr.mhpmevent_rd(15); -- R/W: mhpmevent18
when csr_mhpmevent19_c => csr.rdata(csr.mhpmevent_rd(16)'left downto 0) <= csr.mhpmevent_rd(16); -- R/W: mhpmevent19
when csr_mhpmevent20_c => csr.rdata(csr.mhpmevent_rd(17)'left downto 0) <= csr.mhpmevent_rd(17); -- R/W: mhpmevent20
when csr_mhpmevent21_c => csr.rdata(csr.mhpmevent_rd(18)'left downto 0) <= csr.mhpmevent_rd(18); -- R/W: mhpmevent21
when csr_mhpmevent22_c => csr.rdata(csr.mhpmevent_rd(19)'left downto 0) <= csr.mhpmevent_rd(19); -- R/W: mhpmevent22
when csr_mhpmevent23_c => csr.rdata(csr.mhpmevent_rd(20)'left downto 0) <= csr.mhpmevent_rd(20); -- R/W: mhpmevent23
when csr_mhpmevent24_c => csr.rdata(csr.mhpmevent_rd(21)'left downto 0) <= csr.mhpmevent_rd(21); -- R/W: mhpmevent24
when csr_mhpmevent25_c => csr.rdata(csr.mhpmevent_rd(22)'left downto 0) <= csr.mhpmevent_rd(22); -- R/W: mhpmevent25
when csr_mhpmevent26_c => csr.rdata(csr.mhpmevent_rd(23)'left downto 0) <= csr.mhpmevent_rd(23); -- R/W: mhpmevent26
when csr_mhpmevent27_c => csr.rdata(csr.mhpmevent_rd(24)'left downto 0) <= csr.mhpmevent_rd(24); -- R/W: mhpmevent27
when csr_mhpmevent28_c => csr.rdata(csr.mhpmevent_rd(25)'left downto 0) <= csr.mhpmevent_rd(25); -- R/W: mhpmevent28
when csr_mhpmevent29_c => csr.rdata(csr.mhpmevent_rd(26)'left downto 0) <= csr.mhpmevent_rd(26); -- R/W: mhpmevent29
when csr_mhpmevent30_c => csr.rdata(csr.mhpmevent_rd(27)'left downto 0) <= csr.mhpmevent_rd(27); -- R/W: mhpmevent30
when csr_mhpmevent31_c => csr.rdata(csr.mhpmevent_rd(28)'left downto 0) <= csr.mhpmevent_rd(28); -- R/W: mhpmevent31
when csr_mhpmevent3_c => if (HPM_NUM_CNTS > 00) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(00); else NULL; end if; -- R/W: mhpmevent3
when csr_mhpmevent4_c => if (HPM_NUM_CNTS > 01) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(01); else NULL; end if; -- R/W: mhpmevent4
when csr_mhpmevent5_c => if (HPM_NUM_CNTS > 02) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(02); else NULL; end if; -- R/W: mhpmevent5
when csr_mhpmevent6_c => if (HPM_NUM_CNTS > 03) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(03); else NULL; end if; -- R/W: mhpmevent6
when csr_mhpmevent7_c => if (HPM_NUM_CNTS > 04) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(04); else NULL; end if; -- R/W: mhpmevent7
when csr_mhpmevent8_c => if (HPM_NUM_CNTS > 05) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(05); else NULL; end if; -- R/W: mhpmevent8
when csr_mhpmevent9_c => if (HPM_NUM_CNTS > 06) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(06); else NULL; end if; -- R/W: mhpmevent9
when csr_mhpmevent10_c => if (HPM_NUM_CNTS > 07) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(07); else NULL; end if; -- R/W: mhpmevent10
when csr_mhpmevent11_c => if (HPM_NUM_CNTS > 08) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(08); else NULL; end if; -- R/W: mhpmevent11
when csr_mhpmevent12_c => if (HPM_NUM_CNTS > 09) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(09); else NULL; end if; -- R/W: mhpmevent12
when csr_mhpmevent13_c => if (HPM_NUM_CNTS > 10) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(10); else NULL; end if; -- R/W: mhpmevent13
when csr_mhpmevent14_c => if (HPM_NUM_CNTS > 11) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(11); else NULL; end if; -- R/W: mhpmevent14
when csr_mhpmevent15_c => if (HPM_NUM_CNTS > 12) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(12); else NULL; end if; -- R/W: mhpmevent15
when csr_mhpmevent16_c => if (HPM_NUM_CNTS > 13) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(13); else NULL; end if; -- R/W: mhpmevent16
when csr_mhpmevent17_c => if (HPM_NUM_CNTS > 14) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(14); else NULL; end if; -- R/W: mhpmevent17
when csr_mhpmevent18_c => if (HPM_NUM_CNTS > 15) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(15); else NULL; end if; -- R/W: mhpmevent18
when csr_mhpmevent19_c => if (HPM_NUM_CNTS > 16) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(16); else NULL; end if; -- R/W: mhpmevent19
when csr_mhpmevent20_c => if (HPM_NUM_CNTS > 17) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(17); else NULL; end if; -- R/W: mhpmevent20
when csr_mhpmevent21_c => if (HPM_NUM_CNTS > 18) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(18); else NULL; end if; -- R/W: mhpmevent21
when csr_mhpmevent22_c => if (HPM_NUM_CNTS > 19) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(19); else NULL; end if; -- R/W: mhpmevent22
when csr_mhpmevent23_c => if (HPM_NUM_CNTS > 20) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(20); else NULL; end if; -- R/W: mhpmevent23
when csr_mhpmevent24_c => if (HPM_NUM_CNTS > 21) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(21); else NULL; end if; -- R/W: mhpmevent24
when csr_mhpmevent25_c => if (HPM_NUM_CNTS > 22) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(22); else NULL; end if; -- R/W: mhpmevent25
when csr_mhpmevent26_c => if (HPM_NUM_CNTS > 23) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(23); else NULL; end if; -- R/W: mhpmevent26
when csr_mhpmevent27_c => if (HPM_NUM_CNTS > 24) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(24); else NULL; end if; -- R/W: mhpmevent27
when csr_mhpmevent28_c => if (HPM_NUM_CNTS > 25) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(25); else NULL; end if; -- R/W: mhpmevent28
when csr_mhpmevent29_c => if (HPM_NUM_CNTS > 26) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(26); else NULL; end if; -- R/W: mhpmevent29
when csr_mhpmevent30_c => if (HPM_NUM_CNTS > 27) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(27); else NULL; end if; -- R/W: mhpmevent30
when csr_mhpmevent31_c => if (HPM_NUM_CNTS > 28) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(28); else NULL; end if; -- R/W: mhpmevent31
 
-- counters and timers --
when csr_cycle_c | csr_mcycle_c => -- (R)/(W): [m]cycle: Cycle counter LOW
csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0);
if (cpu_cnt_lo_width_c > 0) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
if (cpu_cnt_hi_width_c > 0) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
 
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
if (cpu_cnt_lo_width_c > 0) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
if (cpu_cnt_hi_width_c > 0) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
 
when csr_time_c => -- (R)/-: time: System time LOW (from MTIME unit)
csr.rdata <= time_i(31 downto 0);
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0);
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0);
when csr_timeh_c => -- (R)/-: timeh: System time HIGH (from MTIME unit)
csr.rdata <= time_i(63 downto 32);
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0);
 
-- hardware performance counters --
when csr_hpmcounter3_c | csr_mhpmcounter3_c => csr.rdata <= csr.mhpmcounter_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3 - low
when csr_hpmcounter4_c | csr_mhpmcounter4_c => csr.rdata <= csr.mhpmcounter_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4 - low
when csr_hpmcounter5_c | csr_mhpmcounter5_c => csr.rdata <= csr.mhpmcounter_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5 - low
when csr_hpmcounter6_c | csr_mhpmcounter6_c => csr.rdata <= csr.mhpmcounter_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6 - low
when csr_hpmcounter7_c | csr_mhpmcounter7_c => csr.rdata <= csr.mhpmcounter_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7 - low
when csr_hpmcounter8_c | csr_mhpmcounter8_c => csr.rdata <= csr.mhpmcounter_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8 - low
when csr_hpmcounter9_c | csr_mhpmcounter9_c => csr.rdata <= csr.mhpmcounter_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9 - low
when csr_hpmcounter10_c | csr_mhpmcounter10_c => csr.rdata <= csr.mhpmcounter_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10 - low
when csr_hpmcounter11_c | csr_mhpmcounter11_c => csr.rdata <= csr.mhpmcounter_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11 - low
when csr_hpmcounter12_c | csr_mhpmcounter12_c => csr.rdata <= csr.mhpmcounter_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12 - low
when csr_hpmcounter13_c | csr_mhpmcounter13_c => csr.rdata <= csr.mhpmcounter_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13 - low
when csr_hpmcounter14_c | csr_mhpmcounter14_c => csr.rdata <= csr.mhpmcounter_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14 - low
when csr_hpmcounter15_c | csr_mhpmcounter15_c => csr.rdata <= csr.mhpmcounter_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15 - low
when csr_hpmcounter16_c | csr_mhpmcounter16_c => csr.rdata <= csr.mhpmcounter_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16 - low
when csr_hpmcounter17_c | csr_mhpmcounter17_c => csr.rdata <= csr.mhpmcounter_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17 - low
when csr_hpmcounter18_c | csr_mhpmcounter18_c => csr.rdata <= csr.mhpmcounter_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18 - low
when csr_hpmcounter19_c | csr_mhpmcounter19_c => csr.rdata <= csr.mhpmcounter_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19 - low
when csr_hpmcounter20_c | csr_mhpmcounter20_c => csr.rdata <= csr.mhpmcounter_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20 - low
when csr_hpmcounter21_c | csr_mhpmcounter21_c => csr.rdata <= csr.mhpmcounter_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21 - low
when csr_hpmcounter22_c | csr_mhpmcounter22_c => csr.rdata <= csr.mhpmcounter_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22 - low
when csr_hpmcounter23_c | csr_mhpmcounter23_c => csr.rdata <= csr.mhpmcounter_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23 - low
when csr_hpmcounter24_c | csr_mhpmcounter24_c => csr.rdata <= csr.mhpmcounter_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24 - low
when csr_hpmcounter25_c | csr_mhpmcounter25_c => csr.rdata <= csr.mhpmcounter_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25 - low
when csr_hpmcounter26_c | csr_mhpmcounter26_c => csr.rdata <= csr.mhpmcounter_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26 - low
when csr_hpmcounter27_c | csr_mhpmcounter27_c => csr.rdata <= csr.mhpmcounter_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27 - low
when csr_hpmcounter28_c | csr_mhpmcounter28_c => csr.rdata <= csr.mhpmcounter_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28 - low
when csr_hpmcounter29_c | csr_mhpmcounter29_c => csr.rdata <= csr.mhpmcounter_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29 - low
when csr_hpmcounter30_c | csr_mhpmcounter30_c => csr.rdata <= csr.mhpmcounter_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30 - low
when csr_hpmcounter31_c | csr_mhpmcounter31_c => csr.rdata <= csr.mhpmcounter_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31 - low
when csr_hpmcounter3_c | csr_mhpmcounter3_c => if (HPM_NUM_CNTS > 00) then csr.rdata <= csr.mhpmcounter_rd(00); else NULL; end if; -- (R)/(W): [m]hpmcounter3 - low
when csr_hpmcounter4_c | csr_mhpmcounter4_c => if (HPM_NUM_CNTS > 01) then csr.rdata <= csr.mhpmcounter_rd(01); else NULL; end if; -- (R)/(W): [m]hpmcounter4 - low
when csr_hpmcounter5_c | csr_mhpmcounter5_c => if (HPM_NUM_CNTS > 02) then csr.rdata <= csr.mhpmcounter_rd(02); else NULL; end if; -- (R)/(W): [m]hpmcounter5 - low
when csr_hpmcounter6_c | csr_mhpmcounter6_c => if (HPM_NUM_CNTS > 03) then csr.rdata <= csr.mhpmcounter_rd(03); else NULL; end if; -- (R)/(W): [m]hpmcounter6 - low
when csr_hpmcounter7_c | csr_mhpmcounter7_c => if (HPM_NUM_CNTS > 04) then csr.rdata <= csr.mhpmcounter_rd(04); else NULL; end if; -- (R)/(W): [m]hpmcounter7 - low
when csr_hpmcounter8_c | csr_mhpmcounter8_c => if (HPM_NUM_CNTS > 05) then csr.rdata <= csr.mhpmcounter_rd(05); else NULL; end if; -- (R)/(W): [m]hpmcounter8 - low
when csr_hpmcounter9_c | csr_mhpmcounter9_c => if (HPM_NUM_CNTS > 06) then csr.rdata <= csr.mhpmcounter_rd(06); else NULL; end if; -- (R)/(W): [m]hpmcounter9 - low
when csr_hpmcounter10_c | csr_mhpmcounter10_c => if (HPM_NUM_CNTS > 07) then csr.rdata <= csr.mhpmcounter_rd(07); else NULL; end if; -- (R)/(W): [m]hpmcounter10 - low
when csr_hpmcounter11_c | csr_mhpmcounter11_c => if (HPM_NUM_CNTS > 08) then csr.rdata <= csr.mhpmcounter_rd(08); else NULL; end if; -- (R)/(W): [m]hpmcounter11 - low
when csr_hpmcounter12_c | csr_mhpmcounter12_c => if (HPM_NUM_CNTS > 09) then csr.rdata <= csr.mhpmcounter_rd(09); else NULL; end if; -- (R)/(W): [m]hpmcounter12 - low
when csr_hpmcounter13_c | csr_mhpmcounter13_c => if (HPM_NUM_CNTS > 10) then csr.rdata <= csr.mhpmcounter_rd(10); else NULL; end if; -- (R)/(W): [m]hpmcounter13 - low
when csr_hpmcounter14_c | csr_mhpmcounter14_c => if (HPM_NUM_CNTS > 11) then csr.rdata <= csr.mhpmcounter_rd(11); else NULL; end if; -- (R)/(W): [m]hpmcounter14 - low
when csr_hpmcounter15_c | csr_mhpmcounter15_c => if (HPM_NUM_CNTS > 12) then csr.rdata <= csr.mhpmcounter_rd(12); else NULL; end if; -- (R)/(W): [m]hpmcounter15 - low
when csr_hpmcounter16_c | csr_mhpmcounter16_c => if (HPM_NUM_CNTS > 13) then csr.rdata <= csr.mhpmcounter_rd(13); else NULL; end if; -- (R)/(W): [m]hpmcounter16 - low
when csr_hpmcounter17_c | csr_mhpmcounter17_c => if (HPM_NUM_CNTS > 14) then csr.rdata <= csr.mhpmcounter_rd(14); else NULL; end if; -- (R)/(W): [m]hpmcounter17 - low
when csr_hpmcounter18_c | csr_mhpmcounter18_c => if (HPM_NUM_CNTS > 15) then csr.rdata <= csr.mhpmcounter_rd(15); else NULL; end if; -- (R)/(W): [m]hpmcounter18 - low
when csr_hpmcounter19_c | csr_mhpmcounter19_c => if (HPM_NUM_CNTS > 16) then csr.rdata <= csr.mhpmcounter_rd(16); else NULL; end if; -- (R)/(W): [m]hpmcounter19 - low
when csr_hpmcounter20_c | csr_mhpmcounter20_c => if (HPM_NUM_CNTS > 17) then csr.rdata <= csr.mhpmcounter_rd(17); else NULL; end if; -- (R)/(W): [m]hpmcounter20 - low
when csr_hpmcounter21_c | csr_mhpmcounter21_c => if (HPM_NUM_CNTS > 18) then csr.rdata <= csr.mhpmcounter_rd(18); else NULL; end if; -- (R)/(W): [m]hpmcounter21 - low
when csr_hpmcounter22_c | csr_mhpmcounter22_c => if (HPM_NUM_CNTS > 19) then csr.rdata <= csr.mhpmcounter_rd(19); else NULL; end if; -- (R)/(W): [m]hpmcounter22 - low
when csr_hpmcounter23_c | csr_mhpmcounter23_c => if (HPM_NUM_CNTS > 20) then csr.rdata <= csr.mhpmcounter_rd(20); else NULL; end if; -- (R)/(W): [m]hpmcounter23 - low
when csr_hpmcounter24_c | csr_mhpmcounter24_c => if (HPM_NUM_CNTS > 21) then csr.rdata <= csr.mhpmcounter_rd(21); else NULL; end if; -- (R)/(W): [m]hpmcounter24 - low
when csr_hpmcounter25_c | csr_mhpmcounter25_c => if (HPM_NUM_CNTS > 22) then csr.rdata <= csr.mhpmcounter_rd(22); else NULL; end if; -- (R)/(W): [m]hpmcounter25 - low
when csr_hpmcounter26_c | csr_mhpmcounter26_c => if (HPM_NUM_CNTS > 23) then csr.rdata <= csr.mhpmcounter_rd(23); else NULL; end if; -- (R)/(W): [m]hpmcounter26 - low
when csr_hpmcounter27_c | csr_mhpmcounter27_c => if (HPM_NUM_CNTS > 24) then csr.rdata <= csr.mhpmcounter_rd(24); else NULL; end if; -- (R)/(W): [m]hpmcounter27 - low
when csr_hpmcounter28_c | csr_mhpmcounter28_c => if (HPM_NUM_CNTS > 25) then csr.rdata <= csr.mhpmcounter_rd(25); else NULL; end if; -- (R)/(W): [m]hpmcounter28 - low
when csr_hpmcounter29_c | csr_mhpmcounter29_c => if (HPM_NUM_CNTS > 26) then csr.rdata <= csr.mhpmcounter_rd(26); else NULL; end if; -- (R)/(W): [m]hpmcounter29 - low
when csr_hpmcounter30_c | csr_mhpmcounter30_c => if (HPM_NUM_CNTS > 27) then csr.rdata <= csr.mhpmcounter_rd(27); else NULL; end if; -- (R)/(W): [m]hpmcounter30 - low
when csr_hpmcounter31_c | csr_mhpmcounter31_c => if (HPM_NUM_CNTS > 28) then csr.rdata <= csr.mhpmcounter_rd(28); else NULL; end if; -- (R)/(W): [m]hpmcounter31 - low
 
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => csr.rdata <= csr.mhpmcounterh_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3h - high
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => csr.rdata <= csr.mhpmcounterh_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4h - high
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => csr.rdata <= csr.mhpmcounterh_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5h - high
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => csr.rdata <= csr.mhpmcounterh_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6h - high
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => csr.rdata <= csr.mhpmcounterh_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7h - high
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => csr.rdata <= csr.mhpmcounterh_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8h - high
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => csr.rdata <= csr.mhpmcounterh_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9h - high
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => csr.rdata <= csr.mhpmcounterh_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10h - high
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => csr.rdata <= csr.mhpmcounterh_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11h - high
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => csr.rdata <= csr.mhpmcounterh_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12h - high
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => csr.rdata <= csr.mhpmcounterh_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13h - high
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => csr.rdata <= csr.mhpmcounterh_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14h - high
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => csr.rdata <= csr.mhpmcounterh_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15h - high
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => csr.rdata <= csr.mhpmcounterh_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16h - high
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => csr.rdata <= csr.mhpmcounterh_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17h - high
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => csr.rdata <= csr.mhpmcounterh_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18h - high
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => csr.rdata <= csr.mhpmcounterh_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19h - high
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => csr.rdata <= csr.mhpmcounterh_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20h - high
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => csr.rdata <= csr.mhpmcounterh_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21h - high
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => csr.rdata <= csr.mhpmcounterh_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22h - high
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => csr.rdata <= csr.mhpmcounterh_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23h - high
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => csr.rdata <= csr.mhpmcounterh_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24h - high
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => csr.rdata <= csr.mhpmcounterh_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25h - high
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => csr.rdata <= csr.mhpmcounterh_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26h - high
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => csr.rdata <= csr.mhpmcounterh_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27h - high
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => csr.rdata <= csr.mhpmcounterh_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28h - high
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => csr.rdata <= csr.mhpmcounterh_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29h - high
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => csr.rdata <= csr.mhpmcounterh_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30h - high
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => csr.rdata <= csr.mhpmcounterh_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31h - high
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => if (HPM_NUM_CNTS > 00) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(00); else NULL; end if; -- (R)/(W): [m]hpmcounter3h - high
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => if (HPM_NUM_CNTS > 01) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(01); else NULL; end if; -- (R)/(W): [m]hpmcounter4h - high
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => if (HPM_NUM_CNTS > 02) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(02); else NULL; end if; -- (R)/(W): [m]hpmcounter5h - high
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => if (HPM_NUM_CNTS > 03) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(03); else NULL; end if; -- (R)/(W): [m]hpmcounter6h - high
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => if (HPM_NUM_CNTS > 04) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(04); else NULL; end if; -- (R)/(W): [m]hpmcounter7h - high
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => if (HPM_NUM_CNTS > 05) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(05); else NULL; end if; -- (R)/(W): [m]hpmcounter8h - high
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => if (HPM_NUM_CNTS > 06) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(06); else NULL; end if; -- (R)/(W): [m]hpmcounter9h - high
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => if (HPM_NUM_CNTS > 07) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(07); else NULL; end if; -- (R)/(W): [m]hpmcounter10h - high
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => if (HPM_NUM_CNTS > 08) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(08); else NULL; end if; -- (R)/(W): [m]hpmcounter11h - high
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => if (HPM_NUM_CNTS > 09) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(09); else NULL; end if; -- (R)/(W): [m]hpmcounter12h - high
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => if (HPM_NUM_CNTS > 10) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(10); else NULL; end if; -- (R)/(W): [m]hpmcounter13h - high
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => if (HPM_NUM_CNTS > 11) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(11); else NULL; end if; -- (R)/(W): [m]hpmcounter14h - high
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => if (HPM_NUM_CNTS > 12) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(12); else NULL; end if; -- (R)/(W): [m]hpmcounter15h - high
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => if (HPM_NUM_CNTS > 13) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(13); else NULL; end if; -- (R)/(W): [m]hpmcounter16h - high
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => if (HPM_NUM_CNTS > 14) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(14); else NULL; end if; -- (R)/(W): [m]hpmcounter17h - high
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => if (HPM_NUM_CNTS > 15) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(15); else NULL; end if; -- (R)/(W): [m]hpmcounter18h - high
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => if (HPM_NUM_CNTS > 16) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(16); else NULL; end if; -- (R)/(W): [m]hpmcounter19h - high
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => if (HPM_NUM_CNTS > 17) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(17); else NULL; end if; -- (R)/(W): [m]hpmcounter20h - high
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => if (HPM_NUM_CNTS > 18) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(18); else NULL; end if; -- (R)/(W): [m]hpmcounter21h - high
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => if (HPM_NUM_CNTS > 19) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(19); else NULL; end if; -- (R)/(W): [m]hpmcounter22h - high
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => if (HPM_NUM_CNTS > 20) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(20); else NULL; end if; -- (R)/(W): [m]hpmcounter23h - high
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => if (HPM_NUM_CNTS > 21) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(21); else NULL; end if; -- (R)/(W): [m]hpmcounter24h - high
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => if (HPM_NUM_CNTS > 22) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(22); else NULL; end if; -- (R)/(W): [m]hpmcounter25h - high
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => if (HPM_NUM_CNTS > 23) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(23); else NULL; end if; -- (R)/(W): [m]hpmcounter26h - high
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => if (HPM_NUM_CNTS > 24) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(24); else NULL; end if; -- (R)/(W): [m]hpmcounter27h - high
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => if (HPM_NUM_CNTS > 25) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(25); else NULL; end if; -- (R)/(W): [m]hpmcounter28h - high
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => if (HPM_NUM_CNTS > 26) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(26); else NULL; end if; -- (R)/(W): [m]hpmcounter29h - high
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => if (HPM_NUM_CNTS > 27) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(27); else NULL; end if; -- (R)/(W): [m]hpmcounter30h - high
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => if (HPM_NUM_CNTS > 28) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(28); else NULL; end if; -- (R)/(W): [m]hpmcounter31h - high
 
-- machine information registers --
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
2706,10 → 2708,12
csr.rdata(6) <= '1'; -- Zxscnt (custom)
csr.rdata(7) <= '0'; -- Zxnocnt (custom)
end if;
csr.rdata(8) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP (physical memory protection)
csr.rdata(9) <= bool_to_ulogic_f(boolean(HPM_NUM_CNTS > 0)); -- HPM (hardware performance monitors)
 
-- undefined/unavailable --
when others =>
csr.rdata <= (others => '0'); -- not implemented
NULL; -- not implemented
 
end case;
end if;
/neorv32_cpu_decompressor.vhd
81,7 → 81,7
ci_illegal_o <= '0';
ci_instr32_o <= (others => '0');
 
-- 22-bit sign-extended immediate for J/JAL --
-- helper: 22-bit sign-extended immediate for J/JAL --
imm20_v := (others => ci_instr16_i(12)); -- sign extension
imm20_v(00):= '0';
imm20_v(01):= ci_instr16_i(3);
96,7 → 96,7
imm20_v(10):= ci_instr16_i(8);
imm20_v(11):= ci_instr16_i(12);
 
-- 12-bit sign-extended immediate for branches --
-- helper: 12-bit sign-extended immediate for branches --
imm12_v := (others => ci_instr16_i(12)); -- sign extension
imm12_v(00):= '0';
imm12_v(01):= ci_instr16_i(3);
/neorv32_cpu_regfile.vhd
121,10 → 121,8
-- valid RF write access? --
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
 
-- destination address --
-- access addresses --
dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
 
-- access addresses --
opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
 
/neorv32_package.vhd
83,7 → 83,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050408"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050500"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
171,7 → 171,7
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
 
-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) --
constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
constant uart0_size_c : natural := 2*4; -- module's address space in bytes
constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
203,7 → 203,7
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
 
-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
constant uart1_size_c : natural := 2*4; -- module's address space in bytes
constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
233,11 → 233,11
constant ctrl_rf_rs2_adr2_c : natural := 8; -- source register 2 address bit 2
constant ctrl_rf_rs2_adr3_c : natural := 9; -- source register 2 address bit 3
constant ctrl_rf_rs2_adr4_c : natural := 10; -- source register 2 address bit 4
constant ctrl_rf_rd_adr0_c : natural := 11; -- destiantion register address bit 0
constant ctrl_rf_rd_adr1_c : natural := 12; -- destiantion register address bit 1
constant ctrl_rf_rd_adr2_c : natural := 13; -- destiantion register address bit 2
constant ctrl_rf_rd_adr3_c : natural := 14; -- destiantion register address bit 3
constant ctrl_rf_rd_adr4_c : natural := 15; -- destiantion register address bit 4
constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
constant ctrl_rf_r0_we_c : natural := 17; -- force write access and force rd=r0
-- alu --
581,6 → 581,12
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
---- debug mode registers --
--constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
--constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
--constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
--constant csr_dsratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
--constant csr_dsratch1_c : std_ulogic_vector(11 downto 0) := x"7b3";
-- machine counters/timers --
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
766,6 → 772,7
constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
-- RISC-V compliant interrupts (async. exceptions) --
constant trap_nmi_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: non-maskable interrupt
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
803,27 → 810,28
--
constant exception_width_c : natural := 10; -- length of this list in bits
-- interrupt source bits --
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7
constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8
constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9
constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10
constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11
constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12
constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13
constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14
constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15
constant interrupt_nm_irq_c : natural := 0; -- non-maskable interrupt
constant interrupt_msw_irq_c : natural := 1; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 2; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 3; -- machine external interrupt
constant interrupt_firq_0_c : natural := 4; -- fast interrupt channel 0
constant interrupt_firq_1_c : natural := 5; -- fast interrupt channel 1
constant interrupt_firq_2_c : natural := 6; -- fast interrupt channel 2
constant interrupt_firq_3_c : natural := 7; -- fast interrupt channel 3
constant interrupt_firq_4_c : natural := 8; -- fast interrupt channel 4
constant interrupt_firq_5_c : natural := 9; -- fast interrupt channel 5
constant interrupt_firq_6_c : natural := 10; -- fast interrupt channel 6
constant interrupt_firq_7_c : natural := 11; -- fast interrupt channel 7
constant interrupt_firq_8_c : natural := 12; -- fast interrupt channel 8
constant interrupt_firq_9_c : natural := 13; -- fast interrupt channel 9
constant interrupt_firq_10_c : natural := 14; -- fast interrupt channel 10
constant interrupt_firq_11_c : natural := 15; -- fast interrupt channel 11
constant interrupt_firq_12_c : natural := 16; -- fast interrupt channel 12
constant interrupt_firq_13_c : natural := 17; -- fast interrupt channel 13
constant interrupt_firq_14_c : natural := 18; -- fast interrupt channel 14
constant interrupt_firq_15_c : natural := 19; -- fast interrupt channel 15
--
constant interrupt_width_c : natural := 19; -- length of this list in bits
constant interrupt_width_c : natural := 20; -- length of this list in bits
 
-- CPU Privilege Modes --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
975,6 → 983,7
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- Interrupts --
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
1042,6 → 1051,8
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
-- non-maskable interrupt --
nm_irq_i : in std_ulogic := '0'; -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
1101,6 → 1112,8
-- FPU interface --
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
-- non-maskable interrupt --
nm_irq_i : in std_ulogic;
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
/neorv32_top.vhd
179,6 → 179,7
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
 
-- Interrupts --
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
455,6 → 456,8
d_bus_priv_o => cpu_d.priv, -- privilege level
-- system time input from MTIME --
time_i => mtime_time, -- current system time
-- non-maskable interrupt --
nm_irq_i => nm_irq_i, -- NMI
-- interrupts (risc-v compliant) --
msw_irq_i => msw_irq_i, -- machine software interrupt
mext_irq_i => mext_irq_i, -- machine external interrupt request
485,12 → 488,17
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
 
-- fast interrupts - platform level (for custom use) --
fast_irq(10) <= soc_firq_i(0);
fast_irq(11) <= soc_firq_i(1);
fast_irq(12) <= soc_firq_i(2);
fast_irq(13) <= soc_firq_i(3);
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
soc_firq_sync: process(clk_i)
begin
if rising_edge(clk_i) then -- make sure they are sync
fast_irq(10) <= soc_firq_i(0);
fast_irq(11) <= soc_firq_i(1);
fast_irq(12) <= soc_firq_i(2);
fast_irq(13) <= soc_firq_i(3);
fast_irq(14) <= soc_firq_i(4);
fast_irq(15) <= soc_firq_i(5);
end if;
end process soc_firq_sync;
 
-- CFS IRQ acknowledge --
cfs_irq_ack <= fast_irq_ack(1);

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