OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 59 to Rev 60
    ↔ Reverse comparison
  •

Rev 59 → Rev 60

/neorv32_cpu_cp_bitmanip.vhd File deleted
/neorv32_application_image.vhd
1,4 → 1,4
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
 
library ieee;
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1066) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1062) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000013",
00000001 => x"00000093",
25,7 → 25,7
00000014 => x"80000197",
00000015 => x"7c818193",
00000016 => x"00000517",
00000017 => x"10050513",
00000017 => x"0fc50513",
00000018 => x"30551073",
00000019 => x"34151073",
00000020 => x"34301073",
56,7 → 56,7
00000045 => x"00000f13",
00000046 => x"00000f93",
00000047 => x"00000417",
00000048 => x"e4440413",
00000048 => x"d4440413",
00000049 => x"00000497",
00000050 => x"f3c48493",
00000051 => x"00042023",
70,7 → 70,7
00000059 => x"00158593",
00000060 => x"ff5ff06f",
00000061 => x"00001597",
00000062 => x"fb458593",
00000062 => x"fa458593",
00000063 => x"80000617",
00000064 => x"f0460613",
00000065 => x"80000697",
83,997 → 83,993
00000072 => x"fedff06f",
00000073 => x"00000513",
00000074 => x"00000593",
00000075 => x"060000ef",
00000075 => x"05c000ef",
00000076 => x"30047073",
00000077 => x"00000013",
00000078 => x"10500073",
00000079 => x"0000006f",
00000080 => x"ff810113",
00000081 => x"00812023",
00000082 => x"00912223",
00000083 => x"34202473",
00000084 => x"02044663",
00000085 => x"34102473",
00000086 => x"00041483",
00000087 => x"0034f493",
00000088 => x"00240413",
00000089 => x"34141073",
00000090 => x"00300413",
00000091 => x"00941863",
00000092 => x"34102473",
00000093 => x"00240413",
00000094 => x"34141073",
00000095 => x"00012403",
00000096 => x"00412483",
00000097 => x"00810113",
00000098 => x"30200073",
00000099 => x"00005537",
00000100 => x"ff010113",
00000101 => x"00000613",
00000102 => x"00000593",
00000103 => x"b0050513",
00000104 => x"00112623",
00000105 => x"248000ef",
00000106 => x"1e5000ef",
00000107 => x"02050063",
00000108 => x"135000ef",
00000109 => x"00000513",
00000110 => x"189000ef",
00000111 => x"00001537",
00000112 => x"d3050513",
00000113 => x"298000ef",
00000114 => x"020000ef",
00000115 => x"00001537",
00000116 => x"d0c50513",
00000117 => x"288000ef",
00000118 => x"00c12083",
00000119 => x"00000513",
00000120 => x"01010113",
00000121 => x"00008067",
00000122 => x"ff010113",
00000123 => x"00000513",
00000124 => x"00812423",
00000125 => x"00112623",
00000126 => x"00000413",
00000127 => x"1a1000ef",
00000128 => x"0ff47513",
00000129 => x"199000ef",
00000130 => x"0c800513",
00000131 => x"420000ef",
00000132 => x"00140413",
00000133 => x"fedff06f",
00000134 => x"fd010113",
00000135 => x"02812423",
00000136 => x"02912223",
00000137 => x"03212023",
00000138 => x"01312e23",
00000139 => x"01412c23",
00000140 => x"02112623",
00000141 => x"01512a23",
00000142 => x"00001a37",
00000143 => x"00050493",
00000144 => x"00058413",
00000145 => x"00058523",
00000146 => x"00000993",
00000147 => x"00410913",
00000148 => x"d4ca0a13",
00000149 => x"00a00593",
00000150 => x"00048513",
00000151 => x"24d000ef",
00000152 => x"00aa0533",
00000153 => x"00054783",
00000154 => x"01390ab3",
00000155 => x"00048513",
00000156 => x"00fa8023",
00000157 => x"00a00593",
00000158 => x"1e9000ef",
00000159 => x"00198993",
00000160 => x"00a00793",
00000161 => x"00050493",
00000162 => x"fcf996e3",
00000163 => x"00090693",
00000164 => x"00900713",
00000165 => x"03000613",
00000166 => x"0096c583",
00000167 => x"00070793",
00000168 => x"fff70713",
00000169 => x"01071713",
00000170 => x"01075713",
00000171 => x"00c59a63",
00000172 => x"000684a3",
00000173 => x"fff68693",
00000174 => x"fe0710e3",
00000175 => x"00000793",
00000176 => x"00f907b3",
00000177 => x"00000593",
00000178 => x"0007c703",
00000179 => x"00070c63",
00000180 => x"00158693",
00000181 => x"00b405b3",
00000182 => x"00e58023",
00000183 => x"01069593",
00000184 => x"0105d593",
00000185 => x"fff78713",
00000186 => x"02f91863",
00000187 => x"00b40433",
00000188 => x"00040023",
00000189 => x"02c12083",
00000190 => x"02812403",
00000191 => x"02412483",
00000192 => x"02012903",
00000193 => x"01c12983",
00000194 => x"01812a03",
00000195 => x"01412a83",
00000196 => x"03010113",
00000197 => x"00008067",
00000198 => x"00070793",
00000199 => x"fadff06f",
00000200 => x"00001637",
00000201 => x"00758693",
00000202 => x"00000713",
00000203 => x"d5860613",
00000204 => x"02000813",
00000205 => x"00e557b3",
00000206 => x"00f7f793",
00000207 => x"00f607b3",
00000208 => x"0007c783",
00000209 => x"00470713",
00000210 => x"fff68693",
00000211 => x"00f680a3",
00000212 => x"ff0712e3",
00000213 => x"00058423",
00000214 => x"00008067",
00000215 => x"fa002023",
00000216 => x"fe002703",
00000217 => x"00151513",
00000218 => x"00000793",
00000219 => x"04a77463",
00000220 => x"000016b7",
00000221 => x"00000713",
00000222 => x"ffe68693",
00000223 => x"04f6e663",
00000224 => x"00367613",
00000225 => x"0035f593",
00000226 => x"fff78793",
00000227 => x"01461613",
00000228 => x"00c7e7b3",
00000229 => x"01659593",
00000230 => x"01871713",
00000231 => x"00b7e7b3",
00000232 => x"00e7e7b3",
00000233 => x"10000737",
00000234 => x"00e7e7b3",
00000235 => x"faf02023",
00000236 => x"00008067",
00000237 => x"00178793",
00000238 => x"01079793",
00000239 => x"40a70733",
00000240 => x"0107d793",
00000241 => x"fa9ff06f",
00000242 => x"ffe70513",
00000243 => x"0fd57513",
00000244 => x"00051a63",
00000245 => x"0037d793",
00000246 => x"00170713",
00000247 => x"0ff77713",
00000248 => x"f9dff06f",
00000249 => x"0017d793",
00000250 => x"ff1ff06f",
00000251 => x"f71ff06f",
00000252 => x"fa002783",
00000253 => x"fe07cee3",
00000254 => x"faa02223",
00000255 => x"00008067",
00000256 => x"ff1ff06f",
00000257 => x"ff010113",
00000258 => x"00812423",
00000259 => x"01212023",
00000260 => x"00112623",
00000261 => x"00912223",
00000262 => x"00050413",
00000263 => x"00a00913",
00000264 => x"00044483",
00000265 => x"00140413",
00000266 => x"00049e63",
00000267 => x"00c12083",
00000268 => x"00812403",
00000269 => x"00412483",
00000270 => x"00012903",
00000271 => x"01010113",
00000272 => x"00008067",
00000273 => x"01249663",
00000274 => x"00d00513",
00000275 => x"fa5ff0ef",
00000276 => x"00048513",
00000277 => x"f9dff0ef",
00000278 => x"fc9ff06f",
00000279 => x"fa9ff06f",
00000280 => x"fa010113",
00000281 => x"04f12a23",
00000282 => x"04410793",
00000283 => x"02812c23",
00000284 => x"03212823",
00000285 => x"03412423",
00000286 => x"03512223",
00000287 => x"03612023",
00000288 => x"01712e23",
00000289 => x"01812c23",
00000290 => x"01912a23",
00000291 => x"02112e23",
00000292 => x"02912a23",
00000293 => x"03312623",
00000294 => x"00050413",
00000295 => x"04b12223",
00000296 => x"04c12423",
00000297 => x"04d12623",
00000298 => x"04e12823",
00000299 => x"05012c23",
00000300 => x"05112e23",
00000301 => x"00f12023",
00000302 => x"02500a13",
00000303 => x"00a00a93",
00000304 => x"07300913",
00000305 => x"07500b13",
00000306 => x"07800b93",
00000307 => x"06300c13",
00000308 => x"06900c93",
00000309 => x"00044483",
00000310 => x"02049c63",
00000311 => x"03c12083",
00000312 => x"03812403",
00000313 => x"03412483",
00000314 => x"03012903",
00000315 => x"02c12983",
00000316 => x"02812a03",
00000317 => x"02412a83",
00000318 => x"02012b03",
00000319 => x"01c12b83",
00000320 => x"01812c03",
00000321 => x"01412c83",
00000322 => x"06010113",
00000323 => x"00008067",
00000324 => x"0d449863",
00000325 => x"00240993",
00000326 => x"00144403",
00000327 => x"05240263",
00000328 => x"00896e63",
00000329 => x"05840c63",
00000330 => x"07940663",
00000331 => x"02500513",
00000332 => x"ec1ff0ef",
00000333 => x"00040513",
00000334 => x"0540006f",
00000335 => x"09640663",
00000336 => x"ff7416e3",
00000337 => x"00012783",
00000338 => x"00410593",
00000339 => x"0007a503",
00000340 => x"00478713",
00000341 => x"00e12023",
00000342 => x"dc9ff0ef",
00000343 => x"0640006f",
00000344 => x"00012783",
00000345 => x"0007a503",
00000346 => x"00478713",
00000347 => x"00e12023",
00000348 => x"e95ff0ef",
00000349 => x"00098413",
00000350 => x"f5dff06f",
00000351 => x"00012783",
00000352 => x"0007c503",
00000353 => x"00478713",
00000354 => x"00e12023",
00000355 => x"e65ff0ef",
00000356 => x"fe5ff06f",
00000357 => x"00012783",
00000358 => x"0007a403",
00000359 => x"00478713",
00000360 => x"00e12023",
00000361 => x"00045863",
00000362 => x"02d00513",
00000363 => x"40800433",
00000364 => x"e41ff0ef",
00000365 => x"00410593",
00000366 => x"00040513",
00000367 => x"c5dff0ef",
00000368 => x"00410513",
00000369 => x"fadff06f",
00000370 => x"00012783",
00000371 => x"00410593",
00000372 => x"00478713",
00000373 => x"0007a503",
00000374 => x"00e12023",
00000375 => x"fe1ff06f",
00000376 => x"01549663",
00000377 => x"00d00513",
00000378 => x"e09ff0ef",
00000379 => x"00140993",
00000380 => x"00048513",
00000381 => x"f99ff06f",
00000382 => x"fd010113",
00000383 => x"00112623",
00000384 => x"00b12a23",
00000385 => x"00c12c23",
00000386 => x"00d12e23",
00000387 => x"02e12023",
00000388 => x"02f12223",
00000389 => x"03012423",
00000390 => x"03112623",
00000391 => x"e45ff0ef",
00000392 => x"00c12083",
00000393 => x"03010113",
00000394 => x"00008067",
00000395 => x"fe010113",
00000396 => x"00112e23",
00000397 => x"00050613",
00000398 => x"00055863",
00000399 => x"40a00633",
00000400 => x"01061613",
00000401 => x"41065613",
00000402 => x"fe002503",
00000403 => x"3e800593",
00000404 => x"00c12623",
00000405 => x"60c000ef",
00000406 => x"00c12603",
00000407 => x"00000593",
00000408 => x"41f65693",
00000409 => x"564000ef",
00000410 => x"01c59593",
00000411 => x"00455513",
00000412 => x"00a5e533",
00000413 => x"00050a63",
00000414 => x"00050863",
00000415 => x"fff50513",
00000416 => x"00000013",
00000417 => x"ff1ff06f",
00000418 => x"01c12083",
00000419 => x"02010113",
00000420 => x"00008067",
00000421 => x"00000000",
00000422 => x"00000000",
00000423 => x"00000000",
00000424 => x"fc010113",
00000425 => x"02112e23",
00000426 => x"02512c23",
00000427 => x"02612a23",
00000428 => x"02712823",
00000429 => x"02a12623",
00000430 => x"02b12423",
00000431 => x"02c12223",
00000432 => x"02d12023",
00000433 => x"00e12e23",
00000434 => x"00f12c23",
00000435 => x"01012a23",
00000436 => x"01112823",
00000437 => x"01c12623",
00000438 => x"01d12423",
00000439 => x"01e12223",
00000440 => x"01f12023",
00000441 => x"34102773",
00000442 => x"34071073",
00000443 => x"342027f3",
00000444 => x"0807ca63",
00000445 => x"00071683",
00000446 => x"00300593",
00000447 => x"0036f693",
00000448 => x"00270613",
00000449 => x"00b69463",
00000450 => x"00470613",
00000451 => x"34161073",
00000452 => x"00b00713",
00000453 => x"04f77c63",
00000454 => x"000017b7",
00000455 => x"91c78793",
00000456 => x"000780e7",
00000457 => x"03c12083",
00000458 => x"03812283",
00000459 => x"03412303",
00000460 => x"03012383",
00000461 => x"02c12503",
00000462 => x"02812583",
00000463 => x"02412603",
00000464 => x"02012683",
00000465 => x"01c12703",
00000466 => x"01812783",
00000467 => x"01412803",
00000468 => x"01012883",
00000469 => x"00c12e03",
00000470 => x"00812e83",
00000471 => x"00412f03",
00000472 => x"00012f83",
00000473 => x"04010113",
00000474 => x"30200073",
00000475 => x"00001737",
00000476 => x"00279793",
00000477 => x"d6c70713",
00000077 => x"10500073",
00000078 => x"ffdff06f",
00000079 => x"ff810113",
00000080 => x"00812023",
00000081 => x"00912223",
00000082 => x"34202473",
00000083 => x"02044663",
00000084 => x"34102473",
00000085 => x"00041483",
00000086 => x"0034f493",
00000087 => x"00240413",
00000088 => x"34141073",
00000089 => x"00300413",
00000090 => x"00941863",
00000091 => x"34102473",
00000092 => x"00240413",
00000093 => x"34141073",
00000094 => x"00012403",
00000095 => x"00412483",
00000096 => x"00810113",
00000097 => x"30200073",
00000098 => x"00005537",
00000099 => x"ff010113",
00000100 => x"00000613",
00000101 => x"00000593",
00000102 => x"b0050513",
00000103 => x"00112623",
00000104 => x"248000ef",
00000105 => x"1d9000ef",
00000106 => x"02050063",
00000107 => x"129000ef",
00000108 => x"00000513",
00000109 => x"17d000ef",
00000110 => x"00001537",
00000111 => x"d2050513",
00000112 => x"298000ef",
00000113 => x"020000ef",
00000114 => x"00001537",
00000115 => x"cfc50513",
00000116 => x"288000ef",
00000117 => x"00c12083",
00000118 => x"00000513",
00000119 => x"01010113",
00000120 => x"00008067",
00000121 => x"ff010113",
00000122 => x"00000513",
00000123 => x"00812423",
00000124 => x"00112623",
00000125 => x"00000413",
00000126 => x"195000ef",
00000127 => x"0ff47513",
00000128 => x"18d000ef",
00000129 => x"0c800513",
00000130 => x"420000ef",
00000131 => x"00140413",
00000132 => x"fedff06f",
00000133 => x"fd010113",
00000134 => x"02812423",
00000135 => x"02912223",
00000136 => x"03212023",
00000137 => x"01312e23",
00000138 => x"01412c23",
00000139 => x"02112623",
00000140 => x"01512a23",
00000141 => x"00001a37",
00000142 => x"00050493",
00000143 => x"00058413",
00000144 => x"00058523",
00000145 => x"00000993",
00000146 => x"00410913",
00000147 => x"d3ca0a13",
00000148 => x"00a00593",
00000149 => x"00048513",
00000150 => x"241000ef",
00000151 => x"00aa0533",
00000152 => x"00054783",
00000153 => x"01390ab3",
00000154 => x"00048513",
00000155 => x"00fa8023",
00000156 => x"00a00593",
00000157 => x"1dd000ef",
00000158 => x"00198993",
00000159 => x"00a00793",
00000160 => x"00050493",
00000161 => x"fcf996e3",
00000162 => x"00090693",
00000163 => x"00900713",
00000164 => x"03000613",
00000165 => x"0096c583",
00000166 => x"00070793",
00000167 => x"fff70713",
00000168 => x"01071713",
00000169 => x"01075713",
00000170 => x"00c59a63",
00000171 => x"000684a3",
00000172 => x"fff68693",
00000173 => x"fe0710e3",
00000174 => x"00000793",
00000175 => x"00f907b3",
00000176 => x"00000593",
00000177 => x"0007c703",
00000178 => x"00070c63",
00000179 => x"00158693",
00000180 => x"00b405b3",
00000181 => x"00e58023",
00000182 => x"01069593",
00000183 => x"0105d593",
00000184 => x"fff78713",
00000185 => x"02f91863",
00000186 => x"00b40433",
00000187 => x"00040023",
00000188 => x"02c12083",
00000189 => x"02812403",
00000190 => x"02412483",
00000191 => x"02012903",
00000192 => x"01c12983",
00000193 => x"01812a03",
00000194 => x"01412a83",
00000195 => x"03010113",
00000196 => x"00008067",
00000197 => x"00070793",
00000198 => x"fadff06f",
00000199 => x"00001637",
00000200 => x"00758693",
00000201 => x"00000713",
00000202 => x"d4860613",
00000203 => x"02000813",
00000204 => x"00e557b3",
00000205 => x"00f7f793",
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00000207 => x"0007c783",
00000208 => x"00470713",
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00000215 => x"fe002703",
00000216 => x"00151513",
00000217 => x"00000793",
00000218 => x"04a77463",
00000219 => x"000016b7",
00000220 => x"00000713",
00000221 => x"ffe68693",
00000222 => x"04f6e663",
00000223 => x"00367613",
00000224 => x"0035f593",
00000225 => x"fff78793",
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00000227 => x"00c7e7b3",
00000228 => x"01659593",
00000229 => x"01871713",
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00000236 => x"00178793",
00000237 => x"01079793",
00000238 => x"40a70733",
00000239 => x"0107d793",
00000240 => x"fa9ff06f",
00000241 => x"ffe70513",
00000242 => x"0fd57513",
00000243 => x"00051a63",
00000244 => x"0037d793",
00000245 => x"00170713",
00000246 => x"0ff77713",
00000247 => x"f9dff06f",
00000248 => x"0017d793",
00000249 => x"ff1ff06f",
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00000251 => x"fa002783",
00000252 => x"fe07cee3",
00000253 => x"faa02223",
00000254 => x"00008067",
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00000256 => x"ff010113",
00000257 => x"00812423",
00000258 => x"01212023",
00000259 => x"00112623",
00000260 => x"00912223",
00000261 => x"00050413",
00000262 => x"00a00913",
00000263 => x"00044483",
00000264 => x"00140413",
00000265 => x"00049e63",
00000266 => x"00c12083",
00000267 => x"00812403",
00000268 => x"00412483",
00000269 => x"00012903",
00000270 => x"01010113",
00000271 => x"00008067",
00000272 => x"01249663",
00000273 => x"00d00513",
00000274 => x"fa5ff0ef",
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00000277 => x"fc9ff06f",
00000278 => x"fa9ff06f",
00000279 => x"fa010113",
00000280 => x"04f12a23",
00000281 => x"04410793",
00000282 => x"02812c23",
00000283 => x"03212823",
00000284 => x"03412423",
00000285 => x"03512223",
00000286 => x"03612023",
00000287 => x"01712e23",
00000288 => x"01812c23",
00000289 => x"01912a23",
00000290 => x"02112e23",
00000291 => x"02912a23",
00000292 => x"03312623",
00000293 => x"00050413",
00000294 => x"04b12223",
00000295 => x"04c12423",
00000296 => x"04d12623",
00000297 => x"04e12823",
00000298 => x"05012c23",
00000299 => x"05112e23",
00000300 => x"00f12023",
00000301 => x"02500a13",
00000302 => x"00a00a93",
00000303 => x"07300913",
00000304 => x"07500b13",
00000305 => x"07800b93",
00000306 => x"06300c13",
00000307 => x"06900c93",
00000308 => x"00044483",
00000309 => x"02049c63",
00000310 => x"03c12083",
00000311 => x"03812403",
00000312 => x"03412483",
00000313 => x"03012903",
00000314 => x"02c12983",
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);
 
/neorv32_bootloader_image.vhd
1,4 → 1,4
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin>
 
library ieee;
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1020) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1019) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000013",
00000001 => x"00000093",
25,7 → 25,7
00000014 => x"80010197",
00000015 => x"7c818193",
00000016 => x"00000517",
00000017 => x"0c050513",
00000017 => x"0bc50513",
00000018 => x"30551073",
00000019 => x"34151073",
00000020 => x"34301073",
40,7 → 40,7
00000029 => x"b0201073",
00000030 => x"b8201073",
00000031 => x"00010417",
00000032 => x"e8440413",
00000032 => x"d8440413",
00000033 => x"00010497",
00000034 => x"f7c48493",
00000035 => x"00042023",
54,7 → 54,7
00000043 => x"00158593",
00000044 => x"ff5ff06f",
00000045 => x"00001597",
00000046 => x"f3c58593",
00000046 => x"f3858593",
00000047 => x"80010617",
00000048 => x"f4460613",
00000049 => x"80010697",
67,967 → 67,966
00000056 => x"fedff06f",
00000057 => x"00000513",
00000058 => x"00000593",
00000059 => x"060000ef",
00000059 => x"05c000ef",
00000060 => x"30047073",
00000061 => x"00000013",
00000062 => x"10500073",
00000063 => x"0000006f",
00000064 => x"ff810113",
00000065 => x"00812023",
00000066 => x"00912223",
00000067 => x"34202473",
00000068 => x"02044663",
00000069 => x"34102473",
00000070 => x"00041483",
00000071 => x"0034f493",
00000072 => x"00240413",
00000073 => x"34141073",
00000074 => x"00300413",
00000075 => x"00941863",
00000076 => x"34102473",
00000077 => x"00240413",
00000078 => x"34141073",
00000079 => x"00012403",
00000080 => x"00412483",
00000081 => x"00810113",
00000082 => x"30200073",
00000083 => x"800007b7",
00000084 => x"0007a023",
00000085 => x"fd010113",
00000086 => x"8001a223",
00000087 => x"02812423",
00000088 => x"fe002403",
00000089 => x"026267b7",
00000090 => x"02112623",
00000091 => x"02912223",
00000092 => x"03212023",
00000093 => x"01312e23",
00000094 => x"01412c23",
00000095 => x"01512a23",
00000096 => x"01612823",
00000097 => x"01712623",
00000098 => x"01812423",
00000099 => x"9ff78793",
00000100 => x"00000613",
00000101 => x"00000593",
00000102 => x"00200513",
00000103 => x"0087f463",
00000104 => x"00400513",
00000105 => x"391000ef",
00000106 => x"00100513",
00000107 => x"431000ef",
00000108 => x"00005537",
00000109 => x"00000613",
00000110 => x"00000593",
00000111 => x"b0050513",
00000112 => x"2bd000ef",
00000113 => x"1c1000ef",
00000114 => x"00245793",
00000115 => x"00a78533",
00000116 => x"00f537b3",
00000117 => x"00b785b3",
00000118 => x"1d9000ef",
00000119 => x"ffff07b7",
00000120 => x"4cc78793",
00000121 => x"30579073",
00000122 => x"08000793",
00000123 => x"30479073",
00000124 => x"30046073",
00000061 => x"10500073",
00000062 => x"ffdff06f",
00000063 => x"ff810113",
00000064 => x"00812023",
00000065 => x"00912223",
00000066 => x"34202473",
00000067 => x"02044663",
00000068 => x"34102473",
00000069 => x"00041483",
00000070 => x"0034f493",
00000071 => x"00240413",
00000072 => x"34141073",
00000073 => x"00300413",
00000074 => x"00941863",
00000075 => x"34102473",
00000076 => x"00240413",
00000077 => x"34141073",
00000078 => x"00012403",
00000079 => x"00412483",
00000080 => x"00810113",
00000081 => x"30200073",
00000082 => x"800007b7",
00000083 => x"0007a023",
00000084 => x"fd010113",
00000085 => x"8001a223",
00000086 => x"02812423",
00000087 => x"fe002403",
00000088 => x"026267b7",
00000089 => x"02112623",
00000090 => x"02912223",
00000091 => x"03212023",
00000092 => x"01312e23",
00000093 => x"01412c23",
00000094 => x"01512a23",
00000095 => x"01612823",
00000096 => x"01712623",
00000097 => x"01812423",
00000098 => x"9ff78793",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"00200513",
00000102 => x"0087f463",
00000103 => x"00400513",
00000104 => x"391000ef",
00000105 => x"00100513",
00000106 => x"431000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
00000110 => x"b0050513",
00000111 => x"2bd000ef",
00000112 => x"1c1000ef",
00000113 => x"00245793",
00000114 => x"00a78533",
00000115 => x"00f537b3",
00000116 => x"00b785b3",
00000117 => x"1d9000ef",
00000118 => x"ffff07b7",
00000119 => x"4c878793",
00000120 => x"30579073",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"00000013",
00000125 => x"00000013",
00000126 => x"00000013",
00000127 => x"ffff1537",
00000128 => x"f1850513",
00000129 => x"31d000ef",
00000130 => x"f1302573",
00000131 => x"250000ef",
00000132 => x"ffff1537",
00000133 => x"f5050513",
00000134 => x"309000ef",
00000135 => x"fe002503",
00000136 => x"23c000ef",
00000137 => x"ffff1537",
00000138 => x"f5850513",
00000139 => x"2f5000ef",
00000140 => x"fe402503",
00000141 => x"228000ef",
00000142 => x"ffff1537",
00000143 => x"f6050513",
00000144 => x"2e1000ef",
00000145 => x"30102573",
00000146 => x"214000ef",
00000147 => x"ffff1537",
00000148 => x"f6850513",
00000149 => x"2cd000ef",
00000150 => x"fc002573",
00000151 => x"200000ef",
00000152 => x"ffff1537",
00000153 => x"f7050513",
00000154 => x"2b9000ef",
00000155 => x"fe802503",
00000156 => x"ffff14b7",
00000157 => x"00341413",
00000158 => x"1e4000ef",
00000159 => x"ffff1537",
00000160 => x"f7850513",
00000161 => x"29d000ef",
00000162 => x"ff802503",
00000163 => x"1d0000ef",
00000164 => x"f8048513",
00000165 => x"28d000ef",
00000166 => x"ff002503",
00000167 => x"1c0000ef",
00000168 => x"ffff1537",
00000169 => x"f8c50513",
00000170 => x"279000ef",
00000171 => x"ffc02503",
00000172 => x"1ac000ef",
00000173 => x"f8048513",
00000174 => x"269000ef",
00000175 => x"ff402503",
00000176 => x"19c000ef",
00000177 => x"ffff1537",
00000178 => x"f9450513",
00000179 => x"255000ef",
00000180 => x"0b5000ef",
00000181 => x"00a404b3",
00000182 => x"0084b433",
00000183 => x"00b40433",
00000184 => x"1e5000ef",
00000185 => x"02050263",
00000186 => x"ffff1537",
00000187 => x"fc050513",
00000188 => x"231000ef",
00000189 => x"0ed000ef",
00000190 => x"02300793",
00000191 => x"02f51263",
00000192 => x"00000513",
00000193 => x"0180006f",
00000194 => x"07d000ef",
00000195 => x"fc85eae3",
00000196 => x"00b41463",
00000197 => x"fc9566e3",
00000198 => x"00100513",
00000199 => x"5d8000ef",
00000200 => x"0a4000ef",
00000201 => x"ffff1937",
00000202 => x"ffff19b7",
00000203 => x"02300a13",
00000204 => x"07200a93",
00000205 => x"06800b13",
00000206 => x"07500b93",
00000207 => x"07300c13",
00000208 => x"ffff14b7",
00000209 => x"fcc90513",
00000210 => x"1d9000ef",
00000211 => x"169000ef",
00000212 => x"00050413",
00000213 => x"13d000ef",
00000214 => x"ed098513",
00000215 => x"1c5000ef",
00000216 => x"fb4400e3",
00000217 => x"01541863",
00000218 => x"ffff02b7",
00000219 => x"00028067",
00000220 => x"fd5ff06f",
00000221 => x"01641663",
00000222 => x"04c000ef",
00000223 => x"fc9ff06f",
00000224 => x"00000513",
00000225 => x"01740e63",
00000226 => x"01841663",
00000227 => x"67c000ef",
00000228 => x"fb5ff06f",
00000229 => x"06c00793",
00000230 => x"00f41863",
00000231 => x"00100513",
00000232 => x"3f0000ef",
00000233 => x"fa1ff06f",
00000234 => x"06500793",
00000235 => x"00f41663",
00000236 => x"020000ef",
00000237 => x"f91ff06f",
00000238 => x"fd448513",
00000239 => x"165000ef",
00000240 => x"f85ff06f",
00000241 => x"ffff1537",
00000242 => x"de450513",
00000243 => x"1550006f",
00000244 => x"800007b7",
00000245 => x"0007a783",
00000246 => x"00079863",
00000247 => x"ffff1537",
00000248 => x"e4850513",
00000249 => x"13d0006f",
00000250 => x"ff010113",
00000251 => x"00112623",
00000252 => x"30047073",
00000126 => x"ffff1537",
00000127 => x"f1450513",
00000128 => x"31d000ef",
00000129 => x"f1302573",
00000130 => x"250000ef",
00000131 => x"ffff1537",
00000132 => x"f4c50513",
00000133 => x"309000ef",
00000134 => x"fe002503",
00000135 => x"23c000ef",
00000136 => x"ffff1537",
00000137 => x"f5450513",
00000138 => x"2f5000ef",
00000139 => x"fe402503",
00000140 => x"228000ef",
00000141 => x"ffff1537",
00000142 => x"f5c50513",
00000143 => x"2e1000ef",
00000144 => x"30102573",
00000145 => x"214000ef",
00000146 => x"ffff1537",
00000147 => x"f6450513",
00000148 => x"2cd000ef",
00000149 => x"fc002573",
00000150 => x"200000ef",
00000151 => x"ffff1537",
00000152 => x"f6c50513",
00000153 => x"2b9000ef",
00000154 => x"fe802503",
00000155 => x"ffff14b7",
00000156 => x"00341413",
00000157 => x"1e4000ef",
00000158 => x"ffff1537",
00000159 => x"f7450513",
00000160 => x"29d000ef",
00000161 => x"ff802503",
00000162 => x"1d0000ef",
00000163 => x"f7c48513",
00000164 => x"28d000ef",
00000165 => x"ff002503",
00000166 => x"1c0000ef",
00000167 => x"ffff1537",
00000168 => x"f8850513",
00000169 => x"279000ef",
00000170 => x"ffc02503",
00000171 => x"1ac000ef",
00000172 => x"f7c48513",
00000173 => x"269000ef",
00000174 => x"ff402503",
00000175 => x"19c000ef",
00000176 => x"ffff1537",
00000177 => x"f9050513",
00000178 => x"255000ef",
00000179 => x"0b5000ef",
00000180 => x"00a404b3",
00000181 => x"0084b433",
00000182 => x"00b40433",
00000183 => x"1e5000ef",
00000184 => x"02050263",
00000185 => x"ffff1537",
00000186 => x"fbc50513",
00000187 => x"231000ef",
00000188 => x"0ed000ef",
00000189 => x"02300793",
00000190 => x"02f51263",
00000191 => x"00000513",
00000192 => x"0180006f",
00000193 => x"07d000ef",
00000194 => x"fc85eae3",
00000195 => x"00b41463",
00000196 => x"fc9566e3",
00000197 => x"00100513",
00000198 => x"5d8000ef",
00000199 => x"0a4000ef",
00000200 => x"ffff1937",
00000201 => x"ffff19b7",
00000202 => x"02300a13",
00000203 => x"07200a93",
00000204 => x"06800b13",
00000205 => x"07500b93",
00000206 => x"07300c13",
00000207 => x"ffff14b7",
00000208 => x"fc890513",
00000209 => x"1d9000ef",
00000210 => x"169000ef",
00000211 => x"00050413",
00000212 => x"13d000ef",
00000213 => x"ecc98513",
00000214 => x"1c5000ef",
00000215 => x"fb4400e3",
00000216 => x"01541863",
00000217 => x"ffff02b7",
00000218 => x"00028067",
00000219 => x"fd5ff06f",
00000220 => x"01641663",
00000221 => x"04c000ef",
00000222 => x"fc9ff06f",
00000223 => x"00000513",
00000224 => x"01740e63",
00000225 => x"01841663",
00000226 => x"67c000ef",
00000227 => x"fb5ff06f",
00000228 => x"06c00793",
00000229 => x"00f41863",
00000230 => x"00100513",
00000231 => x"3f0000ef",
00000232 => x"fa1ff06f",
00000233 => x"06500793",
00000234 => x"00f41663",
00000235 => x"020000ef",
00000236 => x"f91ff06f",
00000237 => x"fd048513",
00000238 => x"165000ef",
00000239 => x"f85ff06f",
00000240 => x"ffff1537",
00000241 => x"de050513",
00000242 => x"1550006f",
00000243 => x"800007b7",
00000244 => x"0007a783",
00000245 => x"00079863",
00000246 => x"ffff1537",
00000247 => x"e4450513",
00000248 => x"13d0006f",
00000249 => x"ff010113",
00000250 => x"00112623",
00000251 => x"30047073",
00000252 => x"00000013",
00000253 => x"00000013",
00000254 => x"00000013",
00000255 => x"ffff1537",
00000256 => x"e6450513",
00000257 => x"11d000ef",
00000258 => x"099000ef",
00000259 => x"fe051ee3",
00000260 => x"ff002783",
00000261 => x"00078067",
00000262 => x"0000006f",
00000263 => x"ff010113",
00000264 => x"00812423",
00000265 => x"00050413",
00000266 => x"ffff1537",
00000267 => x"e7450513",
00000268 => x"00112623",
00000269 => x"0ed000ef",
00000270 => x"03040513",
00000271 => x"0ff57513",
00000272 => x"051000ef",
00000273 => x"30047073",
00000254 => x"ffff1537",
00000255 => x"e6050513",
00000256 => x"11d000ef",
00000257 => x"099000ef",
00000258 => x"fe051ee3",
00000259 => x"ff002783",
00000260 => x"00078067",
00000261 => x"0000006f",
00000262 => x"ff010113",
00000263 => x"00812423",
00000264 => x"00050413",
00000265 => x"ffff1537",
00000266 => x"e7050513",
00000267 => x"00112623",
00000268 => x"0ed000ef",
00000269 => x"03040513",
00000270 => x"0ff57513",
00000271 => x"051000ef",
00000272 => x"30047073",
00000273 => x"00000013",
00000274 => x"00000013",
00000275 => x"00000013",
00000276 => x"00100513",
00000277 => x"189000ef",
00000278 => x"0000006f",
00000279 => x"fe010113",
00000280 => x"01212823",
00000281 => x"00050913",
00000282 => x"ffff1537",
00000283 => x"00912a23",
00000284 => x"e8050513",
00000285 => x"ffff14b7",
00000286 => x"00812c23",
00000287 => x"01312623",
00000288 => x"00112e23",
00000289 => x"01c00413",
00000290 => x"099000ef",
00000291 => x"fe048493",
00000292 => x"ffc00993",
00000293 => x"008957b3",
00000294 => x"00f7f793",
00000295 => x"00f487b3",
00000296 => x"0007c503",
00000297 => x"ffc40413",
00000298 => x"7e8000ef",
00000299 => x"ff3414e3",
00000300 => x"01c12083",
00000301 => x"01812403",
00000302 => x"01412483",
00000303 => x"01012903",
00000304 => x"00c12983",
00000305 => x"02010113",
00000306 => x"00008067",
00000307 => x"fb010113",
00000308 => x"04112623",
00000309 => x"04512423",
00000310 => x"04612223",
00000311 => x"04712023",
00000312 => x"02812e23",
00000313 => x"02a12c23",
00000314 => x"02b12a23",
00000315 => x"02c12823",
00000316 => x"02d12623",
00000317 => x"02e12423",
00000318 => x"02f12223",
00000319 => x"03012023",
00000320 => x"01112e23",
00000321 => x"01c12c23",
00000322 => x"01d12a23",
00000323 => x"01e12823",
00000324 => x"01f12623",
00000325 => x"34202473",
00000326 => x"800007b7",
00000327 => x"00778793",
00000328 => x"06f41a63",
00000329 => x"00000513",
00000330 => x"099000ef",
00000331 => x"658000ef",
00000332 => x"fe002783",
00000333 => x"0027d793",
00000334 => x"00a78533",
00000335 => x"00f537b3",
00000336 => x"00b785b3",
00000337 => x"66c000ef",
00000338 => x"03c12403",
00000339 => x"04c12083",
00000340 => x"04812283",
00000341 => x"04412303",
00000342 => x"04012383",
00000343 => x"03812503",
00000344 => x"03412583",
00000345 => x"03012603",
00000346 => x"02c12683",
00000347 => x"02812703",
00000348 => x"02412783",
00000349 => x"02012803",
00000350 => x"01c12883",
00000351 => x"01812e03",
00000352 => x"01412e83",
00000353 => x"01012f03",
00000354 => x"00c12f83",
00000355 => x"05010113",
00000356 => x"30200073",
00000357 => x"00700793",
00000358 => x"00f41863",
00000359 => x"8041a783",
00000360 => x"00100513",
00000361 => x"02079863",
00000362 => x"ffff1537",
00000363 => x"e8450513",
00000364 => x"770000ef",
00000365 => x"00040513",
00000366 => x"ea5ff0ef",
00000367 => x"ffff1537",
00000368 => x"e9850513",
00000369 => x"75c000ef",
00000370 => x"34102573",
00000371 => x"e91ff0ef",
00000372 => x"00500513",
00000373 => x"e49ff0ef",
00000374 => x"ff010113",
00000375 => x"00000513",
00000376 => x"00112623",
00000377 => x"00812423",
00000378 => x"780000ef",
00000379 => x"09e00513",
00000380 => x"7bc000ef",
00000381 => x"00000513",
00000382 => x"7b4000ef",
00000383 => x"00050413",
00000384 => x"00000513",
00000385 => x"784000ef",
00000386 => x"00c12083",
00000387 => x"0ff47513",
00000388 => x"00812403",
00000389 => x"01010113",
00000390 => x"00008067",
00000391 => x"ff010113",
00000392 => x"00112623",
00000393 => x"00812423",
00000394 => x"00000513",
00000395 => x"73c000ef",
00000396 => x"00500513",
00000397 => x"778000ef",
00000398 => x"00000513",
00000399 => x"770000ef",
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00000401 => x"00147413",
00000402 => x"00000513",
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00000404 => x"fc041ce3",
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00000278 => x"fe010113",
00000279 => x"01212823",
00000280 => x"00050913",
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others => x"00000000"
);
 
/neorv32_bus_keeper.vhd
129,7 → 129,7
else -- pending
if (ack_i = '1') or (err_i = '1') then -- termination by bus system
control.pending <= '0';
elsif (or_all_f(control.timeout) = '0') then -- timeout! terminate bus transfer
elsif (or_reduce_f(control.timeout) = '0') then -- timeout! terminate bus transfer
control.pending <= '0';
control.bus_err <= '1';
end if;
/neorv32_cfs.vhd
124,7 → 124,7
-- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset.
--
-- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO
-- to a specific "control register" located right at the beginning of the devices's address space (so this register is cleared at first).
-- to a specific "control register" located right at the beginning of the device's address space (so this register is cleared at first).
-- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS.
-- Make sure that this clearing does not cause any unintended actions in the CFS.
 
210,17 → 210,15
-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
 
-- write access --
for i in 0 to 3 loop
if (wren = '1') then -- word-wide write-access only!
case addr is -- make sure to use the internal 'addr' signal for the read/write interface
when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
when others => NULL;
end case;
end if;
end loop; -- i
if (wren = '1') then -- word-wide write-access only!
case addr is -- make sure to use the internal "addr" signal for the read/write interface
when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
when others => NULL;
end case;
end if;
 
-- read access --
data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
/neorv32_cpu.vhd
61,7 → 61,6
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
80,7 → 79,7
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
);
port (
-- global control --
130,30 → 129,30
architecture neorv32_cpu_rtl of neorv32_cpu is
 
-- local signals --
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
signal comparator : std_ulogic_vector(1 downto 0); -- comparator result
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
signal bus_d_wait : std_ulogic; -- wait for current bus data access
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
signal ma_instr : std_ulogic; -- misaligned instruction address
signal ma_load : std_ulogic; -- misaligned load data address
signal ma_store : std_ulogic; -- misaligned store data address
signal excl_state : std_ulogic; -- atomic/exclusive access lock status
signal be_instr : std_ulogic; -- bus error on instruction access
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
signal comparator : std_ulogic_vector(1 downto 0); -- comparator result
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
signal bus_d_wait : std_ulogic; -- wait for current bus data access
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
signal ma_instr : std_ulogic; -- misaligned instruction address
signal ma_load : std_ulogic; -- misaligned load data address
signal ma_store : std_ulogic; -- misaligned store data address
signal excl_state : std_ulogic; -- atomic/exclusive access lock status
signal be_instr : std_ulogic; -- bus error on instruction access
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
 
-- co-processor interface --
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
186,12 → 185,6
-- Instruction prefetch buffer size --
assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
 
-- A extension - only lr.w and sc.w are supported --
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG NOTE. Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity note;
 
-- FIXME: Bit manipulation warning --
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
 
-- Co-processor timeout counter (for debugging only) --
assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
 
207,7 → 200,7
 
-- HPM counters check --
assert not (HPM_NUM_CNTS > 29) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
assert not ((HPM_CNT_WIDTH < 1) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 1..64 bit." severity error;
assert not ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
-- HPM counters notifier --
assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters (each " & integer'image(HPM_CNT_WIDTH) & "-bit wide)." severity note;
-- HPM CNT requires Zicsr extension --
216,8 → 209,6
-- Debug mode --
assert not (CPU_EXTENSION_RISCV_DEBUG = true) report "NEORV32 CPU CONFIG NOTE: Implementing RISC-V DEBUG MODE extension." severity note;
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
-- FIXME: debug mode extension warning --
assert not (CPU_EXTENSION_RISCV_DEBUG = true) report "NEORV32 CPU CONFIG WARNING! RISC-V DEBUG MODE extension <CPU_EXTENSION_RISCV_DEBUG> is still EXPERIMENTAL." severity warning;
 
 
-- Control Unit ---------------------------------------------------------------------------
230,7 → 221,6
CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
388,34 → 378,12
end generate;
 
 
-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
-- Co-Processor 2: reseverd ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_bitmanip_inst_true:
if (CPU_EXTENSION_RISCV_B = true) generate
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
start_i => cp_start(2), -- trigger operation
-- data input --
cmp_i => comparator, -- comparator status
rs1_i => rs1, -- rf source 1
rs2_i => rs2, -- rf source 2
-- result and status --
res_o => cp_result(2), -- operation result
valid_o => cp_valid(2) -- data output valid
);
end generate;
cp_result(2) <= (others => '0');
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
 
neorv32_cpu_cp_bitmanip_inst_false:
if (CPU_EXTENSION_RISCV_B = false) generate
cp_result(2) <= (others => '0');
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
end generate;
 
 
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_fpu_inst_true:
/neorv32_cpu_alu.vhd
178,7 → 178,7
elsif (shifter.run = '1') then -- running shift
-- coarse shift: multiples of 4 --
if (TINY_SHIFT_EN = false) and -- use coarse shifts first if TINY SHIFT option is NOT enabled
(or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
(or_reduce_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
266,8 → 266,8
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
 
-- shift operation running? --
shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
shifter.run <= '1' when (or_reduce_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
shifter.halt <= '1' when (or_reduce_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
 
 
-- Co-Processor Arbiter -------------------------------------------------------------------
283,7 → 283,7
cp_ctrl.timeout <= (others => '0');
elsif rising_edge(clk_i) then
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
if (or_all_f(cp_valid_i) = '1') then -- cp computation done?
if (or_reduce_f(cp_valid_i) = '1') then -- cp computation done?
cp_ctrl.busy <= '0';
elsif (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
317,7 → 317,7
end process;
 
-- co-processor operation (still) running? --
cp_ctrl.halt <= (cp_ctrl.busy and (not or_all_f(cp_valid_i))) or cp_ctrl.start;
cp_ctrl.halt <= (cp_ctrl.busy and (not or_reduce_f(cp_valid_i))) or cp_ctrl.start;
 
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
cp_res <= cp_result_i(0) or cp_result_i(1) or cp_result_i(2) or cp_result_i(3) or
/neorv32_cpu_bus.vhd
498,9 → 498,9
 
 
-- final PMP access fault signals --
if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
if_pmp_fault <= or_reduce_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
ld_pmp_fault <= or_reduce_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
st_pmp_fault <= or_reduce_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
 
 
end neorv32_cpu_bus_rtl;
/neorv32_cpu_control.vhd
53,7 → 53,6
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
69,7 → 68,7
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
);
port (
-- global control --
194,14 → 193,12
 
-- instruction decoding helper logic --
type decode_aux_t is record
alu_immediate : std_ulogic;
rs1_is_r0 : std_ulogic;
is_atomic_lr : std_ulogic;
is_atomic_sc : std_ulogic;
is_bitmanip_imm : std_ulogic;
is_bitmanip_reg : std_ulogic;
is_float_op : std_ulogic;
sys_env_cmd : std_ulogic_vector(11 downto 0);
alu_immediate : std_ulogic;
rs1_is_r0 : std_ulogic;
is_atomic_lr : std_ulogic;
is_atomic_sc : std_ulogic;
is_float_op : std_ulogic;
sys_env_cmd : std_ulogic_vector(11 downto 0);
end record;
signal decode_aux : decode_aux_t;
 
320,11 → 317,14
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
--
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
mcycle_msb : std_ulogic; -- counter low-to-high-word overflow
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstret_msb : std_ulogic; -- counter low-to-high-word overflow
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
--
mhpmcounter : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
mhpmcounter_msb : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- counter low-to-high-word overflow
mhpmcounterh : mhpmcnth_t; -- mhpmcounter*h (R/W)
mhpmcounter_rd : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
mhpmcounterh_rd : mhpmcnth_rd_t; -- mhpmcounter*h (R/W): actual read data
339,7 → 339,6
dcsr_ebreakm : std_ulogic; -- dcsr.ebreakm (R/W): behavior of ebreak instruction on m-mode
dcsr_ebreaku : std_ulogic; -- dcsr.ebreaku (R/W): behavior of ebreak instruction on u-mode
dcsr_step : std_ulogic; -- dcsr.step (R/W): single-step mode
dcsr_stepie : std_ulogic; -- dcsr.stepie (R/W): enable IRQs in single-step mode
dcsr_prv : std_ulogic_vector(01 downto 0); -- dcsr.prv (R/W): current privilege level when entering debug mode
dcsr_cause : std_ulogic_vector(02 downto 0); -- dcsr.cause (R/-): why was debug mode entered
dcsr_rd : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register
366,11 → 365,6
end record;
signal debug_ctrl : debug_ctrl_t;
 
-- counter low-to-high-word carry --
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
signal mhpmcounter_msb : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
 
-- (hpm) counter events --
signal cnt_event, cnt_event_nxt : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
802,7 → 796,7
 
-- CPU Control Bus Output -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr)
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr, debug_ctrl)
begin
-- signals from execute engine --
ctrl_o <= ctrl;
828,8 → 822,8
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
-- cpu status --
ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode
ctrl_o(ctrl_trap_c) <= trap_ctrl.env_start_ack; -- cpu is starting a trap handler
ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode
ctrl_o(ctrl_trap_c) <= trap_ctrl.env_start_ack; -- cpu is starting a trap handler
if (CPU_EXTENSION_RISCV_DEBUG = true) then
ctrl_o(ctrl_debug_running_c) <= debug_ctrl.running; -- cpu is currently in debug mode
else
844,19 → 838,17
variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
begin
-- defaults --
decode_aux.alu_immediate <= '0';
decode_aux.rs1_is_r0 <= '0';
decode_aux.is_atomic_lr <= '0';
decode_aux.is_atomic_sc <= '0';
decode_aux.is_bitmanip_imm <= '0';
decode_aux.is_bitmanip_reg <= '0';
decode_aux.is_float_op <= '0';
decode_aux.alu_immediate <= '0';
decode_aux.rs1_is_r0 <= '0';
decode_aux.is_atomic_lr <= '0';
decode_aux.is_atomic_sc <= '0';
decode_aux.is_float_op <= '0';
 
-- is immediate ALU operation? --
decode_aux.alu_immediate <= not execute_engine.i_reg(instr_opcode_msb_c-1);
 
-- is rs1 == r0? --
decode_aux.rs1_is_r0 <= not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
decode_aux.rs1_is_r0 <= not or_reduce_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
 
-- is atomic load-reservate/store-conditional? --
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = "11") then -- valid atomic sub-opcode
864,53 → 856,6
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
end if;
 
-- is BITMANIP instruction? --
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
-- immediate operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
(
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- PCNT
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
)
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLRI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSETI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINVI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- SBEXTI
--
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0000111")) or -- GORCI.b 7 (orc.b)
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0011000")) then -- GREVI.-8 (rev8)
decode_aux.is_bitmanip_imm <= '1';
end if;
-- register operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- PACK
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
(
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
)
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010000") and
(
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD
)
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLR
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSET
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINV
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) then -- SBSEXT
decode_aux.is_bitmanip_reg <= '1';
end if;
 
-- floating-point operations (Zfinx) --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
925,7 → 870,7
 
-- system/environment instructions --
sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c or funct12_dret_c; -- sum-up set bits
decode_aux.sys_env_cmd(11 downto 0) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unsued bits to always-zero
decode_aux.sys_env_cmd <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unused bits to always-zero
end process decode_helper;
 
 
1041,9 → 986,9
trap_ctrl.env_end <= '1';
execute_engine.state_nxt <= TRAP_EXECUTE;
 
when TRAP_EXECUTE => -- Start trap environment - jump to TVEC / return from trap environment - jump to EPC
when TRAP_EXECUTE => -- Start trap environment -> jump to TVEC / return from trap environment -> jump to EPC
-- ------------------------------------------------------------
execute_engine.pc_mux_sel <= '0'; -- next PC (csr.mtvec)
execute_engine.pc_mux_sel <= '0'; -- next_PC
fetch_engine.reset <= '1';
execute_engine.pc_we <= '1';
execute_engine.sleep_nxt <= '0'; -- disable sleep mode
1050,18 → 995,18
execute_engine.state_nxt <= SYS_WAIT;
 
 
when EXECUTE => -- Decode and execute instruction (control has to be here for excatly 1 cyle in any case!)
when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!)
-- ------------------------------------------------------------
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
case opcode_v is
 
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
ctrl_nxt(ctrl_alu_opb_mux_c) <= decode_aux.alu_immediate; -- use IMM as ALU.OPB for immediate operations
ctrl_nxt(ctrl_rf_in_mux_c) <= '0'; -- RF input = ALU result
 
-- ALU arithmetic operation type and ADD/SUB --
-- ALU arithmetic operation type --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_slt_c;
1090,13 → 1035,6
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
-- co-processor bit manipulation operation? --
elsif (CPU_EXTENSION_RISCV_B = true) and
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
-- ALU operation, function select --
else
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
1110,10 → 1048,7
-- multi cycle ALU operation? --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) or -- MULDIV CP op?
((CPU_EXTENSION_RISCV_B = true) and (
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- BITMANIP CP register operation?
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) ) then -- BITMANIP CP immediate operation?
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV CP op?
execute_engine.state_nxt <= ALU_WAIT;
else -- single cycle ALU operation
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1208,7 → 1143,7
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- EBREAK
when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- MRET
when funct12_wfi_c =>
when funct12_wfi_c => -- WFI
if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then
NULL; -- just a NOP when in debug mode
else
1221,7 → 1156,7
else
NULL;
end if;
when others => NULL;-- undefined
when others => NULL; -- undefined
end case;
 
 
1366,7 → 1301,7
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
csr_wacc_v := '1'; -- always write CSR
else -- clear/set
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
csr_wacc_v := or_reduce_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
end if;
 
-- low privilege level access to hpm counters? --
1389,26 → 1324,13
NULL;
end if;
 
-- machine trap setup --
when csr_mstatus_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mstatush_c =>
-- machine trap setup & handling --
when csr_mstatus_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only, NOTE: MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
 
-- machine trap handling --
when csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mtval_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mip_c => -- NOTE: MIP is read-only in the NEORV32
when csr_mip_c | csr_mtval_c => -- NOTE: MIP and MTVAL are read-only in the NEORV32!
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
NULL;
end if;
 
-- physical memory protection - address --
-- physical memory protection - address & configuration --
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
1416,7 → 1338,9
csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c |
csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
if (PMP_NUM_REGIONS > 0) then
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
else
1496,7 → 1420,7
-- debug mode CSRs --
when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
if (CPU_EXTENSION_RISCV_DEBUG = true) then
csr_acc_valid <= debug_ctrl.running; -- DEBUG-mode only
csr_acc_valid <= debug_ctrl.running; -- access in only in debug-mode
else
NULL;
end if;
1528,7 → 1452,7
end if;
 
-- check instructions --
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
case opcode_v is
 
1546,10 → 1470,6
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif (decode_aux.is_bitmanip_reg = '1') then -- bit manipulation
if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
1566,11 → 1486,7
 
when opcode_alui_c => -- check ALUI.funct7
-- ------------------------------------------------------------
if (decode_aux.is_bitmanip_imm = '1') then -- bit manipulation
if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
1677,13 → 1593,13
end if;
end if;
 
-- ecall, ebreak, mret, wfi --
-- ecall, ebreak, mret, wfi, dret --
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = (funct12_dret_c)) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = (funct12_dret_c)) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
illegal_instruction <= '0';
else
1821,13 → 1737,12
end process trap_controller;
 
-- any exception/interrupt? --
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
trap_ctrl.irq_fire <= (or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie and trap_ctrl.db_irq_en) or trap_ctrl.db_irq_fire; -- interrupts CAN be masked
trap_ctrl.exc_fire <= or_reduce_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
trap_ctrl.irq_fire <= (or_reduce_f(trap_ctrl.irq_buf) and csr.mstatus_mie and trap_ctrl.db_irq_en) or trap_ctrl.db_irq_fire; -- interrupts CAN be masked
 
-- debug mode (entry) interrupts --
trap_ctrl.db_irq_en <= '1' when (CPU_EXTENSION_RISCV_DEBUG = false) else
'0' when (debug_ctrl.running = '1') else -- no interrupts when IN debug mode
csr.dcsr_stepie when (csr.dcsr_step = '1') else '1'; -- allow IRQ in single-step mode when dcsr.stepie is set
'0' when (debug_ctrl.running = '1') or (csr.dcsr_step = '1') else '1'; -- no interrupts when IN debug mode or IN single-step mode
trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(interrupt_db_step_c) or trap_ctrl.irq_buf(interrupt_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry
 
-- acknowledge mask output --
2098,7 → 2013,6
csr.dcsr_ebreakm <= '0';
csr.dcsr_ebreaku <= '0';
csr.dcsr_step <= '0';
csr.dcsr_stepie <= '0';
csr.dcsr_prv <= (others => def_rst_val_c);
csr.dcsr_cause <= (others => def_rst_val_c);
csr.dpc <= (others => def_rst_val_c);
2185,10 → 2099,6
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
end if;
-- R/W: mtval - machine bad address/instruction --
if (csr.addr(3 downto 0) = csr_mtval_c(3 downto 0)) then
csr.mtval <= csr.wdata;
end if;
end if;
 
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
2253,7 → 2163,6
-- R/W: dcsr - debug mode control and status register --
if (csr.addr(1 downto 0) = csr_dcsr_c(1 downto 0)) then
csr.dcsr_ebreakm <= csr.wdata(15);
csr.dcsr_stepie <= csr.wdata(2);
csr.dcsr_step <= csr.wdata(2);
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
csr.dcsr_ebreaku <= csr.wdata(12);
2364,17 → 2273,11
csr.mstatus_mpie <= '1';
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
csr.mstatus_mpp <= priv_mode_m_c;
csr.mstatus_mpp <= (others => '0');
end if;
end if;
end if;
 
-- user mode NOT implemented --
if (CPU_EXTENSION_RISCV_U = false) then
csr.privilege <= priv_mode_m_c;
csr.mstatus_mpp <= priv_mode_m_c;
end if;
 
end if; -- /hardware csr access
end if;
 
2391,6 → 2294,7
csr.mcounteren_ir <= '0';
csr.mcounteren_hpm <= (others => '0');
csr.dcsr_ebreaku <= '0';
csr.dcsr_prv <= priv_mode_m_c;
end if;
 
-- pmp disabled --
2425,8 → 2329,6
csr.dcsr_ebreakm <= '0';
csr.dcsr_ebreaku <= '0';
csr.dcsr_step <= '0';
csr.dcsr_stepie <= '0';
csr.dcsr_prv <= (others => '0');
csr.dcsr_cause <= (others => '0');
csr.dpc <= (others => '0');
csr.dscratch0 <= (others => '0');
2475,96 → 2377,100
begin
-- Counter CSRs (each counter is split into two 32-bit counters - coupled via an MSB overflow detector)
if (rstn_i = '0') then
csr.mcycle <= (others => def_rst_val_c);
mcycle_msb <= def_rst_val_c;
csr.mcycleh <= (others => def_rst_val_c);
csr.minstret <= (others => def_rst_val_c);
minstret_msb <= def_rst_val_c;
csr.minstreth <= (others => def_rst_val_c);
csr.mhpmcounter <= (others => (others => def_rst_val_c));
mhpmcounter_msb <= (others => def_rst_val_c);
csr.mhpmcounterh <= (others => (others => def_rst_val_c));
csr.mcycle <= (others => def_rst_val_c);
csr.mcycle_msb <= def_rst_val_c;
csr.mcycleh <= (others => def_rst_val_c);
csr.minstret <= (others => def_rst_val_c);
csr.minstret_msb <= def_rst_val_c;
csr.minstreth <= (others => def_rst_val_c);
csr.mhpmcounter <= (others => (others => def_rst_val_c));
csr.mhpmcounter_msb <= (others => def_rst_val_c);
csr.mhpmcounterh <= (others => (others => def_rst_val_c));
elsif rising_edge(clk_i) then
 
-- [m]cycle --
csr.mcycle(csr.mcycle'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.mcycle <= (others => '0');
mcycle_msb <= '0';
elsif (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
csr.mcycle(cpu_cnt_lo_width_c downto 0) <= '0' & csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
mcycle_msb <= '0';
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
csr.mcycle(cpu_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned(csr.mcycle(cpu_cnt_lo_width_c downto 0)) + 1);
mcycle_msb <= csr.mcycle(cpu_cnt_lo_width_c);
if (cpu_cnt_lo_width_c > 0) then
csr.mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
csr.mcycle(cpu_cnt_lo_width_c downto 0) <= '0' & csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
csr.mcycle(cpu_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned('0' & csr.mcycle(cpu_cnt_lo_width_c-1 downto 0)) + 1);
end if;
else
csr.mcycle <= (others => '-');
csr.mcycle_msb <= '-';
end if;
 
-- [m]cycleh --
csr.mcycleh(csr.mcycleh'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_hi_width_c = 0) then
csr.mcycleh <= (others => '0');
elsif (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
elsif ((mcycle_msb xor csr.mcycle(cpu_cnt_lo_width_c)) = '1') then -- automatic update (continued)
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + 1);
if (cpu_cnt_hi_width_c > 0) then
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
elsif (csr.mcycle_msb = '0') and (csr.mcycle(csr.mcycle'left) = '1') then -- automatic update (continued)
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + 1);
end if;
else
csr.mcycleh <= (others => '-');
end if;
 
 
-- [m]instret --
csr.minstret(csr.minstret'left downto cpu_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (cpu_cnt_lo_width_c = 0) then
csr.minstret <= (others => '0');
minstret_msb <= '0';
elsif (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
csr.minstret(cpu_cnt_lo_width_c downto 0) <= '0' & csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
minstret_msb <= '0';
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update
csr.minstret(cpu_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned(csr.minstret(cpu_cnt_lo_width_c downto 0)) + 1);
minstret_msb <= csr.minstret(csr.minstret'left);
if (cpu_cnt_lo_width_c > 0) then
csr.minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
csr.minstret(cpu_cnt_lo_width_c downto 0) <= '0' & csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update
csr.minstret(cpu_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned('0' & csr.minstret(cpu_cnt_lo_width_c-1 downto 0)) + 1);
end if;
else
csr.minstret <= (others => '-');
csr.minstret_msb <= '-';
end if;
 
-- [m]instreth --
csr.minstreth(csr.minstreth'left downto cpu_cnt_hi_width_c+1) <= (others => '0'); -- set unsued bits to zero
if (cpu_cnt_hi_width_c = 0) then
csr.minstreth <= (others => '0');
elsif (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
elsif ((minstret_msb xor csr.minstret(cpu_cnt_lo_width_c)) = '1') then -- automatic update (continued)
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + 1);
if (cpu_cnt_hi_width_c > 0) then
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
elsif (csr.minstret_msb = '0') and (csr.minstret(csr.minstret'left) = '1') then -- automatic update (continued)
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + 1);
end if;
else
csr.minstreth <= (others => '-');
end if;
 
 
-- [machine] hardware performance monitors (counters) --
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmcounter(i)(csr.mhpmcounter(i)'left downto hpm_cnt_lo_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_lo_width_c = 0) then
csr.mhpmcounter(i) <= (others => '0');
mhpmcounter_msb(i) <= '0';
else
-- [m]hpmcounter* --
 
-- [m]hpmcounter* --
if (hpm_cnt_lo_width_c > 0) then
csr.mhpmcounter_msb(i) <= csr.mhpmcounter(i)(csr.mhpmcounter(i)'left);
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
csr.mhpmcounter(i)(hpm_cnt_lo_width_c downto 0) <= '0' & csr.wdata(hpm_cnt_lo_width_c-1 downto 0);
mhpmcounter_msb(i) <= '0';
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
csr.mhpmcounter(i)(hpm_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounter(i)(hpm_cnt_lo_width_c downto 0)) + 1);
mhpmcounter_msb(i) <= csr.mhpmcounter(i)(csr.mhpmcounter(i)'left);
csr.mhpmcounter(i)(hpm_cnt_lo_width_c downto 0) <= std_ulogic_vector(unsigned('0' & csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0)) + 1);
end if;
else
csr.mhpmcounter(i) <= (others => '-');
csr.mhpmcounter_msb(i) <= '-';
end if;
 
-- [m]hpmcounter*h --
csr.mhpmcounterh(i)(csr.mhpmcounterh(i)'left downto hpm_cnt_hi_width_c+1) <= (others => '0'); -- set unused bits to zero
if (hpm_cnt_hi_width_c = 0) then
csr.mhpmcounterh(i) <= (others => '0');
else
if (hpm_cnt_hi_width_c > 0) then
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0);
elsif ((mhpmcounter_msb(i) xor csr.mhpmcounter(i)(hpm_cnt_lo_width_c)) = '1') then -- automatic update (continued)
elsif (csr.mhpmcounter_msb(i) = '0') and (csr.mhpmcounter(i)(csr.mhpmcounter(i)'left) = '1') then -- automatic update (continued)
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + 1);
end if;
else
csr.mhpmcounterh(i) <= (others => '-');
end if;
 
end loop; -- i
 
end if;
end process csr_counters;
 
 
-- hpm counters read dummy --
hpm_rd_dummy: process(csr)
begin
2598,7 → 2504,7
hpmcnt_trigger <= (others => '0'); -- default
if (HPM_NUM_CNTS /= 0) then
for i in 0 to HPM_NUM_CNTS-1 loop
hpmcnt_trigger(i) <= or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0));
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0));
end loop; -- i
end if;
end if;
2653,15 → 2559,11
-- --------------------------------------------------------------------
when csr_mstatus_c => -- mstatus (r/w): machine status register
csr.rdata(03) <= csr.mstatus_mie; -- MIE
csr.rdata(06) <= '1' and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- UBE: CPU/Processor is BIG-ENDIAN (in user-mode)
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
when csr_mstatush_c => -- mstatush (r/-): machine status register - high part
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode)
when csr_misa_c => -- misa (r/-): ISA and extensions
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
2922,9 → 2824,6
when csr_mzext_c => -- mzext (r/-): available RISC-V Z* sub-extensions
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei
csr.rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zbb (B)
csr.rdata(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zbs (B)
csr.rdata(4) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- Zba (B)
csr.rdata(5) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx ("F-alternative")
if (CPU_CNT_WIDTH = 64) then
csr.rdata(6) <= '0'; -- Zxscnt (custom)
2949,7 → 2848,7
-- undefined/unavailable --
-- --------------------------------------------------------------------
when others =>
NULL; -- not implemented
NULL; -- not implemented, read as zero if read access is granted
 
end case;
end if;
3015,8 → 2914,8
 
-- entry debug mode triggers --
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- we are in debug mode: re-enter debug mode
(csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enable goto-debug-mode in machine mode on "ebreak"
(csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enable goto-debug-mode in user mode on "ebreak"
(csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enabled goto-debug-mode in machine mode on "ebreak"
(csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enabled goto-debug-mode in user mode on "ebreak"
debug_ctrl.trig_halt <= (not debug_ctrl.ext_halt_req(1)) and debug_ctrl.ext_halt_req(0) and (not debug_ctrl.running); -- rising edge detector from external halt request (if not halted already)
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
 
3025,7 → 2924,7
-- -------------------------------------------------------------------------------------------
dcsr_readback_false:
if (CPU_EXTENSION_RISCV_DEBUG = false) generate
csr.dcsr_rd <= (others => '0');
csr.dcsr_rd <= (others => '-');
end generate;
 
dcsr_readback_true:
3036,10 → 2935,10
csr.dcsr_rd(14) <= '0'; -- ebreakh: not available
csr.dcsr_rd(13) <= '0'; -- ebreaks: not available
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
csr.dcsr_rd(11) <= csr.dcsr_stepie; -- stepie: interrupts enabled during single-stepping?
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ???
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME ???
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- cause
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
csr.dcsr_rd(05) <= '0'; -- reserved
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
csr.dcsr_rd(03) <= trap_ctrl.irq_buf(interrupt_nm_irq_c); -- nmip: pending non-maskable interrupt
/neorv32_cpu_cp_fpu.vhd
313,9 → 313,9
begin
for i in 0 to 1 loop -- for rs1 and rs2 inputs
-- check for all-zero/all-one --
op_m_all_zero_v := not or_all_f(op_data(i)(22 downto 00));
op_e_all_zero_v := not or_all_f(op_data(i)(30 downto 23));
op_e_all_one_v := and_all_f(op_data(i)(30 downto 23));
op_m_all_zero_v := not or_reduce_f(op_data(i)(22 downto 00));
op_e_all_zero_v := not or_reduce_f(op_data(i)(30 downto 23));
op_e_all_one_v := and_reduce_f(op_data(i)(30 downto 23));
 
-- check special cases --
op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero
1360,7 → 1360,7
sreg.lower <= mantissa_i(45 downto 23);
sreg.ext_g <= mantissa_i(22);
sreg.ext_r <= mantissa_i(21);
sreg.ext_s <= or_all_f(mantissa_i(20 downto 0));
sreg.ext_s <= or_reduce_f(mantissa_i(20 downto 0));
-- check for special cases --
if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN
ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero
1475,10 → 1475,10
end process ctrl_engine;
 
-- stop shifting when normalized --
sreg.done <= (not or_all_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
sreg.done <= (not or_reduce_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
 
-- all-zero including hidden bit --
sreg.zero <= not or_all_f(sreg.upper);
sreg.zero <= not or_reduce_f(sreg.upper);
 
-- result --
result_o(31) <= ctrl.res_sgn;
1717,8 → 1717,8
 
when S_NORMALIZE_BUSY => -- running normalization cycle
-- ------------------------------------------------------------
sreg.ext_s <= sreg.ext_s or or_all_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
if (or_all_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
sreg.ext_s <= sreg.ext_s or or_reduce_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
if (or_reduce_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
if (ctrl.unsign = '0') then -- signed conversion
ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit
end if;
/neorv32_cpu_cp_muldiv.vhd
163,7 → 163,7
div_res_corr <= '0';
end if;
-- divide by zero? --
opy_is_zero <= not or_all_f(rs2_i); -- set if rs2 = 0
opy_is_zero <= not or_reduce_f(rs2_i); -- set if rs2 = 0
-- abs(rs1) --
if ((rs1_i(rs1_i'left) and rs1_is_signed) = '1') then -- signed division?
div_opx <= std_ulogic_vector(0 - unsigned(rs1_i)); -- make positive
/neorv32_cpu_regfile.vhd
115,8 → 115,8
end process rf_access;
 
-- check if we are writing to x0 --
rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
rd_is_r0 <= not or_reduce_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
not or_reduce_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
 
-- valid RF write access? --
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
/neorv32_debug_dm.vhd
188,7 → 188,7
constant sreg_execute_ack_c : natural := 4; -- -/w: CPU starts to execute program buffer
constant sreg_exception_ack_c : natural := 5; -- -/w: CPU has detected an exception
 
-- code ROM for "park loop" --
-- code ROM containing "park loop" --
type code_rom_file_t is array (0 to 31) of std_ulogic_vector(31 downto 0);
constant code_rom_file : code_rom_file_t := (
00000000 => x"0180006f",
240,9 → 240,9
if rising_edge(clk_i) then
if (dm_reg.dmcontrol_dmactive = '0') or (dmi_rstn_i = '0') then -- DM reset / DM disabled
dm_ctrl.state <= CMD_IDLE;
dm_ctrl.ldsw_progbuf <= instr_nop_c;
dm_ctrl.ldsw_progbuf <= (others => '-');
dci.execute_req <= '0';
dm_ctrl.pbuf_en <= '0';
dm_ctrl.pbuf_en <= '-';
--
dm_ctrl.illegal_cmd <= '-';
dm_ctrl.illegal_state <= '-';
306,12 → 306,12
dm_ctrl.ldsw_progbuf(11 downto 07) <= dm_reg.command(4 downto 0); -- "regno" = destination register
end if;
else
dm_ctrl.ldsw_progbuf <= instr_nop_c;
dm_ctrl.ldsw_progbuf <= instr_nop_c; -- NOP - do nothing
end if;
--
if (dm_reg.command(18) = '1') then -- "postexec" - execute DMI program buffer
if (dm_reg.command(18) = '1') then -- "postexec" - execute program buffer
dm_ctrl.pbuf_en <= '1';
else -- empty program buffer, execute NOPs
else -- execute all program buffer entries as NOPs
dm_ctrl.pbuf_en <= '0';
end if;
--
326,7 → 326,7
 
when CMD_EXE_BUSY => -- wait for CPU to finish
-- ------------------------------------------------------------
if (dci.halt_ack = '1') then -- CPU is parked again -> execution done
if (dci.halt_ack = '1') then -- CPU is parked (halted) again -> execution done
dm_ctrl.state <= CMD_IDLE;
end if;
 
341,9 → 341,9
end case;
 
 
-- error flag register --
-- error flags --
-- ------------------------------------------------------------
if (dm_ctrl.cmderr = "000") then
if (dm_ctrl.cmderr = "000") then -- set new error
if (dm_ctrl.illegal_state = '1') then -- cannot execute since hart is not in expected state
dm_ctrl.cmderr <= "100";
elsif (dci.exception_ack = '1') then -- exception during execution
544,7 → 544,7
-- debug module status register --
when addr_dmstatus_c =>
dmi_resp_data_o(31 downto 23) <= (others => '0'); -- reserved (r/-)
dmi_resp_data_o(22) <= '1'; -- impebreak (r/-): there is an implicit ebreak instruction after the program visible buffer
dmi_resp_data_o(22) <= '1'; -- impebreak (r/-): there is an implicit ebreak instruction after the visible program buffer
dmi_resp_data_o(21 downto 20) <= (others => '0'); -- reserved (r/-)
dmi_resp_data_o(19) <= dm_ctrl.hart_reset; -- allhavereset (r/-): there is only one hart that can be reset
dmi_resp_data_o(18) <= dm_ctrl.hart_reset; -- anyhavereset (r/-): there is only one hart that can be reset
623,9 → 623,9
when addr_progbuf1_c =>
dmi_resp_data_o <= dm_reg.progbuf(1); -- program buffer 1
 
-- system bus access control and status (r/-) --
when addr_sbcs_c =>
dmi_resp_data_o <= (others => '0'); -- bus access not implemented
-- -- system bus access control and status (r/-) --
-- when addr_sbcs_c =>
-- dmi_resp_data_o <= (others => '0'); -- bus access not implemented
 
-- halt summary 0 (r/-) --
when addr_haltsum0_c =>
669,7 → 669,7
-- Access Control ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0';
maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2);
maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address
rden <= acc_en and cpu_rden_i;
wren <= acc_en and cpu_wren_i;
 
711,7 → 711,7
cpu_ack_o <= rden or wren;
cpu_data_o <= (others => '0');
if (rden = '1') then -- output gate
case maddr is -- read data select
case maddr is -- module select
when "00" => -- code ROM
cpu_data_o <= code_rom_file(to_integer(unsigned(cpu_addr_i(6 downto 2))));
when "01" => -- program buffer
/neorv32_gpio.vhd
125,7 → 125,7
in_buf <= gpio_i;
din <= in_buf;
-- IRQ --
irq_o <= or_all_f((in_buf xor din) and irq_en); -- any enabled pin transition triggers an interrupt
irq_o <= or_reduce_f((in_buf xor din) and irq_en); -- any enabled pin transition triggers an interrupt
end if;
end process irq_detector;
 
/neorv32_icache.vhd
259,7 → 259,7
ctrl.state_nxt <= S_BUS_ERROR;
elsif (bus_ack_i = '1') then -- ACK = write to cache and get next word
cache.ctrl_we <= '1'; -- write to cache
if (and_all_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete?
if (and_reduce_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete?
cache.ctrl_tag_we <= '1'; -- current block is valid now
cache.ctrl_valid_we <= '1'; -- write tag of current address
ctrl.state_nxt <= S_CACHE_RESYNC_0;
475,7 → 475,7
history.re_ff <= host_re_i;
if (invalidate_i = '1') then -- invalidate whole cache
history.last_used_set <= (others => '1');
elsif (history.re_ff = '1') and (or_all_f(hit) = '1') and (ctrl_en_i = '0') then -- store last accessed set that caused a hit
elsif (history.re_ff = '1') and (or_reduce_f(hit) = '1') and (ctrl_en_i = '0') then -- store last accessed set that caused a hit
history.last_used_set(to_integer(unsigned(cache_index))) <= not hit(0);
end if;
history.to_be_replaced <= history.last_used_set(to_integer(unsigned(cache_index)));
546,7 → 546,7
end process comparator;
 
-- global hit --
hit_o <= or_all_f(hit);
hit_o <= or_reduce_f(hit);
 
 
-- Cache Data Memory ----------------------------------------------------------------------
/neorv32_mtime.vhd
45,18 → 45,17
entity neorv32_mtime is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- time output for CPU --
time_o : out std_ulogic_vector(63 downto 0); -- current system time
time_o : out std_ulogic_vector(63 downto 0); -- current system time
-- interrupt --
irq_o : out std_ulogic -- interrupt request
irq_o : out std_ulogic -- interrupt request
);
end neorv32_mtime;
 
/neorv32_package.vhd
44,9 → 44,9
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
 
-- (external) bus interface --
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
-- external bus interface --
constant wb_pipe_mode_c : boolean := false; -- external bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
constant xbus_big_endian_c : boolean := false; -- external memory access byte order: true=big-endian, false=little-endian (default)
 
-- CPU core --
constant ipb_entries_c : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
75,10 → 75,9
function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic;
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
function or_all_f(a : std_ulogic_vector) return std_ulogic;
function and_all_f(a : std_ulogic_vector) return std_ulogic;
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
function or_reduce_f(a : std_ulogic_vector) return std_ulogic;
function and_reduce_f(a : std_ulogic_vector) return std_ulogic;
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic;
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
88,7 → 87,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050509"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050605"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
121,45 → 120,73
 
-- IO: Peripheral Devices ("IO") Area --
-- Control register(s) (including the device-enable) should be located at the base address of each device
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
constant io_size_c : natural := 64*4; -- module's address space in bytes, fixed!
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
constant io_size_c : natural := 512; -- module's address space in bytes, fixed!
 
-- Custom Functions Subsystem (CFS) --
constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
constant cfs_size_c : natural := 32*4; -- module's address space in bytes
constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff04";
constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff08";
constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff0c";
constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff10";
constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff14";
constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff18";
constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff1c";
constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff20";
constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff24";
constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff28";
constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff2c";
constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff30";
constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff34";
constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff38";
constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff3c";
constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40";
constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44";
constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48";
constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4c";
constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50";
constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff54";
constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff58";
constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff5c";
constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";
constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff64";
constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff68";
constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff6c";
constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70";
constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff74";
constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78";
constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c";
constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address
constant cfs_size_c : natural := 64*4; -- module's address space in bytes
constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe04";
constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe08";
constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe0c";
constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe10";
constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe14";
constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe18";
constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe1c";
constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe20";
constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe24";
constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe28";
constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe2c";
constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe30";
constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe34";
constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe38";
constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe3c";
constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe40";
constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe44";
constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe48";
constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe4c";
constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe50";
constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe54";
constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe58";
constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe5c";
constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe60";
constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe64";
constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe68";
constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe6c";
constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe70";
constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe74";
constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe78";
constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe7c";
 
-- Pulse-Width Modulation Controller (PWM) --
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80"; -- base address
constant pwm_size_c : natural := 16*4; -- module's address space in bytes
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80";
constant pwm_duty0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe84";
constant pwm_duty1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe88";
constant pwm_duty2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe8c";
constant pwm_duty3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe90";
constant pwm_duty4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe94";
constant pwm_duty5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe98";
constant pwm_duty6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe9c";
constant pwm_duty7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea0";
constant pwm_duty8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea4";
constant pwm_duty9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea8";
constant pwm_duty10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeac";
constant pwm_duty11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb0";
constant pwm_duty12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb4";
constant pwm_duty13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb8";
constant pwm_duty14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffebc";
 
-- reserved --
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
--constant reserved_size_c : natural := 16*4; -- module's address space in bytes
 
-- reserved --
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
--constant reserved_size_c : natural := 32*4; -- module's address space in bytes
 
-- General Purpose Input/Output Unit (GPIO) --
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
constant gpio_size_c : natural := 2*4; -- module's address space in bytes
202,11 → 229,9
constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";
constant twi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";
 
-- Pulse-Width Modulation Controller (PWM) --
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
constant pwm_size_c : natural := 2*4; -- module's address space in bytes
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8";
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc";
-- reserved --
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
--constant reserved_size_c : natural := 2*4; -- module's address space in bytes
 
-- Numerically-Controlled Oscillator (NCO) --
constant nco_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
473,7 → 498,6
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304";
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305";
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306";
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310";
-- machine counter setup --
constant csr_cnt_setup_c : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320";
749,7 → 773,7
-- -------------------------------------------------------------------------------------------
constant cp_sel_csr_rd_c : std_ulogic_vector(2 downto 0) := "000"; -- CSR read access ('Zicsr' extension)
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- multiplication/division operations ('M' extension)
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
--constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- floating-point unit ('Zfinx' extension)
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "100"; -- reserved
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "101"; -- reserved
769,12 → 793,12
-- function select (actual alu result) --
constant alu_func_cmd_arith_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
constant alu_func_cmd_logic_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (multi-cycle)
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
 
-- Trap ID Codes --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- MSB : 1 = async exception (IRQ); 0 = sync exception (eg. ebreak)
-- MSB : 1 = async exception (IRQ); 0 = sync exception (e.g. ebreak)
-- MSB-1 : 1 = entry to debug mode; 0 = normal trapping
-- RISC-V compliant sync. exceptions --
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned
907,7 → 931,6
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
925,7 → 948,7
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
948,7 → 971,7
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
1004,8 → 1027,8
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- PWM (available if IO_PWM_EN = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
-- Custom Functions Subsystem IO --
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
1035,7 → 1058,6
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
1054,7 → 1076,7
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
);
port (
-- global control --
1111,7 → 1133,6
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
1127,7 → 1148,7
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
);
port (
-- global control --
1250,25 → 1271,6
);
end component;
 
-- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_cp_bitmanip
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
start_i : in std_ulogic; -- trigger operation
-- data input --
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
-- result and status --
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
valid_o : out std_ulogic -- data output valid
);
end component;
 
-- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_cp_fpu
1530,18 → 1532,17
component neorv32_mtime
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- time output for CPU --
time_o : out std_ulogic_vector(63 downto 0); -- current system time
time_o : out std_ulogic_vector(63 downto 0); -- current system time
-- interrupt --
irq_o : out std_ulogic -- interrupt request
irq_o : out std_ulogic -- interrupt request
);
end component;
 
1668,6 → 1669,9
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_pwm
generic (
NUM_CHANNELS : natural := 4 -- number of PWM channels (0..60)
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
1681,7 → 1685,7
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
);
end component;
 
1850,7 → 1854,7
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := true; -- implement custom functions subsystem (CFS)?
2012,9 → 2016,9
end if;
end function bool_to_ulogic_f;
 
-- Function: OR all bits ------------------------------------------------------------------
-- Function: OR-reduce all bits -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function or_all_f(a : std_ulogic_vector) return std_ulogic is
function or_reduce_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := '0';
2024,11 → 2028,11
end loop; -- i
end if;
return tmp_v;
end function or_all_f;
end function or_reduce_f;
 
-- Function: AND all bits -----------------------------------------------------------------
-- Function: AND-reduce all bits ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function and_all_f(a : std_ulogic_vector) return std_ulogic is
function and_reduce_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := '1';
2038,11 → 2042,11
end loop; -- i
end if;
return tmp_v;
end function and_all_f;
end function and_reduce_f;
 
-- Function: XOR all bits -----------------------------------------------------------------
-- Function: XOR-reduce all bits ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function xor_all_f(a : std_ulogic_vector) return std_ulogic is
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := '0';
2052,22 → 2056,8
end loop; -- i
end if;
return tmp_v;
end function xor_all_f;
end function xor_reduce_f;
 
-- Function: XNOR all bits ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := '1';
if (a'low < a'high) then -- not null range?
for i in a'low to a'high loop
tmp_v := tmp_v xnor a(i);
end loop; -- i
end if;
return tmp_v;
end function xnor_all_f;
 
-- Function: Convert std_ulogic_vector to hex char ----------------------------------------
-- -------------------------------------------------------------------------------------------
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
/neorv32_pwm.vhd
1,12 → 1,12
-- #################################################################################################
-- # << NEORV32 - Pulse Width Modulation Controller (PWM) >> #
-- # ********************************************************************************************* #
-- # Simple 4-channel PWM controller with 8 bit resolution for the duty cycle and programmable #
-- # clock. #
-- # Simple PWM controller with 8 bit resolution for the duty cycle and programmable base #
-- # frequency. The controller supports up to 60 PWM channels. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
43,6 → 43,9
use neorv32.neorv32_package.all;
 
entity neorv32_pwm is
generic (
NUM_CHANNELS : natural := 4 -- number of PWM channels (0..60)
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
56,15 → 59,12
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
);
end neorv32_pwm;
 
architecture neorv32_pwm_rtl of neorv32_pwm is
 
-- internal configuration --
constant num_pwm_channels_c : natural := 4; -- number of PWM channels, fixed!
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(pwm_size_c); -- low address boundary bit
82,11 → 82,14
signal rden : std_ulogic; -- read enable
 
-- accessible regs --
type pwm_ch_t is array (0 to num_pwm_channels_c-1) of std_ulogic_vector(7 downto 0);
type pwm_ch_t is array (0 to NUM_CHANNELS-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch : pwm_ch_t; -- duty cycle (r/w)
signal enable : std_ulogic; -- enable unit (r/w)
signal prsc : std_ulogic_vector(2 downto 0); -- clock prescaler (r/w)
 
type pwm_ch_rd_t is array (0 to 60-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch_rd : pwm_ch_rd_t; -- duty cycle read-back
 
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
 
95,6 → 98,11
 
begin
 
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (NUM_CHANNELS > 60) report "NEORV32 PROCESSOR CONFIG ERROR! <IO.PWM> invalid number of channels! Has to be 0..60.!" severity error;
 
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = pwm_base_c(hi_abb_c downto lo_abb_c)) else '0';
109,34 → 117,57
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
 
-- write access --
if (wren = '1') then
if (addr = pwm_ctrl_addr_c) then -- control register
-- control register --
if (addr = pwm_ctrl_addr_c) then
enable <= data_i(ctrl_enable_c);
prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
end if;
if (addr = pwm_duty_addr_c) then -- duty cycle register
for i in 0 to 3 loop
pwm_ch(i) <= data_i(7+i*8 downto 0+i*8);
end loop;
end if;
-- duty cycle registers --
for i in 0 to NUM_CHANNELS-1 loop -- channel loop
if (addr(5 downto 2) = std_ulogic_vector(to_unsigned((i/4)+1, 4))) then -- 4 channels per register; add ctrl reg offset
pwm_ch(i) <= data_i((i mod 4)*8+7 downto (i mod 4)*8+0);
end if;
end loop;
end if;
 
-- read access --
data_o <= (others => '0');
if (rden = '1') then
if (addr = pwm_ctrl_addr_c) then
data_o(ctrl_enable_c) <= enable;
data_o(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c) <= prsc;
else -- pwm_duty_addr_c
data_o(07 downto 00) <= pwm_ch(0);
data_o(15 downto 08) <= pwm_ch(1);
data_o(23 downto 16) <= pwm_ch(2);
data_o(31 downto 24) <= pwm_ch(3);
end if;
case addr(5 downto 2) is
when x"0" => data_o(ctrl_enable_c) <= enable; data_o(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c) <= prsc;
when x"1" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(3) & pwm_ch_rd(2) & pwm_ch_rd(1) & pwm_ch_rd(0); else NULL; end if;
when x"2" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(7) & pwm_ch_rd(6) & pwm_ch_rd(5) & pwm_ch_rd(4); else NULL; end if;
when x"3" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(11) & pwm_ch_rd(10) & pwm_ch_rd(9) & pwm_ch_rd(8); else NULL; end if;
when x"4" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(15) & pwm_ch_rd(14) & pwm_ch_rd(13) & pwm_ch_rd(12); else NULL; end if;
when x"5" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(19) & pwm_ch_rd(18) & pwm_ch_rd(17) & pwm_ch_rd(16); else NULL; end if;
when x"6" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(23) & pwm_ch_rd(22) & pwm_ch_rd(21) & pwm_ch_rd(20); else NULL; end if;
when x"7" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(27) & pwm_ch_rd(26) & pwm_ch_rd(25) & pwm_ch_rd(24); else NULL; end if;
when x"8" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(31) & pwm_ch_rd(30) & pwm_ch_rd(29) & pwm_ch_rd(28); else NULL; end if;
when x"9" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(35) & pwm_ch_rd(34) & pwm_ch_rd(33) & pwm_ch_rd(32); else NULL; end if;
when x"a" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(39) & pwm_ch_rd(38) & pwm_ch_rd(37) & pwm_ch_rd(36); else NULL; end if;
when x"b" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(43) & pwm_ch_rd(42) & pwm_ch_rd(41) & pwm_ch_rd(40); else NULL; end if;
when x"c" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(47) & pwm_ch_rd(46) & pwm_ch_rd(45) & pwm_ch_rd(44); else NULL; end if;
when x"d" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(51) & pwm_ch_rd(50) & pwm_ch_rd(49) & pwm_ch_rd(48); else NULL; end if;
when x"e" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(55) & pwm_ch_rd(54) & pwm_ch_rd(53) & pwm_ch_rd(52); else NULL; end if;
when x"f" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(59) & pwm_ch_rd(58) & pwm_ch_rd(57) & pwm_ch_rd(56); else NULL; end if;
when others => NULL;
end case;
end if;
end if;
end process wr_access;
 
-- duty cycle read-back --
pwm_dc_rd_gen: process(pwm_ch)
begin
pwm_ch_rd <= (others => (others => '0'));
for i in 0 to NUM_CHANNELS-1 loop
pwm_ch_rd(i) <= pwm_ch(i);
end loop;
end process pwm_dc_rd_gen;
 
-- PWM clock select --
clkgen_en_o <= enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(prsc)));
147,20 → 178,26
pwm_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- pwm counter --
-- pwm base counter --
if (enable = '0') then
pwm_cnt <= (others => '0');
elsif (prsc_tick = '1') then
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
 
-- channels --
for i in 0 to num_pwm_channels_c-1 loop
for i in 0 to NUM_CHANNELS-1 loop
--if (pwm_cnt = pwm_ch(i)) or (pwm_ch(i) = x"00") or (enable = '0') then
-- pwm_o(i) <= '0';
--elsif (pwm_cnt = x"00") then
-- pwm_o(i) <= '1';
--end if;
if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
pwm_o(i) <= '0';
else
pwm_o(i) <= '1';
end if;
end loop; -- i, pwm channel
end loop;
end if;
end process pwm_core;
 
/neorv32_sysinfo.vhd
71,7 → 71,7
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := true; -- implement custom functions subsystem (CFS)?
143,7 → 143,7
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented?
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented?
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented?
/neorv32_top.vhd
58,7 → 58,6
 
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
79,7 → 78,7
 
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (1..64)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
 
-- Internal Instruction memory --
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
107,7 → 106,7
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
172,8 → 171,8
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
 
-- PWM (available if IO_PWM_EN = true) --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
 
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
208,13 → 207,10
constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
 
-- reset generator --
signal rstn_i_sync0 : std_ulogic;
signal rstn_i_sync1 : std_ulogic;
signal rstn_i_sync2 : std_ulogic;
signal rstn_gen : std_ulogic_vector(3 downto 0);
signal ext_rstn : std_ulogic;
signal sys_rstn : std_ulogic;
signal wdt_rstn : std_ulogic;
signal rstn_gen : std_ulogic_vector(7 downto 0);
signal ext_rstn : std_ulogic;
signal sys_rstn : std_ulogic;
signal wdt_rstn : std_ulogic;
 
-- clock generator --
signal clk_div : std_ulogic_vector(11 downto 0);
273,52 → 269,26
signal io_rden : std_ulogic;
signal io_wren : std_ulogic;
 
-- read-back buses -
signal imem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal imem_ack : std_ulogic;
signal dmem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal dmem_ack : std_ulogic;
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal bootrom_ack : std_ulogic;
signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal wishbone_ack : std_ulogic;
signal wishbone_err : std_ulogic;
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal gpio_ack : std_ulogic;
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal mtime_ack : std_ulogic;
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal uart0_ack : std_ulogic;
signal uart1_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal uart1_ack : std_ulogic;
signal spi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal spi_ack : std_ulogic;
signal twi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal twi_ack : std_ulogic;
signal pwm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal pwm_ack : std_ulogic;
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal wdt_ack : std_ulogic;
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal trng_ack : std_ulogic;
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal cfs_ack : std_ulogic;
signal nco_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal nco_ack : std_ulogic;
signal neoled_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal neoled_ack : std_ulogic;
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal sysinfo_ack : std_ulogic;
signal bus_keeper_err : std_ulogic;
signal dm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal dm_ack : std_ulogic;
-- module response bus - entry type --
type resp_bus_entry_t is record
rdata : std_ulogic_vector(data_width_c-1 downto 0);
ack : std_ulogic;
err : std_ulogic;
end record;
constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0');
 
-- module response bus - device ID --
type resp_bus_id_t is (RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI,
RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NCO, RESP_NEOLED, RESP_SYSINFO, RESP_OCD);
 
-- module response bus --
type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c);
 
-- IRQs --
signal mtime_irq : std_ulogic;
--
signal fast_irq : std_ulogic_vector(15 downto 0);
signal fast_irq_ack : std_ulogic_vector(15 downto 0);
--
signal mtime_irq : std_ulogic;
signal gpio_irq : std_ulogic;
signal wdt_irq : std_ulogic;
signal uart0_rxd_irq : std_ulogic;
332,8 → 302,9
signal neoled_irq : std_ulogic;
 
-- misc --
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
 
begin
 
366,45 → 337,32
 
-- Reset Generator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
reset_generator_sync: process(clk_i)
reset_generator: process(rstn_i, clk_i)
begin
-- make sure the external reset is free of metastability and has a minimal duration of 1 clock cycle
if rising_edge(clk_i) then
rstn_i_sync0 <= rstn_i;
rstn_i_sync1 <= rstn_i_sync0;
rstn_i_sync2 <= rstn_i_sync1;
end if;
end process reset_generator_sync;
 
-- keep internal reset active for at least 4 clock cycles
reset_generator: process(rstn_i_sync1, rstn_i_sync2, clk_i)
begin
if ((rstn_i_sync1 and rstn_i_sync2) = '0') then -- signal stable?
if (rstn_i = '0') then
rstn_gen <= (others => '0');
sys_rstn <= '0';
elsif rising_edge(clk_i) then
-- keep internal reset active for at least <rstn_gen'size> clock cycles --
rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
-- system reset: can also be triggered by watchdog and debug module --
sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn;
end if;
end process reset_generator;
 
ext_rstn <= rstn_gen(rstn_gen'left); -- the beautified external reset signal
-- beautified external reset signal --
ext_rstn <= rstn_gen(rstn_gen'left);
 
-- internal reset buffer --
soc_reset_generator: process(clk_i)
begin
if rising_edge(clk_i) then
sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn; -- system reset: can also be triggered by watchdog and debug module
end if;
end process soc_reset_generator;
 
 
-- Clock Generator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
clock_generator: process(sys_rstn, clk_i)
begin
if (sys_rstn = '0') then
clk_gen_en <= (others => '-');
clk_div <= (others => '0');
clk_div_ff <= (others => '0');
clk_gen_en <= (others => '0');
clk_div_ff <= (others => '-');
clk_gen <= (others => '-');
elsif rising_edge(clk_i) then
-- fresh clocks anyone? --
clk_gen_en(0) <= wdt_cg_en;
416,17 → 374,12
clk_gen_en(6) <= cfs_cg_en;
clk_gen_en(7) <= nco_cg_en;
clk_gen_en(8) <= neoled_cg_en;
if (or_all_f(clk_gen_en) = '1') then
-- actual clock generator --
if (or_reduce_f(clk_gen_en) = '1') then
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
end if;
-- clock enables: rising edge detectors --
clk_div_ff <= clk_div;
end if;
end process clock_generator;
 
-- clock enables: rising edge detectors --
clock_generator_edge: process(clk_i)
begin
if rising_edge(clk_i) then
clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2
clk_gen(clk_div4_c) <= clk_div(1) and (not clk_div_ff(1)); -- CLK/4
clk_gen(clk_div8_c) <= clk_div(2) and (not clk_div_ff(2)); -- CLK/8
436,7 → 389,7
clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048
clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096
end if;
end process clock_generator_edge;
end process clock_generator;
 
 
-- CPU Core -------------------------------------------------------------------------------
449,7 → 402,6
CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
467,7 → 419,7
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (1..64)
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64)
)
port map (
-- global control --
646,21 → 598,32
p_bus_err_i => p_bus.err -- bus transfer error
);
 
-- static signals --
p_bus.priv <= cpu_i.priv; -- current CPU privilege level: cpu_i.priv == cpu_d.priv
-- current CPU privilege level --
p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv
 
-- processor bus: CPU transfer data input --
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or neoled_rdata or sysinfo_rdata) or dm_rdata;
-- fence operation (unused) --
p_bus.fence <= cpu_d.fence or cpu_i.fence;
 
-- processor bus: CPU transfer ACK input --
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack) or dm_ack;
-- bus response --
bus_response: process(resp_bus, bus_keeper_err)
variable rdata_v : std_ulogic_vector(data_width_c-1 downto 0);
variable ack_v : std_ulogic;
variable err_v : std_ulogic;
begin
rdata_v := (others => '0');
ack_v := '0';
err_v := '0';
for i in resp_bus'range loop
rdata_v := rdata_v or resp_bus(i).rdata; -- read data
ack_v := ack_v or resp_bus(i).ack; -- acknowledge
err_v := err_v or resp_bus(i).err; -- error
end loop; -- i
p_bus.rdata <= rdata_v; -- processor bus: CPU transfer data input
p_bus.ack <= ack_v; -- processor bus: CPU transfer ACK input
p_bus.err <= err_v or bus_keeper_err; -- processor bus: CPU transfer data bus error input
end process;
 
-- processor bus: CPU transfer data bus error input --
p_bus.err <= bus_keeper_err or wishbone_err;
 
 
-- Processor-Internal Bus Keeper (BUS_KEEPER) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_bus_keeper_inst: neorv32_bus_keeper
699,21 → 662,21
BOOTLOADER_EN => BOOTLOADER_EN -- implement and use bootloader?
)
port map (
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => imem_rdata, -- data out
ack_o => imem_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_IMEM).rdata, -- data out
ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge
);
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
end generate;
 
neorv32_int_imem_inst_false:
if (MEM_INT_IMEM_EN = false) generate
imem_rdata <= (others => '0');
imem_ack <= '0';
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
end generate;
 
 
727,21 → 690,21
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
)
port map (
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => dmem_rdata, -- data out
ack_o => dmem_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_DMEM).rdata, -- data out
ack_o => resp_bus(RESP_DMEM).ack -- transfer acknowledge
);
resp_bus(RESP_DMEM).err <= '0'; -- no access error possible
end generate;
 
neorv32_int_dmem_inst_false:
if (MEM_INT_DMEM_EN = false) generate
dmem_rdata <= (others => '0');
dmem_ack <= '0';
resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c;
end generate;
 
 
755,18 → 718,18
BOOTROM_SIZE => boot_rom_size_c -- processor-internal boot TOM memory size in bytes
)
port map (
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
addr_i => p_bus.addr, -- address
data_o => bootrom_rdata, -- data out
ack_o => bootrom_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
addr_i => p_bus.addr, -- address
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge
);
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
end generate;
 
neorv32_boot_rom_inst_false:
if (BOOTLOADER_EN = false) generate
bootrom_rdata <= (others => '0');
bootrom_ack <= '0';
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
end generate;
 
 
788,48 → 751,47
)
port map (
-- global control --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active
-- host access --
src_i => p_bus.src, -- access type (0: data, 1:instruction)
addr_i => p_bus.addr, -- address
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => wishbone_rdata, -- data out
lock_i => p_bus.lock, -- exclusive access request
ack_o => wishbone_ack, -- transfer acknowledge
err_o => wishbone_err, -- transfer error
priv_i => p_bus.priv, -- current CPU privilege level
src_i => p_bus.src, -- access type (0: data, 1:instruction)
addr_i => p_bus.addr, -- address
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out
lock_i => p_bus.lock, -- exclusive access request
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error
priv_i => p_bus.priv, -- current CPU privilege level
-- wishbone interface --
wb_tag_o => wb_tag_o, -- request tag
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data
wb_we_o => wb_we_o, -- read/write
wb_sel_o => wb_sel_o, -- byte enable
wb_stb_o => wb_stb_o, -- strobe
wb_cyc_o => wb_cyc_o, -- valid cycle
wb_lock_o => wb_lock_o, -- exclusive access request
wb_ack_i => wb_ack_i, -- transfer acknowledge
wb_err_i => wb_err_i -- transfer error
wb_tag_o => wb_tag_o, -- request tag
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data
wb_we_o => wb_we_o, -- read/write
wb_sel_o => wb_sel_o, -- byte enable
wb_stb_o => wb_stb_o, -- strobe
wb_cyc_o => wb_cyc_o, -- valid cycle
wb_lock_o => wb_lock_o, -- exclusive access request
wb_ack_i => wb_ack_i, -- transfer acknowledge
wb_err_i => wb_err_i -- transfer error
);
end generate;
 
neorv32_wishbone_inst_false:
if (MEM_EXT_EN = false) generate
wishbone_rdata <= (others => '0');
wishbone_ack <= '0';
wishbone_err <= '0';
resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c;
--
wb_adr_o <= (others => '0');
wb_dat_o <= (others => '0');
wb_we_o <= '0';
wb_sel_o <= (others => '0');
wb_stb_o <= '0';
wb_cyc_o <= '0';
wb_tag_o <= (others => '0');
wb_adr_o <= (others => '0');
wb_dat_o <= (others => '0');
wb_we_o <= '0';
wb_sel_o <= (others => '0');
wb_stb_o <= '0';
wb_cyc_o <= '0';
wb_lock_o <= '0';
wb_tag_o <= (others => '0');
end generate;
 
 
838,7 → 800,7
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region
-- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity)
io_wren <= io_acc and p_bus.we and and_all_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region
 
 
-- Custom Functions Subsystem (CFS) -------------------------------------------------------
853,32 → 815,32
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active, use as async
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => cfs_rdata, -- data out
ack_o => cfs_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active, use as async
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_CFS).rdata, -- data out
ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => cfs_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- "clock" inputs
clkgen_en_o => cfs_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- "clock" inputs
-- CPU state --
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
-- interrupt --
irq_o => cfs_irq, -- interrupt request
irq_ack_i => cfs_irq_ack, -- interrupt acknowledge
irq_o => cfs_irq, -- interrupt request
irq_ack_i => cfs_irq_ack, -- interrupt acknowledge
-- custom io (conduit) --
cfs_in_i => cfs_in_i, -- custom inputs
cfs_out_o => cfs_out_o -- custom outputs
cfs_in_i => cfs_in_i, -- custom inputs
cfs_out_o => cfs_out_o -- custom outputs
);
resp_bus(RESP_CFS).err <= '0'; -- no access error possible
end generate;
 
neorv32_cfs_inst_false:
if (IO_CFS_EN = false) generate
cfs_rdata <= (others => '0');
cfs_ack <= '0';
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
cfs_cg_en <= '0';
cfs_irq <= '0';
cfs_out_o <= (others => '0');
892,27 → 854,27
neorv32_gpio_inst: neorv32_gpio
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => gpio_rdata, -- data out
ack_o => gpio_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_GPIO).rdata, -- data out
ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge
-- parallel io --
gpio_o => gpio_o,
gpio_i => gpio_i,
-- interrupt --
irq_o => gpio_irq -- pin-change interrupt
irq_o => gpio_irq -- pin-change interrupt
);
resp_bus(RESP_GPIO).err <= '0'; -- no access error possible
end generate;
 
neorv32_gpio_inst_false:
if (IO_GPIO_EN = false) generate
gpio_rdata <= (others => '0');
gpio_ack <= '0';
gpio_o <= (others => '0');
gpio_irq <= '0';
resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c;
gpio_o <= (others => '0');
gpio_irq <= '0';
end generate;
 
 
923,27 → 885,27
neorv32_wdt_inst: neorv32_wdt
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- global reset line, low-active
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => wdt_rdata, -- data out
ack_o => wdt_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- global reset line, low-active
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_WDT).rdata, -- data out
ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- timeout event --
irq_o => wdt_irq, -- timeout IRQ
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async!
irq_o => wdt_irq, -- timeout IRQ
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async!
);
resp_bus(RESP_WDT).err <= '0'; -- no access error possible
end generate;
 
neorv32_wdt_inst_false:
if (IO_WDT_EN = false) generate
wdt_rdata <= (others => '0');
wdt_ack <= '0';
resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c;
wdt_irq <= '0';
wdt_rstn <= '1';
wdt_cg_en <= '0';
957,32 → 919,49
neorv32_mtime_inst: neorv32_mtime
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset, low-active, async
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => mtime_rdata, -- data out
ack_o => mtime_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_MTIME).rdata, -- data out
ack_o => resp_bus(RESP_MTIME).ack, -- transfer acknowledge
-- time output for CPU --
time_o => mtime_time, -- current system time
time_o => mtime_time, -- current system time
-- interrupt --
irq_o => mtime_irq -- interrupt request
irq_o => mtime_irq -- interrupt request
);
resp_bus(RESP_MTIME).err <= '0'; -- no access error possible
end generate;
 
neorv32_mtime_inst_false:
if (IO_MTIME_EN = false) generate
mtime_rdata <= (others => '0');
mtime_time <= mtime_i; -- use external machine timer time signal
mtime_ack <= '0';
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c;
mtime_time <= mtime_i; -- use external machine timer time signal
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
end generate;
 
mtime_o <= mtime_time when (IO_MTIME_EN = true) else (others => '0'); -- system time output
 
-- system time output LO --
mtime_sync: process(clk_i)
begin
if rising_edge(clk_i) then
-- buffer low word one clock cycle to compensate for MTIME's 1-cycle delay
-- when overflowing from low-word to high-word -> only relevant for processor-external devices
-- processor-internal devices (= the CPU) do not care about this delay offset as 64-bit MTIME.TIME
-- cannot be accessed within a single cycle
if (IO_MTIME_EN = true) then
mtime_o(31 downto 0) <= mtime_time(31 downto 0);
else
mtime_o(31 downto 0) <= (others => '0');
end if;
end if;
end process mtime_sync;
 
-- system time output HI --
mtime_o(63 downto 32) <= mtime_time(63 downto 32) when (IO_MTIME_EN = true) else (others => '0');
 
 
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
-- -------------------------------------------------------------------------------------------
neorv32_uart0_inst_true:
993,32 → 972,32
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart0_rdata, -- data out
ack_o => uart0_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_UART0).rdata, -- data out
ack_o => resp_bus(RESP_UART0).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart0_cg_en, -- enable clock generator
clkgen_en_o => uart0_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart0_txd_o,
uart_rxd_i => uart0_rxd_i,
-- hardware flow control --
uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional
uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
);
resp_bus(RESP_UART0).err <= '0'; -- no access error possible
end generate;
 
neorv32_uart0_inst_false:
if (IO_UART0_EN = false) generate
uart0_rdata <= (others => '0');
uart0_ack <= '0';
resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c;
uart0_txd_o <= '0';
uart0_rts_o <= '0';
uart0_cg_en <= '0';
1037,32 → 1016,32
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => uart1_rdata, -- data out
ack_o => uart1_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_UART1).rdata, -- data out
ack_o => resp_bus(RESP_UART1).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart1_cg_en, -- enable clock generator
clkgen_en_o => uart1_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart1_txd_o,
uart_rxd_i => uart1_rxd_i,
-- hardware flow control --
uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional
uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional
-- interrupts --
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
);
resp_bus(RESP_UART1).err <= '0'; -- no access error possible
end generate;
 
neorv32_uart1_inst_false:
if (IO_UART1_EN = false) generate
uart1_rdata <= (others => '0');
uart1_ack <= '0';
resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c;
uart1_txd_o <= '0';
uart1_rts_o <= '0';
uart1_cg_en <= '0';
1078,35 → 1057,35
neorv32_spi_inst: neorv32_spi
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => spi_rdata, -- data out
ack_o => spi_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_SPI).rdata, -- data out
ack_o => resp_bus(RESP_SPI).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
spi_sck_o => spi_sck_o, -- SPI serial clock
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o, -- SPI CS
spi_sck_o => spi_sck_o, -- SPI serial clock
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o, -- SPI CS
-- interrupt --
irq_o => spi_irq -- transmission done interrupt
irq_o => spi_irq -- transmission done interrupt
);
resp_bus(RESP_SPI).err <= '0'; -- no access error possible
end generate;
 
neorv32_spi_inst_false:
if (IO_SPI_EN = false) generate
spi_rdata <= (others => '0');
spi_ack <= '0';
spi_sck_o <= '0';
spi_sdo_o <= '0';
spi_csn_o <= (others => '1'); -- CSn lines are low-active
spi_cg_en <= '0';
spi_irq <= '0';
resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c;
spi_sck_o <= '0';
spi_sdo_o <= '0';
spi_csn_o <= (others => '1'); -- CSn lines are low-active
spi_cg_en <= '0';
spi_irq <= '0';
end generate;
 
 
1117,28 → 1096,28
neorv32_twi_inst: neorv32_twi
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => twi_rdata, -- data out
ack_o => twi_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_TWI).rdata, -- data out
ack_o => resp_bus(RESP_TWI).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => twi_cg_en, -- enable clock generator
clkgen_en_o => twi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
twi_sda_io => twi_sda_io, -- serial data line
twi_scl_io => twi_scl_io, -- serial clock line
twi_sda_io => twi_sda_io, -- serial data line
twi_scl_io => twi_scl_io, -- serial clock line
-- interrupt --
irq_o => twi_irq -- transfer done IRQ
irq_o => twi_irq -- transfer done IRQ
);
resp_bus(RESP_TWI).err <= '0'; -- no access error possible
end generate;
 
neorv32_twi_inst_false:
if (IO_TWI_EN = false) generate
twi_rdata <= (others => '0');
twi_ack <= '0';
resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
-- twi_sda_io <= 'Z'; -- FIXME?
-- twi_scl_io <= 'Z'; -- FIXME?
twi_cg_en <= '0';
1149,29 → 1128,32
-- Pulse-Width Modulation Controller (PWM) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_pwm_inst_true:
if (IO_PWM_EN = true) generate
if (IO_PWM_NUM_CH > 0) generate
neorv32_pwm_inst: neorv32_pwm
generic map (
NUM_CHANNELS => IO_PWM_NUM_CH -- number of PWM channels (0..60)
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => pwm_rdata, -- data out
ack_o => pwm_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_PWM).rdata, -- data out
ack_o => resp_bus(RESP_PWM).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- pwm output channels --
pwm_o => pwm_o
);
resp_bus(RESP_PWM).err <= '0'; -- no access error possible
end generate;
 
neorv32_pwm_inst_false:
if (IO_PWM_EN = false) generate
pwm_rdata <= (others => '0');
pwm_ack <= '0';
if (IO_PWM_NUM_CH = 0) generate
resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c;
pwm_cg_en <= '0';
pwm_o <= (others => '0');
end generate;
1184,25 → 1166,25
neorv32_nco_inst: neorv32_nco
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => nco_rdata, -- data out
ack_o => nco_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_NCO).rdata, -- data out
ack_o => resp_bus(RESP_NCO).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => nco_cg_en, -- enable clock generator
clkgen_en_o => nco_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- NCO output --
nco_o => nco_o
);
resp_bus(RESP_NCO).err <= '0'; -- no access error possible
end generate;
 
neorv32_nco_inst_false:
if (IO_NCO_EN = false) generate
nco_rdata <= (others => '0');
nco_ack <= '0';
resp_bus(RESP_NCO) <= resp_bus_entry_terminate_c;
nco_cg_en <= '0';
nco_o <= (others => '0');
end generate;
1215,20 → 1197,20
neorv32_trng_inst: neorv32_trng
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => trng_rdata, -- data out
ack_o => trng_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_TRNG).rdata, -- data out
ack_o => resp_bus(RESP_TRNG).ack -- transfer acknowledge
);
resp_bus(RESP_TRNG).err <= '0'; -- no access error possible
end generate;
 
neorv32_trng_inst_false:
if (IO_TRNG_EN = false) generate
trng_rdata <= (others => '0');
trng_ack <= '0';
resp_bus(RESP_TRNG) <= resp_bus_entry_terminate_c;
end generate;
 
 
1239,27 → 1221,27
neorv32_neoled_inst: neorv32_neoled
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => neoled_rdata, -- data out
ack_o => neoled_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_NEOLED).rdata, -- data out
ack_o => resp_bus(RESP_NEOLED).ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => neoled_cg_en, -- enable clock generator
clkgen_en_o => neoled_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- interrupt --
irq_o => neoled_irq, -- interrupt request
irq_o => neoled_irq, -- interrupt request
-- NEOLED output --
neoled_o => neoled_o -- serial async data line
neoled_o => neoled_o -- serial async data line
);
resp_bus(RESP_NEOLED).err <= '0'; -- no access error possible
end generate;
 
neorv32_neoled_inst_false:
if (IO_NEOLED_EN = false) generate
neoled_rdata <= (others => '0');
neoled_ack <= '0';
resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c;
neoled_cg_en <= '0';
neoled_irq <= '0';
neoled_o <= '0';
1297,7 → 1279,7
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
1306,14 → 1288,16
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
data_o => sysinfo_rdata, -- data out
ack_o => sysinfo_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
data_o => resp_bus(RESP_SYSINFO).rdata, -- data out
ack_o => resp_bus(RESP_SYSINFO).ack -- transfer acknowledge
);
 
resp_bus(RESP_SYSINFO).err <= '0'; -- no access error possible
 
 
-- **************************************************************************************************************************
-- On-Chip Debugger Complex
-- **************************************************************************************************************************
1326,8 → 1310,8
neorv32_debug_dm_inst: neorv32_debug_dm
port map (
-- global control --
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- external reset, low-active
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- external reset, low-active
-- debug module interface (DMI) --
dmi_rstn_i => dmi.rstn,
dmi_req_valid_i => dmi.req_valid,
1335,21 → 1319,22
dmi_req_addr_i => dmi.req_addr,
dmi_req_op_i => dmi.req_op,
dmi_req_data_i => dmi.req_data,
dmi_resp_valid_o => dmi.resp_valid, -- response valid when set
dmi_resp_ready_i => dmi.resp_ready, -- ready to receive respond
dmi_resp_valid_o => dmi.resp_valid, -- response valid when set
dmi_resp_ready_i => dmi.resp_ready, -- ready to receive respond
dmi_resp_data_o => dmi.resp_data,
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error
-- CPU bus access --
cpu_addr_i => p_bus.addr, -- address
cpu_rden_i => p_bus.re, -- read enable
cpu_wren_i => p_bus.we, -- write enable
cpu_data_i => p_bus.wdata, -- data in
cpu_data_o => dm_rdata, -- data out
cpu_ack_o => dm_ack, -- transfer acknowledge
cpu_addr_i => p_bus.addr, -- address
cpu_rden_i => p_bus.re, -- read enable
cpu_wren_i => p_bus.we, -- write enable
cpu_data_i => p_bus.wdata, -- data in
cpu_data_o => resp_bus(RESP_OCD).rdata, -- data out
cpu_ack_o => resp_bus(RESP_OCD).ack, -- transfer acknowledge
-- CPU control --
cpu_ndmrstn_o => dci_ndmrstn, -- soc reset
cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode)
cpu_ndmrstn_o => dci_ndmrstn, -- soc reset
cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode)
);
resp_bus(RESP_OCD).err <= '0'; -- no access error possible
end generate;
 
neorv32_debug_dm_false:
1359,10 → 1344,9
dmi.resp_data <= (others => '0');
dmi.resp_err <= '0';
--
dci_ndmrstn <= '0';
dci_halt_req <= '0';
dm_rdata <= (others => '0');
dm_ack <= '0';
resp_bus(RESP_OCD) <= resp_bus_entry_terminate_c;
dci_ndmrstn <= '1';
dci_halt_req <= '0';
end generate;
 
 
/neorv32_trng.vhd
124,10 → 124,11
 
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Total number of ring-oscillators has to be >0." severity error;
assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters in fisrt ring has to be odd." severity error;
assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters increment for each next ring has to be even." severity error;
assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Total number of ring-oscillators has to be >0." severity error;
assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters in fisrt ring has to be odd." severity error;
assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters increment for each next ring has to be even." severity error;
 
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
190,7 → 191,7
neumann_debiasing_sync: process(clk_i)
begin
if rising_edge(clk_i) then
debiasing.sreg <= debiasing.sreg(debiasing.sreg'left-1 downto 0) & xor_all_f(osc_array_data);
debiasing.sreg <= debiasing.sreg(debiasing.sreg'left-1 downto 0) & xor_reduce_f(osc_array_data);
debiasing.state <= (not debiasing.state) and osc_array_en_out(num_roscs_c-1); -- start toggling when last RO is enabled -> process in every second cycle
end if;
end process neumann_debiasing_sync;
225,7 → 226,7
processing.cnt <= std_ulogic_vector(unsigned(processing.cnt) + 1);
end if;
if (lfsr_en_c = true) then -- LFSR post-processing
processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & (xnor_all_f(processing.sreg and lfsr_taps_c) xnor debiasing.data);
processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & ((not xor_reduce_f(processing.sreg and lfsr_taps_c)) xnor debiasing.data);
else -- NO post-processing
processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & debiasing.data;
end if;
321,11 → 322,6
 
begin
 
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not ((NUM_INV mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TNRG.ring_oscillator - Number of inverters in ring has to be odd." severity error;
 
 
-- Ring Oscillator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ring_osc: process(enable_i, enable_sreg, inv_chain)
/neorv32_uart.vhd
241,8 → 241,8
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
data_o(ctrl_uart_cts_c) <= uart_cts_ff(1);
else -- uart_id_rtx_addr_c
data_o(data_rx_avail_c) <= or_all_f(uart_rx.avail);
data_o(data_rx_overr_c) <= and_all_f(uart_rx.avail);
data_o(data_rx_avail_c) <= or_reduce_f(uart_rx.avail);
data_o(data_rx_overr_c) <= and_reduce_f(uart_rx.avail);
data_o(data_rx_ferr_c) <= uart_rx.ferr_rd;
data_o(data_rx_perr_c) <= uart_rx.perr_rd;
data_o(7 downto 0) <= uart_rx.data_rd;
280,7 → 280,7
uart_tx.sreg(0) <= '1';
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
uart_tx.sreg <= '1' & (xor_reduce_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
else
uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
end if;
344,7 → 344,7
if (uart_rx.bitcnt = "0000") then
uart_rx.busy <= '0'; -- done
-- data buffer (double buffering) --
uart_rx.perr(0) <= ctrl(ctrl_uart_pmode1_c) and (xor_all_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
uart_rx.perr(0) <= ctrl(ctrl_uart_pmode1_c) and (xor_reduce_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
uart_rx.ferr(0) <= not uart_rx.sreg(9); -- check stop bit (error if not set)
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_rx.data(0) <= uart_rx.sreg(7 downto 0);
/neorv32_wishbone.vhd
193,12 → 193,12
-- buffer all outgoing signals --
ctrl.we <= wren_i or ctrl.wr_req;
ctrl.adr <= addr_i;
if (xbus_big_endian_c = true) then -- endianness conversion
if (xbus_big_endian_c = true) then -- big-endian
ctrl.wdat <= bswap32_f(data_i);
ctrl.sel <= bit_rev_f(ben_i);
else -- little-endian
ctrl.wdat <= data_i;
ctrl.sel <= ben_i;
else
ctrl.wdat <= bswap32_f(data_i);
ctrl.sel <= bit_rev_f(ben_i);
end if;
ctrl.src <= src_i;
ctrl.lock <= lock_i;
217,7 → 217,7
elsif (wb_ack_i = '1') then -- normal bus termination
ctrl.ack <= '1';
ctrl.state <= IDLE;
elsif (timeout_en_c = true) and (or_all_f(ctrl.timeout) = '0') then -- valid timeout
elsif (timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0') then -- valid timeout
ctrl.err <= '1';
ctrl.state <= IDLE;
end if;
243,7 → 243,7
end process bus_arbiter;
 
-- host access --
data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
data_o <= ctrl.rdat when (xbus_big_endian_c = false) else bswap32_f(ctrl.rdat); -- endianness conversion
ack_o <= ctrl.ack;
err_o <= ctrl.err;
 

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