OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 9 to Rev 11
    ↔ Reverse comparison
  •

Rev 9 → Rev 11

/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin>
 
library ieee;
use ieee.std_logic_1164.all;
8,888 → 8,1146
 
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000013",
00000001 => x"00000093",
00000002 => x"00008113",
00000003 => x"00010193",
00000004 => x"00018213",
00000005 => x"00020293",
00000006 => x"00028313",
00000007 => x"00030393",
00000008 => x"00038413",
00000009 => x"00040493",
00000010 => x"00048513",
00000011 => x"00050593",
00000012 => x"00058613",
00000013 => x"00060693",
00000014 => x"00068713",
00000015 => x"00070793",
00000016 => x"00078813",
00000017 => x"00080893",
00000018 => x"00088913",
00000019 => x"00090993",
00000020 => x"00098a13",
00000021 => x"000a0a93",
00000022 => x"000a8b13",
00000023 => x"000b0b93",
00000024 => x"000b8c13",
00000025 => x"000c0c93",
00000026 => x"000c8d13",
00000027 => x"000d0d93",
00000028 => x"000d8e13",
00000029 => x"000e0e93",
00000030 => x"000e8f13",
00000031 => x"000f0f93",
00000032 => x"00000013",
00000033 => x"fc5025f3",
00000034 => x"fc702673",
00000035 => x"00c58133",
00000036 => x"ffc10113",
00000037 => x"00010413",
00000038 => x"80000197",
00000039 => x"7e818193",
00000040 => x"00000597",
00000041 => x"0b458593",
00000042 => x"30559073",
00000043 => x"fc5025f3",
00000044 => x"00000617",
00000045 => x"1f060613",
00000046 => x"02000693",
00000047 => x"00c5a023",
00000048 => x"00458593",
00000049 => x"fff68693",
00000050 => x"fed01ae3",
00000051 => x"f8000593",
00000052 => x"0005a023",
00000053 => x"00458593",
00000054 => x"feb01ce3",
00000055 => x"fff00593",
00000056 => x"f8b02c23",
00000057 => x"f8b02e23",
00000058 => x"80000597",
00000059 => x"f9858593",
00000060 => x"80000617",
00000061 => x"f9060613",
00000062 => x"00c5d863",
00000063 => x"00058023",
00000064 => x"00158593",
00000065 => x"ff5ff06f",
00000066 => x"00001597",
00000067 => x"cc058593",
00000068 => x"80000617",
00000069 => x"f7060613",
00000070 => x"80000697",
00000071 => x"f6868693",
00000072 => x"00d65c63",
00000073 => x"00058703",
00000074 => x"00e60023",
00000075 => x"00158593",
00000076 => x"00160613",
00000077 => x"fedff06f",
00000078 => x"00000513",
00000079 => x"00000593",
00000080 => x"164000ef",
00000081 => x"10500073",
00000082 => x"30047073",
00000083 => x"10500073",
00000084 => x"0000006f",
00000085 => x"f8810113",
00000086 => x"00112023",
00000087 => x"00312223",
00000088 => x"00412423",
00000089 => x"00512623",
00000090 => x"00612823",
00000091 => x"00712a23",
00000092 => x"00812c23",
00000093 => x"00912e23",
00000094 => x"02a12023",
00000095 => x"02b12223",
00000096 => x"02c12423",
00000097 => x"02d12623",
00000098 => x"02e12823",
00000099 => x"02f12a23",
00000100 => x"03012c23",
00000101 => x"03112e23",
00000102 => x"05212023",
00000103 => x"05312223",
00000104 => x"05412423",
00000105 => x"05512623",
00000106 => x"05612823",
00000107 => x"05712a23",
00000108 => x"05812c23",
00000109 => x"05912e23",
00000110 => x"07a12023",
00000111 => x"07b12223",
00000112 => x"07c12423",
00000113 => x"07d12623",
00000114 => x"07e12823",
00000115 => x"07f12a23",
00000116 => x"342022f3",
00000117 => x"00f2f313",
00000118 => x"00231313",
00000119 => x"fc5020f3",
00000120 => x"00130333",
00000121 => x"341020f3",
00000122 => x"0002cc63",
00000123 => x"34a022f3",
00000124 => x"0022f293",
00000125 => x"00208093",
00000126 => x"005080b3",
00000127 => x"0080006f",
00000128 => x"04030313",
00000129 => x"00032283",
00000130 => x"ffc10113",
00000131 => x"00112023",
00000132 => x"000280e7",
00000133 => x"00012083",
00000134 => x"00410113",
00000135 => x"34109073",
00000136 => x"00012083",
00000137 => x"00412183",
00000138 => x"00812203",
00000139 => x"00c12283",
00000140 => x"01012303",
00000141 => x"01412383",
00000142 => x"01812403",
00000143 => x"01c12483",
00000144 => x"02012503",
00000145 => x"02412583",
00000146 => x"02812603",
00000147 => x"02c12683",
00000148 => x"03012703",
00000149 => x"03412783",
00000150 => x"03812803",
00000151 => x"03c12883",
00000152 => x"04012903",
00000153 => x"04412983",
00000154 => x"04812a03",
00000155 => x"04c12a83",
00000156 => x"05012b03",
00000157 => x"05412b83",
00000158 => x"05812c03",
00000159 => x"05c12c83",
00000160 => x"06012d03",
00000161 => x"06412d83",
00000162 => x"06812e03",
00000163 => x"06c12e83",
00000164 => x"07012f03",
00000165 => x"07412f83",
00000166 => x"07810113",
00000167 => x"30200073",
00000168 => x"00008067",
00000169 => x"ff010113",
00000170 => x"00112623",
00000171 => x"00812423",
00000172 => x"6cc000ef",
00000173 => x"04050663",
00000174 => x"2c8000ef",
00000175 => x"00005537",
00000176 => x"00000613",
00000177 => x"00000593",
00000178 => x"b0050513",
00000179 => x"408000ef",
00000180 => x"00001537",
00000181 => x"adc50513",
00000182 => x"498000ef",
00000183 => x"00000513",
00000184 => x"6ac000ef",
00000185 => x"00000413",
00000186 => x"0ff47513",
00000187 => x"6a0000ef",
00000188 => x"0c800513",
00000189 => x"6d0000ef",
00000190 => x"00140413",
00000191 => x"fedff06f",
00000192 => x"00c12083",
00000193 => x"00812403",
00000194 => x"01010113",
00000195 => x"00008067",
00000196 => x"00001537",
00000197 => x"ff010113",
00000198 => x"af850513",
00000199 => x"00112623",
00000200 => x"00812423",
00000201 => x"00912223",
00000202 => x"01212023",
00000203 => x"49c000ef",
00000204 => x"c81025f3",
00000205 => x"c0102673",
00000206 => x"00001537",
00000207 => x"b2050513",
00000208 => x"488000ef",
00000209 => x"34202473",
00000210 => x"34102973",
00000211 => x"34a024f3",
00000212 => x"04045663",
00000213 => x"00001537",
00000214 => x"b3850513",
00000215 => x"46c000ef",
00000216 => x"00001537",
00000217 => x"00090593",
00000218 => x"b5050513",
00000219 => x"45c000ef",
00000220 => x"00001537",
00000221 => x"b7050513",
00000222 => x"450000ef",
00000223 => x"00b00793",
00000224 => x"0487e063",
00000225 => x"00001737",
00000226 => x"00241793",
00000227 => x"d7c70713",
00000228 => x"00e787b3",
00000229 => x"0007a783",
00000230 => x"00078067",
00000231 => x"00001537",
00000232 => x"b4450513",
00000233 => x"424000ef",
00000234 => x"0024f793",
00000235 => x"00079663",
00000236 => x"ffc90913",
00000237 => x"fadff06f",
00000238 => x"ffe90913",
00000239 => x"fa5ff06f",
00000240 => x"800007b7",
00000241 => x"00778713",
00000242 => x"10e40e63",
00000243 => x"00b78713",
00000244 => x"12e40063",
00000245 => x"00378793",
00000246 => x"10f40063",
00000247 => x"00001537",
00000248 => x"00040593",
00000249 => x"cd450513",
00000250 => x"3e0000ef",
00000251 => x"0100006f",
00000252 => x"00001537",
00000253 => x"b7850513",
00000254 => x"3d0000ef",
00000255 => x"00001537",
00000256 => x"d6850513",
00000257 => x"0240006f",
00000258 => x"00001537",
00000259 => x"b9850513",
00000260 => x"fe9ff06f",
00000261 => x"00001537",
00000262 => x"bb450513",
00000263 => x"3ac000ef",
00000264 => x"00001537",
00000265 => x"bc850513",
00000266 => x"3a0000ef",
00000267 => x"343025f3",
00000268 => x"00001537",
00000269 => x"ce450513",
00000270 => x"390000ef",
00000271 => x"00001537",
00000272 => x"00048593",
00000273 => x"cec50513",
00000274 => x"0024f493",
00000275 => x"37c000ef",
00000276 => x"00049863",
00000277 => x"00001537",
00000278 => x"d0850513",
00000279 => x"36c000ef",
00000280 => x"341025f3",
00000281 => x"00001537",
00000282 => x"d1850513",
00000283 => x"35c000ef",
00000284 => x"00812403",
00000285 => x"00c12083",
00000286 => x"00412483",
00000287 => x"00012903",
00000288 => x"00001537",
00000289 => x"d4050513",
00000290 => x"01010113",
00000291 => x"33c0006f",
00000292 => x"00001537",
00000293 => x"be050513",
00000294 => x"f61ff06f",
00000295 => x"00001537",
00000296 => x"bf450513",
00000297 => x"f55ff06f",
00000298 => x"00001537",
00000299 => x"c0c50513",
00000300 => x"f49ff06f",
00000301 => x"00001537",
00000302 => x"c2050513",
00000303 => x"f3dff06f",
00000304 => x"00001537",
00000305 => x"c3c50513",
00000306 => x"f31ff06f",
00000307 => x"00001537",
00000308 => x"c5050513",
00000309 => x"f25ff06f",
00000310 => x"00001537",
00000311 => x"c6c50513",
00000312 => x"f19ff06f",
00000313 => x"00001537",
00000314 => x"c8850513",
00000315 => x"f0dff06f",
00000316 => x"00001537",
00000317 => x"cac50513",
00000318 => x"f01ff06f",
00000319 => x"ff010113",
00000320 => x"00812423",
00000321 => x"00912223",
00000322 => x"00112623",
00000323 => x"00700793",
00000324 => x"00050413",
00000325 => x"00058493",
00000326 => x"02a7fc63",
00000327 => x"00b00793",
00000328 => x"02f50863",
00000329 => x"01300793",
00000330 => x"02f50063",
00000331 => x"01700793",
00000332 => x"04f50463",
00000333 => x"01b00793",
00000334 => x"00100513",
00000335 => x"02f41463",
00000336 => x"00b00513",
00000337 => x"0080006f",
00000338 => x"00300513",
00000339 => x"448000ef",
00000340 => x"fc502573",
00000341 => x"00241413",
00000342 => x"00a40433",
00000343 => x"00942023",
00000344 => x"00000513",
00000345 => x"00c12083",
00000346 => x"00812403",
00000347 => x"00412483",
00000348 => x"01010113",
00000349 => x"00008067",
00000350 => x"00700513",
00000351 => x"fd1ff06f",
00000352 => x"ff010113",
00000353 => x"00812423",
00000354 => x"00912223",
00000355 => x"01212023",
00000356 => x"00112623",
00000357 => x"00000413",
00000358 => x"02000493",
00000359 => x"00040513",
00000360 => x"00140413",
00000361 => x"31000593",
00000362 => x"0ff47413",
00000363 => x"f51ff0ef",
00000364 => x"fe9416e3",
00000365 => x"00c12083",
00000366 => x"00812403",
00000367 => x"00412483",
00000368 => x"00012903",
00000369 => x"01010113",
00000370 => x"00008067",
00000371 => x"fd010113",
00000372 => x"02812423",
00000373 => x"02912223",
00000374 => x"03212023",
00000375 => x"01312e23",
00000376 => x"01412c23",
00000377 => x"02112623",
00000378 => x"01512a23",
00000379 => x"00001a37",
00000380 => x"00050493",
00000381 => x"00058413",
00000382 => x"00058523",
00000383 => x"00000993",
00000384 => x"00410913",
00000385 => x"daca0a13",
00000386 => x"00a00593",
00000387 => x"00048513",
00000388 => x"468000ef",
00000389 => x"00aa0533",
00000390 => x"00054783",
00000391 => x"01390ab3",
00000392 => x"00048513",
00000393 => x"00fa8023",
00000394 => x"00a00593",
00000395 => x"404000ef",
00000396 => x"00198993",
00000397 => x"00a00793",
00000398 => x"00050493",
00000399 => x"fcf996e3",
00000400 => x"00090693",
00000401 => x"00900713",
00000402 => x"03000613",
00000403 => x"0096c583",
00000404 => x"00070793",
00000405 => x"fff70713",
00000406 => x"01071713",
00000407 => x"01075713",
00000408 => x"00c59a63",
00000409 => x"000684a3",
00000410 => x"fff68693",
00000411 => x"fe0710e3",
00000412 => x"00000793",
00000413 => x"00f907b3",
00000414 => x"00000593",
00000415 => x"0007c703",
00000416 => x"00070c63",
00000417 => x"00158693",
00000418 => x"00b405b3",
00000419 => x"00e58023",
00000420 => x"01069593",
00000421 => x"0105d593",
00000422 => x"fff78713",
00000423 => x"02f91863",
00000424 => x"00b40433",
00000425 => x"00040023",
00000426 => x"02c12083",
00000427 => x"02812403",
00000428 => x"02412483",
00000429 => x"02012903",
00000430 => x"01c12983",
00000431 => x"01812a03",
00000432 => x"01412a83",
00000433 => x"03010113",
00000434 => x"00008067",
00000435 => x"00070793",
00000436 => x"fadff06f",
00000437 => x"fa002023",
00000438 => x"fc1026f3",
00000439 => x"00000713",
00000440 => x"00151513",
00000441 => x"04a6f263",
00000442 => x"000016b7",
00000443 => x"00000793",
00000444 => x"ffe68693",
00000445 => x"04e6e463",
00000446 => x"00167613",
00000447 => x"0015f593",
00000448 => x"01879793",
00000449 => x"01e61613",
00000450 => x"00c7e7b3",
00000451 => x"01d59593",
00000452 => x"00b7e7b3",
00000453 => x"00e7e7b3",
00000454 => x"10000737",
00000455 => x"00e7e7b3",
00000456 => x"faf02023",
00000457 => x"00008067",
00000458 => x"00170793",
00000459 => x"01079713",
00000460 => x"40a686b3",
00000461 => x"01075713",
00000462 => x"fadff06f",
00000463 => x"ffe78513",
00000464 => x"0fd57513",
00000465 => x"00051a63",
00000466 => x"00375713",
00000467 => x"00178793",
00000468 => x"0ff7f793",
00000469 => x"fa1ff06f",
00000470 => x"00175713",
00000471 => x"ff1ff06f",
00000472 => x"fa002783",
00000473 => x"fe07cee3",
00000474 => x"faa02223",
00000475 => x"00008067",
00000476 => x"ff010113",
00000477 => x"00812423",
00000478 => x"01212023",
00000479 => x"00112623",
00000480 => x"00912223",
00000481 => x"00050413",
00000482 => x"00a00913",
00000483 => x"00044483",
00000484 => x"00140413",
00000485 => x"00049e63",
00000486 => x"00c12083",
00000487 => x"00812403",
00000488 => x"00412483",
00000489 => x"00012903",
00000490 => x"01010113",
00000491 => x"00008067",
00000492 => x"01249663",
00000493 => x"00d00513",
00000494 => x"fa9ff0ef",
00000495 => x"00048513",
00000496 => x"fa1ff0ef",
00000497 => x"fc9ff06f",
00000498 => x"fa010113",
00000499 => x"02912a23",
00000500 => x"04f12a23",
00000501 => x"000014b7",
00000502 => x"04410793",
00000503 => x"02812c23",
00000504 => x"03212823",
00000505 => x"03412423",
00000506 => x"03512223",
00000507 => x"03612023",
00000508 => x"01712e23",
00000509 => x"02112e23",
00000510 => x"03312623",
00000511 => x"01812c23",
00000512 => x"00050413",
00000513 => x"04b12223",
00000514 => x"04c12423",
00000515 => x"04d12623",
00000516 => x"04e12823",
00000517 => x"05012c23",
00000518 => x"05112e23",
00000519 => x"00f12023",
00000520 => x"02500a13",
00000521 => x"00a00a93",
00000522 => x"07300913",
00000523 => x"07500b13",
00000524 => x"07800b93",
00000525 => x"db848493",
00000526 => x"00044c03",
00000527 => x"020c0463",
00000528 => x"134c1263",
00000529 => x"00144783",
00000530 => x"00240993",
00000531 => x"09278c63",
00000532 => x"04f96263",
00000533 => x"06300713",
00000534 => x"0ae78463",
00000535 => x"06900713",
00000536 => x"0ae78c63",
00000537 => x"03c12083",
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00000539 => x"03412483",
00000540 => x"03012903",
00000541 => x"02c12983",
00000542 => x"02812a03",
00000543 => x"02412a83",
00000544 => x"02012b03",
00000545 => x"01c12b83",
00000546 => x"01812c03",
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00000549 => x"0b678c63",
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00000553 => x"00068513",
00000554 => x"0007a583",
00000555 => x"00478713",
00000556 => x"00e12023",
00000557 => x"02000613",
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00000560 => x"00f7f793",
00000561 => x"00f487b3",
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00000584 => x"00478713",
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00000600 => x"fe1ff06f",
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00000604 => x"00140993",
00000605 => x"000c0513",
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00000625 => x"ff010113",
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00000640 => x"fddff06f",
00000641 => x"00050613",
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00000643 => x"0015f693",
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00000646 => x"0015d593",
00000647 => x"00161613",
00000648 => x"fe0596e3",
00000649 => x"00008067",
00000650 => x"06054063",
00000651 => x"0605c663",
00000652 => x"00058613",
00000653 => x"00050593",
00000654 => x"fff00513",
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00000661 => x"feb66ae3",
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00000666 => x"0016d693",
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00000668 => x"fe0696e3",
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00000671 => x"fb5ff0ef",
00000672 => x"00058513",
00000673 => x"00028067",
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/neorv32_bootloader_image.vhd
41,982 → 41,988
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others => x"00000000"
);
 
/neorv32_cpu.vhd
88,20 → 88,23
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- bus interface --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
);
end neorv32_cpu;
 
126,7 → 129,6
signal be_instr : std_ulogic; -- bus error on instruction access
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
signal bus_busy : std_ulogic; -- bus unit is busy
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
201,6 → 203,8
-- external interrupt --
clic_irq_i => clic_irq_i, -- CLIC interrupt request
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
-- system time input from MTIME --
time_i => time_i, -- current system time
-- bus access exceptions --
mar_i => mar, -- memory address register
ma_instr_i => ma_instr, -- misaligned instruction address
209,7 → 213,6
be_instr_i => be_instr, -- bus error on instruction access
be_load_i => be_load, -- bus error on load data access
be_store_i => be_store, -- bus error on store data access
bus_exc_ack_o => bus_exc_ack, -- bus exception error acknowledge
bus_busy_i => bus_busy -- bus unit is busy
);
 
238,6 → 241,9
-- ALU ------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_alu_inst: neorv32_cpu_alu
generic map (
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
299,40 → 305,41
-- -------------------------------------------------------------------------------------------
neorv32_cpu_bus_inst: neorv32_cpu_bus
generic map (
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
-- data input --
wdata_i => rs2, -- write data
pc_i => fetch_pc, -- current PC for instruction fetch
alu_i => alu_res, -- ALU result
wdata_i => rs2, -- write data
pc_i => fetch_pc, -- current PC for instruction fetch
alu_i => alu_res, -- ALU result
-- data output --
instr_o => instr, -- instruction
rdata_o => rdata, -- read data
instr_o => instr, -- instruction
rdata_o => rdata, -- read data
-- status --
mar_o => mar, -- current memory address register
ma_instr_o => ma_instr, -- misaligned instruction address
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_instr_o => be_instr, -- bus error on instruction access
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
bus_wait_o => bus_wait, -- wait for bus operation to finish
bus_busy_o => bus_busy, -- bus unit is busy
exc_ack_i => bus_exc_ack, -- exception controller ACK
mar_o => mar, -- current memory address register
ma_instr_o => ma_instr, -- misaligned instruction address
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_instr_o => be_instr, -- bus error on instruction access
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
bus_wait_o => bus_wait, -- wait for bus operation to finish
bus_busy_o => bus_busy, -- bus unit is busy
-- bus system --
bus_addr_o => bus_addr_o, -- bus access address
bus_rdata_i => bus_rdata_i, -- bus read data
bus_wdata_o => bus_wdata_o, -- bus write data
bus_ben_o => bus_ben_o, -- byte enable
bus_we_o => bus_we_o, -- write enable
bus_re_o => bus_re_o, -- read enable
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
bus_err_i => bus_err_i -- bus transfer error
bus_addr_o => bus_addr_o, -- bus access address
bus_rdata_i => bus_rdata_i, -- bus read data
bus_wdata_o => bus_wdata_o, -- bus write data
bus_ben_o => bus_ben_o, -- byte enable
bus_we_o => bus_we_o, -- write enable
bus_re_o => bus_re_o, -- read enable
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
bus_err_i => bus_err_i -- bus transfer error
);
 
 
/neorv32_cpu_alu.vhd
42,6 → 42,9
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_alu is
generic (
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
200,7 → 203,7
cp_rb_ff0 <= '0';
cp_rb_ff1 <= '0';
elsif rising_edge(clk_i) then
if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then -- FIXME add second cp (floating point stuff?)
if (CPU_EXTENSION_RISCV_M = true) then -- FIXME add second cp (floating point stuff?)
cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
cp_rb_ff0 <= '0';
cp_rb_ff1 <= cp_rb_ff0;
/neorv32_cpu_bus.vhd
43,40 → 43,41
 
entity neorv32_cpu_bus is
generic (
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- data input --
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- data output --
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
-- status --
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data access
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
exc_ack_i : in std_ulogic; -- exception controller ACK
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data access
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
-- bus system --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
);
end neorv32_cpu_bus;
 
103,9 → 104,7
-- -------------------------------------------------------------------------------------------
mem_adr_reg: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
mar <= (others => '0');
elsif rising_edge(clk_i) then
if rising_edge(clk_i) then
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
mar <= alu_i;
end if;
113,7 → 112,7
end process mem_adr_reg;
 
-- address output --
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch?
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? keep output at PC as long as IF request is active
mar_o <= mar;
 
-- write request output --
120,7 → 119,7
bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
 
-- read request output (also used for instruction fetch) --
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or ((bus_if_req or ctrl_i(ctrl_bus_if_c)) and (not misaligned_instr));
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr)); -- FIXME i_reg and misaligned
 
 
-- Write Data -----------------------------------------------------------------------------
223,7 → 222,7
align_err <= '0';
bus_timeout <= (others => '0');
elsif rising_edge(clk_i) then
if (bus_busy = '0') then -- wait for new request
if (bus_busy = '0') or (ctrl_i(ctrl_bus_reset_c) = '1') then -- wait for new request or reset
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all?
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access
233,10 → 232,10
align_err <= '0';
else -- bus transfer in progress
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1);
align_err <= (align_err or misaligned_data or misaligned_instr) and (not exc_ack_i);
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not exc_ack_i);
align_err <= (align_err or misaligned_data or misaligned_instr) and (not ctrl_i(ctrl_bus_exc_ack_c));
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not ctrl_i(ctrl_bus_exc_ack_c));
if (align_err = '1') or (access_err = '1') then
if (exc_ack_i = '1') then -- wait for controller to ack exception
if (ctrl_i(ctrl_bus_exc_ack_c) = '1') then -- wait for controller to ack exception
bus_if_req <= '0';
bus_rd_req <= '0';
bus_wr_req <= '0';
262,6 → 261,9
ma_load_o <= bus_rd_req and align_err;
ma_store_o <= bus_wr_req and align_err;
 
-- terminate bus access --
bus_cancel_o <= (bus_busy and (align_err or access_err)) or ctrl_i(ctrl_bus_reset_c);
 
-- wait for bus --
bus_busy_o <= bus_busy;
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
291,10 → 293,10
begin
-- check instruction access --
misaligned_instr <= '0'; -- default
if (ctrl_i(ctrl_sys_c_ext_en_c) = '1') then -- 16-bit and 32-bit instruction accesses
misaligned_instr <= '0';
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
misaligned_instr <= '0'; -- no alignment exceptions possible
else -- 32-bit instruction accesses only
if (pc_i(1 downto 0) /= "00") then
if (pc_i(1) = '1') then -- PC(0) is always zero
misaligned_instr <= '1';
end if;
end if;
/neorv32_cpu_control.vhd
104,6 → 104,8
-- external interrupt --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- bus access exceptions --
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
ma_instr_i : in std_ulogic; -- misaligned instruction address
112,7 → 114,6
be_instr_i : in std_ulogic; -- bus error on instruction access
be_load_i : in std_ulogic; -- bus error on load data access
be_store_i : in std_ulogic; -- bus error on store data access
bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge
bus_busy_i : in std_ulogic -- bus unit is busy
);
end neorv32_cpu_control;
140,6 → 141,7
ci_return_nxt : std_ulogic;
reset : std_ulogic;
bus_err_ack : std_ulogic;
bus_reset : std_ulogic;
end record;
signal fetch_engine : fetch_engine_t;
 
179,6 → 181,8
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
sleep : std_ulogic; -- CPU in sleep mode
sleep_nxt : std_ulogic; -- CPU in sleep mode
end record;
signal execute_engine : execute_engine_t;
 
212,8 → 216,6
 
-- fast bus access --
signal bus_fast_ir : std_ulogic;
signal bus_fast_rd : std_ulogic;
signal bus_fast_wr : std_ulogic;
 
-- RISC-V control and status registers (CSRs) --
type csr_t is record
228,21 → 230,19
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W)
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/-)
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
cycle : std_ulogic_vector(32 downto 0); -- cycle, mtime (R/-), plus carry bit
instret : std_ulogic_vector(32 downto 0); -- instret (R/-), plus carry bit
cycleh : std_ulogic_vector(31 downto 0); -- cycleh, mtimeh (R/-)
instreth : std_ulogic_vector(31 downto 0); -- instreth (R/-)
misa_c_en : std_ulogic; -- misa: C extension enable bit (R/W)
misa_m_en : std_ulogic; -- misa: M extension enable bit (R/W)
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
end record;
signal csr : csr_t;
 
signal cycle_msb : std_ulogic;
signal instret_msb : std_ulogic;
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
 
-- illegal instruction check --
signal illegal_instruction : std_ulogic;
330,6 → 330,7
fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg;
fetch_engine.ci_return_nxt <= fetch_engine.ci_return;
fetch_engine.bus_err_ack <= '0';
fetch_engine.bus_reset <= '0';
 
-- instruction prefetch buffer interface --
ipb.we <= '0';
340,12 → 341,12
-- state machine --
case fetch_engine.state is
 
when IFETCH_RESET => -- reset engine, prefetch buffer, get PC
when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
-- ------------------------------------------------------------
fetch_engine.i_buf_state_nxt <= (others => '0');
fetch_engine.ci_return_nxt <= '0';
fetch_engine.bus_reset <= '1'; -- reset bus unit
ipb.clear <= '1'; -- clear instruction prefetch buffer
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them
fetch_engine.state_nxt <= IFETCH_0;
 
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
364,7 → 365,7
fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0);
fetch_engine.state_nxt <= IFETCH_2;
end if;
 
fetch_engine.i_buf_state_nxt(0) <= '1';
if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception?
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them
373,11 → 374,11
when IFETCH_2 => -- construct instruction and issue
-- ------------------------------------------------------------
if (fetch_engine.i_buf_state(1) = '1') then
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) or (csr.misa_c_en = '0') then -- 32-bit aligned
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) or (csr.misa_c_en = '0') then -- uncompressed
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
548,6 → 549,8
end if;
execute_engine.state <= SYS_WAIT;
execute_engine.state_prev <= SYS_WAIT;
--
execute_engine.sleep <= '0';
elsif rising_edge(clk_i) then
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
if (execute_engine.state = EXECUTE) then
555,6 → 558,8
end if;
execute_engine.state <= execute_engine.state_nxt;
execute_engine.state_prev <= execute_engine.state;
--
execute_engine.sleep <= execute_engine.sleep_nxt;
end if;
end process execute_engine_fsm_sync_rst;
 
582,7 → 587,7
 
-- CPU Control Bus Output -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_output: process(ctrl, execute_engine, csr, bus_fast_ir, bus_fast_rd, bus_fast_wr)
ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)
begin
ctrl_o <= ctrl;
-- direct output of register addresses --
591,11 → 596,9
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
-- bus access requests --
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
ctrl_o(ctrl_bus_rd_c) <= ctrl(ctrl_bus_rd_c) or bus_fast_rd;
ctrl_o(ctrl_bus_wr_c) <= ctrl(ctrl_bus_wr_c) or bus_fast_wr;
-- cpu extension control --
ctrl_o(ctrl_sys_c_ext_en_c) <= csr.misa_c_en; -- C extension enabled
ctrl_o(ctrl_sys_m_ext_en_c) <= csr.misa_m_en; -- M extension enabled
-- bus control --
ctrl_o(ctrl_bus_exc_ack_c) <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack;
ctrl_o(ctrl_bus_reset_c) <= fetch_engine.bus_reset;
end process ctrl_output;
 
 
614,6 → 617,7
execute_engine.is_jump_nxt <= '0';
execute_engine.is_ci_nxt <= execute_engine.is_ci;
execute_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0';
execute_engine.sleep_nxt <= execute_engine.sleep;
 
-- instruction dispatch --
fetch_engine.reset <= '0';
623,10 → 627,6
trap_ctrl.env_start_ack <= '0';
trap_ctrl.env_end <= '0';
 
-- bus access (fast) --
bus_fast_rd <= '0';
bus_fast_wr <= '0';
 
-- exception trigger --
trap_ctrl.instr_be <= '0';
trap_ctrl.instr_ma <= '0';
708,16 → 708,21
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0);
execute_engine.pc_nxt <= ipb.raddr(data_width_c-1 downto 1) & '0'; -- the PC according to the current instruction
execute_engine.state_nxt <= EXECUTE;
if (execute_engine.sleep = '1') then
execute_engine.state_nxt <= TRAP;
else
execute_engine.state_nxt <= EXECUTE;
end if;
end if;
end if;
 
when TRAP => -- Start trap environment (also used as sleep state)
when TRAP => -- Start trap environment (also used as cpu sleep state)
-- ------------------------------------------------------------
fetch_engine.reset <= '1';
if (trap_ctrl.env_start = '1') then
trap_ctrl.env_start_ack <= '1';
execute_engine.sleep_nxt <= '0'; -- waky waky
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 1) & '0';
fetch_engine.reset <= '1';
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
732,18 → 737,23
ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV?
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP
-- multi cycle alu operation? --
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001")) then -- MULDIV?
execute_engine.state_nxt <= ALU_WAIT;
elsif (alu_operation_v = alu_cmd_shift_c) then -- multi-cycle shift operation?
execute_engine.state_nxt <= ALU_WAIT;
else
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
execute_engine.state_nxt <= DISPATCH;
end if;
-- cp access? --
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV?
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP
end if;
 
 
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0
817,22 → 827,20
--
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
when x"000" => -- ECALL
when funct12_ecall_c => -- ECALL
trap_ctrl.env_call <= '1';
execute_engine.state_nxt <= SYS_WAIT;
when x"001" => -- EBREAK
when funct12_ebreak_c => -- EBREAK
trap_ctrl.break_point <= '1';
execute_engine.state_nxt <= SYS_WAIT;
when x"302" => -- MRET
trap_ctrl.env_end <= '1';
execute_engine.pc_nxt <= csr.mepc(data_width_c-1 downto 1) & '0';
fetch_engine.reset <= '1';
execute_engine.state_nxt <= SYS_WAIT;
when x"105" => -- WFI
execute_engine.state_nxt <= TRAP;
when funct12_mret_c => -- MRET
trap_ctrl.env_end <= '1';
execute_engine.pc_nxt <= csr.mepc(data_width_c-1 downto 1) & '0';
fetch_engine.reset <= '1';
when funct12_wfi_c => -- WFI = "CPU sleep"
execute_engine.sleep_nxt <= '1'; -- good night
when others => -- undefined
NULL;
end case;
execute_engine.state_nxt <= SYS_WAIT;
elsif (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access
execute_engine.state_nxt <= CSR_ACCESS;
else
892,7 → 900,7
-- RF write back --
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
 
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
-- ------------------------------------------------------------
906,19 → 914,21
when BRANCH => -- update PC for taken branches and jumps
-- ------------------------------------------------------------
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then
execute_engine.pc_nxt <= alu_add_i(data_width_c-1 downto 1) & '0';
fetch_engine.reset <= '1';
execute_engine.pc_nxt <= alu_add_i(data_width_c-1 downto 1) & '0'; -- branch/jump destination
fetch_engine.reset <= '1';
execute_engine.state_nxt <= SYS_WAIT;
else
execute_engine.state_nxt <= DISPATCH;
end if;
execute_engine.state_nxt <= SYS_WAIT;
 
when LOAD => -- trigger memory read request
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_rd_c) <= '1';--bus_fast_rd <= '1'; -- fast read request
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- fast read request
execute_engine.state_nxt <= LOADSTORE_0;
 
when STORE => -- trigger memory write request
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_wr_c) <= '1';--bus_fast_wr <= '1'; -- fast write request
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- fast write request
execute_engine.state_nxt <= LOADSTORE_0;
 
when LOADSTORE_0 => -- memory latency
951,6 → 961,8
-- -------------------------------------------------------------------------------------------
illegal_instruction_check: process(execute_engine, csr, ctrl_nxt, ci_illegal)
begin
-- illegal instructions are checked in the EXECUTE stage
-- the execute engine will only commit valid instructions
if (execute_engine.state = EXECUTE) then
-- defaults --
illegal_instruction <= '0';
1023,7 → 1035,7
 
when opcode_alu_c => -- check ALU funct3 & funct7
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
if (CPU_EXTENSION_RISCV_M = false) or (csr.misa_m_en = '0') then -- not implemented or disabled
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
illegal_instruction <= '1';
end if;
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
1064,10 → 1076,10
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip
--
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycle
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- time
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (IO_MTIME_USE = true)) or -- time
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instret
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycleh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- timeh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (IO_MTIME_USE = true)) or -- timeh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instreth
--
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycle
1092,10 → 1104,10
-- ecall, ebreak, mret, wfi --
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000000000000") or -- ECALL
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000000000001") or -- EBREAK
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "001100000010") or -- MRET
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000100000101") then -- WFI
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
illegal_instruction <= '0';
else
illegal_instruction <= '1';
1108,7 → 1120,7
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
illegal_instruction <= '1';
else -- compressed instruction: illegal or disabled / not implemented
illegal_compressed <= ci_illegal or (not csr.misa_c_en);
illegal_compressed <= ci_illegal;
end if;
 
end case;
1161,8 → 1173,8
 
-- trap control --
if (trap_ctrl.env_start = '0') then -- no started trap handler
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- exception/IRQ detected!
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program
trap_ctrl.exc_src <= trap_ctrl.exc_buf; -- capture exception source for hardware
trap_ctrl.exc_ack <= '1'; -- clear execption
1184,13 → 1196,7
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- classic exceptions (faults/traps) cannot be masked
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- classic interrupts can be enabled/disabled
 
-- exception acknowledge for bus unit --
bus_exc_ack_o <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack;
 
-- exception/interrupt/status ID visible for program --
csr.mcause <= trap_ctrl.cause;
 
 
-- Trap Priority Detector -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
trap_priority: process(trap_ctrl)
1284,22 → 1290,14
-- Control and Status Registers (CSRs)
-- ****************************************************************************************************************************
 
-- CSR CPU Access -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_cpu_acc: process(clk_i)
begin
if rising_edge(clk_i) then
csr.we <= csr.we_nxt;
csr.re <= csr.re_nxt;
end if;
end process csr_cpu_acc;
 
 
-- Control and Status Registers Write Access ----------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_write_access: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
csr.we <= '0';
csr.re <= '0';
--
csr.mstatus_mie <= '0';
csr.mstatus_mpie <= '0';
csr.mie_msie <= '0';
1309,55 → 1307,64
csr.mtval <= (others => '0');
csr.mepc <= (others => '0');
csr.mip_msip <= '0';
csr.misa_c_en <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
csr.misa_m_en <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- access --
csr.we <= csr.we_nxt;
csr.re <= csr.re_nxt;
 
-- defaults --
csr.mip_msip <= '0';
 
-- register that can be modified by user --
-- registers that can be modified by user --
if (csr.we = '1') then -- manual update
 
-- machine trap setup --
if (execute_engine.i_reg(31 downto 24) = x"30") then
if (execute_engine.i_reg(23 downto 20) = x"0") then -- R/W: mstatus - machine status register
csr.mstatus_mie <= csr_wdata_i(03);
csr.mstatus_mpie <= csr_wdata_i(07);
-- Machine CSRs: Standard read/write
if (execute_engine.i_reg(31 downto 28) = x"3") then
-- machine trap setup --
if (execute_engine.i_reg(27 downto 24) = x"0") then
case execute_engine.i_reg(23 downto 20) is
when x"0" => -- R/W: mstatus - machine status register
csr.mstatus_mie <= csr_wdata_i(03);
csr.mstatus_mpie <= csr_wdata_i(07);
when x"4" => -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr_wdata_i;
when others =>
NULL;
end case;
end if;
if (execute_engine.i_reg(23 downto 20) = x"1") then -- R/W: misa - machine instruction set extensions
csr.misa_c_en <= csr_wdata_i(02); -- C extension enable/disable during runtime
csr.misa_m_en <= csr_wdata_i(12); -- M extension enable/disable during runtime
-- machine trap handling --
if (execute_engine.i_reg(27 downto 24) = x"4") then
case execute_engine.i_reg(23 downto 20) is
when x"0" => -- R/W: mscratch - machine scratch register
csr.mscratch <= csr_wdata_i;
when x"1" => -- R/W: mepc - machine exception program counter
csr.mepc <= csr_wdata_i;
when x"2" => -- R/W: mcause - machine trap cause
csr.mcause <= csr_wdata_i;
when x"3" => -- R/W: mtval - machine bad address or instruction
csr.mtval <= csr_wdata_i;
when x"4" => -- R/W: mip - machine interrupt pending
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger
when others =>
NULL;
end case;
end if;
if (execute_engine.i_reg(23 downto 20) = x"4") then -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
end if;
if (execute_engine.i_reg(23 downto 20) = x"5") then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr_wdata_i;
end if;
end if;
 
-- machine trap handling --
if (execute_engine.i_reg(31 downto 24) = x"34") then
if (execute_engine.i_reg(23 downto 20) = x"0") then -- R/W: mscratch - machine scratch register
csr.mscratch <= csr_wdata_i;
end if;
if (execute_engine.i_reg(23 downto 20) = x"1") then-- R/W: mepc - machine exception program counter
csr.mepc <= csr_wdata_i;
end if;
if (execute_engine.i_reg(23 downto 20) = x"4") then -- R/W: mip - machine interrupt pending
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger
end if;
end if;
-- automatic update by hardware --
else
 
else -- automatic update by hardware
 
-- machine exception PC & exception value register --
if (trap_ctrl.env_start_ack = '1') then -- trap handler started?
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only (mtval not defined for interrupts)
csr.mcause <= trap_ctrl.cause;
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
csr.mtval <= (others => '0');
csr.mtval <= (others => '0'); -- mtval not defined for interrupts
else -- for EXCEPTIONS (according to their priority)
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
1392,91 → 1399,100
begin
if rising_edge(clk_i) then
csr_rdata_o <= (others => '0'); -- default
if (CPU_EXTENSION_RISCV_Zicsr = true) then -- implement CSR access at all?
if (csr.re = '1') then
case execute_engine.i_reg(31 downto 20) is
-- machine trap setup --
when x"300" => -- R/W: mstatus - machine status register
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
csr_rdata_o(11) <= '1'; -- MPP low
csr_rdata_o(12) <= '1'; -- MPP high
when x"301" => -- R/W: misa - ISA and extensions
csr_rdata_o(02) <= csr.misa_c_en; -- C CPU extension
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
csr_rdata_o(12) <= csr.misa_m_en; -- M CPU extension
csr_rdata_o(23) <= '1'; -- X CPU extension: non-standard extensions
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
when x"304" => -- R/W: mie - machine interrupt-enable register
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr_rdata_o <= csr.mtvec;
-- machine trap handling --
when x"340" => -- R/W: mscratch - machine scratch register
csr_rdata_o <= csr.mscratch;
when x"341" => -- R/W: mepc - machine exception program counter
csr_rdata_o <= csr.mepc;
when x"342" => -- R/-: mcause - machine trap cause
csr_rdata_o <= csr.mcause;
when x"343" => -- R/-: mtval - machine bad address or instruction
csr_rdata_o <= csr.mtval;
when x"344" => -- R/W: mip - machine interrupt pending
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
-- counter and timers --
when x"c00" | x"c01" | x"b00" => -- R/-: cycle/time/mcycle: Cycle counter LOW / Timer LOW
csr_rdata_o <= csr.cycle(31 downto 0);
when x"c02" | x"b02" => -- R/-: instret/minstret: Instructions-retired counter LOW
csr_rdata_o <= csr.instret(31 downto 0);
when x"c80" | x"c81" | x"b80" => -- R/-: cycleh/timeh/mcycleh: Cycle counter HIGH / Timer HIGH
csr_rdata_o <= csr.cycleh;
when x"c82" | x"b82" => -- R/-: instreth/minstreth: Instructions-retired counter HIGH
csr_rdata_o <= csr.instreth;
-- machine information registers --
when x"f13" => -- R/-: mimpid - implementation ID / version
csr_rdata_o <= hw_version_c;
when x"f14" => -- R/-: mhartid - hardware thread ID
csr_rdata_o <= HART_ID;
-- CUSTOM read-only machine CSRs --
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader?
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface?
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter?
--
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)?
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)?
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
when x"fc1" => -- R/-: mclock - processor clock speed
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
csr_rdata_o <= MEM_ISPACE_BASE;
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
csr_rdata_o <= MEM_DSPACE_BASE;
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32));
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32));
-- undefined/unavailable --
when others =>
csr_rdata_o <= (others => '0'); -- not implemented (yet)
end case;
end if;
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
case execute_engine.i_reg(31 downto 20) is
 
-- machine trap setup --
when x"300" => -- R/W: mstatus - machine status register
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
csr_rdata_o(11) <= '1'; -- MPP low
csr_rdata_o(12) <= '1'; -- MPP high
when x"301" => -- R/-: misa - ISA and extensions
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
when x"304" => -- R/W: mie - machine interrupt-enable register
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr_rdata_o <= csr.mtvec;
 
-- machine trap handling --
when x"340" => -- R/W: mscratch - machine scratch register
csr_rdata_o <= csr.mscratch;
when x"341" => -- R/W: mepc - machine exception program counter
csr_rdata_o <= csr.mepc;
when x"342" => -- R/W: mcause - machine trap cause
csr_rdata_o <= csr.mcause;
when x"343" => -- R/W: mtval - machine bad address or instruction
csr_rdata_o <= csr.mtval;
when x"344" => -- R/W: mip - machine interrupt pending
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
 
-- counter and timers --
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
csr_rdata_o <= csr.mcycle(31 downto 0);
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
csr_rdata_o <= csr.minstret(31 downto 0);
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
csr_rdata_o <= csr.mcycleh;
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
csr_rdata_o <= csr.minstreth;
 
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
csr_rdata_o <= time_i(31 downto 0);
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
csr_rdata_o <= time_i(63 downto 32);
 
-- machine information registers --
when x"f13" => -- R/-: mimpid - implementation ID / version
csr_rdata_o <= hw_version_c;
when x"f14" => -- R/-: mhartid - hardware thread ID
csr_rdata_o <= HART_ID;
 
-- CUSTOM read-only machine CSRs --
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader?
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface?
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter?
--
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)?
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)?
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
when x"fc1" => -- R/-: mclock - processor clock speed
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
csr_rdata_o <= MEM_ISPACE_BASE;
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
csr_rdata_o <= MEM_DSPACE_BASE;
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32));
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32));
 
-- undefined/unavailable --
when others =>
csr_rdata_o <= (others => '0'); -- not implemented
 
end case;
end if;
end if;
end process csr_read_access;
1487,29 → 1503,47
csr_counters: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
csr.cycle <= (others => '0');
csr.instret <= (others => '0');
csr.cycleh <= (others => '0');
csr.instreth <= (others => '0');
cycle_msb <= '0';
instret_msb <= '0';
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true) then
-- low word overflow buffers --
cycle_msb <= csr.cycle(csr.cycle'left);
instret_msb <= csr.instret(csr.instret'left);
-- low word counters --
csr.cycle <= std_ulogic_vector(unsigned(csr.cycle) + 1);
if (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then
csr.instret <= std_ulogic_vector(unsigned(csr.instret) + 1);
 
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
csr.mcycle(31 downto 0) <= csr_wdata_i;
csr.mcycle(32) <= '0';
elsif (execute_engine.sleep = '0') then -- automatic update
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
end if;
-- high word counters --
if ((cycle_msb xor csr.cycle(csr.cycle'left)) = '1') then
csr.cycleh <= std_ulogic_vector(unsigned(csr.cycleh) + 1);
 
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
csr.mcycleh <= csr_wdata_i;
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
if ((instret_msb xor csr.instret(csr.instret'left)) = '1') then
csr.instreth <= std_ulogic_vector(unsigned(csr.instreth) + 1);
 
-- minstret (instret) --
minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
csr.minstret(31 downto 0) <= csr_wdata_i;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
 
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
csr.minstreth <= csr_wdata_i;
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
 
end if;
end if;
end process csr_counters;
/neorv32_mtime.vhd
7,6 → 7,7
-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is #
-- # written again. #
-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. #
-- # Note: The register of this unit can only be written in WORD MODE. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
58,6 → 59,8
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- time output for CPU --
time_o : out std_ulogic_vector(63 downto 0); -- current system time
-- interrupt --
irq_o : out std_ulogic -- interrupt request
);
75,7 → 78,8
signal wren : std_ulogic; -- module access enable
 
-- accessible regs --
signal mtimecmp : std_ulogic_vector(63 downto 0);
signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
signal mtime_lo : std_ulogic_vector(32 downto 0);
signal mtime_lo_msb_ff : std_ulogic;
signal mtime_hi : std_ulogic_vector(31 downto 0);
85,8 → 89,6
signal cmp_lo_ff : std_ulogic;
signal cmp_hi : std_ulogic;
signal cmp_match_ff : std_ulogic;
signal irq_flag : std_ulogic;
signal irq_flag_ff : std_ulogic;
 
begin
 
94,52 → 96,38
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wren <= acc_en and wren_i;
wren <= acc_en and wren_i and and_all_f(ben_i);
 
 
-- System Time Update ---------------------------------------------------------------------
-- Write Access ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
system_time: process(clk_i)
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
mtime_lo <= (others => '0');
mtime_hi <= (others => '0');
else
-- mtime low --
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
-- mtime high --
if ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
-- mtimecmp --
if (wren = '1') then
if (addr = mtime_cmp_lo_addr_c) then -- low
mtimecmp_lo <= data_i;
end if;
if (addr = mtime_cmp_hi_addr_c) then -- high
mtimecmp_hi <= data_i;
end if;
end if;
end if;
end process system_time;
 
 
-- Write Access ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
-- mtimecmp low --
if (wren = '1') and (addr = mtime_cmp_lo_addr_c) then
for i in 0 to 3 loop
if (ben_i(i) = '1') then
mtimecmp(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8);
end if;
end loop; -- byte enable
-- mtime low --
if (wren = '1') and (addr = mtime_time_lo_addr_c) then
mtime_lo_msb_ff <= '0';
mtime_lo <= '0' & data_i;
else -- auto increment
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
end if;
 
-- mtimecmp high --
if (wren = '1') and (addr = mtime_cmp_hi_addr_c) then
for i in 0 to 3 loop
if (ben_i(i) = '1') then
mtimecmp(32+7+i*8 downto 32+0+i*8) <= data_i(7+i*8 downto 0+i*8);
end if;
end loop; -- byte enable
-- mtime high --
if (wren = '1') and (addr = mtime_time_hi_addr_c) then
mtime_hi <= data_i;
elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
end if;
end if;
end process wr_access;
150,6 → 138,7
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
data_o <= (others => '0'); -- default
if (rden_i = '1') and (acc_en = '1') then
if (addr = mtime_time_lo_addr_c) then -- mtime LOW
157,15 → 146,18
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH
data_o <= mtime_hi;
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW
data_o <= mtimecmp(31 downto 00);
data_o <= mtimecmp_lo;
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH
data_o <= mtimecmp(63 downto 32);
data_o <= mtimecmp_hi;
end if;
end if;
end if;
end process rd_access;
 
-- time output for cpu --
time_o <= mtime_hi & mtime_lo(31 downto 00);
 
 
-- Comparator -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cmp_sync: process(clk_i)
173,38 → 165,13
if rising_edge(clk_i) then
cmp_lo_ff <= cmp_lo;
cmp_match_ff <= cmp_lo_ff and cmp_hi;
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
end if;
end process cmp_sync;
 
-- test words --
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp(31 downto 00))) else '0';
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp(63 downto 32))) else '0';
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0';
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0';
 
 
-- Interrupt Logic ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_ctrl: process(clk_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
irq_flag_ff <= '0';
irq_flag <= '0';
else
irq_flag_ff <= irq_flag;
if (irq_flag = '0') then -- idle
irq_flag <= '0';
if (cmp_match_ff = '1') then
irq_flag <= '1';
end if;
elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK
irq_flag <= '0';
end if;
end if;
end if;
end process irq_ctrl;
 
-- irq output to CPU --
irq_o <= irq_flag and (not irq_flag_ff); -- rising edge detector
 
 
end neorv32_mtime_rtl;
/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000100"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy!
 
-- Internal Functions ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
178,16 → 178,15
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions
-- co-processor --
constant ctrl_cp_use_c : natural := 40; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 42; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2
-- system --
constant ctrl_sys_c_ext_en_c : natural := 46; -- CPU C extension enabled
constant ctrl_sys_m_ext_en_c : natural := 47; -- CPU M extension enabled
constant ctrl_cp_use_c : natural := 42; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
-- control bus size --
constant ctrl_width_c : natural := 48; -- control bus size
 
277,6 → 276,14
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
 
-- RISC-V Funct12 --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- system --
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
 
-- Co-Processor Operations ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- cp ids --
453,20 → 460,23
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- bus interface --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
);
end component;
 
533,6 → 543,8
-- external interrupt --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- bus access exceptions --
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
ma_instr_i : in std_ulogic; -- misaligned instruction address
541,7 → 553,6
be_instr_i : in std_ulogic; -- bus error on instruction access
be_load_i : in std_ulogic; -- bus error on load data access
be_store_i : in std_ulogic; -- bus error on store data access
bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge
bus_busy_i : in std_ulogic -- bus unit is busy
);
end component;
570,6 → 581,9
-- Component: CPU ALU ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_alu
generic (
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
616,40 → 630,41
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_bus
generic (
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- data input --
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- data output --
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
-- status --
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
exc_ack_i : in std_ulogic; -- exception controller ACK
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
-- bus system --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
);
end component;
 
732,6 → 747,8
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- time output for CPU --
time_o : out std_ulogic_vector(63 downto 0); -- current system time
-- interrupt --
irq_o : out std_ulogic -- interrupt request
);
940,6 → 957,7
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
cancel_i : in std_ulogic; -- cancel current bus transaction
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic; -- transfer error
-- wishbone interface --
/neorv32_top.vhd
52,9 → 52,9
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
142,14 → 142,18
signal pwm_cg_en : std_ulogic;
 
-- cpu bus --
signal cpu_addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
signal cpu_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
signal cpu_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
signal cpu_ben : std_ulogic_vector(03 downto 0); -- byte enable
signal cpu_we : std_ulogic; -- write enable
signal cpu_re : std_ulogic; -- read enable
signal cpu_ack : std_ulogic; -- bus transfer acknowledge
signal cpu_err : std_ulogic; -- bus transfer error
type cpu_bus_t is record
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ben : std_ulogic_vector(03 downto 0); -- byte enable
we : std_ulogic; -- write enable
re : std_ulogic; -- read enable
cancel : std_ulogic; -- cancel current transfer
ack : std_ulogic; -- bus transfer acknowledge
err : std_ulogic; -- bus transfer error
end record;
signal cpu : cpu_bus_t;
 
-- io space access --
signal io_acc : std_ulogic;
198,6 → 202,9
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
 
-- misc --
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
 
begin
 
-- Sanity Checks --------------------------------------------------------------------------
352,32 → 359,35
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
-- bus interface --
bus_addr_o => cpu_addr, -- bus access address
bus_rdata_i => cpu_rdata, -- bus read data
bus_wdata_o => cpu_wdata, -- bus write data
bus_ben_o => cpu_ben, -- byte enable
bus_we_o => cpu_we, -- write enable
bus_re_o => cpu_re, -- read enable
bus_ack_i => cpu_ack, -- bus transfer acknowledge
bus_err_i => cpu_err, -- bus transfer error
bus_addr_o => cpu.addr, -- bus access address
bus_rdata_i => cpu.rdata, -- bus read data
bus_wdata_o => cpu.wdata, -- bus write data
bus_ben_o => cpu.ben, -- byte enable
bus_we_o => cpu.we, -- write enable
bus_re_o => cpu.re, -- read enable
bus_cancel_o => cpu.cancel, -- cancel current bus transaction
bus_ack_i => cpu.ack, -- bus transfer acknowledge
bus_err_i => cpu.err, -- bus transfer error
-- system time input from MTIME --
time_i => mtime_time, -- current system time
-- external interrupts --
clic_irq_i => clic_irq, -- CLIC interrupt request
mtime_irq_i => mtime_irq -- machine timer interrupt
clic_irq_i => clic_irq, -- CLIC interrupt request
mtime_irq_i => mtime_irq -- machine timer interrupt
);
 
-- CPU data input --
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
 
-- CPU ACK input --
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
 
-- CPU bus error input --
cpu_err <= wishbone_err;
cpu.err <= wishbone_err;
 
 
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
393,12 → 403,12
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_re, -- read enable
wren_i => cpu_we, -- write enable
ben_i => cpu_ben, -- byte write enable
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
upen_i => '1', -- update enable
addr_i => cpu_addr, -- address
data_i => cpu_wdata, -- data in
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => imem_rdata, -- data out
ack_o => imem_ack -- transfer acknowledge
);
422,11 → 432,11
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_re, -- read enable
wren_i => cpu_we, -- write enable
ben_i => cpu_ben, -- byte write enable
addr_i => cpu_addr, -- address
data_i => cpu_wdata, -- data in
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => dmem_rdata, -- data out
ack_o => dmem_ack -- transfer acknowledge
);
446,8 → 456,8
neorv32_boot_rom_inst: neorv32_boot_rom
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_re, -- read enable
addr_i => cpu_addr, -- address
rden_i => cpu.re, -- read enable
addr_i => cpu.addr, -- address
data_o => bootrom_rdata, -- data out
ack_o => bootrom_ack -- transfer acknowledge
);
483,12 → 493,13
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active
-- host access --
addr_i => cpu_addr, -- address
rden_i => cpu_re, -- read enable
wren_i => cpu_we, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
addr_i => cpu.addr, -- address
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => wishbone_rdata, -- data out
cancel_i => cpu.cancel, -- cancel current transaction
ack_o => wishbone_ack, -- transfer acknowledge
err_o => wishbone_err, -- transfer error
-- wishbone interface --
521,9 → 532,9
 
-- IO Access? -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
io_acc <= '1' when (cpu_addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and cpu_re;
io_wren <= io_acc and cpu_we;
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and cpu.re;
io_wren <= io_acc and cpu.we;
 
 
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
534,11 → 545,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => gpio_rdata, -- data out
ack_o => gpio_ack, -- transfer acknowledge
-- parallel io --
568,9 → 579,9
clk_i => clk_i, -- global clock line
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
addr_i => cpu_addr, -- address
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => clic_rdata, -- data out
ack_o => clic_ack, -- transfer acknowledge
-- cpu interrupt --
615,9 → 626,9
rstn_i => ext_rstn, -- global reset line, low-active
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
addr_i => cpu_addr, -- address
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => wdt_rdata, -- data out
ack_o => wdt_ack, -- transfer acknowledge
-- clock generator --
648,13 → 659,15
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset, low-active, async
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => mtime_rdata, -- data out
ack_o => mtime_ack, -- transfer acknowledge
-- time output for CPU --
time_o => mtime_time, -- current system time
-- interrupt --
irq_o => mtime_irq -- interrupt request
);
663,6 → 676,7
neorv32_mtime_inst_false:
if (IO_MTIME_USE = false) generate
mtime_rdata <= (others => '0');
mtime_time <= (others => '0');
mtime_ack <= '0';
mtime_irq <= '0';
end generate;
676,11 → 690,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => uart_rdata, -- data out
ack_o => uart_ack, -- transfer acknowledge
-- clock generator --
712,11 → 726,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => spi_rdata, -- data out
ack_o => spi_ack, -- transfer acknowledge
-- clock generator --
752,11 → 766,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => twi_rdata, -- data out
ack_o => twi_ack, -- transfer acknowledge
-- clock generator --
789,11 → 803,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => pwm_rdata, -- data out
ack_o => pwm_ack, -- transfer acknowledge
-- clock generator --
821,11 → 835,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => trng_rdata, -- data out
ack_o => trng_ack -- transfer acknowledge
);
846,11 → 860,11
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu_addr, -- address
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu_ben, -- byte write enable
data_i => cpu_wdata, -- data in
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => devnull_rdata, -- data out
ack_o => devnull_ack -- transfer acknowledge
);
/neorv32_wishbone.vhd
72,6 → 72,7
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
cancel_i : in std_ulogic; -- cancel current bus transaction
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic; -- transfer error
-- wishbone interface --
108,7 → 109,7
-- -------------------------------------------------------------------------------------------
sanity_check: process(clk_i)
begin
if rising_edge(clk_i) then -- just for simulation
if rising_edge(clk_i) then
if (INTERFACE_REG_STAGES > 2) then
assert false report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
end if;
144,10 → 145,8
-- bus cycle --
if (INTERFACE_REG_STAGES = 0) then
wb_cyc_ff <= '0'; -- unused
elsif (INTERFACE_REG_STAGES = 1) then
wb_cyc_ff <= wb_access and ((not wb_ack_i) or (not wb_err_i));
elsif (INTERFACE_REG_STAGES = 2) then
wb_cyc_ff <= wb_access and ((not wb_ack_ff) or (not wb_err_ff));
else
wb_cyc_ff <= (wb_cyc_ff or wb_access) and ((not wb_ack_i) or (not wb_err_i)) and (not cancel_i);
end if;
-- bus strobe --
wb_stb_ff1 <= wb_stb_ff0;
188,10 → 187,12
buffer_stages_one: process(clk_i)
begin
if rising_edge(clk_i) then
wb_adr_o <= addr_i;
wb_dat_o <= data_i;
wb_sel_o <= ben_i;
wb_we_o <= wren_i;
if (wb_cyc_ff = '0') then
wb_adr_o <= addr_i;
wb_dat_o <= data_i;
wb_sel_o <= ben_i;
wb_we_o <= wren_i;
end if;
end if;
end process buffer_stages_one;
data_o <= wb_dat_i;
202,11 → 203,13
buffer_stages_two: process(clk_i)
begin
if rising_edge(clk_i) then
wb_adr_o <= addr_i;
wb_dat_o <= data_i;
wb_sel_o <= ben_i;
wb_we_o <= wren_i;
data_o <= wb_dat_i;
if (wb_cyc_ff = '0') then
wb_adr_o <= addr_i;
wb_dat_o <= data_i;
wb_sel_o <= ben_i;
wb_we_o <= wren_i;
data_o <= wb_dat_i;
end if;
end if;
end process buffer_stages_two;
end generate;

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