URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/ghdl/ghdl_sim.sh
24,12 → 24,12
|
# List files |
echo "Simulation source files:" |
ls -al $srcdir_core |
ls -al $srcdir_sim |
ls -l $srcdir_core |
ls -l $srcdir_sim |
|
# Just a hint |
echo "" |
echo "Tip: Compile application with USER_FLAGS+=-DDEVNULL_UART_OVERRIDE to have faster UART/console output." |
echo "Tip: Compile application with USER_FLAGS+=-DDEVNULL_UART_OVERRIDE to have faster UART/console output via NEORV32.DEVNULL." |
echo "" |
|
# Analyse sources; libs and images at first! |
39,6 → 39,7
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_bus.vhd |
/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="244577083fs"></ZoomStartTime> |
<ZoomEndTime time="245084584fs"></ZoomEndTime> |
<Cursor1Time time="244825000fs"></Cursor1Time> |
<ZoomStartTime time="820966fs"></ZoomStartTime> |
<ZoomEndTime time="923467fs"></ZoomEndTime> |
<Cursor1Time time="866866fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="203"></NameColumnWidth> |
<ValueColumnWidth column_width="102"></ValueColumnWidth> |
<ValueColumnWidth column_width="94"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="95" /> |
<WVObjectSize size="112" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
127,80 → 127,6
<obj_property name="ElementShortName">execute_engine</obj_property> |
<obj_property name="ObjectShortName">execute_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
<obj_property name="CustomSignalColor">#FF00FF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_prev" type="other"> |
<obj_property name="ElementShortName">.state_prev</obj_property> |
<obj_property name="ObjectShortName">.state_prev</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic"> |
<obj_property name="ElementShortName">.is_ci</obj_property> |
<obj_property name="ObjectShortName">.is_ci</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_ci_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump" type="logic"> |
<obj_property name="ElementShortName">.is_jump</obj_property> |
<obj_property name="ObjectShortName">.is_jump</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_jump_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_jump_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic"> |
<obj_property name="ElementShortName">.branch_taken</obj_property> |
<obj_property name="ObjectShortName">.branch_taken</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array"> |
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep" type="logic"> |
<obj_property name="ElementShortName">.sleep</obj_property> |
<obj_property name="ObjectShortName">.sleep</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep_nxt" type="logic"> |
<obj_property name="ElementShortName">.sleep_nxt</obj_property> |
<obj_property name="ObjectShortName">.sleep_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.if_rst" type="logic"> |
<obj_property name="ElementShortName">.if_rst</obj_property> |
<obj_property name="ObjectShortName">.if_rst</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.if_rst_nxt" type="logic"> |
<obj_property name="ElementShortName">.if_rst_nxt</obj_property> |
<obj_property name="ObjectShortName">.if_rst_nxt</obj_property> |
</wvobject> |
</wvobject> |
<wvobject type="divider" fp_name="divider139"> |
<obj_property name="label">CPU: Control.TRAP</obj_property> |
355,12 → 281,10
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/cpu_i" type="array"> |
<obj_property name="ElementShortName">cpu_i</obj_property> |
<obj_property name="ObjectShortName">cpu_i</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/cpu_d" type="array"> |
<obj_property name="ElementShortName">cpu_d</obj_property> |
<obj_property name="ObjectShortName">cpu_d</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/PMP_USE" type="other"> |
<obj_property name="ElementShortName">PMP_USE</obj_property> |
482,4 → 406,72
<obj_property name="ElementShortName">acc_en</obj_property> |
<obj_property name="ObjectShortName">acc_en</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider238"> |
<obj_property name="label">EXT_MEM Interface</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_adr_o" type="array"> |
<obj_property name="ElementShortName">wb_adr_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">wb_adr_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_dat_i" type="array"> |
<obj_property name="ElementShortName">wb_dat_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">wb_dat_i[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_dat_o" type="array"> |
<obj_property name="ElementShortName">wb_dat_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">wb_dat_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_we_o" type="logic"> |
<obj_property name="ElementShortName">wb_we_o</obj_property> |
<obj_property name="ObjectShortName">wb_we_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_sel_o" type="array"> |
<obj_property name="ElementShortName">wb_sel_o[3:0]</obj_property> |
<obj_property name="ObjectShortName">wb_sel_o[3:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_stb_o" type="logic"> |
<obj_property name="ElementShortName">wb_stb_o</obj_property> |
<obj_property name="ObjectShortName">wb_stb_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_cyc_o" type="logic"> |
<obj_property name="ElementShortName">wb_cyc_o</obj_property> |
<obj_property name="ObjectShortName">wb_cyc_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_ack_i" type="logic"> |
<obj_property name="ElementShortName">wb_ack_i</obj_property> |
<obj_property name="ObjectShortName">wb_ack_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/wb_err_i" type="logic"> |
<obj_property name="ElementShortName">wb_err_i</obj_property> |
<obj_property name="ObjectShortName">wb_err_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/fence_o" type="logic"> |
<obj_property name="ElementShortName">fence_o</obj_property> |
<obj_property name="ObjectShortName">fence_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/fencei_o" type="logic"> |
<obj_property name="ElementShortName">fencei_o</obj_property> |
<obj_property name="ObjectShortName">fencei_o</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider238"> |
<obj_property name="label">IO: CFU</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cfu_inst_true/neorv32_cfu_inst/wr_en" type="logic"> |
<obj_property name="ElementShortName">wr_en</obj_property> |
<obj_property name="ObjectShortName">wr_en</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cfu_inst_true/neorv32_cfu_inst/rd_en" type="logic"> |
<obj_property name="ElementShortName">rd_en</obj_property> |
<obj_property name="ObjectShortName">rd_en</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cfu_inst_true/neorv32_cfu_inst/cfu_reg_in" type="array"> |
<obj_property name="ElementShortName">cfu_reg_in[0:3][31:0]</obj_property> |
<obj_property name="ObjectShortName">cfu_reg_in[0:3][31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cfu_inst_true/neorv32_cfu_inst/cfu_reg_out" type="array"> |
<obj_property name="ElementShortName">cfu_reg_out[0:3][31:0]</obj_property> |
<obj_property name="ObjectShortName">cfu_reg_out[0:3][31:0]</obj_property> |
</wvobject> |
</wave_config> |
/neorv32_tb.vhd
60,6 → 60,7
constant baud_rate_c : real := 19200.0; -- standard UART baudrate |
constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address |
constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes |
constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1) |
-- ------------------------------------------------------------------------------------------- |
|
-- text.io -- |
103,16 → 104,18
end record; |
signal wb_cpu : wishbone_t; |
|
-- Wishbone memory -- |
type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0); |
type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0); |
type wb_mem_t is record |
ram : wb_mem_ram_t; |
rdata : wb_mem_read_latency_t; |
acc_en : std_ulogic; |
ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0); |
rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0); |
end record; |
signal wb_mem : wb_mem_t; |
|
-- Wishbone memory, SimCom -- |
type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0); |
signal wb_mem_file : wb_mem_file_t := (others => (others => '0')); |
signal rb_en : std_ulogic; |
signal r_data : std_ulogic_vector(31 downto 0); |
signal wb_acc_en : std_ulogic; |
signal wb_mem_rdata : std_ulogic_vector(31 downto 0); |
signal wb_mem_ack : std_ulogic; |
|
begin |
|
-- Clock/Reset Generator ------------------------------------------------------------------ |
137,24 → 140,19
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.? |
-- Extension Options -- |
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier |
-- Physical Memory Protection (PMP) -- |
PMP_USE => true, -- implement PMP? |
PMP_NUM_REGIONS => 4, -- number of regions (max 16) |
PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space |
MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte |
-- Internal Instruction memory -- |
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE => x"80000000", -- base address of data memory space |
MEM_DSPACE_SIZE => 8*1024, -- total size of data memory space in byte |
-- Internal Data memory -- |
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
-- External memory interface -- |
MEM_EXT_USE => true, -- implement external memory bus interface? |
MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2) |
MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout |
166,8 → 164,9
IO_TWI_USE => true, -- implement two-wire interface (TWI)? |
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_TRNG_USE => false, -- CANNOT BE SIMULATED! |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED! |
IO_DEVNULL_USE => true, -- implement dummy device (DEVNULL)? |
IO_CFU_USE => true -- implement custom functions unit (CFU)? |
) |
port map ( |
-- Global control -- |
210,12 → 209,7
twi_scl <= 'H'; |
twi_sda <= 'H'; |
|
-- Wishbone read-back -- |
wb_cpu.rdata <= wb_mem_rdata; |
wb_cpu.ack <= wb_mem_ack; |
wb_cpu.err <= '0'; |
|
|
-- Console UART Receiver ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
uart_rx_console: process(clk_gen) |
270,27 → 264,40
|
-- Wishbone Memory ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
wb_mem_file_access: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control |
wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge |
if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access |
for i in 0 to 3 loop |
if (wb_cpu.sel(i) = '1') then |
wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8); |
end if; |
end loop; -- i |
end if; |
r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned |
wb_mem_ram_access: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
-- control -- |
wb_mem.rb_en(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and (not wb_cpu.we); -- read-back control |
wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge |
-- write access -- |
if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access |
for i in 0 to 3 loop |
if (wb_cpu.sel(i) = '1') then |
wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8); |
end if; |
end loop; -- i |
end if; |
end process wb_mem_file_access; |
-- read access -- |
wb_mem.rdata(0) <= wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned |
-- virtual read and ack latency -- |
if (wb_mem_latency_c > 1) then |
for i in 1 to wb_mem_latency_c-1 loop |
wb_mem.rdata(i) <= wb_mem.rdata(i-1); |
wb_mem.rb_en(i) <= wb_mem.rb_en(i-1); |
wb_mem.ack(i) <= wb_mem.ack(i-1); |
end loop; |
end if; |
end if; |
end process wb_mem_ram_access; |
|
-- wb mem access -- |
wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0'; |
-- wishbone memory access? -- |
wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0'; |
|
-- output gate -- |
wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0'); |
-- output to cpu -- |
wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate |
wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1); |
wb_cpu.err <= '0'; |
|
|
end neorv32_tb_rtl; |