URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/neorv32_tb.vhd
1,11 → 1,11
-- ################################################################################################# |
-- # << NEORV32 - Simple Testbench >> # |
-- # << NEORV32 - Default Testbench >> # |
-- # ********************************************************************************************* # |
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o # |
-- # signals. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). # |
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. # |
-- # The testbench configures the processor with all optional element enabled by default. # |
-- # signal. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). Futhermore, this testbench provides a simple RAM connected # |
-- # to the external Wishbone bus. The testbench configures the processor with all optional # |
-- # elements enabled by default. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
103,6 → 103,7
cyc : std_ulogic; -- valid cycle |
ack : std_ulogic; -- transfer acknowledge |
err : std_ulogic; -- transfer error |
tag : std_ulogic_vector(2 downto 0); -- tag |
end record; |
signal wb_cpu : wishbone_t; |
|
126,8 → 127,8
-- How to simulate a boot from an external memory -- |
-- ---------------------------------------------- -- |
-- The simulated Wishbone memory can be initialized with the compiled application init. |
-- 1. Uncomment the init_wbmen function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image |
-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB) |
-- 1. Uncomment the init_wbmem function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image |
-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB -> 16*1024) |
-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false) |
-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";) |
-- 5. Simulate! |
157,7 → 158,8
-- General -- |
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => false, -- implement processor-internal bootloader? |
USER_CODE => x"19880704", -- custom user code |
USER_CODE => x"12345678", -- custom user code |
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
198,6 → 200,7
clk_i => clk_gen, -- global clock, rising edge |
rstn_i => rst_gen, -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o => wb_cpu.tag, -- tag |
wb_adr_o => wb_cpu.addr, -- address |
wb_dat_i => wb_cpu.rdata, -- read data |
wb_dat_o => wb_cpu.wdata, -- write data |
232,7 → 235,7
mext_irq_i => '0' -- machine external interrupt |
); |
|
-- TWI termination -- |
-- TWI termination (pull-ups) -- |
twi_scl <= 'H'; |
twi_sda <= 'H'; |
|