URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 44 to Rev 45
- ↔ Reverse comparison
Rev 44 → Rev 45
/ghdl/ghdl_sim.sh
41,7 → 41,7
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cache.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_icache.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu0.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu1.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
/rtl_modules/neorv32_imem.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
48,7 → 48,7
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address |
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes |
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory? |
BOOTLOADER_USE : boolean := true -- implement and use bootloader? |
BOOTLOADER_EN : boolean := true -- implement and use bootloader? |
); |
port ( |
clk_i : in std_ulogic; -- global clock line |
/neorv32_tb.vhd
1,7 → 1,8
-- ################################################################################################# |
-- # << NEORV32 - Default Testbench >> # |
-- # ********************************************************************************************* # |
-- # Use the "User Configuration" section to configure the testbench according to your need. # |
-- # The processor is configured to use a maximum of functional units (for testing purpose). # |
-- # Use the "User Configuration" section to configure the testbench according to your needs. # |
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
204,6 → 205,7
ICACHE_EN => icache_en_c, -- implement instruction cache |
ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_EN => true, -- implement external memory bus interface? |
-- Processor peripherals -- |
498,7 → 500,7
|
-- Wishbone IRQ Triggers ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
ext_irq_trigger: process(clk_gen) |
irq_trigger: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
-- default -- |
523,7 → 525,7
wb_mei.ack <= '1'; |
end if; |
end if; |
end process ext_irq_trigger; |
end process irq_trigger; |
|
|
end neorv32_tb_rtl; |