URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 45 to Rev 47
- ↔ Reverse comparison
Rev 45 → Rev 47
/ghdl/ghdl_sim.sh
42,8 → 42,7
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_icache.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu0.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu1.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfs.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_bus.vhd |
/neorv32_tb.vhd
73,9 → 73,8
constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) |
constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes |
constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay |
-- machine interrupt triggers -- |
constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt |
constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt |
-- simulation interrupt trigger -- |
constant irq_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; |
-- ------------------------------------------------------------------------------------------- |
|
-- internals - hands off! -- |
109,6 → 108,7
|
-- irq -- |
signal msi_ring, mei_ring : std_ulogic; |
signal soc_firq_ring : std_ulogic_vector(3 downto 0); |
|
-- Wishbone bus -- |
type wishbone_t is record |
124,7 → 124,7
tag : std_ulogic_vector(2 downto 0); -- tag |
lock : std_ulogic; -- locked/exclusive bus access |
end record; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t; |
|
-- Wishbone memories -- |
type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0); |
190,7 → 190,7
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_NUM_REGIONS => 5, -- number of regions (0..64) |
PMP_NUM_REGIONS => 4, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29) |
217,8 → 217,8
IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => true, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => false, -- trng cannot be simulated |
IO_CFU0_EN => true, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => true -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => true, -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG => (others => '0') -- custom CFS configuration generic |
) |
port map ( |
-- Global control -- |
255,9 → 255,13
twi_scl_io => twi_scl, -- twi serial clock line |
-- PWM -- |
pwm_o => open, -- pwm channels |
-- Custom Functions Subsystem IO -- |
cfs_in_i => (others => '0'), -- custom CFS inputs |
cfs_out_o => open, -- custom CFS outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => (others => '0'), -- current system time |
-- Interrupts -- |
soc_firq_i => soc_firq_ring, -- fast interrupt channels |
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false |
msw_irq_i => msi_ring, -- machine software interrupt |
mext_irq_i => mei_ring -- machine external interrupt |
347,33 → 351,24
wb_mem_c.cyc <= wb_cpu.cyc; |
wb_mem_c.lock <= wb_cpu.lock; |
|
wb_msi.addr <= wb_cpu.addr; |
wb_msi.wdata <= wb_cpu.wdata; |
wb_msi.we <= wb_cpu.we; |
wb_msi.sel <= wb_cpu.sel; |
wb_msi.tag <= wb_cpu.tag; |
wb_msi.cyc <= wb_cpu.cyc; |
wb_msi.lock <= wb_cpu.lock; |
wb_irq.addr <= wb_cpu.addr; |
wb_irq.wdata <= wb_cpu.wdata; |
wb_irq.we <= wb_cpu.we; |
wb_irq.sel <= wb_cpu.sel; |
wb_irq.tag <= wb_cpu.tag; |
wb_irq.cyc <= wb_cpu.cyc; |
wb_irq.lock <= wb_cpu.lock; |
|
wb_mei.addr <= wb_cpu.addr; |
wb_mei.wdata <= wb_cpu.wdata; |
wb_mei.we <= wb_cpu.we; |
wb_mei.sel <= wb_cpu.sel; |
wb_mei.tag <= wb_cpu.tag; |
wb_mei.cyc <= wb_cpu.cyc; |
wb_mei.lock <= wb_cpu.lock; |
|
-- CPU read-back signals (no mux here since peripherals have "output gates") -- |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err; |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err; |
|
-- peripheral select via STROBE signal -- |
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; |
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0'; |
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0'; |
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0'; |
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0'; |
wb_irq.stb <= wb_cpu.stb when (wb_cpu.addr = irq_trigger_c) else '0'; |
|
|
-- Wishbone Memory A (simulated external IMEM) -------------------------------------------- |
503,27 → 498,22
irq_trigger: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
-- default -- |
msi_ring <= '0'; |
wb_msi.rdata <= (others => '0'); |
wb_msi.ack <= '0'; |
wb_msi.err <= '0'; |
mei_ring <= '0'; |
wb_mei.rdata <= (others => '0'); |
wb_mei.ack <= '0'; |
wb_mei.err <= '0'; |
|
-- machine software interrupt -- |
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then |
msi_ring <= '1'; |
wb_msi.ack <= '1'; |
-- bus interface -- |
wb_irq.rdata <= (others => '0'); |
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we; |
wb_irq.err <= '0'; |
-- trigger IRQ using CSR.MIE bit layout -- |
msi_ring <= '0'; |
mei_ring <= '0'; |
soc_firq_ring <= (others => '0'); |
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we) = '1') then |
msi_ring <= wb_irq.wdata(03); -- machine software interrupt |
mei_ring <= wb_irq.wdata(11); -- machine software interrupt |
soc_firq_ring(0) <= wb_irq.wdata(20); -- fast interrupt channel 4 |
soc_firq_ring(1) <= wb_irq.wdata(21); -- fast interrupt channel 5 |
soc_firq_ring(2) <= wb_irq.wdata(22); -- fast interrupt channel 6 |
soc_firq_ring(3) <= wb_irq.wdata(22); -- fast interrupt channel 7 |
end if; |
|
-- machine external interrupt -- |
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then |
mei_ring <= '1'; |
wb_mei.ack <= '1'; |
end if; |
end if; |
end process irq_trigger; |
|