URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 52 to Rev 53
- ↔ Reverse comparison
Rev 52 → Rev 53
/neorv32_tb.vhd
134,8 → 134,8
cyc : std_ulogic; -- valid cycle |
ack : std_ulogic; -- transfer acknowledge |
err : std_ulogic; -- transfer error |
tag : std_ulogic_vector(2 downto 0); -- tag |
lock : std_ulogic; -- locked/exclusive bus access |
tag : std_ulogic_vector(03 downto 0); -- request tag |
tag_r : std_ulogic; -- response tag |
end record; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t; |
|
145,6 → 145,9
type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0); |
type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0); |
|
-- exclusive access / reservation -- |
signal ext_mem_c_atomic_reservation : std_ulogic := '0'; |
|
-- init function -- |
-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed |
impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is |
243,7 → 246,7
clk_i => clk_gen, -- global clock, rising edge |
rstn_i => rst_gen, -- global reset, low-active, async |
-- Wishbone bus interface (available if MEM_EXT_EN = true) -- |
wb_tag_o => wb_cpu.tag, -- tag |
wb_tag_o => wb_cpu.tag, -- request tag |
wb_adr_o => wb_cpu.addr, -- address |
wb_dat_i => wb_cpu.rdata, -- read data |
wb_dat_o => wb_cpu.wdata, -- write data |
251,7 → 254,7
wb_sel_o => wb_cpu.sel, -- byte enable |
wb_stb_o => wb_cpu.stb, -- strobe |
wb_cyc_o => wb_cpu.cyc, -- valid cycle |
wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access |
wb_tag_i => wb_cpu.tag_r, -- response tag |
wb_ack_i => wb_cpu.ack, -- transfer acknowledge |
wb_err_i => wb_cpu.err, -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
414,7 → 417,6
wb_mem_a.sel <= wb_cpu.sel; |
wb_mem_a.tag <= wb_cpu.tag; |
wb_mem_a.cyc <= wb_cpu.cyc; |
wb_mem_a.lock <= wb_cpu.lock; |
|
wb_mem_b.addr <= wb_cpu.addr; |
wb_mem_b.wdata <= wb_cpu.wdata; |
422,7 → 424,6
wb_mem_b.sel <= wb_cpu.sel; |
wb_mem_b.tag <= wb_cpu.tag; |
wb_mem_b.cyc <= wb_cpu.cyc; |
wb_mem_b.lock <= wb_cpu.lock; |
|
wb_mem_c.addr <= wb_cpu.addr; |
wb_mem_c.wdata <= wb_cpu.wdata; |
430,7 → 431,6
wb_mem_c.sel <= wb_cpu.sel; |
wb_mem_c.tag <= wb_cpu.tag; |
wb_mem_c.cyc <= wb_cpu.cyc; |
wb_mem_c.lock <= wb_cpu.lock; |
|
wb_irq.addr <= wb_cpu.addr; |
wb_irq.wdata <= wb_cpu.wdata; |
438,12 → 438,12
wb_irq.sel <= wb_cpu.sel; |
wb_irq.tag <= wb_cpu.tag; |
wb_irq.cyc <= wb_cpu.cyc; |
wb_irq.lock <= wb_cpu.lock; |
|
-- CPU read-back signals (no mux here since peripherals have "output gates") -- |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err; |
wb_cpu.tag_r <= wb_mem_a.tag_r or wb_mem_b.tag_r or wb_mem_c.tag_r or wb_irq.tag_r; |
|
-- peripheral select via STROBE signal -- |
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; |
480,8 → 480,9
end if; |
|
-- bus output register -- |
wb_mem_a.err <= '0'; |
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then |
wb_mem_a.err <= '0'; |
wb_mem_a.tag_r <= '0'; |
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then |
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1); |
wb_mem_a.ack <= '1'; |
else |
520,8 → 521,9
end if; |
|
-- bus output register -- |
wb_mem_b.err <= '0'; |
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then |
wb_mem_b.err <= '0'; |
wb_mem_b.tag_r <= '0'; |
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then |
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1); |
wb_mem_b.ack <= '1'; |
else |
559,16 → 561,30
end loop; |
end if; |
|
-- error to simulate interrupted LOCKED/EXCLUSIVE bus access -- |
wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail |
-- EXCLUSIVE bus access ----------------------------------------------------- |
-- ----------------------------------------------------------------------------- |
-- make a reservation -- |
if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') and -- valid access |
(wb_mem_c.tag(3) = '1') and -- make a reservation if there is a request (LR.W instruction) |
(wb_mem_c.addr(2) = '0') then -- only possible for even word-addresses - odd word-addresses will fail |
ext_mem_c_atomic_reservation <= '1'; |
-- clear reservation -- |
elsif (wb_mem_c.ack = '1') and -- end of access |
(wb_mem_c.tag(3) = '0') then -- end of exclusive access |
ext_mem_c_atomic_reservation <= '0'; |
end if; |
-- ----------------------------------------------------------------------------- |
|
-- bus output register -- |
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then |
wb_mem_c.err <= '0'; |
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then |
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1); |
wb_mem_c.ack <= '1'; |
wb_mem_c.tag_r <= ext_mem_c_atomic_reservation; |
else |
wb_mem_c.rdata <= (others => '0'); |
wb_mem_c.ack <= '0'; |
wb_mem_c.tag_r <= '0'; |
end if; |
end if; |
end process ext_mem_c_access; |
583,6 → 599,7
wb_irq.rdata <= (others => '0'); |
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel); |
wb_irq.err <= '0'; |
wb_irq.tag_r <= '0'; |
-- trigger IRQ using CSR.MIE bit layout -- |
msi_ring <= '0'; |
mei_ring <= '0'; |