URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/ghdl/ghdl_sim.sh
53,6 → 53,8
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_cp_muldiv.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_decompressor.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_regfile.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_debug_dm.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_debug_dtm.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_dmem.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_gpio.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_imem.vhd |
/neorv32_tb.vhd
1,9 → 1,9
-- ################################################################################################# |
-- # << NEORV32 - Default Testbench >> # |
-- # << NEORV32 - Default Processor Testbench >> # |
-- # ********************************************************************************************* # |
-- # The processor is configured to use a maximum of functional units (for testing purpose). # |
-- # Use the "User Configuration" section to configure the testbench according to your needs. # |
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. # |
-- # See NEORV32 data sheet for more information. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
193,6 → 193,8
BOOTLOADER_EN => false, -- implement processor-internal bootloader? |
USER_CODE => x"12345678", -- custom user code |
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit) |
-- On-Chip Debugger (OCD) -- |
ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? |
CPU_EXTENSION_RISCV_B => true, -- implement bit manipulation extensions? |
250,6 → 252,12
-- Global control -- |
clk_i => clk_gen, -- global clock, rising edge |
rstn_i => rst_gen, -- global reset, low-active, async |
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- |
jtag_trst_i => '1', -- low-active TAP reset (optional) |
jtag_tck_i => '0', -- serial clock |
jtag_tdi_i => '0', -- serial data input |
jtag_tdo_o => open, -- serial data output |
jtag_tms_i => '0', -- mode select |
-- Wishbone bus interface (available if MEM_EXT_EN = true) -- |
wb_tag_o => wb_cpu.tag, -- request tag |
wb_adr_o => wb_cpu.addr, -- address |
295,8 → 303,9
nco_o => open, -- numerically-controlled oscillator channels |
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- |
neoled_o => open, -- async serial data line |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => (others => '0'), -- current system time |
-- System time -- |
mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) |
mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) |
-- Interrupts -- |
nm_irq_i => nmi_ring, -- non-maskable interrupt |
soc_firq_i => soc_firq_ring, -- fast interrupt channels |