OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sim
    from Rev 62 to Rev 63
    ↔ Reverse comparison
  •

Rev 62 → Rev 63

/ghdl.setup.sh
8,7 → 8,8
 
ghdl -i --work=neorv32 --workdir=build \
../rtl/core/*.vhd \
../rtl/templates/processor/*.vhd \
../rtl/templates/system/*.vhd \
../rtl/processor_templates/*.vhd \
../rtl/system_integration/*.vhd \
../rtl/test_setups/*.vhd \
neorv32_tb.simple.vhd \
uart_rx.simple.vhd
/neorv32_imem.iram.simple.vhd
0,0 → 1,154
-- #################################################################################################
-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> #
-- # ********************************************************************************************* #
-- # This version is intended for SIMULATION ONLY! #
-- # It implements the IMEM as pre-initialized RAM. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
 
entity neorv32_imem is
generic (
IMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address
IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes
IMEM_AS_IROM : boolean -- implement IMEM as pre-initialized read-only memory?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_imem;
 
architecture neorv32_imem_rtl of neorv32_imem is
 
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit
 
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
 
-- ---------------------------------------------------- --
-- << SIMULATION ONLY!!! >> IMEM as pre-initialized RAM --
-- ---------------------------------------------------- --
 
-- application (image) size in bytes --
constant imem_app_size_c : natural := (application_init_image'length)*4;
 
-- RAM - initialized with executable code --
signal mem_ram : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
 
-- read data --
signal mem_ram_rd : std_ulogic_vector(31 downto 0);
 
begin
 
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal [SIM-only!] IMEM as RAM (" & natural'image(IMEM_SIZE) &
" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;
--
assert not (imem_app_size_c > IMEM_SIZE) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) &
" bytes) does not fit into processor-internal IMEM (" & natural'image(IMEM_SIZE) & " bytes)!" severity error;
 
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned
 
 
-- Implement IMEM as pre-initialized RAM --------------------------------------------------
-- -------------------------------------------------------------------------------------------
mem_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (acc_en = '1') then
if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0
mem_ram(to_integer(unsigned(addr)))(07 downto 00) <= data_i(07 downto 00);
else
mem_ram_rd(07 downto 00) <= mem_ram(to_integer(unsigned(addr)))(07 downto 00);
end if;
if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1
mem_ram(to_integer(unsigned(addr)))(15 downto 08) <= data_i(15 downto 08);
else
mem_ram_rd(15 downto 08) <= mem_ram(to_integer(unsigned(addr)))(15 downto 08);
end if;
if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2
mem_ram(to_integer(unsigned(addr)))(23 downto 16) <= data_i(23 downto 16);
else
mem_ram_rd(23 downto 16) <= mem_ram(to_integer(unsigned(addr)))(23 downto 16);
end if;
if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3
mem_ram(to_integer(unsigned(addr)))(31 downto 24) <= data_i(31 downto 24);
else
mem_ram_rd(31 downto 24) <= mem_ram(to_integer(unsigned(addr)))(31 downto 24);
end if;
end if;
end if;
end process mem_access;
 
-- read data --
rdata <= mem_ram_rd;
 
 
-- Bus Feedback ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
bus_feedback: process(clk_i)
begin
if rising_edge(clk_i) then
rden <= acc_en and rden_i;
ack_o <= acc_en and (rden_i or wren_i);
end if;
end process bus_feedback;
 
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
 
 
end neorv32_imem_rtl;
/neorv32_tb.simple.vhd
53,6 → 53,7
CPU_EXTENSION_RISCV_E : boolean := false;
CPU_EXTENSION_RISCV_M : boolean := true;
CPU_EXTENSION_RISCV_U : boolean := true;
CPU_EXTENSION_RISCV_Zbb : boolean := true;
CPU_EXTENSION_RISCV_Zicsr : boolean := true;
CPU_EXTENSION_RISCV_Zifencei : boolean := true;
EXT_IMEM_C : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
169,7 → 170,6
generic map (
-- General --
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
USER_CODE => x"12345678", -- custom user code
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
180,6 → 180,7
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbb => CPU_EXTENSION_RISCV_Zbb,-- implement basic bit-manipulation sub-extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
/neorv32_tb.vhd
219,7 → 219,7
if ci_mode then
-- No need to send the full expectation in one big chunk
check_uart(net, uart1_rx_handle, nul & nul);
check_uart(net, uart1_rx_handle, "0/45" & cr & lf);
check_uart(net, uart1_rx_handle, "0/46" & cr & lf);
end if;
 
-- Apply some random data on each SLINK inputs and expect it to
257,7 → 257,7
 
-- Wait a bit more if some extra unexpected data is produced. If so,
-- uart_rx will fail
wait for (20 * 1e9 / baud0_rate_c) * ns;
wait for (20 * (1e9 / baud0_rate_c)) * ns;
 
test_runner_cleanup(runner);
end process;
278,7 → 278,6
generic map (
-- General --
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
USER_CODE => x"12345678", -- custom user code
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
289,6 → 288,7
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbb => true, -- implement basic bit-manipulation sub-extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
/run_riscv_arch_test.sh
48,12 → 48,12
./work/sim/ghdl.setup.sh
 
# work in progress FIXME
printf "\n\e[1;33mWARNING! 'Zifencei' test is currently disabled (work in progress). \e[0m\n\n"
printf "\n\e[1;33mWARNING! 'rv32e/*' tests are work in progress! \e[0m\n\n"
 
makeArgs="-C ../sw/isa-test/riscv-arch-test NEORV32_ROOT=$(pwd)/.. XLEN=32 RISCV_TARGET=neorv32"
makeTargets='clean build run verify'
 
[ -n "$1" ] && SUITES="$@" || SUITES='I C M privilege'
[ -n "$1" ] && SUITES="$@" || SUITES='I C M privilege Zifencei'
 
for suite in $SUITES; do
case "$suite" in
61,9 → 61,12
C) make --silent $makeArgs SIM_TIME=400us RISCV_DEVICE=C $makeTargets;;
M) make --silent $makeArgs SIM_TIME=800us RISCV_DEVICE=M $makeTargets;;
privilege) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=privilege $makeTargets;;
Zifencei) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT $makeTargets;;
 
rv32e_C) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/C $makeTargets;;
rv32e_E) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/E $makeTargets;;
rv32e_M) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/M $makeTargets;;
esac
done
 
#make $makeArgs SIM_TIME=200us RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT $makeTargets
 
printf "\nRISC-V architecture tests completed successfully"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.