OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example/floating_point_test
    from Rev 62 to Rev 63
    ↔ Reverse comparison
  •

Rev 62 → Rev 63

/main.c
123,7 → 123,7
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// check if Zfinx extension is implemented at all
if (neorv32_cpu_check_zext(CSR_MZEXT_ZFINX) == 0) {
if ((SYSINFO_CPU & (1<<SYSINFO_CPU_ZFINX)) == 0) {
neorv32_uart_print("Error! <Zfinx> extension not synthesized!\n");
return 1;
}
148,11 → 148,6
neorv32_uart_printf("Test cases per instruction: %u\n", (uint32_t)NUM_TEST_CASES);
neorv32_uart_printf("NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.\n\n");
 
// enable FPU extension
uint32_t mstatus = neorv32_cpu_csr_read(CSR_MSTATUS);
mstatus |= 1 << CSR_MSTATUS_FS_L; // state = initial
neorv32_cpu_csr_write(CSR_MSTATUS, mstatus);
 
// clear exception status word
neorv32_cpu_csr_write(CSR_FFLAGS, 0); // real hardware
feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
/neorv32_zfinx_extension_intrinsics.h
182,14 → 182,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fadd.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000000, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
213,14 → 210,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsub.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000100, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
244,14 → 238,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmul.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0001000, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
275,14 → 266,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmin.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
306,14 → 294,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmax.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b001, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
334,14 → 319,11
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.wu.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return result;
}
 
361,14 → 343,11
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.w.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x0, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return (int32_t)result;
}
 
387,14 → 366,11
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.s.wu a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
414,14 → 390,11
register uint32_t tmp_a __asm__ ("a0") = (uint32_t)rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.s.w a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x0, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
445,14 → 418,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// feq.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b010, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return result;
}
 
475,14 → 445,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// flt.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b001, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return result;
}
 
505,14 → 472,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fle.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return result;
}
 
535,14 → 499,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnj.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
566,14 → 527,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjn.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b001, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
597,14 → 555,11
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjx.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
return res.float_value;
}
625,14 → 580,11
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fclass.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1110000, x0, a0, 0b001, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
return result;
}
 

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