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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/include
    from Rev 22 to Rev 23
    ↔ Reverse comparison
  •

Rev 22 → Rev 23

/neorv32.h
220,9 → 220,9
**************************************************************************/
/**@{*/
/** instruction memory base address (r/w/x) */
// -> use value from MEM_ISPACE_BASE generic
// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
/** data memory base address (r/w/x) */
// -> use value from MEM_DSPACE_BASE generic
// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
/** bootloader memory base address (r/-/x) */
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
/** peripheral/IO devices memory base address (r/w/x) */
234,8 → 234,8
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
**************************************************************************/
/**@{*/
/** GPIO parallel input port 32-bit (r/-) */
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL))
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
#define GPIO_INPUT (*(IO_REG32 0xFFFFFF80UL))
/** GPIO parallel output port 32-bit (r/w) */
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
/**@}*/
442,24 → 442,34
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** TRNG control register (r/w) */
/** TRNG control/data register (r/w) */
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0UL))
/** TRNG data register (r/-) */
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL))
 
/** TRNG control register bits */
/** TRNG control/data register bits */
enum NEORV32_TRNG_CT_enum {
TRNG_CT_TAP_LSB = 0, /**< TRNG control register(0) (r/w): TAP mask (16-bit) LSB */
TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
TRNG_CT_EN = 31 /**< TRNG control register(31) (r/w): TRNG enable */
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data (8-bit) LSB */
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data (8-bit) MSB */
TRNG_CT_VALID = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */
TRNG_CT_ERROR_0 = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */
TRNG_CT_ERROR_1 = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */
TRNG_CT_EN = 31 /**< TRNG data/control register(31) (r/w): TRNG enable */
};
/**@}*/
/**@}*/
 
/** WTD data register bits */
enum NEORV32_TRNG_DUTY_enum {
TRNG_DATA_LSB = 0, /**< TRNG data register(0) (r/-): Random data (16-bit) LSB */
TRNG_DATA_MSB = 15, /**< TRNG data register(15) (r/-): Random data (16-bit) MSB */
TRNG_DATA_VALID = 31 /**< TRNG data register(31) (r/-): Random data output valid */
};
 
/**********************************************************************//**
* @name IO Device: Custom Functions Unit (CFU)
**************************************************************************/
/**@{*/
/** CFU register 0 ((r)/(w)) */
#define CFU_REG_0 (*(IO_REG32 0xFFFFFFD0UL)) // (r)/(w): CFU register 0, user-defined
/** CFU register 1 ((r)/(w)) */
#define CFU_REG_1 (*(IO_REG32 0xFFFFFFD4UL)) // (r)/(w): CFU register 1, user-defined
/** CFU register 2 ((r)/(w)) */
#define CFU_REG_2 (*(IO_REG32 0xFFFFFFD8UL)) // (r)/(w): CFU register 2, user-defined
/** CFU register 3 ((r)/(w)) */
#define CFU_REG_3 (*(IO_REG32 0xFFFFFFDCUL)) // (r)/(w): CFU register 3, user-defined
/**@}*/
 
 
474,15 → 484,15
/** SYSINFO(2): Clock speed */
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
/** SYSINFO(3): reserved */
#define SYSINFO_reserved1 (*(IO_ROM32 0xFFFFFFECUL))
#define SYSINFO_reserved (*(IO_ROM32 0xFFFFFFECUL))
/** SYSINFO(4): Instruction memory address space base */
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
/** SYSINFO(5): Data memory address space base */
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
/** SYSINFO(6): Instruction memory address space size in bytes */
#define SYSINFO_ISPACE_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
/** SYSINFO(7): Data memory address space size in bytes */
#define SYSINFO_DSPACE_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
/**@}*/
 
 
503,9 → 513,9
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
 
SYSINFO_FEATURES_IO_CFU = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit implemented when 1 (via IO_CFU_USE generic) */
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (25) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
};
 
 
/neorv32_gpio.h
49,8 → 49,9
void neorv32_gpio_pin_set(uint8_t p);
void neorv32_gpio_pin_clr(uint8_t p);
void neorv32_gpio_pin_toggle(uint8_t p);
uint16_t neorv32_gpio_pin_get(uint8_t p);
void neorv32_gpio_port_set(uint16_t d);
uint16_t neorv32_gpio_port_get(void);
uint32_t neorv32_gpio_pin_get(uint8_t p);
void neorv32_gpio_port_set(uint32_t d);
uint32_t neorv32_gpio_port_get(void);
void neorv32_gpio_pin_change_config(uint32_t pin_sel);
 
#endif // neorv32_gpio_h
/neorv32_spi.h
51,5 → 51,6
void neorv32_spi_cs_en(uint8_t cs);
void neorv32_spi_cs_dis(uint8_t cs);
uint32_t neorv32_spi_trans(uint32_t tx_data);
int neorv32_spi_busy(void);
 
#endif // neorv32_spi_h
/neorv32_trng.h
46,9 → 46,8
 
// prototypes
int neorv32_trng_available(void);
int neorv32_trng_setup(uint16_t tap_mask);
uint16_t neorv32_trng_find_tap_mask(void);
void neorv32_trng_enable(void);
void neorv32_trng_disable(void);
int neorv32_trng_get(uint16_t *data);
int neorv32_trng_get(uint8_t *data);
 
#endif // neorv32_trng_h
/neorv32_twi.h
49,6 → 49,7
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en);
void neorv32_twi_disable(void);
void neorv32_twi_mack_enable(void);
int neorv32_twi_busy(void);
int neorv32_twi_start_trans(uint8_t a);
int neorv32_twi_trans(uint8_t d);
uint8_t neorv32_twi_get_data(void);
/neorv32_uart.h
52,6 → 52,7
void neorv32_uart_setup(uint32_t baudrate, uint8_t rx_irq, uint8_t tx_irq);
void neorv32_uart_disable(void);
void neorv32_uart_putc(char c);
int neorv32_uart_tx_busy(void);
char neorv32_uart_getc(void);
int neorv32_uart_char_received(void);
char neorv32_uart_char_received_get(void);

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