URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw/lib/include
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/neorv32.h
1080,6 → 1080,8
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 5, /**< SYSINFO_FEATURES (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */ |
SYSINFO_FEATURES_ICACHE = 6, /**< SYSINFO_FEATURES (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */ |
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SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */ |
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SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */ |
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */ |
SYSINFO_FEATURES_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */ |
/neorv32_cpu.h
52,7 → 52,6
uint64_t neorv32_cpu_get_systime(void); |
void neorv32_cpu_delay_ms(int16_t time_ms); |
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void); |
int neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired); |
uint32_t neorv32_cpu_pmp_get_num_regions(void); |
uint32_t neorv32_cpu_pmp_get_granularity(void); |
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config); |
68,7 → 67,32
* |
* @param[in] addr Address (32-bit). |
* @param[in] wdata Data word (32-bit) to store. |
* @return Operation status (32-bit). |
**************************************************************************/ |
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_store_conditional(uint32_t addr, uint32_t wdata) { |
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#if defined __riscv_atomic || defined __riscv_a |
register uint32_t reg_addr = addr; |
register uint32_t reg_data = wdata; |
register uint32_t reg_status; |
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asm volatile ("sc.w %[status], %[da], (%[ad])" : [status] "=r" (reg_status) : [da] "r" (reg_data), [ad] "r" (reg_addr)); |
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return reg_status; |
#else |
return 1; // always failing |
#endif |
} |
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/**********************************************************************//** |
* Conditional store unsigned word to address space if atomic access reservation is valid. |
* |
* @note An unaligned access address will raise an alignment exception. |
* |
* @param[in] addr Address (32-bit). |
* @param[in] wdata Data word (32-bit) to store. |
**************************************************************************/ |
inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata) { |
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register uint32_t reg_addr = addr; |
111,6 → 135,30
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/**********************************************************************//** |
* Load unsigned word from address space and make reservation for atomic access. |
* |
* @note An unaligned access address will raise an alignment exception. |
* |
* @param[in] addr Address (32-bit). |
* @return Read data word (32-bit). |
**************************************************************************/ |
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_reservate_word(uint32_t addr) { |
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register uint32_t reg_addr = addr; |
register uint32_t reg_data; |
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#if defined __riscv_atomic || defined __riscv_a |
asm volatile ("lr.w %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); |
#else |
asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); |
#endif |
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return (uint32_t)reg_data; |
} |
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/**********************************************************************//** |
* Load unsigned word from address space. |
* |
* @note An unaligned access address will raise an alignment exception. |