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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/neorv32_clic.c
61,7 → 61,7
**************************************************************************/
int neorv32_clic_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_CLIC)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_CLIC)) {
return 1;
}
else {
/neorv32_cpu.c
49,7 → 49,7
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
*
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
* return 0 if success, 1 if error (invalid irq_sel).
* @return 0 if success, 1 if error (invalid irq_sel).
**************************************************************************/
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
 
67,7 → 67,7
* Disable specific CPU interrupt.
*
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
* return 0 if success, 1 if error (invalid irq_sel).
* @return 0 if success, 1 if error (invalid irq_sel).
**************************************************************************/
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
 
82,6 → 82,139
 
 
/**********************************************************************//**
* Get cycle count from cycle[h].
*
* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
*
* @return Current cycle counter (64 bit).
**************************************************************************/
uint64_t neorv32_cpu_get_cycle(void) {
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
uint32_t tmp1, tmp2, tmp3;
while(1) {
tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
if (tmp1 == tmp3) {
break;
}
}
 
cycles.uint32[0] = tmp2;
cycles.uint32[1] = tmp3;
 
return cycles.uint64;
}
 
 
/**********************************************************************//**
* Set mcycle[h] counter.
*
* @param[in] value New value for mcycle[h] CSR (64-bit).
**************************************************************************/
void neorv32_cpu_set_mcycle(uint64_t value) {
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
cycles.uint64 = value;
 
neorv32_cpu_csr_write(CSR_MCYCLE, 0);
neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
}
 
 
/**********************************************************************//**
* Get retired instructions counter from instret[h].
*
* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
*
* @return Current instructions counter (64 bit).
**************************************************************************/
uint64_t neorv32_cpu_get_instret(void) {
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
uint32_t tmp1, tmp2, tmp3;
while(1) {
tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
if (tmp1 == tmp3) {
break;
}
}
 
cycles.uint32[0] = tmp2;
cycles.uint32[1] = tmp3;
 
return cycles.uint64;
}
 
 
/**********************************************************************//**
* Set retired instructions counter minstret[h].
*
* @param[in] value New value for mcycle[h] CSR (64-bit).
**************************************************************************/
void neorv32_cpu_set_minstret(uint64_t value) {
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
cycles.uint64 = value;
 
neorv32_cpu_csr_write(CSR_MINSTRET, 0);
neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
}
 
 
/**********************************************************************//**
* Get current system time from time[h] CSR.
*
* @note This function requires the MTIME system timer to be implemented.
*
* @return Current system time (64 bit).
**************************************************************************/
uint64_t neorv32_cpu_get_systime(void) {
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
uint32_t tmp1, tmp2, tmp3;
while(1) {
tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
tmp2 = neorv32_cpu_csr_read(CSR_TIME);
tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
if (tmp1 == tmp3) {
break;
}
}
 
cycles.uint32[0] = tmp2;
cycles.uint32[1] = tmp3;
 
return cycles.uint64;
}
 
 
/**********************************************************************//**
* Simple delay function (not very precise) using busy wait.
*
* @param[in] time_ms Time in ms to wait.
88,7 → 221,7
**************************************************************************/
void neorv32_cpu_delay_ms(uint32_t time_ms) {
 
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
uint32_t cnt = clock_speed * time_ms;
 
/neorv32_gpio.c
52,7 → 52,7
**************************************************************************/
int neorv32_gpio_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_GPIO)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_GPIO)) {
return 1;
}
else {
/neorv32_mtime.c
52,7 → 52,7
**************************************************************************/
int neorv32_mtime_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_MTIME)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_MTIME)) {
return 1;
}
else {
70,7 → 70,17
**************************************************************************/
void neorv32_mtime_set_time(uint64_t time) {
 
MTIME = time;
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
cycles.uint64 = time;
 
MTIME_LO = 0;
MTIME_HI = cycles.uint32[1];
MTIME_LO = cycles.uint32[0];
 
}
 
 
83,7 → 93,25
**************************************************************************/
uint64_t neorv32_mtime_get_time(void) {
 
return MTIME;
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cycles;
 
uint32_t tmp1, tmp2, tmp3;
while(1) {
tmp1 = MTIME_HI;
tmp2 = MTIME_LO;
tmp3 = MTIME_HI;
if (tmp1 == tmp3) {
break;
}
}
 
cycles.uint32[0] = tmp2;
cycles.uint32[1] = tmp3;
 
return cycles.uint64;
}
 
 
/neorv32_pwm.c
52,7 → 52,7
**************************************************************************/
int neorv32_pwm_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_PWM)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_PWM)) {
return 1;
}
else {
/neorv32_rte.c
46,7 → 46,6
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
static void __neorv32_rte_print_hw_version(void) __attribute__((unused));
 
 
/**********************************************************************//**
94,7 → 93,7
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
 
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
vt_base = vt_base + (((uint32_t)exc_id) << 2);
(*(IO_REG32 (vt_base))) = (uint32_t)handler;
 
127,7 → 126,7
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
 
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
vt_base = vt_base + (((uint32_t)exc_id) << 2);
(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
 
161,9 → 160,9
register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
register uint32_t trap_inst;
 
// get faulting instruction
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
 
 
if (trap_cause & 0x80000000) {
neorv32_uart_printf("INTERRUPT");
}
196,7 → 195,7
}
 
// fault address
neorv32_uart_printf("\nFaulting instruction: 0x%x\n", trap_inst);
neorv32_uart_printf("\nFaulting instruction (low): 0x%x\n", trap_inst);
neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
 
if ((trap_inst & 3) != 3) {
224,11 → 223,14
neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
// Hart ID
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
// Custom user code
neorv32_uart_printf("User code: 0x%x\n", SYSINFO_USER_CODE);
 
// HW version
neorv32_uart_printf("Hardware version: ");
__neorv32_rte_print_hw_version();
neorv32_rte_print_hw_version();
neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
 
// CPU architecture
260,69 → 262,65
}
neorv32_uart_printf("(0x%x)\n", tmp);
 
// Performance counters
neorv32_uart_printf("CNT & time CSRs: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
 
// Clock speed
neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
neorv32_uart_printf("Clock speed: %u Hz\n", SYSINFO_CLK);
 
// Memory configuration
neorv32_uart_printf("\n-- Memory Configuration --\n");
 
uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
uint32_t size = SYSINFO_ISPACE_SIZE;
uint32_t base = SYSINFO_ISPACE_BASE;
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
neorv32_uart_printf("Internal IMEM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
neorv32_uart_printf("Internal IMEM as ROM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
 
size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
size = SYSINFO_DSPACE_SIZE;
base = SYSINFO_DSPACE_BASE;
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
neorv32_uart_printf("Internal DMEM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
 
neorv32_uart_printf("Bootloader: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
 
neorv32_uart_printf("External interface: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
 
// peripherals
neorv32_uart_printf("\n-- Peripherals --\n");
tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
tmp = SYSINFO_FEATURES;
 
neorv32_uart_printf("GPIO: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
 
neorv32_uart_printf("MTIME: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
 
neorv32_uart_printf("UART: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
 
neorv32_uart_printf("SPI: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
 
neorv32_uart_printf("TWI: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
 
neorv32_uart_printf("PWM: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
 
neorv32_uart_printf("WDT: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
 
neorv32_uart_printf("CLIC: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC));
 
neorv32_uart_printf("TRNG: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
 
neorv32_uart_printf("DEVNULL: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
}
 
 
344,10 → 342,9
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Private function to show the processor version in human-readable format.
* @note This function is used by neorv32_rte_print_hw_config(void) only.
* NEORV32 runtime environment: Function to show the processor version in human-readable format.
**************************************************************************/
static void __neorv32_rte_print_hw_version(void) {
void neorv32_rte_print_hw_version(void) {
 
uint32_t i;
char tmp, cnt;
/neorv32_spi.c
52,7 → 52,7
**************************************************************************/
int neorv32_spi_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_SPI)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) {
return 1;
}
else {
/neorv32_trng.c
52,7 → 52,7
**************************************************************************/
int neorv32_trng_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TRNG)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TRNG)) {
return 1;
}
else {
/neorv32_twi.c
52,7 → 52,7
**************************************************************************/
int neorv32_twi_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TWI)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TWI)) {
return 1;
}
else {
/neorv32_uart.c
59,7 → 59,7
**************************************************************************/
int neorv32_uart_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_UART)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART)) {
return 1;
}
else {
80,7 → 80,7
UART_CT = 0; // reset
 
// raw baud rate prescaler
uint32_t clock = neorv32_cpu_csr_read(CSR_MCLOCK);
uint32_t clock = SYSINFO_CLK;
uint16_t i = 0; // BAUD rate divisor
uint8_t p = 0; // prsc = CLK/2
while (clock >= 2*baudrate) {
/neorv32_wdt.c
52,7 → 52,7
**************************************************************************/
int neorv32_wdt_available(void) {
 
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_WDT)) {
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_WDT)) {
return 1;
}
else {

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