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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 26 to Rev 30
    ↔ Reverse comparison
  •

Rev 26 → Rev 30

/neorv32_rte.c
254,22 → 254,20
neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
// ID
neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
 
tmp = neorv32_cpu_csr_read(CSR_MARCHID);
neorv32_uart_printf("Architecture ID: 0x%x", tmp);
neorv32_uart_printf("Architecture ID: 0x%x", tmp);
 
// Custom user code/ID
neorv32_uart_printf("\nUser ID: 0x%x\n", SYSINFO_USER_CODE);
 
// HW version
neorv32_uart_printf("Hardware version: ");
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
neorv32_rte_print_hw_version();
neorv32_uart_printf(")\n");
 
// CPU architecture
neorv32_uart_printf("\nArchitecture: ");
neorv32_uart_printf("Architecture: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
tmp = (tmp >> 30) & 0x03;
if (tmp == 0) {
286,7 → 284,7
}
// CPU extensions
neorv32_uart_printf("\nExtensions: ");
neorv32_uart_printf("\nExtensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
307,8 → 305,9
 
 
// Misc
neorv32_uart_printf("\n\n-- System --\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("\n\n\n-- Processor --\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
 
 
// Memory configuration
329,7 → 328,7
neorv32_uart_printf("Bootloader: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
 
neorv32_uart_printf("External interface: ");
neorv32_uart_printf("External M interface: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
 
// peripherals
337,34 → 336,31
 
tmp = SYSINFO_FEATURES;
 
neorv32_uart_printf("GPIO: ");
neorv32_uart_printf("GPIO: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
 
neorv32_uart_printf("MTIME: ");
neorv32_uart_printf("MTIME: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
 
neorv32_uart_printf("UART: ");
neorv32_uart_printf("UART: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
 
neorv32_uart_printf("SPI: ");
neorv32_uart_printf("SPI: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
 
neorv32_uart_printf("TWI: ");
neorv32_uart_printf("TWI: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
 
neorv32_uart_printf("PWM: ");
neorv32_uart_printf("PWM: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
 
neorv32_uart_printf("WDT: ");
neorv32_uart_printf("WDT: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
 
neorv32_uart_printf("TRNG: ");
neorv32_uart_printf("TRNG: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
 
neorv32_uart_printf("DEVNULL: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
 
neorv32_uart_printf("CFU: ");
neorv32_uart_printf("CFU: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU));
}
 
/neorv32_uart.c
71,6 → 71,8
/**********************************************************************//**
* Enable and configure UART.
*
* @warning The 'UART_SIM_MODE' compiler flag will redirect all UART TX data to the simulation output. Use this for simulations only!
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] rx_irq Enable RX interrupt (data received) when 1.
* @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
112,7 → 114,16
uint32_t tx_irq_en = (uint32_t)(tx_irq & 1);
tx_irq_en = tx_irq_en << UART_CT_TX_IRQ;
 
UART_CT = prsc | baud | uart_en | rx_irq_en | tx_irq_en;
/* Enable the UART for SIM mode. */
/* Only use this for simulation! */
#ifdef UART_SIM_MODE
#warning UART_SIM_MODE enabled! Sending all UART.TX to text.io simulation output instead of real UART transmitter. Use this for simulations only!
uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
#else
uint32_t sim_mode = 0;
#endif
 
UART_CT = prsc | baud | uart_en | rx_irq_en | tx_irq_en | sim_mode;
}
 
 
129,21 → 140,18
* Send single char via UART.
*
* @note This function is blocking.
* @warning The 'DEVNULL_UART_OVERRIDE' compiler user flag will forward all UART TX data to the DEVNULL simulation console output.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart_putc(char c) {
 
#ifdef DEVNULL_UART_OVERRIDE
#warning UART OVERRIDE! Sending all UART.TX data to DEVNULL simulation output instead of UART transmitter. Use this for simulations only!
DEVNULL_DATA = (uint32_t)c;
#ifdef UART_SIM_MODE
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#else
// wait for previous transfer to finish
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#endif
 
}
 
 

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