URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw/lib/source
- from Rev 34 to Rev 35
- ↔ Reverse comparison
Rev 34 → Rev 35
/neorv32_cpu.c
246,11 → 246,11
**************************************************************************/ |
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) { |
|
register uint32_t mask = (1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L); |
asm volatile ("csrrc zero, mstatus, %[input_j]" : : [input_j] "r" (mask)); |
// make sure to use NO registers in here! -> naked |
|
// return switching to user mode |
asm volatile ("csrw mepc, ra"); |
asm volatile ("mret"); |
asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can use ra as general purpose register in here |
"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits |
"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode |
"mret \n\t" // return and switch to user mode |
: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L))); |
} |
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/neorv32_pwm.c
105,6 → 105,10
duty_mask = duty_mask << (channel * 8); |
duty_new = duty_new << (channel * 8); |
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PWM_DUTY &= ~duty_mask; // clear previous duty cycle |
PWM_DUTY |= duty_new; // set new duty cycle |
uint32_t duty_cycle = PWM_DUTY; |
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duty_cycle &= ~duty_mask; // clear previous duty cycle |
duty_cycle |= duty_new; // set new duty cycle |
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PWM_DUTY = duty_cycle; |
} |
/neorv32_rte.c
227,7 → 227,7
} |
|
// instruction address |
neorv32_uart_print(" @ "); |
neorv32_uart_print(" @ PC="); |
__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores actual mepc to mscratch |
|
// additional info |
326,7 → 326,7
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neorv32_uart_printf("\n- Min granularity: "); |
if (i < 29) { |
neorv32_uart_printf("%u bytes per region (0x%x)\n", (uint32_t)(1 << (i+1+2)), pmp_test_g); |
neorv32_uart_printf("%u bytes per region\n", (uint32_t)(1 << (i+1+2))); |
} |
else { |
neorv32_uart_printf("2^%u bytes per region\n", i+1+2); |
485,8 → 485,8
|
// serial division |
cnt = 0; |
while (tmp >= 10) { |
tmp = tmp - 10; |
while (tmp >= 16) { |
tmp = tmp - 16; |
cnt++; |
} |
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/neorv32_twi.c
66,8 → 66,9
* |
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] irq_en Enable transfer-done interrupt when 1. |
* @param[in] ckst_en Enable clock-stretching by peripherals when 1. |
**************************************************************************/ |
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en) { |
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en, uint8_t ckst_en) { |
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TWI_CT = 0; // reset |
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80,7 → 81,10
uint32_t ct_irq = (uint32_t)(irq_en & 0x01); |
ct_irq = ct_irq << TWI_CT_IRQ_EN; |
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TWI_CT = ct_enable | ct_prsc | ct_irq; |
uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01); |
ct_cksten = ct_cksten << TWI_CT_CKSTEN; |
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TWI_CT = ct_enable | ct_prsc | ct_irq | ct_cksten; |
} |
|
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/neorv32_uart.c
118,7 → 118,7
/* Enable the UART for SIM mode. */ |
/* Only use this for simulation! */ |
#ifdef UART_SIM_MODE |
#warning UART_SIM_MODE enabled! Sending all UART.TX to text.io simulation output instead of real UART transmitter. Use this for simulations only! |
#warning UART_SIM_MODE enabled! Sending all UART.TX data to text.io simulation output instead of real UART transmitter. Use this for simulations only! |
uint32_t sim_mode = 1 << UART_CT_SIM_MODE; |
#else |
uint32_t sim_mode = 0; |